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mayhem-firmware/hardware/portapack_h1/gps.sch

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Upstream merge to make new revision of PortaPack work (#206) * Power: Turn off additional peripheral clock branches. * Update schematic with new symbol table and KiCad standard symbols. Fix up wires. * Schematic: Update power net labels. * Schematic: Update footprint names to match library changes. * Schematic: Update header vendor and part numbers. * Schematic: Specify (arbitrary) value for PDN# net. * Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space. * Schematic: Add reference oscillator -- options for clipped sine or HCMOS output. * Schematic: Update copyright year. * Schematic: Remove CLKOUT to CPLD. It was a half-baked idea. * Schematic: Add (experimental) GPS circuit. Add note about charging circuit. Update date and revision to match PCB. * PCB: Update from schematic change: now revision 20180819. Diff was extensive due to net renumbering... * PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual. PCB: Address DRC clearance violation between via and oscillator pad. * PCB: Update copyright on drawing. * Update schematic and PCB date and revision. * gitignore: Sublime Text editor project/workspace files * Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze... * Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field. * LPC43xx: Add CGU IDIVx struct/union type. * Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use. * HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02) * MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class. * MAX V CPLD: Add BYPASS, SAMPLE support. Rename enter_isp -> enable, exit_isp -> disable. Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing. * MAX V CPLD: Reverse verify data checking logic to make it a little faster. * CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream. * Si5351: Refactor code, make one of the registers more type-safe. Clock Manager: Track selected reference clock source for later use in user interface. * Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal. It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise... * PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external. * CPLD: Add pins and logic for new PortaPack hardware feature(s). * CPLD: Bitstream to support new hardware features. * Clock Generator: Add a couple more setter methods for ClockControl registers. * Clock Manager: Use shared MCU CLKIN clock control configuration constant. * Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty. * Clock Manager: Remove redundant clock generator output enable. * Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM. * Bootstrap: Get CPU operating at max frequency as soon as possible. Update SPIFI speed comment. Make some more LPC43xx types into unions with uint32_t. * Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it. * Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream. * Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated. * Bootstrap: Consolidate clock configuration, update SPIFI rate comment. * Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward. Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out... * ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution. * PortaPack IO: Expose method to set reference oscillator enable pin. * Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader. * Pin configuration: Disable input buffers on pins that are never read. * Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution." This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03. * Remove unused board files. * Add LPC43xx functions. * chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits. * LPC43xx: Add MCPWM peripheral struct. * clock generator: Use recommended PLL reset register value. Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000. * GPIO: Tweak masking of SCU function. I don't remember why I thought this was necessary... * HAL: Explicitly turn on timer peripheral clocks used as systicks, during init. * SCU: Add struct to hold pin configuration. * PAL: Add functions to address The Glitch. https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/ * PAL/board: New IO initialization code Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch. * Merge M0 and M4 to eliminate need for bootstrap firmware During _early_init, detect if we're running on the M4 or M0. If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep. If M0: do all the other things. * Pins: Miscellaneous SCU configuration tweaks. * Little code clarity improvement. * bootstrap: Remove, not necessary. * Clock Manager: Large re-working to support external references. * Fix merge conflicts
2019-01-11 06:56:21 +00:00
EESchema Schematic File Version 4
LIBS:portapack_h1-cache
EELAYER 26 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 6 6
Title "PortaPack H1"
Date "2018-08-20"
Rev "20180820"
Comp "ShareBrained Technology, Inc."
Comment1 "Copyright © 2014-2018 Jared Boone"
Comment2 "License: GNU General Public License, version 2"
Comment3 ""
Comment4 ""
$EndDescr
$Comp
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F 2 "ublox:MAX-M8" H 5800 2900 60 0001 C CNN
F 3 "" H 5800 2900 60 0001 C CNN
F 4 "DNP" H 5800 3450 50 0000 C CNN "DNP"
1 5800 2900
1 0 0 -1
$EndComp
$Comp
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F 3 "~" H 4600 3450 50 0001 C CNN
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1 4600 3450
1 0 0 -1
$EndComp
$Comp
L Device:L L1
U 1 1 5B7E0E02
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F 0 "L1" H 4403 2946 50 0000 L CNN
F 1 "27N" H 4403 2855 50 0000 L CNN
F 2 "ipc_indc:IPC_INDC100X50X60L20N" H 4350 2900 50 0001 C CNN
F 3 "~" H 4350 2900 50 0001 C CNN
F 4 "DNP" H 4450 2750 50 0000 C CNN "DNP"
1 4350 2900
0 -1 -1 0
$EndComp
$Comp
L power:GND #PWR0108
U 1 1 5B7E0F42
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F 3 "" H 4600 3700 50 0001 C CNN
1 4600 3700
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR0109
U 1 1 5B7E0F5A
P 5100 3400
F 0 "#PWR0109" H 5100 3150 50 0001 C CNN
F 1 "GND" H 5105 3227 50 0000 C CNN
F 2 "" H 5100 3400 50 0001 C CNN
F 3 "" H 5100 3400 50 0001 C CNN
1 5100 3400
1 0 0 -1
$EndComp
Wire Wire Line
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Wire Wire Line
5100 2500 5100 2700
Wire Wire Line
5200 2700 5100 2700
Connection ~ 5100 2700
Wire Wire Line
5100 2700 5100 3000
Wire Wire Line
5200 2600 4100 2600
Text HLabel 3200 3100 0 60 BiDi ~ 0
SDA
Text HLabel 3200 3500 0 60 BiDi ~ 0
SCL
$Comp
L power:GND #PWR0110
U 1 1 5B7E1247
P 6500 3400
F 0 "#PWR0110" H 6500 3150 50 0001 C CNN
F 1 "GND" H 6505 3227 50 0000 C CNN
F 2 "" H 6500 3400 50 0001 C CNN
F 3 "" H 6500 3400 50 0001 C CNN
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1 0 0 -1
$EndComp
Wire Wire Line
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Wire Wire Line
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Text HLabel 7800 1800 2 60 Input ~ 0
V_BACKUP
Text HLabel 6650 1800 0 60 Input ~ 0
VCC
Wire Wire Line
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Wire Wire Line
6400 2700 6800 2700
$Comp
L tp:TP TP7
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P 4900 3300
F 0 "TP7" H 4750 3300 50 0000 C CNN
F 1 "TP" H 4900 3300 50 0001 C CNN
F 2 "tp:TP_1MM" H 4900 3300 60 0001 C CNN
F 3 "" H 4900 3300 60 0001 C CNN
1 4900 3300
1 0 0 -1
$EndComp
Wire Wire Line
5000 3300 5200 3300
Text HLabel 6900 3000 2 60 Output ~ 0
TIMEPULSE
Wire Wire Line
6400 3000 6900 3000
$Comp
L tp:TP TP8
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F 1 "TP" H 7000 2900 50 0001 C CNN
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-1 0 0 1
$EndComp
Wire Wire Line
6400 2900 6900 2900
$Comp
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F 1 "TP" H 7000 3100 50 0001 C CNN
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F 3 "" H 7000 3100 60 0001 C CNN
1 7000 3100
-1 0 0 1
$EndComp
Wire Wire Line
6400 3100 6900 3100
Text HLabel 7800 2500 2 60 Input ~ 0
RESET#
Wire Wire Line
6400 2500 7700 2500
$Comp
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F 1 "100N" H 6915 3405 50 0000 L CNN
F 2 "ipc_capc:IPC_CAPC100X50X55L25N" H 6838 3300 50 0001 C CNN
F 3 "~" H 6800 3450 50 0001 C CNN
F 4 "DNP" H 7000 3300 50 0000 C CNN "DNP"
1 6800 3450
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR0111
U 1 1 5B7E5197
P 6800 3700
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F 1 "GND" H 6805 3527 50 0000 C CNN
F 2 "" H 6800 3700 50 0001 C CNN
F 3 "" H 6800 3700 50 0001 C CNN
1 6800 3700
1 0 0 -1
$EndComp
Wire Wire Line
6800 3600 6800 3700
Wire Wire Line
6800 2700 6800 2600
$Comp
L Device:R R25
U 1 1 5B7E62C8
P 7700 2750
F 0 "R25" H 7770 2796 50 0000 L CNN
F 1 "100K" V 7700 2650 50 0000 L CNN
F 2 "ipc_resc:IPC_RESC100X50X40L25N" V 7630 2750 50 0001 C CNN
F 3 "~" H 7700 2750 50 0001 C CNN
F 4 "DNP" H 7850 2700 50 0000 C CNN "DNP"
1 7700 2750
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR0112
U 1 1 5B7E633A
P 7700 3000
F 0 "#PWR0112" H 7700 2750 50 0001 C CNN
F 1 "GND" H 7705 2827 50 0000 C CNN
F 2 "" H 7700 3000 50 0001 C CNN
F 3 "" H 7700 3000 50 0001 C CNN
1 7700 3000
1 0 0 -1
$EndComp
Wire Wire Line
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Connection ~ 7700 2500
Wire Wire Line
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Wire Wire Line
7700 2900 7700 3000
$Comp
L passive:FBEAD FB1
U 1 1 5B7E9718
P 3550 3100
F 0 "FB1" H 3550 3300 50 0000 C CNN
F 1 "FBEAD" H 3544 3227 50 0001 C CNN
F 2 "ipc_beadc:IPC_BEADC160X80X95L40N" H 3544 3234 60 0001 C CNN
F 3 "" H 3550 3100 60 0000 C CNN
F 4 "DNP" H 3550 3200 50 0000 C CNN "DNP"
F 5 "Murata" H 0 0 50 0001 C CNN "Mfr"
F 6 "BLM18HE152SN1D" H 0 0 50 0001 C CNN "Part"
1 3550 3100
1 0 0 -1
$EndComp
$Comp
L passive:FBEAD FB3
U 1 1 5B7E9798
P 3550 3500
F 0 "FB3" H 3550 3700 50 0000 C CNN
F 1 "FBEAD" H 3544 3627 50 0001 C CNN
F 2 "ipc_beadc:IPC_BEADC160X80X95L40N" H 3550 3500 60 0001 C CNN
F 3 "" H 3550 3500 60 0000 C CNN
F 4 "DNP" H 3550 3600 50 0000 C CNN "DNP"
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1 3550 3500
1 0 0 -1
$EndComp
Wire Wire Line
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Wire Wire Line
3200 3500 3300 3500
Wire Wire Line
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Wire Wire Line
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Wire Wire Line
3900 3200 5200 3200
$Comp
L Device:R R24
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P 7550 1800
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F 1 "0R" V 7550 1800 50 0000 C CNN
F 2 "ipc_resc:IPC_RESC100X50X40L25N" V 7480 1800 50 0001 C CNN
F 3 "~" H 7550 1800 50 0001 C CNN
F 4 "DNP" V 7650 1800 50 0000 C CNN "DNP"
1 7550 1800
0 1 1 0
$EndComp
$Comp
L Device:R R23
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F 3 "~" H 7050 1800 50 0001 C CNN
F 4 "DNP" V 7150 1800 50 0000 C CNN "DNP"
1 7050 1800
0 1 1 0
$EndComp
NoConn ~ 5200 2800
Wire Wire Line
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Connection ~ 5100 3000
Wire Wire Line
5100 3000 5100 3400
Text HLabel 6900 3200 2 60 Output ~ 0
TX_READY
Wire Wire Line
6400 3200 6900 3200
$Comp
L conn_rf:CONN_COAX P1
U 1 1 5B78522B
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1 2550 2600
-1 0 0 -1
$EndComp
$Comp
L power:GND #PWR0113
U 1 1 5B7852CC
P 2550 2900
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F 2 "" H 2550 2900 50 0001 C CNN
F 3 "" H 2550 2900 50 0001 C CNN
1 2550 2900
1 0 0 -1
$EndComp
Wire Wire Line
2550 2800 2550 2900
Wire Wire Line
3800 3100 5200 3100
$Comp
L Device:R R26
U 1 1 5B78A3E5
P 4850 2900
F 0 "R26" V 4750 2900 50 0000 C CNN
F 1 "10R" V 4850 2900 50 0000 C CNN
F 2 "ipc_resc:IPC_RESC100X50X40L25N" V 4780 2900 50 0001 C CNN
F 3 "~" H 4850 2900 50 0001 C CNN
F 4 "DNP" V 4950 2900 50 0000 C CNN "DNP"
1 4850 2900
0 1 1 0
$EndComp
Wire Wire Line
5200 2900 5000 2900
Wire Wire Line
4700 2900 4600 2900
Wire Wire Line
4600 2900 4600 3300
Wire Wire Line
4600 3600 4600 3700
Wire Wire Line
4600 2900 4500 2900
Connection ~ 4600 2900
Wire Wire Line
4200 2900 4100 2900
Wire Wire Line
4100 2900 4100 2600
Connection ~ 4100 2600
Wire Wire Line
2700 2600 4100 2600
Wire Wire Line
7800 1800 7700 1800
Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Connection ~ 6800 2600
Connection ~ 6800 1800
Wire Wire Line
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Wire Wire Line
6400 2800 7300 2800
Wire Wire Line
7300 1800 7300 2800
Connection ~ 7300 1800
Wire Wire Line
7300 1800 7200 1800
Wire Wire Line
6800 2700 6800 3300
Connection ~ 6800 2700
$EndSCHEMATC
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