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https://github.com/portapack-mayhem/mayhem-firmware.git
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103 lines
2.7 KiB
C
103 lines
2.7 KiB
C
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/*
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ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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#include "ch.h"
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#include "hal.h"
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/**
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* @brief PAL setup.
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* @details Digital I/O ports static configuration as defined in @p board.h.
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* This variable is used by the HAL when initializing the PAL driver.
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*/
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#if HAL_USE_PAL || defined(__DOXYGEN__)
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const PALConfig pal_default_config =
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{
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#if defined(PORTA)
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{VAL_PORTA, VAL_DDRA},
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#endif
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#if defined(PORTB)
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{VAL_PORTB, VAL_DDRB},
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#endif
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#if defined(PORTC)
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{VAL_PORTC, VAL_DDRC},
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#endif
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#if defined(PORTD)
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{VAL_PORTD, VAL_DDRD},
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#endif
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#if defined(PORTE)
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{VAL_PORTE, VAL_DDRE},
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#endif
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#if defined(PORTF)
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{VAL_PORTF, VAL_DDRF},
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#endif
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#if defined(PORTG)
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{VAL_PORTG, VAL_DDRG},
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#endif
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#if defined(PORTH)
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{VAL_PORTH, VAL_DDRH},
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#endif
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#if defined(PORTJ)
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{VAL_PORTJ, VAL_DDRJ},
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#endif
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#if defined(PORTK)
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{VAL_PORTK, VAL_DDRK},
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#endif
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#if defined(PORTL)
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{VAL_PORTL, VAL_DDRL},
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#endif
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};
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#endif /* HAL_USE_PAL */
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/**
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* @brief Timer0 interrupt handler.
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*/
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CH_IRQ_HANDLER(TIMER0_COMPA_vect) {
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CH_IRQ_PROLOGUE();
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chSysLockFromIsr();
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chSysTimerHandlerI();
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chSysUnlockFromIsr();
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CH_IRQ_EPILOGUE();
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}
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/**
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* Board-specific initialization code.
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*/
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void boardInit(void) {
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/*
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* External interrupts setup, all disabled initially.
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*/
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EICRA = 0x00;
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EICRB = 0x00;
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EIMSK = 0x00;
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/*
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* Timer 0 setup.
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*/
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TCCR0A = (1 << WGM01) | (0 << WGM00) | /* CTC mode. */
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(0 << COM0A1) | (0 << COM0A0) | /* OC0A disabled. */
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(0 << COM0B1) | (0 << COM0B0); /* OC0B disabled. */
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TCCR0B = (0 << WGM02) | /* CTC mode. */
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(0 << CS02) | (1 << CS01) | (1 << CS00); /* CLK/64 clock. */
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OCR0A = F_CPU / 64 / CH_FREQUENCY - 1;
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TCNT0 = 0; /* Reset counter. */
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TIFR0 = (1 << OCF0A); /* Reset pending. */
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TIMSK0 = (1 << OCIE0A); /* IRQ on compare. */
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}
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