mirror of
https://github.com/portapack-mayhem/mayhem-firmware.git
synced 2025-01-10 22:53:39 +00:00
80 lines
1.6 KiB
Tcl
80 lines
1.6 KiB
Tcl
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map -import
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if { [info exists DESIGN] && ! [info exists TOP_MODULE] } {
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set TOP_MODULE "$DESIGN"
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}
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if { ! [info exists DESIGN] } {
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set DESIGN "portapack_h4m_cpld"
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}
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if { ! [info exists TOP_MODULE] } {
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set TOP_MODULE "top"
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}
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set verilogs { }
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if { [ llength $verilogs ] == 0 } {
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set verilogs "A:/Users/jLynx/Documents/Code/C/portapack-mayhem/hardware/portapack_h4m/CPLD/AG256SL100/${DESIGN}.v"
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}
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foreach verilog $verilogs {
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read_verilog "$verilog"
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}
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read_verilog -sv -lib +/agm/rodina/cells_sim.v
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read_verilog -sv -lib +/agm/common/m9k_bb.v
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read_verilog -sv -lib +/agm/common/altpll_bb.v
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hierarchy -check -top ${TOP_MODULE}
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synth -run coarse -top ${DESIGN}
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map proc
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opt_expr
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opt_clean
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check
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opt
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wreduce
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alumacc
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share
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opt
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fsm
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opt -fast
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memory -nomap
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opt_clean
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memory_bram -rules +/agm/common/brams.txt
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techmap -map +/agm/common/brams_map.v
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opt -fast -mux_undef -undriven -fine -full
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memory_map
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opt -undriven -fine
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techmap -autoproc -map +/techmap.v -map +/agm/rodina/arith_map.v
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dffsr2dff
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dff2dffe -direct-match \$_DFF_*
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opt -full
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techmap -map +/agm/rodina/cells_map.v
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agm_dffeas
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opt -full
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clean -purge
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setundef -undriven -zero
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abc -markgroups -dff
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opt_expr -mux_undef -undriven -full
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opt_merge
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opt_rmdff
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opt_clean
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abc -lut 4
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clean
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techmap -map +/agm/rodina/cells_map.v
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dffinit -ff dffeas Q INIT
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clean -purge
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hierarchy -check
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check -noinit
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write_verilog -bitblasted -attr2comment -defparam -decimal -renameprefix syn_ ${DESIGN}.vqm
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# exec sed -i "/\\\\\\\$paramod/s/\[$=\\]/_/g" ${DESIGN}.vqm
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