mirror of
https://github.com/portapack-mayhem/mayhem-firmware.git
synced 2024-12-15 12:38:11 +00:00
300 lines
12 KiB
C
300 lines
12 KiB
C
|
/*
|
||
|
|
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
|
||
|
|
|
||
|
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||
|
|
you may not use this file except in compliance with the License.
|
||
|
|
You may obtain a copy of the License at
|
||
|
|
|
||
|
|
http://www.apache.org/licenses/LICENSE-2.0
|
||
|
|
|
||
|
|
Unless required by applicable law or agreed to in writing, software
|
||
|
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||
|
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||
|
|
See the License for the specific language governing permissions and
|
||
|
|
limitations under the License.
|
||
|
|
*/
|
||
|
|
|
||
|
|
/*
|
||
|
|
* STM32F4xx drivers configuration.
|
||
|
|
* The following settings override the default settings present in
|
||
|
|
* the various device driver implementation headers.
|
||
|
|
* Note that the settings for each driver only have effect if the whole
|
||
|
|
* driver is enabled in halconf.h.
|
||
|
|
*
|
||
|
|
* IRQ priorities:
|
||
|
|
* 15...0 Lowest...Highest.
|
||
|
|
*
|
||
|
|
* DMA priorities:
|
||
|
|
* 0...3 Lowest...Highest.
|
||
|
|
*/
|
||
|
|
|
||
|
|
#define STM32F4xx_MCUCONF
|
||
|
|
|
||
|
|
/*
|
||
|
|
* HAL driver system settings.
|
||
|
|
*/
|
||
|
|
#define STM32_NO_INIT FALSE
|
||
|
|
#define STM32_HSI_ENABLED TRUE
|
||
|
|
#define STM32_LSI_ENABLED TRUE
|
||
|
|
#define STM32_HSE_ENABLED TRUE
|
||
|
|
#define STM32_LSE_ENABLED FALSE
|
||
|
|
#define STM32_CLOCK48_REQUIRED TRUE
|
||
|
|
#define STM32_SW STM32_SW_PLL
|
||
|
|
#define STM32_PLLSRC STM32_PLLSRC_HSE
|
||
|
|
#define STM32_PLLM_VALUE 12
|
||
|
|
#define STM32_PLLN_VALUE 336
|
||
|
|
#define STM32_PLLP_VALUE 2
|
||
|
|
#define STM32_PLLQ_VALUE 7
|
||
|
|
#define STM32_HPRE STM32_HPRE_DIV1
|
||
|
|
#define STM32_PPRE1 STM32_PPRE1_DIV4
|
||
|
|
#define STM32_PPRE2 STM32_PPRE2_DIV2
|
||
|
|
#define STM32_RTCSEL STM32_RTCSEL_LSI
|
||
|
|
#define STM32_RTCPRE_VALUE 8
|
||
|
|
#define STM32_MCO1SEL STM32_MCO1SEL_HSI
|
||
|
|
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
|
||
|
|
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
|
||
|
|
#define STM32_MCO2PRE STM32_MCO2PRE_DIV5
|
||
|
|
#define STM32_I2SSRC STM32_I2SSRC_CKIN
|
||
|
|
#define STM32_PLLI2SN_VALUE 192
|
||
|
|
#define STM32_PLLI2SR_VALUE 5
|
||
|
|
#define STM32_PVD_ENABLE FALSE
|
||
|
|
#define STM32_PLS STM32_PLS_LEV0
|
||
|
|
#define STM32_BKPRAM_ENABLE FALSE
|
||
|
|
|
||
|
|
/*
|
||
|
|
* ADC driver system settings.
|
||
|
|
*/
|
||
|
|
#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4
|
||
|
|
#define STM32_ADC_USE_ADC1 FALSE
|
||
|
|
#define STM32_ADC_USE_ADC2 FALSE
|
||
|
|
#define STM32_ADC_USE_ADC3 FALSE
|
||
|
|
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
|
||
|
|
#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
||
|
|
#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
|
||
|
|
#define STM32_ADC_ADC1_DMA_PRIORITY 2
|
||
|
|
#define STM32_ADC_ADC2_DMA_PRIORITY 2
|
||
|
|
#define STM32_ADC_ADC3_DMA_PRIORITY 2
|
||
|
|
#define STM32_ADC_IRQ_PRIORITY 6
|
||
|
|
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6
|
||
|
|
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6
|
||
|
|
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6
|
||
|
|
|
||
|
|
/*
|
||
|
|
* CAN driver system settings.
|
||
|
|
*/
|
||
|
|
#define STM32_CAN_USE_CAN1 FALSE
|
||
|
|
#define STM32_CAN_USE_CAN2 FALSE
|
||
|
|
#define STM32_CAN_CAN1_IRQ_PRIORITY 11
|
||
|
|
#define STM32_CAN_CAN2_IRQ_PRIORITY 11
|
||
|
|
|
||
|
|
/*
|
||
|
|
* EXT driver system settings.
|
||
|
|
*/
|
||
|
|
#define STM32_EXT_EXTI0_IRQ_PRIORITY 6
|
||
|
|
#define STM32_EXT_EXTI1_IRQ_PRIORITY 6
|
||
|
|
#define STM32_EXT_EXTI2_IRQ_PRIORITY 6
|
||
|
|
#define STM32_EXT_EXTI3_IRQ_PRIORITY 6
|
||
|
|
#define STM32_EXT_EXTI4_IRQ_PRIORITY 6
|
||
|
|
#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6
|
||
|
|
#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6
|
||
|
|
#define STM32_EXT_EXTI16_IRQ_PRIORITY 6
|
||
|
|
#define STM32_EXT_EXTI17_IRQ_PRIORITY 15
|
||
|
|
#define STM32_EXT_EXTI18_IRQ_PRIORITY 6
|
||
|
|
#define STM32_EXT_EXTI19_IRQ_PRIORITY 6
|
||
|
|
#define STM32_EXT_EXTI20_IRQ_PRIORITY 6
|
||
|
|
#define STM32_EXT_EXTI21_IRQ_PRIORITY 15
|
||
|
|
#define STM32_EXT_EXTI22_IRQ_PRIORITY 15
|
||
|
|
|
||
|
|
/*
|
||
|
|
* GPT driver system settings.
|
||
|
|
*/
|
||
|
|
#define STM32_GPT_USE_TIM1 FALSE
|
||
|
|
#define STM32_GPT_USE_TIM2 FALSE
|
||
|
|
#define STM32_GPT_USE_TIM3 FALSE
|
||
|
|
#define STM32_GPT_USE_TIM4 FALSE
|
||
|
|
#define STM32_GPT_USE_TIM5 FALSE
|
||
|
|
#define STM32_GPT_USE_TIM6 FALSE
|
||
|
|
#define STM32_GPT_USE_TIM7 FALSE
|
||
|
|
#define STM32_GPT_USE_TIM8 FALSE
|
||
|
|
#define STM32_GPT_USE_TIM9 FALSE
|
||
|
|
#define STM32_GPT_USE_TIM11 FALSE
|
||
|
|
#define STM32_GPT_USE_TIM12 FALSE
|
||
|
|
#define STM32_GPT_USE_TIM14 FALSE
|
||
|
|
#define STM32_GPT_TIM1_IRQ_PRIORITY 7
|
||
|
|
#define STM32_GPT_TIM2_IRQ_PRIORITY 7
|
||
|
|
#define STM32_GPT_TIM3_IRQ_PRIORITY 7
|
||
|
|
#define STM32_GPT_TIM4_IRQ_PRIORITY 7
|
||
|
|
#define STM32_GPT_TIM5_IRQ_PRIORITY 7
|
||
|
|
#define STM32_GPT_TIM6_IRQ_PRIORITY 7
|
||
|
|
#define STM32_GPT_TIM7_IRQ_PRIORITY 7
|
||
|
|
#define STM32_GPT_TIM8_IRQ_PRIORITY 7
|
||
|
|
#define STM32_GPT_TIM9_IRQ_PRIORITY 7
|
||
|
|
#define STM32_GPT_TIM11_IRQ_PRIORITY 7
|
||
|
|
#define STM32_GPT_TIM12_IRQ_PRIORITY 7
|
||
|
|
#define STM32_GPT_TIM14_IRQ_PRIORITY 7
|
||
|
|
|
||
|
|
/*
|
||
|
|
* I2C driver system settings.
|
||
|
|
*/
|
||
|
|
#define STM32_I2C_USE_I2C1 FALSE
|
||
|
|
#define STM32_I2C_USE_I2C2 FALSE
|
||
|
|
#define STM32_I2C_USE_I2C3 FALSE
|
||
|
|
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
|
||
|
|
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
||
|
|
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||
|
|
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
|
||
|
|
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||
|
|
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||
|
|
#define STM32_I2C_I2C1_IRQ_PRIORITY 5
|
||
|
|
#define STM32_I2C_I2C2_IRQ_PRIORITY 5
|
||
|
|
#define STM32_I2C_I2C3_IRQ_PRIORITY 5
|
||
|
|
#define STM32_I2C_I2C1_DMA_PRIORITY 3
|
||
|
|
#define STM32_I2C_I2C2_DMA_PRIORITY 3
|
||
|
|
#define STM32_I2C_I2C3_DMA_PRIORITY 3
|
||
|
|
#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt()
|
||
|
|
#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt()
|
||
|
|
#define STM32_I2C_I2C3_DMA_ERROR_HOOK() chSysHalt()
|
||
|
|
|
||
|
|
/*
|
||
|
|
* ICU driver system settings.
|
||
|
|
*/
|
||
|
|
#define STM32_ICU_USE_TIM1 FALSE
|
||
|
|
#define STM32_ICU_USE_TIM2 FALSE
|
||
|
|
#define STM32_ICU_USE_TIM3 FALSE
|
||
|
|
#define STM32_ICU_USE_TIM4 FALSE
|
||
|
|
#define STM32_ICU_USE_TIM5 FALSE
|
||
|
|
#define STM32_ICU_USE_TIM8 FALSE
|
||
|
|
#define STM32_ICU_USE_TIM9 FALSE
|
||
|
|
#define STM32_ICU_TIM1_IRQ_PRIORITY 7
|
||
|
|
#define STM32_ICU_TIM2_IRQ_PRIORITY 7
|
||
|
|
#define STM32_ICU_TIM3_IRQ_PRIORITY 7
|
||
|
|
#define STM32_ICU_TIM4_IRQ_PRIORITY 7
|
||
|
|
#define STM32_ICU_TIM5_IRQ_PRIORITY 7
|
||
|
|
#define STM32_ICU_TIM8_IRQ_PRIORITY 7
|
||
|
|
#define STM32_ICU_TIM9_IRQ_PRIORITY 7
|
||
|
|
|
||
|
|
/*
|
||
|
|
* MAC driver system settings.
|
||
|
|
*/
|
||
|
|
#define STM32_MAC_TRANSMIT_BUFFERS 2
|
||
|
|
#define STM32_MAC_RECEIVE_BUFFERS 4
|
||
|
|
#define STM32_MAC_BUFFERS_SIZE 1522
|
||
|
|
#define STM32_MAC_PHY_TIMEOUT 100
|
||
|
|
#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE
|
||
|
|
#define STM32_MAC_ETH1_IRQ_PRIORITY 13
|
||
|
|
#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0
|
||
|
|
|
||
|
|
/*
|
||
|
|
* MAC driver system settings.
|
||
|
|
*/
|
||
|
|
#define STM32_MAC_TRANSMIT_BUFFERS 2
|
||
|
|
#define STM32_MAC_RECEIVE_BUFFERS 4
|
||
|
|
#define STM32_MAC_BUFFERS_SIZE 1522
|
||
|
|
#define STM32_MAC_PHY_TIMEOUT 100
|
||
|
|
#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE
|
||
|
|
#define STM32_MAC_ETH1_IRQ_PRIORITY 13
|
||
|
|
#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0
|
||
|
|
|
||
|
|
/*
|
||
|
|
* PWM driver system settings.
|
||
|
|
*/
|
||
|
|
#define STM32_PWM_USE_ADVANCED FALSE
|
||
|
|
#define STM32_PWM_USE_TIM1 FALSE
|
||
|
|
#define STM32_PWM_USE_TIM2 FALSE
|
||
|
|
#define STM32_PWM_USE_TIM3 FALSE
|
||
|
|
#define STM32_PWM_USE_TIM4 FALSE
|
||
|
|
#define STM32_PWM_USE_TIM5 FALSE
|
||
|
|
#define STM32_PWM_USE_TIM8 FALSE
|
||
|
|
#define STM32_PWM_USE_TIM9 FALSE
|
||
|
|
#define STM32_PWM_TIM1_IRQ_PRIORITY 7
|
||
|
|
#define STM32_PWM_TIM2_IRQ_PRIORITY 7
|
||
|
|
#define STM32_PWM_TIM3_IRQ_PRIORITY 7
|
||
|
|
#define STM32_PWM_TIM4_IRQ_PRIORITY 7
|
||
|
|
#define STM32_PWM_TIM5_IRQ_PRIORITY 7
|
||
|
|
#define STM32_PWM_TIM8_IRQ_PRIORITY 7
|
||
|
|
#define STM32_PWM_TIM9_IRQ_PRIORITY 7
|
||
|
|
|
||
|
|
/*
|
||
|
|
* SERIAL driver system settings.
|
||
|
|
*/
|
||
|
|
#define STM32_SERIAL_USE_USART1 FALSE
|
||
|
|
#define STM32_SERIAL_USE_USART2 FALSE
|
||
|
|
#define STM32_SERIAL_USE_USART3 FALSE
|
||
|
|
#define STM32_SERIAL_USE_UART4 FALSE
|
||
|
|
#define STM32_SERIAL_USE_UART5 FALSE
|
||
|
|
#define STM32_SERIAL_USE_USART6 TRUE
|
||
|
|
#define STM32_SERIAL_USART1_PRIORITY 12
|
||
|
|
#define STM32_SERIAL_USART2_PRIORITY 12
|
||
|
|
#define STM32_SERIAL_USART3_PRIORITY 12
|
||
|
|
#define STM32_SERIAL_UART4_PRIORITY 12
|
||
|
|
#define STM32_SERIAL_UART5_PRIORITY 12
|
||
|
|
#define STM32_SERIAL_USART6_PRIORITY 12
|
||
|
|
|
||
|
|
/*
|
||
|
|
* SPI driver system settings.
|
||
|
|
*/
|
||
|
|
#define STM32_SPI_USE_SPI1 FALSE
|
||
|
|
#define STM32_SPI_USE_SPI2 FALSE
|
||
|
|
#define STM32_SPI_USE_SPI3 FALSE
|
||
|
|
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
|
||
|
|
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
|
||
|
|
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||
|
|
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||
|
|
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
|
||
|
|
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
|
||
|
|
#define STM32_SPI_SPI1_DMA_PRIORITY 1
|
||
|
|
#define STM32_SPI_SPI2_DMA_PRIORITY 1
|
||
|
|
#define STM32_SPI_SPI3_DMA_PRIORITY 1
|
||
|
|
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
|
||
|
|
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
|
||
|
|
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
|
||
|
|
#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt()
|
||
|
|
|
||
|
|
/*
|
||
|
|
* UART driver system settings.
|
||
|
|
*/
|
||
|
|
#define STM32_UART_USE_USART1 FALSE
|
||
|
|
#define STM32_UART_USE_USART2 FALSE
|
||
|
|
#define STM32_UART_USE_USART3 FALSE
|
||
|
|
#define STM32_UART_USE_UART4 FALSE
|
||
|
|
#define STM32_UART_USE_UART5 FALSE
|
||
|
|
#define STM32_UART_USE_USART6 FALSE
|
||
|
|
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
||
|
|
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||
|
|
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||
|
|
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
||
|
|
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
||
|
|
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||
|
|
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||
|
|
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||
|
|
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
|
||
|
|
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
|
||
|
|
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
||
|
|
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
|
||
|
|
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
||
|
|
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
||
|
|
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
||
|
|
#define STM32_UART_UART4_IRQ_PRIORITY 12
|
||
|
|
#define STM32_UART_UART5_IRQ_PRIORITY 12
|
||
|
|
#define STM32_UART_USART6_IRQ_PRIORITY 12
|
||
|
|
#define STM32_UART_USART1_DMA_PRIORITY 0
|
||
|
|
#define STM32_UART_USART2_DMA_PRIORITY 0
|
||
|
|
#define STM32_UART_USART3_DMA_PRIORITY 0
|
||
|
|
#define STM32_UART_UART4_DMA_PRIORITY 0
|
||
|
|
#define STM32_UART_UART5_DMA_PRIORITY 0
|
||
|
|
#define STM32_UART_USART6_DMA_PRIORITY 0
|
||
|
|
#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
|
||
|
|
|
||
|
|
/*
|
||
|
|
* USB driver system settings.
|
||
|
|
*/
|
||
|
|
#define STM32_USB_USE_OTG1 TRUE
|
||
|
|
#define STM32_USB_USE_OTG2 TRUE
|
||
|
|
#define STM32_USB_OTG1_IRQ_PRIORITY 14
|
||
|
|
#define STM32_USB_OTG2_IRQ_PRIORITY 14
|
||
|
|
#define STM32_USB_OTG1_RX_FIFO_SIZE 512
|
||
|
|
#define STM32_USB_OTG2_RX_FIFO_SIZE 1024
|
||
|
|
#define STM32_USB_OTG_THREAD_PRIO LOWPRIO
|
||
|
|
#define STM32_USB_OTG_THREAD_STACK_SIZE 128
|
||
|
|
#define STM32_USB_OTGFIFO_FILL_BASEPRI 0
|