2016-08-06 08:49:45 +02:00
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/*
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* Copyright (C) 2014 Jared Boone, ShareBrained Technology, Inc.
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* Copyright (C) 2016 Furrtek
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*
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* This file is part of PortaPack.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 51 Franklin Street,
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* Boston, MA 02110-1301, USA.
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*/
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2015-07-08 08:39:24 -07:00
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#include "ui_widget.hpp"
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#include "ui_painter.hpp"
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2016-02-05 17:40:14 +01:00
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#include "portapack.hpp"
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2015-07-08 08:39:24 -07:00
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#include <cstdint>
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#include <cstddef>
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#include <algorithm>
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2016-01-31 09:34:24 +01:00
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#include "string_format.hpp"
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2016-02-05 17:40:14 +01:00
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using namespace portapack;
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2015-07-08 08:39:24 -07:00
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namespace ui {
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2015-08-14 21:17:23 -07:00
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static bool ui_dirty = true;
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void dirty_set() {
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2023-05-19 08:16:05 +12:00
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ui_dirty = true;
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2015-08-14 21:17:23 -07:00
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}
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void dirty_clear() {
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2023-05-19 08:16:05 +12:00
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ui_dirty = false;
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2015-08-14 21:17:23 -07:00
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}
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bool is_dirty() {
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2023-05-19 08:16:05 +12:00
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return ui_dirty;
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2015-08-14 21:17:23 -07:00
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}
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2015-07-08 08:39:24 -07:00
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/* Widget ****************************************************************/
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2023-05-19 08:16:05 +12:00
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const std::vector<Widget*> Widget::no_children{};
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2016-02-07 11:24:25 -08:00
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2015-07-08 08:39:24 -07:00
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Point Widget::screen_pos() {
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2023-05-19 08:16:05 +12:00
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return screen_rect().location();
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2015-07-08 08:39:24 -07:00
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}
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Size Widget::size() const {
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2023-05-19 08:16:05 +12:00
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return _parent_rect.size();
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2015-07-08 08:39:24 -07:00
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}
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2016-05-09 21:05:11 +02:00
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Rect Widget::screen_rect() const {
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2023-05-19 08:16:05 +12:00
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return parent() ? (parent_rect() + parent()->screen_pos()) : parent_rect();
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2016-12-06 09:28:48 -08:00
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}
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Rect Widget::parent_rect() const {
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2023-05-19 08:16:05 +12:00
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return _parent_rect;
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2015-07-08 08:39:24 -07:00
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}
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void Widget::set_parent_rect(const Rect new_parent_rect) {
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2023-05-19 08:16:05 +12:00
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_parent_rect = new_parent_rect;
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set_dirty();
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2015-07-08 08:39:24 -07:00
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}
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Widget* Widget::parent() const {
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2023-05-19 08:16:05 +12:00
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return parent_;
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2015-07-08 08:39:24 -07:00
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}
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void Widget::set_parent(Widget* const widget) {
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2023-05-19 08:16:05 +12:00
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if (widget == parent_) {
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return;
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}
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2016-09-05 15:04:28 -07:00
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2023-05-19 08:16:05 +12:00
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if (parent_ && !widget) {
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// We have a parent, but are losing it. Update visible status.
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dirty_overlapping_children_in_rect(screen_rect());
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visible(false);
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}
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2015-07-08 08:39:24 -07:00
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2023-05-19 08:16:05 +12:00
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parent_ = widget;
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2016-09-05 15:04:28 -07:00
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2023-05-19 08:16:05 +12:00
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set_dirty();
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2015-07-08 08:39:24 -07:00
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}
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void Widget::set_dirty() {
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2023-05-19 08:16:05 +12:00
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flags.dirty = true;
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dirty_set();
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2015-07-08 08:39:24 -07:00
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}
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bool Widget::dirty() const {
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2023-05-19 08:16:05 +12:00
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return flags.dirty;
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2015-07-08 08:39:24 -07:00
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}
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void Widget::set_clean() {
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2023-05-19 08:16:05 +12:00
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flags.dirty = false;
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2015-07-08 08:39:24 -07:00
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}
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void Widget::hidden(bool hide) {
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2023-05-19 08:16:05 +12:00
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if (hide != flags.hidden) {
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flags.hidden = hide;
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// If parent is hidden, either of these is a no-op.
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if (hide) {
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// TODO: Instead of dirtying parent entirely, dirty only children
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// that overlap with this widget.
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// parent()->dirty_overlapping_children_in_rect(parent_rect());
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/* TODO: Notify self and all non-hidden children that they're
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* now effectively hidden?
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*/
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} else {
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set_dirty();
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/* TODO: Notify self and all non-hidden children that they're
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* now effectively shown?
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*/
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}
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}
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2015-07-08 08:39:24 -07:00
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}
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void Widget::focus() {
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2023-05-19 08:16:05 +12:00
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context().focus_manager().set_focus_widget(this);
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2015-07-08 08:39:24 -07:00
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}
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void Widget::on_focus() {
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2023-05-19 08:16:05 +12:00
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// set_dirty();
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2015-07-08 08:39:24 -07:00
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}
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void Widget::blur() {
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2023-05-19 08:16:05 +12:00
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context().focus_manager().set_focus_widget(nullptr);
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2015-07-08 08:39:24 -07:00
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}
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void Widget::on_blur() {
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2023-05-19 08:16:05 +12:00
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// set_dirty();
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2015-07-08 08:39:24 -07:00
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}
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bool Widget::focusable() const {
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2023-05-19 08:16:05 +12:00
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return flags.focusable;
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2015-07-08 08:39:24 -07:00
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}
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2016-02-07 10:32:38 -08:00
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void Widget::set_focusable(const bool value) {
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2023-05-19 08:16:05 +12:00
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flags.focusable = value;
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2015-07-08 08:39:24 -07:00
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}
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bool Widget::has_focus() {
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2023-05-19 08:16:05 +12:00
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return (context().focus_manager().focus_widget() == this);
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2015-07-08 08:39:24 -07:00
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}
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bool Widget::on_key(const KeyEvent event) {
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2023-05-19 08:16:05 +12:00
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(void)event;
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return false;
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2015-07-08 08:39:24 -07:00
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}
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bool Widget::on_encoder(const EncoderEvent event) {
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2023-05-19 08:16:05 +12:00
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(void)event;
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return false;
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2015-07-08 08:39:24 -07:00
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}
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bool Widget::on_touch(const TouchEvent event) {
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2023-05-19 08:16:05 +12:00
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(void)event;
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return false;
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2015-07-08 08:39:24 -07:00
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}
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2016-02-07 11:24:25 -08:00
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const std::vector<Widget*>& Widget::children() const {
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2023-05-19 08:16:05 +12:00
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return no_children;
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2015-07-08 08:39:24 -07:00
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}
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Context& Widget::context() const {
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2023-06-28 12:50:11 -07:00
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chDbgAssert(parent_, "parent_ is null",
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"Check that parent isn't null before deref.");
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2023-05-19 08:16:05 +12:00
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return parent()->context();
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2015-07-08 08:39:24 -07:00
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}
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void Widget::set_style(const Style* new_style) {
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2023-05-19 08:16:05 +12:00
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if (new_style != style_) {
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style_ = new_style;
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set_dirty();
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}
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2015-07-08 08:39:24 -07:00
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}
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const Style& Widget::style() const {
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2023-05-19 08:16:05 +12:00
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return style_ ? *style_ : parent()->style();
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2015-07-08 08:39:24 -07:00
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}
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void Widget::visible(bool v) {
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2023-05-19 08:16:05 +12:00
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if (v != flags.visible) {
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flags.visible = v;
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/* TODO: This on_show/on_hide implementation seems inelegant.
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* But I need *some* way to take/configure resources when
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* a widget becomes visible, and reverse the process when the
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* widget becomes invisible, whether the widget (or parent) is
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* hidden, or the widget (or parent) is removed from the tree.
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*/
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if (v) {
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on_show();
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} else {
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on_hide();
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// Set all children invisible too.
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for (const auto child : children()) {
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child->visible(false);
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}
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}
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}
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2015-07-08 08:39:24 -07:00
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}
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2016-02-07 10:32:38 -08:00
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bool Widget::highlighted() const {
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2023-05-19 08:16:05 +12:00
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return flags.highlighted;
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2016-02-07 10:32:38 -08:00
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}
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void Widget::set_highlighted(const bool value) {
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2023-05-19 08:16:05 +12:00
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flags.highlighted = value;
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2016-02-07 10:32:38 -08:00
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}
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2016-01-31 09:34:24 +01:00
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void Widget::dirty_overlapping_children_in_rect(const Rect& child_rect) {
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2023-05-19 08:16:05 +12:00
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for (auto child : children()) {
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if (!child_rect.intersect(child->parent_rect()).is_empty()) {
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child->set_dirty();
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}
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}
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2016-01-31 09:34:24 +01:00
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}
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2015-07-08 08:39:24 -07:00
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/* View ******************************************************************/
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void View::paint(Painter& painter) {
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2023-05-19 08:16:05 +12:00
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painter.fill_rectangle(
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screen_rect(),
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style().background);
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2015-07-08 08:39:24 -07:00
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}
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void View::add_child(Widget* const widget) {
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2023-05-19 08:16:05 +12:00
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if (widget) {
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if (widget->parent() == nullptr) {
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widget->set_parent(this);
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children_.push_back(widget);
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}
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}
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2015-07-08 08:39:24 -07:00
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}
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2016-09-05 14:53:04 -07:00
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void View::add_children(const std::initializer_list<Widget*> children) {
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2023-05-19 08:16:05 +12:00
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children_.insert(std::end(children_), children);
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for (auto child : children) {
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child->set_parent(this);
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}
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2015-07-08 08:39:24 -07:00
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}
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void View::remove_child(Widget* const widget) {
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2023-05-19 08:16:05 +12:00
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if (widget) {
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children_.erase(std::remove(children_.begin(), children_.end(), widget), children_.end());
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widget->set_parent(nullptr);
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}
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2015-07-08 08:39:24 -07:00
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}
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2016-12-09 18:21:47 +01:00
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void View::remove_children(const std::vector<Widget*>& children) {
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2023-05-19 08:16:05 +12:00
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for (auto child : children) {
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remove_child(child);
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}
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2016-12-09 18:21:47 +01:00
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}
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2016-02-07 11:24:25 -08:00
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const std::vector<Widget*>& View::children() const {
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2023-05-19 08:16:05 +12:00
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return children_;
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2015-07-08 08:39:24 -07:00
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}
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2016-01-31 09:34:24 +01:00
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std::string View::title() const {
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2023-05-19 08:16:05 +12:00
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return "";
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2016-01-31 09:34:24 +01:00
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};
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2017-08-16 10:02:57 +01:00
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/* OptionTabView *********************************************************/
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OptionTabView::OptionTabView(Rect parent_rect) {
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2023-05-19 08:16:05 +12:00
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set_parent_rect(parent_rect);
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add_child(&check_enable);
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hidden(true);
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check_enable.on_select = [this](Checkbox&, bool value) {
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enabled = value;
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};
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2017-08-16 10:02:57 +01:00
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}
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void OptionTabView::set_enabled(bool value) {
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2023-05-19 08:16:05 +12:00
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check_enable.set_value(value);
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2017-08-16 10:02:57 +01:00
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}
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bool OptionTabView::is_enabled() {
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2023-05-19 08:16:05 +12:00
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return check_enable.value();
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2017-08-16 10:02:57 +01:00
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}
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void OptionTabView::set_type(std::string type) {
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2023-05-19 08:16:05 +12:00
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check_enable.set_text("Transmit " + type);
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2017-08-16 10:02:57 +01:00
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}
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void OptionTabView::focus() {
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2023-05-19 08:16:05 +12:00
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check_enable.focus();
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2017-08-16 10:02:57 +01:00
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}
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2015-07-08 08:39:24 -07:00
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/* Rectangle *************************************************************/
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2016-05-25 11:32:06 -07:00
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Rectangle::Rectangle(
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2023-05-19 08:16:05 +12:00
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Color c)
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: Widget{},
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color{c} {
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2016-05-25 11:32:06 -07:00
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}
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2016-01-31 09:34:24 +01:00
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Rectangle::Rectangle(
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2023-05-19 08:16:05 +12:00
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Rect parent_rect,
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Color c)
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: Widget{parent_rect},
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color{c} {
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2016-01-31 09:34:24 +01:00
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}
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2015-07-08 08:39:24 -07:00
|
|
|
void Rectangle::set_color(const Color c) {
|
2023-05-19 08:16:05 +12:00
|
|
|
color = c;
|
|
|
|
set_dirty();
|
2015-07-08 08:39:24 -07:00
|
|
|
}
|
|
|
|
|
2016-07-29 04:52:51 +02:00
|
|
|
void Rectangle::set_outline(const bool outline) {
|
2023-05-19 08:16:05 +12:00
|
|
|
_outline = outline;
|
|
|
|
set_dirty();
|
2016-07-29 04:52:51 +02:00
|
|
|
}
|
|
|
|
|
2015-07-08 08:39:24 -07:00
|
|
|
void Rectangle::paint(Painter& painter) {
|
2023-05-19 08:16:05 +12:00
|
|
|
if (!_outline) {
|
|
|
|
painter.fill_rectangle(
|
|
|
|
screen_rect(),
|
|
|
|
color);
|
|
|
|
} else {
|
|
|
|
painter.draw_rectangle(
|
|
|
|
screen_rect(),
|
|
|
|
color);
|
|
|
|
}
|
2015-07-08 08:39:24 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Text ******************************************************************/
|
|
|
|
|
2016-01-31 09:34:24 +01:00
|
|
|
Text::Text(
|
2023-05-19 08:16:05 +12:00
|
|
|
Rect parent_rect,
|
|
|
|
std::string text)
|
|
|
|
: Widget{parent_rect},
|
|
|
|
text{text} {
|
2016-01-31 09:34:24 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
Text::Text(
|
2023-05-19 08:16:05 +12:00
|
|
|
Rect parent_rect)
|
|
|
|
: Text{parent_rect, {}} {
|
2016-01-31 09:34:24 +01:00
|
|
|
}
|
|
|
|
|
2015-07-08 08:39:24 -07:00
|
|
|
void Text::set(const std::string value) {
|
2023-05-19 08:16:05 +12:00
|
|
|
text = value;
|
|
|
|
set_dirty();
|
2015-07-08 08:39:24 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
void Text::paint(Painter& painter) {
|
2023-05-19 08:16:05 +12:00
|
|
|
const auto rect = screen_rect();
|
|
|
|
const auto s = style();
|
2016-01-31 09:34:24 +01:00
|
|
|
|
2023-05-19 08:16:05 +12:00
|
|
|
painter.fill_rectangle(rect, s.background);
|
2016-01-31 08:37:08 +01:00
|
|
|
|
2023-05-19 08:16:05 +12:00
|
|
|
painter.draw_string(
|
|
|
|
rect.location(),
|
|
|
|
s,
|
|
|
|
text);
|
2015-07-08 08:39:24 -07:00
|
|
|
}
|
|
|
|
|
2017-02-12 04:05:21 +00:00
|
|
|
/* Labels ****************************************************************/
|
|
|
|
|
|
|
|
Labels::Labels(
|
2023-05-19 08:16:05 +12:00
|
|
|
std::initializer_list<Label> labels)
|
|
|
|
: labels_{labels} {
|
2017-02-12 04:05:21 +00:00
|
|
|
}
|
|
|
|
|
2017-02-12 07:23:31 +00:00
|
|
|
void Labels::set_labels(std::initializer_list<Label> labels) {
|
2023-05-19 08:16:05 +12:00
|
|
|
labels_ = labels;
|
|
|
|
set_dirty();
|
2017-02-12 04:05:21 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void Labels::paint(Painter& painter) {
|
2023-05-19 08:16:05 +12:00
|
|
|
for (auto& label : labels_) {
|
|
|
|
painter.draw_string(
|
|
|
|
label.pos + screen_pos(),
|
|
|
|
style().font,
|
|
|
|
label.color,
|
|
|
|
style().background,
|
|
|
|
label.text);
|
|
|
|
}
|
2017-02-12 04:05:21 +00:00
|
|
|
}
|
|
|
|
|
2017-09-20 07:50:59 +01:00
|
|
|
/* LiveDateTime **********************************************************/
|
|
|
|
|
|
|
|
void LiveDateTime::on_tick_second() {
|
2023-05-19 08:16:05 +12:00
|
|
|
rtcGetTime(&RTCD1, &datetime);
|
|
|
|
text = "";
|
|
|
|
if (!hide_clock) {
|
|
|
|
if (date_enabled) {
|
|
|
|
text = to_string_dec_uint(datetime.year(), 4, '0') + "-" +
|
|
|
|
to_string_dec_uint(datetime.month(), 2, '0') + "-" +
|
|
|
|
to_string_dec_uint(datetime.day(), 2, '0') + " ";
|
|
|
|
} else {
|
|
|
|
text = " ";
|
|
|
|
}
|
|
|
|
|
|
|
|
text = text + to_string_dec_uint(datetime.hour(), 2, '0') + ":" + to_string_dec_uint(datetime.minute(), 2, '0');
|
|
|
|
|
|
|
|
if (seconds_enabled) {
|
|
|
|
text += ":";
|
|
|
|
|
|
|
|
if (init_delay == 0)
|
|
|
|
text += to_string_dec_uint(datetime.second(), 2, '0');
|
|
|
|
else {
|
|
|
|
// Placeholder while the seconds are not updated
|
|
|
|
text += "XX";
|
|
|
|
init_delay--;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
set_dirty();
|
2017-09-20 07:50:59 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
LiveDateTime::LiveDateTime(
|
2023-05-19 08:16:05 +12:00
|
|
|
Rect parent_rect)
|
|
|
|
: Widget{parent_rect} {
|
|
|
|
signal_token_tick_second = rtc_time::signal_tick_second += [this]() {
|
|
|
|
this->on_tick_second();
|
|
|
|
};
|
2017-09-20 07:50:59 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
LiveDateTime::~LiveDateTime() {
|
2023-05-19 08:16:05 +12:00
|
|
|
rtc_time::signal_tick_second -= signal_token_tick_second;
|
2017-09-20 07:50:59 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
void LiveDateTime::paint(Painter& painter) {
|
2023-05-19 08:16:05 +12:00
|
|
|
const auto rect = screen_rect();
|
|
|
|
const auto s = style();
|
2017-09-20 07:50:59 +01:00
|
|
|
|
2023-05-19 08:16:05 +12:00
|
|
|
on_tick_second();
|
2017-09-20 07:50:59 +01:00
|
|
|
|
2023-05-19 08:16:05 +12:00
|
|
|
painter.fill_rectangle(rect, s.background);
|
|
|
|
|
|
|
|
painter.draw_string(
|
|
|
|
rect.location(),
|
|
|
|
s,
|
|
|
|
text);
|
2017-09-20 07:50:59 +01:00
|
|
|
}
|
2023-05-19 08:16:05 +12:00
|
|
|
void LiveDateTime::set_hide_clock(bool new_value) {
|
|
|
|
this->hide_clock = new_value;
|
2021-05-16 11:41:09 +02:00
|
|
|
}
|
2017-09-20 07:50:59 +01:00
|
|
|
|
2023-05-19 08:16:05 +12:00
|
|
|
void LiveDateTime::set_date_enabled(bool new_value) {
|
|
|
|
this->date_enabled = new_value;
|
2020-08-08 04:24:57 -04:00
|
|
|
}
|
|
|
|
|
|
|
|
void LiveDateTime::set_seconds_enabled(bool new_value) {
|
2023-05-19 08:16:05 +12:00
|
|
|
this->seconds_enabled = new_value;
|
2020-08-08 04:24:57 -04:00
|
|
|
}
|
|
|
|
|
2016-05-11 23:57:22 +02:00
|
|
|
/* BigFrequency **********************************************************/
|
|
|
|
|
|
|
|
BigFrequency::BigFrequency(
|
2023-05-19 08:16:05 +12:00
|
|
|
Rect parent_rect,
|
|
|
|
rf::Frequency frequency)
|
|
|
|
: Widget{parent_rect},
|
|
|
|
_frequency{frequency} {
|
2016-05-11 23:57:22 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
void BigFrequency::set(const rf::Frequency frequency) {
|
2023-05-19 08:16:05 +12:00
|
|
|
_frequency = frequency;
|
|
|
|
set_dirty();
|
2016-05-11 23:57:22 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
void BigFrequency::paint(Painter& painter) {
|
2023-05-19 08:16:05 +12:00
|
|
|
uint32_t i, digit_def;
|
|
|
|
std::array<char, 7> digits;
|
|
|
|
char digit;
|
|
|
|
Point digit_pos;
|
|
|
|
ui::Color segment_color;
|
|
|
|
|
|
|
|
const auto rect = screen_rect();
|
|
|
|
|
|
|
|
// Erase
|
|
|
|
painter.fill_rectangle({{0, rect.location().y()}, {240, 52}}, ui::Color::black());
|
|
|
|
|
|
|
|
// Prepare digits
|
|
|
|
if (!_frequency) {
|
|
|
|
digits.fill(10); // ----.---
|
|
|
|
digit_pos = {0, rect.location().y()};
|
|
|
|
} else {
|
|
|
|
_frequency /= 1000; // GMMM.KKK(uuu)
|
|
|
|
|
|
|
|
for (i = 0; i < 7; i++) {
|
|
|
|
digits[6 - i] = _frequency % 10;
|
|
|
|
_frequency /= 10;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Remove leading zeros
|
|
|
|
for (i = 0; i < 3; i++) {
|
|
|
|
if (!digits[i])
|
|
|
|
digits[i] = 16; // "Don't draw" code
|
|
|
|
else
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
digit_pos = {(Coord)(240 - ((7 * digit_width) + 8) - (i * digit_width)) / 2, rect.location().y()};
|
|
|
|
}
|
|
|
|
|
|
|
|
segment_color = style().foreground;
|
|
|
|
|
|
|
|
// Draw
|
|
|
|
for (i = 0; i < 7; i++) {
|
|
|
|
digit = digits[i];
|
|
|
|
|
|
|
|
if (digit < 16) {
|
|
|
|
digit_def = segment_font[(uint8_t)digit];
|
|
|
|
|
|
|
|
for (size_t s = 0; s < 7; s++) {
|
|
|
|
if (digit_def & 1)
|
|
|
|
painter.fill_rectangle({digit_pos + segments[s].location(), segments[s].size()}, segment_color);
|
|
|
|
digit_def >>= 1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (i == 3) {
|
|
|
|
// Dot
|
|
|
|
painter.fill_rectangle({digit_pos + Point(34, 48), {4, 4}}, segment_color);
|
|
|
|
digit_pos += {(digit_width + 8), 0};
|
|
|
|
} else {
|
|
|
|
digit_pos += {digit_width, 0};
|
|
|
|
}
|
|
|
|
}
|
2016-05-11 23:57:22 +02:00
|
|
|
}
|
|
|
|
|
2016-05-09 20:42:20 +02:00
|
|
|
/* ProgressBar ***********************************************************/
|
|
|
|
|
|
|
|
ProgressBar::ProgressBar(
|
2023-05-19 08:16:05 +12:00
|
|
|
Rect parent_rect)
|
|
|
|
: Widget{parent_rect} {
|
2016-05-09 20:42:20 +02:00
|
|
|
}
|
|
|
|
|
2016-08-26 08:11:24 +02:00
|
|
|
void ProgressBar::set_max(const uint32_t max) {
|
2023-05-19 08:16:05 +12:00
|
|
|
if (max == _max) return;
|
|
|
|
|
|
|
|
if (_value > _max)
|
|
|
|
_value = _max;
|
|
|
|
|
|
|
|
_max = max;
|
|
|
|
set_dirty();
|
2016-07-28 00:08:05 +02:00
|
|
|
}
|
|
|
|
|
2016-08-26 08:11:24 +02:00
|
|
|
void ProgressBar::set_value(const uint32_t value) {
|
2023-05-19 08:16:05 +12:00
|
|
|
if (value == _value) return;
|
|
|
|
|
|
|
|
if (value > _max)
|
|
|
|
_value = _max;
|
|
|
|
else
|
|
|
|
_value = value;
|
|
|
|
set_dirty();
|
2016-05-09 20:42:20 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
void ProgressBar::paint(Painter& painter) {
|
2023-05-19 08:16:05 +12:00
|
|
|
int v_scaled;
|
2016-05-09 20:42:20 +02:00
|
|
|
|
2023-05-19 08:16:05 +12:00
|
|
|
const auto sr = screen_rect();
|
|
|
|
const auto s = style();
|
2016-05-09 20:42:20 +02:00
|
|
|
|
2023-05-19 08:16:05 +12:00
|
|
|
v_scaled = (sr.size().width() * _value) / _max;
|
|
|
|
|
|
|
|
painter.fill_rectangle({sr.location(), {v_scaled, sr.size().height()}}, style().foreground);
|
|
|
|
painter.fill_rectangle({{sr.location().x() + v_scaled, sr.location().y()}, {sr.size().width() - v_scaled, sr.size().height()}}, s.background);
|
|
|
|
|
|
|
|
painter.draw_rectangle(sr, s.foreground);
|
2016-05-09 20:42:20 +02:00
|
|
|
}
|
|
|
|
|
2016-07-29 04:52:51 +02:00
|
|
|
/* Console ***************************************************************/
|
|
|
|
|
|
|
|
Console::Console(
|
2023-05-19 08:16:05 +12:00
|
|
|
Rect parent_rect)
|
|
|
|
: Widget{parent_rect} {
|
2016-07-29 04:52:51 +02:00
|
|
|
}
|
|
|
|
|
2020-06-28 20:06:00 +02:00
|
|
|
void Console::clear(bool clear_buffer = false) {
|
2023-05-19 08:16:05 +12:00
|
|
|
if (clear_buffer)
|
|
|
|
buffer.clear();
|
|
|
|
|
|
|
|
if (!hidden() && visible()) {
|
|
|
|
display.fill_rectangle(
|
|
|
|
screen_rect(),
|
|
|
|
Color::black());
|
|
|
|
}
|
|
|
|
|
|
|
|
pos = {0, 0};
|
2016-07-29 04:52:51 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
void Console::write(std::string message) {
|
2023-05-19 08:16:05 +12:00
|
|
|
bool escape = false;
|
|
|
|
|
|
|
|
if (!hidden() && visible()) {
|
|
|
|
const Style& s = style();
|
|
|
|
const Font& font = s.font;
|
|
|
|
const auto rect = screen_rect();
|
|
|
|
ui::Color pen_color = s.foreground;
|
|
|
|
|
|
|
|
for (const auto c : message) {
|
|
|
|
if (escape) {
|
|
|
|
if (c <= 15)
|
|
|
|
pen_color = term_colors[(uint8_t)c];
|
|
|
|
else
|
|
|
|
pen_color = s.foreground;
|
|
|
|
escape = false;
|
|
|
|
} else {
|
|
|
|
if (c == '\n') {
|
|
|
|
crlf();
|
|
|
|
} else if (c == '\x1B') {
|
|
|
|
escape = true;
|
|
|
|
} else {
|
|
|
|
const auto glyph = font.glyph(c);
|
|
|
|
const auto advance = glyph.advance();
|
|
|
|
if ((pos.x() + advance.x()) > rect.width()) {
|
|
|
|
crlf();
|
|
|
|
}
|
|
|
|
const Point pos_glyph{
|
|
|
|
rect.left() + pos.x(),
|
|
|
|
display.scroll_area_y(pos.y())};
|
|
|
|
display.draw_glyph(pos_glyph, glyph, pen_color, s.background);
|
|
|
|
pos += {advance.x(), 0};
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
buffer = message;
|
|
|
|
} else {
|
|
|
|
if (buffer.size() < 256) buffer += message;
|
|
|
|
}
|
2016-07-29 04:52:51 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
void Console::writeln(std::string message) {
|
2023-05-19 08:16:05 +12:00
|
|
|
write(message + "\n");
|
|
|
|
// crlf();
|
2016-07-29 04:52:51 +02:00
|
|
|
}
|
|
|
|
|
2017-01-16 13:36:28 +00:00
|
|
|
void Console::paint(Painter&) {
|
2023-05-19 08:16:05 +12:00
|
|
|
write(buffer);
|
2016-07-29 04:52:51 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
void Console::on_show() {
|
2023-05-19 08:16:05 +12:00
|
|
|
enable_scrolling(true);
|
|
|
|
clear();
|
|
|
|
// visible = true;
|
2016-07-29 04:52:51 +02:00
|
|
|
}
|
|
|
|
|
2021-03-07 16:05:23 -06:00
|
|
|
bool Console::scrolling_enabled = false;
|
|
|
|
|
2023-05-19 08:16:05 +12:00
|
|
|
void Console::enable_scrolling(bool enable) {
|
|
|
|
if (enable) {
|
|
|
|
const auto screen_r = screen_rect();
|
|
|
|
display.scroll_set_area(screen_r.top(), screen_r.bottom());
|
|
|
|
display.scroll_set_position(0);
|
|
|
|
scrolling_enabled = true;
|
|
|
|
} else {
|
|
|
|
display.scroll_disable();
|
|
|
|
scrolling_enabled = false;
|
|
|
|
}
|
2021-03-07 16:05:23 -06:00
|
|
|
}
|
|
|
|
|
2016-07-29 04:52:51 +02:00
|
|
|
void Console::on_hide() {
|
2023-05-19 08:16:05 +12:00
|
|
|
/* TODO: Clear region to eliminate brief flash of content at un-shifted
|
|
|
|
* position?
|
|
|
|
*/
|
|
|
|
enable_scrolling(false);
|
|
|
|
// visible = false;
|
2016-07-29 04:52:51 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
void Console::crlf() {
|
2023-05-19 08:16:05 +12:00
|
|
|
if (hidden() || !visible()) return;
|
2016-07-29 04:52:51 +02:00
|
|
|
|
2023-05-19 08:16:05 +12:00
|
|
|
const Style& s = style();
|
|
|
|
const auto sr = screen_rect();
|
|
|
|
const auto line_height = s.font.line_height();
|
|
|
|
pos = {0, pos.y() + line_height};
|
|
|
|
const int32_t y_excess = pos.y() + line_height - sr.height();
|
|
|
|
if (y_excess > 0) {
|
|
|
|
if (!scrolling_enabled) {
|
|
|
|
enable_scrolling(true);
|
|
|
|
}
|
|
|
|
display.scroll(-y_excess);
|
|
|
|
pos = {pos.x(), pos.y() - y_excess};
|
|
|
|
|
|
|
|
const Rect dirty{sr.left(), display.scroll_area_y(pos.y()), sr.width(), line_height};
|
|
|
|
display.fill_rectangle(dirty, s.background);
|
|
|
|
}
|
2016-07-29 04:52:51 +02:00
|
|
|
}
|
|
|
|
|
2016-02-04 10:27:53 +01:00
|
|
|
/* Checkbox **************************************************************/
|
|
|
|
|
2016-02-05 17:40:14 +01:00
|
|
|
Checkbox::Checkbox(
|
2023-05-19 08:16:05 +12:00
|
|
|
Point parent_pos,
|
|
|
|
size_t length,
|
|
|
|
std::string text,
|
|
|
|
bool small)
|
|
|
|
: Widget{},
|
|
|
|
text_{text},
|
|
|
|
small_{small} {
|
|
|
|
if (!small_)
|
|
|
|
set_parent_rect({parent_pos, {static_cast<ui::Dim>((8 * length) + 24), 24}});
|
|
|
|
else
|
|
|
|
set_parent_rect({parent_pos, {static_cast<ui::Dim>((8 * length) + 16), 16}});
|
|
|
|
|
|
|
|
set_focusable(true);
|
2016-02-05 17:40:14 +01:00
|
|
|
}
|
|
|
|
|
2016-02-04 10:27:53 +01:00
|
|
|
void Checkbox::set_text(const std::string value) {
|
2023-05-19 08:16:05 +12:00
|
|
|
text_ = value;
|
|
|
|
set_dirty();
|
2016-02-04 10:27:53 +01:00
|
|
|
}
|
|
|
|
|
2016-12-09 18:21:47 +01:00
|
|
|
bool Checkbox::set_value(const bool value) {
|
2023-05-19 08:16:05 +12:00
|
|
|
value_ = value;
|
|
|
|
set_dirty();
|
|
|
|
|
|
|
|
if (on_select) {
|
|
|
|
on_select(*this, value_);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
return false;
|
2016-02-04 10:27:53 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
bool Checkbox::value() const {
|
2023-05-19 08:16:05 +12:00
|
|
|
return value_;
|
2016-02-04 10:27:53 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
void Checkbox::paint(Painter& painter) {
|
2023-05-19 08:16:05 +12:00
|
|
|
const auto r = screen_rect();
|
|
|
|
|
|
|
|
const auto paint_style = (has_focus() || highlighted()) ? style().invert() : style();
|
|
|
|
|
|
|
|
const auto x = r.location().x();
|
|
|
|
const auto y = r.location().y();
|
|
|
|
|
|
|
|
const auto label_r = paint_style.font.size_of(text_);
|
|
|
|
|
|
|
|
if (!small_) {
|
|
|
|
painter.draw_rectangle({{r.location()}, {24, 24}}, style().foreground);
|
|
|
|
|
|
|
|
painter.fill_rectangle({x + 1, y + 1, 24 - 2, 24 - 2}, style().background);
|
|
|
|
|
|
|
|
// Highlight
|
|
|
|
painter.draw_rectangle({x + 2, y + 2, 24 - 4, 24 - 4}, paint_style.background);
|
|
|
|
|
|
|
|
if (value_ == true) {
|
|
|
|
// Check
|
|
|
|
portapack::display.draw_line({x + 2, y + 14}, {x + 6, y + 18}, ui::Color::green());
|
|
|
|
portapack::display.draw_line({x + 6, y + 18}, {x + 20, y + 4}, ui::Color::green());
|
|
|
|
} else {
|
|
|
|
// Cross
|
|
|
|
portapack::display.draw_line({x + 1, y + 1}, {x + 24 - 2, y + 24 - 2}, ui::Color::red());
|
|
|
|
portapack::display.draw_line({x + 24 - 2, y + 1}, {x + 1, y + 24 - 2}, ui::Color::red());
|
|
|
|
}
|
|
|
|
|
|
|
|
painter.draw_string(
|
|
|
|
{static_cast<Coord>(x + 24 + 4),
|
|
|
|
static_cast<Coord>(y + (24 - label_r.height()) / 2)},
|
|
|
|
paint_style,
|
|
|
|
text_);
|
|
|
|
} else {
|
|
|
|
painter.draw_rectangle({{r.location()}, {16, 16}}, style().foreground);
|
|
|
|
|
|
|
|
painter.fill_rectangle({x + 1, y + 1, 16 - 2, 16 - 2}, style().background);
|
|
|
|
|
|
|
|
// Highlight
|
|
|
|
painter.draw_rectangle({x + 1, y + 1, 16 - 2, 16 - 2}, paint_style.background);
|
|
|
|
|
|
|
|
if (value_ == true) {
|
|
|
|
// Check
|
|
|
|
portapack::display.draw_line({x + 2, y + 8}, {x + 6, y + 12}, ui::Color::green());
|
|
|
|
portapack::display.draw_line({x + 6, y + 12}, {x + 13, y + 5}, ui::Color::green());
|
|
|
|
} else {
|
|
|
|
// Cross
|
|
|
|
portapack::display.draw_line({x + 1, y + 1}, {x + 16 - 2, y + 16 - 2}, ui::Color::red());
|
|
|
|
portapack::display.draw_line({x + 16 - 2, y + 1}, {x + 1, y + 16 - 2}, ui::Color::red());
|
|
|
|
}
|
|
|
|
|
|
|
|
painter.draw_string(
|
|
|
|
{static_cast<Coord>(x + 16 + 2),
|
|
|
|
static_cast<Coord>(y + (16 - label_r.height()) / 2)},
|
|
|
|
paint_style,
|
|
|
|
text_);
|
|
|
|
}
|
2016-02-04 10:27:53 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
bool Checkbox::on_key(const KeyEvent key) {
|
2023-05-19 08:16:05 +12:00
|
|
|
if (key == KeyEvent::Select)
|
|
|
|
return set_value(not value_);
|
2016-02-04 10:27:53 +01:00
|
|
|
|
2023-05-19 08:16:05 +12:00
|
|
|
return false;
|
2016-02-04 10:27:53 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
bool Checkbox::on_touch(const TouchEvent event) {
|
2023-05-19 08:16:05 +12:00
|
|
|
switch (event.type) {
|
|
|
|
case TouchEvent::Type::Start:
|
|
|
|
set_highlighted(true);
|
|
|
|
set_dirty();
|
|
|
|
return true;
|
|
|
|
|
|
|
|
case TouchEvent::Type::End:
|
|
|
|
set_highlighted(false);
|
|
|
|
value_ = not value_;
|
|
|
|
set_dirty();
|
|
|
|
if (on_select) {
|
|
|
|
on_select(*this, value_);
|
|
|
|
}
|
|
|
|
return true;
|
|
|
|
|
|
|
|
default:
|
|
|
|
return false;
|
|
|
|
}
|
2016-02-04 10:27:53 +01:00
|
|
|
}
|
|
|
|
|
2015-07-08 08:39:24 -07:00
|
|
|
/* Button ****************************************************************/
|
|
|
|
|
2016-02-05 17:40:14 +01:00
|
|
|
Button::Button(
|
2023-05-19 08:16:05 +12:00
|
|
|
Rect parent_rect,
|
|
|
|
std::string text,
|
|
|
|
bool instant_exec)
|
|
|
|
: Widget{parent_rect},
|
|
|
|
text_{text},
|
|
|
|
instant_exec_{instant_exec} {
|
|
|
|
set_focusable(true);
|
2015-07-08 08:39:24 -07:00
|
|
|
}
|
|
|
|
|
2016-01-31 09:34:24 +01:00
|
|
|
void Button::set_text(const std::string value) {
|
2023-05-19 08:16:05 +12:00
|
|
|
text_ = value;
|
|
|
|
set_dirty();
|
2015-09-10 20:36:39 +02:00
|
|
|
}
|
|
|
|
|
2015-07-08 08:39:24 -07:00
|
|
|
std::string Button::text() const {
|
2023-05-19 08:16:05 +12:00
|
|
|
return text_;
|
2015-07-08 08:39:24 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
void Button::paint(Painter& painter) {
|
2023-05-19 08:16:05 +12:00
|
|
|
Color bg, fg;
|
|
|
|
const auto r = screen_rect();
|
|
|
|
|
|
|
|
if (has_focus() || highlighted()) {
|
|
|
|
bg = style().foreground;
|
|
|
|
fg = Color::black();
|
|
|
|
} else {
|
|
|
|
bg = Color::grey();
|
|
|
|
fg = style().foreground;
|
|
|
|
}
|
|
|
|
|
|
|
|
const Style paint_style = {style().font, bg, fg};
|
|
|
|
|
|
|
|
painter.draw_rectangle({r.location(), {r.size().width(), 1}}, Color::light_grey());
|
|
|
|
painter.draw_rectangle({r.location().x(), r.location().y() + r.size().height() - 1, r.size().width(), 1}, Color::dark_grey());
|
|
|
|
painter.draw_rectangle({r.location().x() + r.size().width() - 1, r.location().y(), 1, r.size().height()}, Color::dark_grey());
|
|
|
|
|
|
|
|
painter.fill_rectangle(
|
|
|
|
{r.location().x(), r.location().y() + 1, r.size().width() - 1, r.size().height() - 2},
|
|
|
|
paint_style.background);
|
|
|
|
|
|
|
|
const auto label_r = paint_style.font.size_of(text_);
|
|
|
|
painter.draw_string(
|
|
|
|
{r.location().x() + (r.size().width() - label_r.width()) / 2, r.location().y() + (r.size().height() - label_r.height()) / 2},
|
|
|
|
paint_style,
|
|
|
|
text_);
|
2015-07-08 08:39:24 -07:00
|
|
|
}
|
|
|
|
|
2016-08-26 08:11:24 +02:00
|
|
|
void Button::on_focus() {
|
2023-05-19 08:16:05 +12:00
|
|
|
if (on_highlight)
|
|
|
|
on_highlight(*this);
|
2016-08-26 08:11:24 +02:00
|
|
|
}
|
|
|
|
|
2015-07-08 08:39:24 -07:00
|
|
|
bool Button::on_key(const KeyEvent key) {
|
2023-05-19 08:16:05 +12:00
|
|
|
if (key == KeyEvent::Select) {
|
|
|
|
if (on_select) {
|
|
|
|
on_select(*this);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
if (on_dir) {
|
|
|
|
return on_dir(*this, key);
|
|
|
|
}
|
|
|
|
}
|
2015-07-08 08:39:24 -07:00
|
|
|
|
2023-05-19 08:16:05 +12:00
|
|
|
return false;
|
2015-07-08 08:39:24 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
bool Button::on_touch(const TouchEvent event) {
|
2023-05-19 08:16:05 +12:00
|
|
|
switch (event.type) {
|
|
|
|
case TouchEvent::Type::Start:
|
|
|
|
set_highlighted(true);
|
|
|
|
set_dirty();
|
|
|
|
if (on_touch_press) {
|
|
|
|
on_touch_press(*this);
|
|
|
|
}
|
|
|
|
if (on_select && instant_exec_) {
|
|
|
|
on_select(*this);
|
|
|
|
}
|
|
|
|
return true;
|
|
|
|
|
|
|
|
case TouchEvent::Type::End:
|
|
|
|
set_highlighted(false);
|
|
|
|
set_dirty();
|
|
|
|
if (on_touch_release) {
|
|
|
|
on_touch_release(*this);
|
|
|
|
}
|
|
|
|
if (on_select && !instant_exec_) {
|
|
|
|
on_select(*this);
|
|
|
|
}
|
|
|
|
return true;
|
|
|
|
|
|
|
|
default:
|
|
|
|
return false;
|
|
|
|
}
|
2015-07-08 08:39:24 -07:00
|
|
|
#if 0
|
|
|
|
switch(event.type) {
|
|
|
|
case TouchEvent::Type::Start:
|
|
|
|
flags.highlighted = true;
|
|
|
|
set_dirty();
|
|
|
|
return true;
|
|
|
|
|
|
|
|
case TouchEvent::Type::Move:
|
|
|
|
{
|
|
|
|
const bool new_highlighted = screen_rect().contains(event.point);
|
|
|
|
if( flags.highlighted != new_highlighted ) {
|
|
|
|
flags.highlighted = new_highlighted;
|
|
|
|
set_dirty();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return true;
|
|
|
|
|
|
|
|
case TouchEvent::Type::End:
|
|
|
|
if( flags.highlighted ) {
|
|
|
|
flags.highlighted = false;
|
|
|
|
set_dirty();
|
|
|
|
if( on_select ) {
|
|
|
|
on_select(*this);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return true;
|
|
|
|
|
|
|
|
default:
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2022-09-11 16:09:05 +02:00
|
|
|
/* ButtonWithEncoder ****************************************************************/
|
|
|
|
|
|
|
|
ButtonWithEncoder::ButtonWithEncoder(
|
2023-05-19 08:16:05 +12:00
|
|
|
Rect parent_rect,
|
|
|
|
std::string text,
|
|
|
|
bool instant_exec)
|
|
|
|
: Widget{parent_rect},
|
|
|
|
text_{text},
|
|
|
|
instant_exec_{instant_exec} {
|
|
|
|
set_focusable(true);
|
2022-09-11 16:09:05 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
void ButtonWithEncoder::set_text(const std::string value) {
|
2023-05-19 08:16:05 +12:00
|
|
|
text_ = value;
|
|
|
|
set_dirty();
|
2022-09-11 16:09:05 +02:00
|
|
|
}
|
|
|
|
int32_t ButtonWithEncoder::get_encoder_delta() {
|
2023-05-19 08:16:05 +12:00
|
|
|
return encoder_delta;
|
2022-09-11 16:09:05 +02:00
|
|
|
}
|
2023-05-19 08:16:05 +12:00
|
|
|
void ButtonWithEncoder::set_encoder_delta(const int32_t delta) {
|
|
|
|
encoder_delta = delta;
|
2022-09-11 16:09:05 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
std::string ButtonWithEncoder::text() const {
|
2023-05-19 08:16:05 +12:00
|
|
|
return text_;
|
2022-09-11 16:09:05 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
void ButtonWithEncoder::paint(Painter& painter) {
|
2023-05-19 08:16:05 +12:00
|
|
|
Color bg, fg;
|
|
|
|
const auto r = screen_rect();
|
2022-09-11 16:09:05 +02:00
|
|
|
|
2023-05-19 08:16:05 +12:00
|
|
|
if (has_focus() || highlighted()) {
|
|
|
|
bg = style().foreground;
|
|
|
|
fg = Color::black();
|
|
|
|
} else {
|
|
|
|
bg = Color::grey();
|
|
|
|
fg = style().foreground;
|
|
|
|
}
|
2022-09-11 16:09:05 +02:00
|
|
|
|
2023-05-19 08:16:05 +12:00
|
|
|
const Style paint_style = {style().font, bg, fg};
|
2022-09-11 16:09:05 +02:00
|
|
|
|
2023-05-19 08:16:05 +12:00
|
|
|
painter.draw_rectangle({r.location(), {r.size().width(), 1}}, Color::light_grey());
|
|
|
|
painter.draw_rectangle({r.location().x(), r.location().y() + r.size().height() - 1, r.size().width(), 1}, Color::dark_grey());
|
|
|
|
painter.draw_rectangle({r.location().x() + r.size().width() - 1, r.location().y(), 1, r.size().height()}, Color::dark_grey());
|
2022-09-11 16:09:05 +02:00
|
|
|
|
2023-05-19 08:16:05 +12:00
|
|
|
painter.fill_rectangle(
|
|
|
|
{r.location().x(), r.location().y() + 1, r.size().width() - 1, r.size().height() - 2},
|
|
|
|
paint_style.background);
|
|
|
|
|
|
|
|
const auto label_r = paint_style.font.size_of(text_);
|
|
|
|
painter.draw_string(
|
|
|
|
{r.location().x() + (r.size().width() - label_r.width()) / 2, r.location().y() + (r.size().height() - label_r.height()) / 2},
|
|
|
|
paint_style,
|
|
|
|
text_);
|
2022-09-11 16:09:05 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
void ButtonWithEncoder::on_focus() {
|
2023-05-19 08:16:05 +12:00
|
|
|
if (on_highlight)
|
|
|
|
on_highlight(*this);
|
2022-09-11 16:09:05 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
bool ButtonWithEncoder::on_key(const KeyEvent key) {
|
2023-05-19 08:16:05 +12:00
|
|
|
if (key == KeyEvent::Select) {
|
|
|
|
if (on_select) {
|
|
|
|
on_select(*this);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
if (on_dir) {
|
|
|
|
return on_dir(*this, key);
|
|
|
|
}
|
|
|
|
}
|
2022-09-11 16:09:05 +02:00
|
|
|
|
2023-05-19 08:16:05 +12:00
|
|
|
return false;
|
2022-09-11 16:09:05 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
bool ButtonWithEncoder::on_touch(const TouchEvent event) {
|
2023-05-19 08:16:05 +12:00
|
|
|
switch (event.type) {
|
|
|
|
case TouchEvent::Type::Start:
|
|
|
|
set_highlighted(true);
|
|
|
|
set_dirty();
|
|
|
|
if (on_touch_press) {
|
|
|
|
on_touch_press(*this);
|
|
|
|
}
|
|
|
|
if (on_select && instant_exec_) {
|
|
|
|
on_select(*this);
|
|
|
|
}
|
|
|
|
return true;
|
|
|
|
|
|
|
|
case TouchEvent::Type::End:
|
|
|
|
set_highlighted(false);
|
|
|
|
set_dirty();
|
|
|
|
if (on_touch_release) {
|
|
|
|
on_touch_release(*this);
|
|
|
|
}
|
|
|
|
if (on_select && !instant_exec_) {
|
|
|
|
on_select(*this);
|
|
|
|
}
|
|
|
|
return true;
|
|
|
|
|
|
|
|
default:
|
|
|
|
return false;
|
|
|
|
}
|
2022-09-11 16:09:05 +02:00
|
|
|
#if 0
|
|
|
|
switch(event.type) {
|
|
|
|
case TouchEvent::Type::Start:
|
|
|
|
flags.highlighted = true;
|
|
|
|
set_dirty();
|
|
|
|
return true;
|
|
|
|
|
|
|
|
case TouchEvent::Type::Move:
|
|
|
|
{
|
|
|
|
const bool new_highlighted = screen_rect().contains(event.point);
|
|
|
|
if( flags.highlighted != new_highlighted ) {
|
|
|
|
flags.highlighted = new_highlighted;
|
|
|
|
set_dirty();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return true;
|
|
|
|
|
|
|
|
case TouchEvent::Type::End:
|
|
|
|
if( flags.highlighted ) {
|
|
|
|
flags.highlighted = false;
|
|
|
|
set_dirty();
|
|
|
|
if( on_select ) {
|
|
|
|
on_select(*this);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return true;
|
|
|
|
|
|
|
|
default:
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
bool ButtonWithEncoder::on_encoder(const EncoderEvent delta) {
|
2023-05-19 08:16:05 +12:00
|
|
|
if (delta != 0) {
|
|
|
|
encoder_delta += delta;
|
|
|
|
delta_change = true;
|
|
|
|
on_change();
|
|
|
|
} else
|
|
|
|
delta_change = 0;
|
|
|
|
return true;
|
2022-09-11 16:09:05 +02:00
|
|
|
}
|
|
|
|
|
UI Redesign for Portapack-Havoc (#268)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* PCB: Change PCB stackup, Tg, clarify solder mask color, use more metric.
* PCB: Move HackRF header P9 to B.CrtYd layer.
* PCB: Change a Tg reference I missed.
* PCB: Update footprints for parts with mismatched CAD->tape rotation.
Adjust a few layer choice and line thickness bits.
* PCB: Got cold feet, switched back to rectangular pads.
* PCB: Add Eco layers to be visible and Gerber output.
* PCB: Use aux origin for plotting, for tidier coordinates.
* PCB: Output Gerber job file, because why not?
* Schematic: Correct footprints for two reference-related components.
* Schematic: Remove manfuacturer and part number for DNP component.
* Schematic: Specify resistor value, manufacturer, part number for reference oscillator series termination.
* PCB: Update netlist and footprints from schematic.
* Netlist: Updated component values, footprints.
* PCB: Nudge some components and traces to address DRC clearance violations.
* PCB: Allow KiCad to update zone timestamps (again?!).
* PCB: Generate *all* Gerber layers.
* Schematic, PCB: Update revision to 20181025.
* PCB: Adjust fab layer annotations orientation and font size.
* PCB: Hide mounting hole reference designators on silk layer.
* PCB: Shrink U1, U3 pads to get 0.2mm space between pads.
* PCB: Set pad-to-mask clearance to zero, leave up to fab. Set minimum mask web to 0.2mm for non-black options.
* PCB: Revise U1 pad shape, mask, paste, thermal drills.
Clearance is improved at corner pads.
* PCB: Tweak U3 for better thermal pad/drill/mask/paste design.
* PCB: Change solder mask color to blue.
* Schematic, PCB: Update revision to 20181029.
* PCB: Bump minimum mask web down a tiny bit because KiCad is having trouble with math.
* Update schematic
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Clock Manager: Actually store chosen clock reference
Similarly-named local was covering a member and discarding the value.
* Clock Manager: Reference type which contains source, frequency.
* Setup: Display reference source, frequency in frequency correction screen.
* LPC43xx API: Add extern "C" for use from C++.
* Use LPC43xx API for SGPIO, GPDMA, I2S initialization.
* I2S: Add BASE_AUDIO_CLK management.
* Add MOTOCON_PWM clock/reset structure.
* Serial: Fix dumb typos.
* Serial: Remove extra reference operator.
* Serial: Cut-and-paste error in structure type name.
* Move SCU structure from PAL to LPC43xx API.
It'd be nice if I gave some thought to where code should live before I commit it.
* VAA power: Move code to HackRF board file
It doesn't belong in PAL.
* MAX5 CPLD: Add SAMPLE and EXTEST methods.
* Flash image: Change packing scheme to use flash more efficiently.
Application is now a single image for both M4 bootstrap and M0.
Baseband images come immediately after application binary. No need to align to large blocks (and waste lots of flash).
* Clock Manager: Remove PLL1 power down function.
* Move and rename peripherals reset function to board module.
* Remove unused peripheral/clock management.
* Clock Manager: Extract switch to IRC into separate function.
* Clock Manager: More explicit shutdown of clocks, clock generator.
* Move initialization to board module.
* ChibiOS: Rename "application" board, add "baseband" board.
There are now two ChibiOS "boards", one which runs the application and does the hardware setup. The other board, "baseband", does very little setup.
* Clock Manager: Remove unused crystal enable/disable code.
* Clock Manager: Restore clock configuration to SPIFI bootloader state before app shutdown.
* Reset peripherals on app shutdown.
Be careful not to reset M0APP (the core we're running on) or GPIO (which is holding the hardware in a stable state).
* M4/baseband hal_lld_init: use IDIVA, which is configured earlier by M0.
This was causing problems during restart into HackRF mode. Baseband hal_lld_init changed M4 clock from IDIVA (set by M0) to PLL1, which was unceremoniously turned off during shutdown.
* Audio app: Stop audio PLL on shutdown.
* M4 HAL: Make LPC43XX_M4_CLK_SRC optional.
This was changing the BASE_M4_CLK when a baseband was run.
* LPC43xx C++ layer: Fix IDIVx constructor IDIV narrow field width.
* Application board: hide the peripherals_reset function, as it isn't useful except during hardware init.
* Consolidate hardware init code to some degree.
ClockManager is super-overloaded and murky in its purpose.
Migrate audio from IDIVC to IDIVD, to more closely resemble initial clock scheme, so it's simpler to get back to it during shutdown.
* Migrate some startup code to application board.
* Si5351: Use correct methods for reset().
update_output_enable_control() doesn't reset the enabled outputs to the reset state, unless the object is freshly initialized, which it isn't when performing firmware shutdown.
For similar reasons, use set_clock_control() instead of setting internal state and then using the update function.
* GPIO: Set SPIFI CS pin to match input buffer state coming out of bootloader.
* Change application board.c to .cpp, with required dependent changes
* Board: Clean up SCU configuration code/data.
* I2S: Add shutdown code and use it.
* LPC43xx: Consolidate a bunch of structures that had been scattered all over.
...because I'm an undisciplined coder.
* I2S: Fix ordering of branch and base clock disable.
Core was hanging, presumably because the register interface on the branch/peripheral was unresponsive after the base clock was disabled.
* Controls: Save and expose raw navigation wheel switch state
I need to do some work on debouncing and ignoring simultaneous key presses.
* Controls: Add debug view for switches state.
* Controls: Ignore all key presses until all keys are released.
This should address some mechanical quirks of the navigation wheel used on the PortaPack.
* Clock Manager: Wait for only the necessary PLL to lock.
Wasn't working on PortaPacks without a built-in clock reference, as that uses the other PLL.
TODO: Switching PLLs may be kind of pointless now...
* CMake: Pull HackRF project from GitHub and build.
* CMake: Remove commented code.
* CMake: Clone HackRF via HTTPS, not SSH.
* CMake: Extra pause for slow post-DFU firmware boot-up.
* CMake: TODO to fix SVF/XSVF file source.
* CMake: Ask HackRF hackrf_usb to make DFU binary.
* Travis-CI: Add dfu-util, now that HackRF firmware is being built for inclusion.
* Travis-CI: Update build environment to Ubuntu xenial
Previously Trusty.
* Travis-CI: Incorrectly structured my request for dfu-util package.
I'm soooo talented.
* ldscript: Mark flash, ram with correct R/W/X flags.
* ldscript: Enlarge M0 flash region to 1Mbyte, the size of the HackRF SPI flash.
* Receiver: Hide PPM adjustment if clock source is not HackRF crystal.
* Documentation: Update product photos and README.
* Documentation: Add TCXO feature to README description.
* Application: Rearrange files to match HAVOC directory structure.
* Map view in AIS (#213)
* Added GeoMapView to AISRecentEntryDetailView
* Added autoupdate in AIS map
* Revert "Map view in AIS (#213)"
This reverts commit 262c030224b9ea3e56ff1c8a66246e7ecf30e41f.
This commit will be cherry-picked onto a clean branch, then re-committed after a troublesome pull request is reverted.
* Revert "Upstream merge to make new revision of PortaPack work (#206)"
This reverts commit 920b98f7c9a30371b643c42949066fb7d2441daf.
This pull request was missing some changes and was preventing firmware from functioning on older PortaPacks.
* CPLD: Pull bitstream from HackRF project.
* SGPIO: Identify pins on CPLD by their new functions. Pull down HOST_SYNC_EN.
* CPLD: Don't load HackRF CPLD bitstream into RAM.
Trying to converge CPLD implementations, so this shouldn't be necesssary. HOWEVER, it would be good to *check* the CPLD contents and provide a way to update, if necessary.
* CPLD: Tweak clock generator config to match CPLD timing changes in HackRF.
* PinConfig: Drive CPLD pins correctly.
* CMake: Use jboone/hackrf master branch, now that CPLD fixes are there.
* CMake: Fix HackRF CPLD SVF dependency.
Build would break on the first pass, but work if you restarted make.
* CMake: Fix my misuse of the HackRF CMake configuration -- was building from too deep in the directory tree
* CMake: Work-around for CMake 3.5 not supporting ExternalProject_Add SOURCE_SUBDIR.
* CMake: Choose a CMP0005 policy to quiet CMake warnings.
* Settings: Show active clock reference. Only show PPM adjustment for HackRF source.
* Setup: Format clock reference frequency in MHz, not Hz.
* Radio Settings: Change reference clock text color.
Make consistent color with other un-editable text.
TODO: This is a bit of a hack to get ui::Text objects to support custom colors, like the Label structures used elsewhere.
* Pin config: VREGMODE=1, add other pins for completeness, comment detail
* Pin setup: More useful comments.
* Pin setup: Change some defaults, only set up PortaPack pins if detected.
* Pin setup: Disable LPC pull-ups on PP CPLD data bus, as CPLD is pulling up.
* Baseband: Allow larger HackRF firmware image.
* HackRF: Remove USER_INTERFACE CMake variable.
* CPLD: Make use of HackRF CPLD tool to generate code.
* Release: Add generation of MD5SUMS, SHA256SUMS during "make release"
* Clock generator: Match clock output currents to HackRF firmware.
Someday, we will share a code base again...
* CMake: Make "firmware" target part of the "all" target.
So now an unqualified "make" will make the firmware binary.
* CMake: Change how HackRF firmware is incorporated into binary.
Use the separate HackRF "RAM" binary. Get rid of the strip-dfu utility, since there's no longer a need to extract the binary from the DFU.
* CMake: Renamed GIT_REVISION* -> GIT_VERSION* to match HackRF build env.
* CMake: Bring git version handling closer to HackRF for code reuse.
* Travis-CI: Rework CI release artifact output.
* Travis-CI: Don't assign PROJECT_NAME within deploy-nightly.sh
* Travis-CI: Oops, don't include distro package for compiler...
...when also installing it from a third-party PPA.
* Travis-CI: Update GCC package, old one seems "retired"?
* Travis-CI: OK, the gcc-arm-none-eabi package is NOT current. Undoing...
* Travis-CI: Path oopsies.
* Travis-CI: More path confusion. I think this will do it. *touch wood*
* Travis-CI: Update build message sent to FreeNode #portapack IRC.
* Travis-CI: Break out BUILD_DATE from BUILD_NAME.
* Travis-CI: Introduce build directories, include MD5 and SHA256 hashes.
* Travis-CI: Fix MD5SUMS/SHA256SUMS paths.
* Travis-CI: Fix typo generating name for binary links.
* Power: Keep 1V8 off until after VAA is brought up.
* Power: Bring up VAA in several steps to keep voltage swing small.
* About: Show longer commit/tag version string.
* Versioning: Report non-CI builds with "local-" version prefix.
* Travis-CI: Report new nightly build site in IRC notification.
* Change use of GIT_VERSION to VERSION_STRING
Required by prior merge.
* Git: add "hackrf" submodule.
* CMake: Use hackrf submodule for build, stop pulling during build.
* Travis: Fix build paths due to CMake submodule changes.
* Travis: Explicitly update submodules recursively
* Revert "Travis: Explicitly update submodules recursively"
This reverts commit b246438d805f431e727e01b7407540e932e89ee1.
* Travis: Try to sort out hackrf submodule output paths...
* Travis: I don't know what I'm doing.
* CMake: "make firmware" problem due to target vs. path used for dependency.
* HackRF: Incorporate YAML security fix.
* CMake: Fix more places where targets should be used...
...instead of paths to outputs.
* CMake: Add DFU file to "make firmware" outputs
* HackRF: Update submodule for CMake m0_bin.s path fix.
* added encoder support to alphanum
* added encoder support to freq-keypad
* UI Redesign -
added BtnGrid & NewButton widgets and created a new button-based
layout, with both encoder and touchscreen are supported.
* Scanner changes:
- using SCANNER.TXT for frequencies, ranges also supported. file
format is the same as any other frequency file, thus can be edited
via the Frequency Manager.
- add nfm bw selector & time-to-wait to the UI
- add SCANNER.TXT to sdcard dir
orignal idea & scanner file adopted from user 'bicurico'
* small changes to scanner
* remember last category on frequency manager
* fix: cast int16_t instead of uint16_t (although i doubt we will
have more than 32767 buttons in the array...)
* added a missing last_category_id on freq manager
2019-10-29 23:53:54 +02:00
|
|
|
/* NewButton ****************************************************************/
|
|
|
|
|
|
|
|
NewButton::NewButton(
|
2023-05-19 08:16:05 +12:00
|
|
|
Rect parent_rect,
|
|
|
|
std::string text,
|
|
|
|
const Bitmap* bitmap)
|
|
|
|
: NewButton{parent_rect, text, bitmap, Color::dark_cyan()} {}
|
2023-05-11 13:46:38 -07:00
|
|
|
|
|
|
|
NewButton::NewButton(
|
2023-05-19 08:16:05 +12:00
|
|
|
Rect parent_rect,
|
|
|
|
std::string text,
|
|
|
|
const Bitmap* bitmap,
|
|
|
|
Color color)
|
|
|
|
: Widget{parent_rect},
|
|
|
|
text_{text},
|
|
|
|
bitmap_{bitmap},
|
|
|
|
color_{color} {
|
|
|
|
set_focusable(true);
|
UI Redesign for Portapack-Havoc (#268)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* PCB: Change PCB stackup, Tg, clarify solder mask color, use more metric.
* PCB: Move HackRF header P9 to B.CrtYd layer.
* PCB: Change a Tg reference I missed.
* PCB: Update footprints for parts with mismatched CAD->tape rotation.
Adjust a few layer choice and line thickness bits.
* PCB: Got cold feet, switched back to rectangular pads.
* PCB: Add Eco layers to be visible and Gerber output.
* PCB: Use aux origin for plotting, for tidier coordinates.
* PCB: Output Gerber job file, because why not?
* Schematic: Correct footprints for two reference-related components.
* Schematic: Remove manfuacturer and part number for DNP component.
* Schematic: Specify resistor value, manufacturer, part number for reference oscillator series termination.
* PCB: Update netlist and footprints from schematic.
* Netlist: Updated component values, footprints.
* PCB: Nudge some components and traces to address DRC clearance violations.
* PCB: Allow KiCad to update zone timestamps (again?!).
* PCB: Generate *all* Gerber layers.
* Schematic, PCB: Update revision to 20181025.
* PCB: Adjust fab layer annotations orientation and font size.
* PCB: Hide mounting hole reference designators on silk layer.
* PCB: Shrink U1, U3 pads to get 0.2mm space between pads.
* PCB: Set pad-to-mask clearance to zero, leave up to fab. Set minimum mask web to 0.2mm for non-black options.
* PCB: Revise U1 pad shape, mask, paste, thermal drills.
Clearance is improved at corner pads.
* PCB: Tweak U3 for better thermal pad/drill/mask/paste design.
* PCB: Change solder mask color to blue.
* Schematic, PCB: Update revision to 20181029.
* PCB: Bump minimum mask web down a tiny bit because KiCad is having trouble with math.
* Update schematic
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Clock Manager: Actually store chosen clock reference
Similarly-named local was covering a member and discarding the value.
* Clock Manager: Reference type which contains source, frequency.
* Setup: Display reference source, frequency in frequency correction screen.
* LPC43xx API: Add extern "C" for use from C++.
* Use LPC43xx API for SGPIO, GPDMA, I2S initialization.
* I2S: Add BASE_AUDIO_CLK management.
* Add MOTOCON_PWM clock/reset structure.
* Serial: Fix dumb typos.
* Serial: Remove extra reference operator.
* Serial: Cut-and-paste error in structure type name.
* Move SCU structure from PAL to LPC43xx API.
It'd be nice if I gave some thought to where code should live before I commit it.
* VAA power: Move code to HackRF board file
It doesn't belong in PAL.
* MAX5 CPLD: Add SAMPLE and EXTEST methods.
* Flash image: Change packing scheme to use flash more efficiently.
Application is now a single image for both M4 bootstrap and M0.
Baseband images come immediately after application binary. No need to align to large blocks (and waste lots of flash).
* Clock Manager: Remove PLL1 power down function.
* Move and rename peripherals reset function to board module.
* Remove unused peripheral/clock management.
* Clock Manager: Extract switch to IRC into separate function.
* Clock Manager: More explicit shutdown of clocks, clock generator.
* Move initialization to board module.
* ChibiOS: Rename "application" board, add "baseband" board.
There are now two ChibiOS "boards", one which runs the application and does the hardware setup. The other board, "baseband", does very little setup.
* Clock Manager: Remove unused crystal enable/disable code.
* Clock Manager: Restore clock configuration to SPIFI bootloader state before app shutdown.
* Reset peripherals on app shutdown.
Be careful not to reset M0APP (the core we're running on) or GPIO (which is holding the hardware in a stable state).
* M4/baseband hal_lld_init: use IDIVA, which is configured earlier by M0.
This was causing problems during restart into HackRF mode. Baseband hal_lld_init changed M4 clock from IDIVA (set by M0) to PLL1, which was unceremoniously turned off during shutdown.
* Audio app: Stop audio PLL on shutdown.
* M4 HAL: Make LPC43XX_M4_CLK_SRC optional.
This was changing the BASE_M4_CLK when a baseband was run.
* LPC43xx C++ layer: Fix IDIVx constructor IDIV narrow field width.
* Application board: hide the peripherals_reset function, as it isn't useful except during hardware init.
* Consolidate hardware init code to some degree.
ClockManager is super-overloaded and murky in its purpose.
Migrate audio from IDIVC to IDIVD, to more closely resemble initial clock scheme, so it's simpler to get back to it during shutdown.
* Migrate some startup code to application board.
* Si5351: Use correct methods for reset().
update_output_enable_control() doesn't reset the enabled outputs to the reset state, unless the object is freshly initialized, which it isn't when performing firmware shutdown.
For similar reasons, use set_clock_control() instead of setting internal state and then using the update function.
* GPIO: Set SPIFI CS pin to match input buffer state coming out of bootloader.
* Change application board.c to .cpp, with required dependent changes
* Board: Clean up SCU configuration code/data.
* I2S: Add shutdown code and use it.
* LPC43xx: Consolidate a bunch of structures that had been scattered all over.
...because I'm an undisciplined coder.
* I2S: Fix ordering of branch and base clock disable.
Core was hanging, presumably because the register interface on the branch/peripheral was unresponsive after the base clock was disabled.
* Controls: Save and expose raw navigation wheel switch state
I need to do some work on debouncing and ignoring simultaneous key presses.
* Controls: Add debug view for switches state.
* Controls: Ignore all key presses until all keys are released.
This should address some mechanical quirks of the navigation wheel used on the PortaPack.
* Clock Manager: Wait for only the necessary PLL to lock.
Wasn't working on PortaPacks without a built-in clock reference, as that uses the other PLL.
TODO: Switching PLLs may be kind of pointless now...
* CMake: Pull HackRF project from GitHub and build.
* CMake: Remove commented code.
* CMake: Clone HackRF via HTTPS, not SSH.
* CMake: Extra pause for slow post-DFU firmware boot-up.
* CMake: TODO to fix SVF/XSVF file source.
* CMake: Ask HackRF hackrf_usb to make DFU binary.
* Travis-CI: Add dfu-util, now that HackRF firmware is being built for inclusion.
* Travis-CI: Update build environment to Ubuntu xenial
Previously Trusty.
* Travis-CI: Incorrectly structured my request for dfu-util package.
I'm soooo talented.
* ldscript: Mark flash, ram with correct R/W/X flags.
* ldscript: Enlarge M0 flash region to 1Mbyte, the size of the HackRF SPI flash.
* Receiver: Hide PPM adjustment if clock source is not HackRF crystal.
* Documentation: Update product photos and README.
* Documentation: Add TCXO feature to README description.
* Application: Rearrange files to match HAVOC directory structure.
* Map view in AIS (#213)
* Added GeoMapView to AISRecentEntryDetailView
* Added autoupdate in AIS map
* Revert "Map view in AIS (#213)"
This reverts commit 262c030224b9ea3e56ff1c8a66246e7ecf30e41f.
This commit will be cherry-picked onto a clean branch, then re-committed after a troublesome pull request is reverted.
* Revert "Upstream merge to make new revision of PortaPack work (#206)"
This reverts commit 920b98f7c9a30371b643c42949066fb7d2441daf.
This pull request was missing some changes and was preventing firmware from functioning on older PortaPacks.
* CPLD: Pull bitstream from HackRF project.
* SGPIO: Identify pins on CPLD by their new functions. Pull down HOST_SYNC_EN.
* CPLD: Don't load HackRF CPLD bitstream into RAM.
Trying to converge CPLD implementations, so this shouldn't be necesssary. HOWEVER, it would be good to *check* the CPLD contents and provide a way to update, if necessary.
* CPLD: Tweak clock generator config to match CPLD timing changes in HackRF.
* PinConfig: Drive CPLD pins correctly.
* CMake: Use jboone/hackrf master branch, now that CPLD fixes are there.
* CMake: Fix HackRF CPLD SVF dependency.
Build would break on the first pass, but work if you restarted make.
* CMake: Fix my misuse of the HackRF CMake configuration -- was building from too deep in the directory tree
* CMake: Work-around for CMake 3.5 not supporting ExternalProject_Add SOURCE_SUBDIR.
* CMake: Choose a CMP0005 policy to quiet CMake warnings.
* Settings: Show active clock reference. Only show PPM adjustment for HackRF source.
* Setup: Format clock reference frequency in MHz, not Hz.
* Radio Settings: Change reference clock text color.
Make consistent color with other un-editable text.
TODO: This is a bit of a hack to get ui::Text objects to support custom colors, like the Label structures used elsewhere.
* Pin config: VREGMODE=1, add other pins for completeness, comment detail
* Pin setup: More useful comments.
* Pin setup: Change some defaults, only set up PortaPack pins if detected.
* Pin setup: Disable LPC pull-ups on PP CPLD data bus, as CPLD is pulling up.
* Baseband: Allow larger HackRF firmware image.
* HackRF: Remove USER_INTERFACE CMake variable.
* CPLD: Make use of HackRF CPLD tool to generate code.
* Release: Add generation of MD5SUMS, SHA256SUMS during "make release"
* Clock generator: Match clock output currents to HackRF firmware.
Someday, we will share a code base again...
* CMake: Make "firmware" target part of the "all" target.
So now an unqualified "make" will make the firmware binary.
* CMake: Change how HackRF firmware is incorporated into binary.
Use the separate HackRF "RAM" binary. Get rid of the strip-dfu utility, since there's no longer a need to extract the binary from the DFU.
* CMake: Renamed GIT_REVISION* -> GIT_VERSION* to match HackRF build env.
* CMake: Bring git version handling closer to HackRF for code reuse.
* Travis-CI: Rework CI release artifact output.
* Travis-CI: Don't assign PROJECT_NAME within deploy-nightly.sh
* Travis-CI: Oops, don't include distro package for compiler...
...when also installing it from a third-party PPA.
* Travis-CI: Update GCC package, old one seems "retired"?
* Travis-CI: OK, the gcc-arm-none-eabi package is NOT current. Undoing...
* Travis-CI: Path oopsies.
* Travis-CI: More path confusion. I think this will do it. *touch wood*
* Travis-CI: Update build message sent to FreeNode #portapack IRC.
* Travis-CI: Break out BUILD_DATE from BUILD_NAME.
* Travis-CI: Introduce build directories, include MD5 and SHA256 hashes.
* Travis-CI: Fix MD5SUMS/SHA256SUMS paths.
* Travis-CI: Fix typo generating name for binary links.
* Power: Keep 1V8 off until after VAA is brought up.
* Power: Bring up VAA in several steps to keep voltage swing small.
* About: Show longer commit/tag version string.
* Versioning: Report non-CI builds with "local-" version prefix.
* Travis-CI: Report new nightly build site in IRC notification.
* Change use of GIT_VERSION to VERSION_STRING
Required by prior merge.
* Git: add "hackrf" submodule.
* CMake: Use hackrf submodule for build, stop pulling during build.
* Travis: Fix build paths due to CMake submodule changes.
* Travis: Explicitly update submodules recursively
* Revert "Travis: Explicitly update submodules recursively"
This reverts commit b246438d805f431e727e01b7407540e932e89ee1.
* Travis: Try to sort out hackrf submodule output paths...
* Travis: I don't know what I'm doing.
* CMake: "make firmware" problem due to target vs. path used for dependency.
* HackRF: Incorporate YAML security fix.
* CMake: Fix more places where targets should be used...
...instead of paths to outputs.
* CMake: Add DFU file to "make firmware" outputs
* HackRF: Update submodule for CMake m0_bin.s path fix.
* added encoder support to alphanum
* added encoder support to freq-keypad
* UI Redesign -
added BtnGrid & NewButton widgets and created a new button-based
layout, with both encoder and touchscreen are supported.
* Scanner changes:
- using SCANNER.TXT for frequencies, ranges also supported. file
format is the same as any other frequency file, thus can be edited
via the Frequency Manager.
- add nfm bw selector & time-to-wait to the UI
- add SCANNER.TXT to sdcard dir
orignal idea & scanner file adopted from user 'bicurico'
* small changes to scanner
* remember last category on frequency manager
* fix: cast int16_t instead of uint16_t (although i doubt we will
have more than 32767 buttons in the array...)
* added a missing last_category_id on freq manager
2019-10-29 23:53:54 +02:00
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}
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void NewButton::set_text(const std::string value) {
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2023-05-19 08:16:05 +12:00
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text_ = value;
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set_dirty();
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UI Redesign for Portapack-Havoc (#268)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* PCB: Change PCB stackup, Tg, clarify solder mask color, use more metric.
* PCB: Move HackRF header P9 to B.CrtYd layer.
* PCB: Change a Tg reference I missed.
* PCB: Update footprints for parts with mismatched CAD->tape rotation.
Adjust a few layer choice and line thickness bits.
* PCB: Got cold feet, switched back to rectangular pads.
* PCB: Add Eco layers to be visible and Gerber output.
* PCB: Use aux origin for plotting, for tidier coordinates.
* PCB: Output Gerber job file, because why not?
* Schematic: Correct footprints for two reference-related components.
* Schematic: Remove manfuacturer and part number for DNP component.
* Schematic: Specify resistor value, manufacturer, part number for reference oscillator series termination.
* PCB: Update netlist and footprints from schematic.
* Netlist: Updated component values, footprints.
* PCB: Nudge some components and traces to address DRC clearance violations.
* PCB: Allow KiCad to update zone timestamps (again?!).
* PCB: Generate *all* Gerber layers.
* Schematic, PCB: Update revision to 20181025.
* PCB: Adjust fab layer annotations orientation and font size.
* PCB: Hide mounting hole reference designators on silk layer.
* PCB: Shrink U1, U3 pads to get 0.2mm space between pads.
* PCB: Set pad-to-mask clearance to zero, leave up to fab. Set minimum mask web to 0.2mm for non-black options.
* PCB: Revise U1 pad shape, mask, paste, thermal drills.
Clearance is improved at corner pads.
* PCB: Tweak U3 for better thermal pad/drill/mask/paste design.
* PCB: Change solder mask color to blue.
* Schematic, PCB: Update revision to 20181029.
* PCB: Bump minimum mask web down a tiny bit because KiCad is having trouble with math.
* Update schematic
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Clock Manager: Actually store chosen clock reference
Similarly-named local was covering a member and discarding the value.
* Clock Manager: Reference type which contains source, frequency.
* Setup: Display reference source, frequency in frequency correction screen.
* LPC43xx API: Add extern "C" for use from C++.
* Use LPC43xx API for SGPIO, GPDMA, I2S initialization.
* I2S: Add BASE_AUDIO_CLK management.
* Add MOTOCON_PWM clock/reset structure.
* Serial: Fix dumb typos.
* Serial: Remove extra reference operator.
* Serial: Cut-and-paste error in structure type name.
* Move SCU structure from PAL to LPC43xx API.
It'd be nice if I gave some thought to where code should live before I commit it.
* VAA power: Move code to HackRF board file
It doesn't belong in PAL.
* MAX5 CPLD: Add SAMPLE and EXTEST methods.
* Flash image: Change packing scheme to use flash more efficiently.
Application is now a single image for both M4 bootstrap and M0.
Baseband images come immediately after application binary. No need to align to large blocks (and waste lots of flash).
* Clock Manager: Remove PLL1 power down function.
* Move and rename peripherals reset function to board module.
* Remove unused peripheral/clock management.
* Clock Manager: Extract switch to IRC into separate function.
* Clock Manager: More explicit shutdown of clocks, clock generator.
* Move initialization to board module.
* ChibiOS: Rename "application" board, add "baseband" board.
There are now two ChibiOS "boards", one which runs the application and does the hardware setup. The other board, "baseband", does very little setup.
* Clock Manager: Remove unused crystal enable/disable code.
* Clock Manager: Restore clock configuration to SPIFI bootloader state before app shutdown.
* Reset peripherals on app shutdown.
Be careful not to reset M0APP (the core we're running on) or GPIO (which is holding the hardware in a stable state).
* M4/baseband hal_lld_init: use IDIVA, which is configured earlier by M0.
This was causing problems during restart into HackRF mode. Baseband hal_lld_init changed M4 clock from IDIVA (set by M0) to PLL1, which was unceremoniously turned off during shutdown.
* Audio app: Stop audio PLL on shutdown.
* M4 HAL: Make LPC43XX_M4_CLK_SRC optional.
This was changing the BASE_M4_CLK when a baseband was run.
* LPC43xx C++ layer: Fix IDIVx constructor IDIV narrow field width.
* Application board: hide the peripherals_reset function, as it isn't useful except during hardware init.
* Consolidate hardware init code to some degree.
ClockManager is super-overloaded and murky in its purpose.
Migrate audio from IDIVC to IDIVD, to more closely resemble initial clock scheme, so it's simpler to get back to it during shutdown.
* Migrate some startup code to application board.
* Si5351: Use correct methods for reset().
update_output_enable_control() doesn't reset the enabled outputs to the reset state, unless the object is freshly initialized, which it isn't when performing firmware shutdown.
For similar reasons, use set_clock_control() instead of setting internal state and then using the update function.
* GPIO: Set SPIFI CS pin to match input buffer state coming out of bootloader.
* Change application board.c to .cpp, with required dependent changes
* Board: Clean up SCU configuration code/data.
* I2S: Add shutdown code and use it.
* LPC43xx: Consolidate a bunch of structures that had been scattered all over.
...because I'm an undisciplined coder.
* I2S: Fix ordering of branch and base clock disable.
Core was hanging, presumably because the register interface on the branch/peripheral was unresponsive after the base clock was disabled.
* Controls: Save and expose raw navigation wheel switch state
I need to do some work on debouncing and ignoring simultaneous key presses.
* Controls: Add debug view for switches state.
* Controls: Ignore all key presses until all keys are released.
This should address some mechanical quirks of the navigation wheel used on the PortaPack.
* Clock Manager: Wait for only the necessary PLL to lock.
Wasn't working on PortaPacks without a built-in clock reference, as that uses the other PLL.
TODO: Switching PLLs may be kind of pointless now...
* CMake: Pull HackRF project from GitHub and build.
* CMake: Remove commented code.
* CMake: Clone HackRF via HTTPS, not SSH.
* CMake: Extra pause for slow post-DFU firmware boot-up.
* CMake: TODO to fix SVF/XSVF file source.
* CMake: Ask HackRF hackrf_usb to make DFU binary.
* Travis-CI: Add dfu-util, now that HackRF firmware is being built for inclusion.
* Travis-CI: Update build environment to Ubuntu xenial
Previously Trusty.
* Travis-CI: Incorrectly structured my request for dfu-util package.
I'm soooo talented.
* ldscript: Mark flash, ram with correct R/W/X flags.
* ldscript: Enlarge M0 flash region to 1Mbyte, the size of the HackRF SPI flash.
* Receiver: Hide PPM adjustment if clock source is not HackRF crystal.
* Documentation: Update product photos and README.
* Documentation: Add TCXO feature to README description.
* Application: Rearrange files to match HAVOC directory structure.
* Map view in AIS (#213)
* Added GeoMapView to AISRecentEntryDetailView
* Added autoupdate in AIS map
* Revert "Map view in AIS (#213)"
This reverts commit 262c030224b9ea3e56ff1c8a66246e7ecf30e41f.
This commit will be cherry-picked onto a clean branch, then re-committed after a troublesome pull request is reverted.
* Revert "Upstream merge to make new revision of PortaPack work (#206)"
This reverts commit 920b98f7c9a30371b643c42949066fb7d2441daf.
This pull request was missing some changes and was preventing firmware from functioning on older PortaPacks.
* CPLD: Pull bitstream from HackRF project.
* SGPIO: Identify pins on CPLD by their new functions. Pull down HOST_SYNC_EN.
* CPLD: Don't load HackRF CPLD bitstream into RAM.
Trying to converge CPLD implementations, so this shouldn't be necesssary. HOWEVER, it would be good to *check* the CPLD contents and provide a way to update, if necessary.
* CPLD: Tweak clock generator config to match CPLD timing changes in HackRF.
* PinConfig: Drive CPLD pins correctly.
* CMake: Use jboone/hackrf master branch, now that CPLD fixes are there.
* CMake: Fix HackRF CPLD SVF dependency.
Build would break on the first pass, but work if you restarted make.
* CMake: Fix my misuse of the HackRF CMake configuration -- was building from too deep in the directory tree
* CMake: Work-around for CMake 3.5 not supporting ExternalProject_Add SOURCE_SUBDIR.
* CMake: Choose a CMP0005 policy to quiet CMake warnings.
* Settings: Show active clock reference. Only show PPM adjustment for HackRF source.
* Setup: Format clock reference frequency in MHz, not Hz.
* Radio Settings: Change reference clock text color.
Make consistent color with other un-editable text.
TODO: This is a bit of a hack to get ui::Text objects to support custom colors, like the Label structures used elsewhere.
* Pin config: VREGMODE=1, add other pins for completeness, comment detail
* Pin setup: More useful comments.
* Pin setup: Change some defaults, only set up PortaPack pins if detected.
* Pin setup: Disable LPC pull-ups on PP CPLD data bus, as CPLD is pulling up.
* Baseband: Allow larger HackRF firmware image.
* HackRF: Remove USER_INTERFACE CMake variable.
* CPLD: Make use of HackRF CPLD tool to generate code.
* Release: Add generation of MD5SUMS, SHA256SUMS during "make release"
* Clock generator: Match clock output currents to HackRF firmware.
Someday, we will share a code base again...
* CMake: Make "firmware" target part of the "all" target.
So now an unqualified "make" will make the firmware binary.
* CMake: Change how HackRF firmware is incorporated into binary.
Use the separate HackRF "RAM" binary. Get rid of the strip-dfu utility, since there's no longer a need to extract the binary from the DFU.
* CMake: Renamed GIT_REVISION* -> GIT_VERSION* to match HackRF build env.
* CMake: Bring git version handling closer to HackRF for code reuse.
* Travis-CI: Rework CI release artifact output.
* Travis-CI: Don't assign PROJECT_NAME within deploy-nightly.sh
* Travis-CI: Oops, don't include distro package for compiler...
...when also installing it from a third-party PPA.
* Travis-CI: Update GCC package, old one seems "retired"?
* Travis-CI: OK, the gcc-arm-none-eabi package is NOT current. Undoing...
* Travis-CI: Path oopsies.
* Travis-CI: More path confusion. I think this will do it. *touch wood*
* Travis-CI: Update build message sent to FreeNode #portapack IRC.
* Travis-CI: Break out BUILD_DATE from BUILD_NAME.
* Travis-CI: Introduce build directories, include MD5 and SHA256 hashes.
* Travis-CI: Fix MD5SUMS/SHA256SUMS paths.
* Travis-CI: Fix typo generating name for binary links.
* Power: Keep 1V8 off until after VAA is brought up.
* Power: Bring up VAA in several steps to keep voltage swing small.
* About: Show longer commit/tag version string.
* Versioning: Report non-CI builds with "local-" version prefix.
* Travis-CI: Report new nightly build site in IRC notification.
* Change use of GIT_VERSION to VERSION_STRING
Required by prior merge.
* Git: add "hackrf" submodule.
* CMake: Use hackrf submodule for build, stop pulling during build.
* Travis: Fix build paths due to CMake submodule changes.
* Travis: Explicitly update submodules recursively
* Revert "Travis: Explicitly update submodules recursively"
This reverts commit b246438d805f431e727e01b7407540e932e89ee1.
* Travis: Try to sort out hackrf submodule output paths...
* Travis: I don't know what I'm doing.
* CMake: "make firmware" problem due to target vs. path used for dependency.
* HackRF: Incorporate YAML security fix.
* CMake: Fix more places where targets should be used...
...instead of paths to outputs.
* CMake: Add DFU file to "make firmware" outputs
* HackRF: Update submodule for CMake m0_bin.s path fix.
* added encoder support to alphanum
* added encoder support to freq-keypad
* UI Redesign -
added BtnGrid & NewButton widgets and created a new button-based
layout, with both encoder and touchscreen are supported.
* Scanner changes:
- using SCANNER.TXT for frequencies, ranges also supported. file
format is the same as any other frequency file, thus can be edited
via the Frequency Manager.
- add nfm bw selector & time-to-wait to the UI
- add SCANNER.TXT to sdcard dir
orignal idea & scanner file adopted from user 'bicurico'
* small changes to scanner
* remember last category on frequency manager
* fix: cast int16_t instead of uint16_t (although i doubt we will
have more than 32767 buttons in the array...)
* added a missing last_category_id on freq manager
2019-10-29 23:53:54 +02:00
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}
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std::string NewButton::text() const {
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2023-05-19 08:16:05 +12:00
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return text_;
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UI Redesign for Portapack-Havoc (#268)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* PCB: Change PCB stackup, Tg, clarify solder mask color, use more metric.
* PCB: Move HackRF header P9 to B.CrtYd layer.
* PCB: Change a Tg reference I missed.
* PCB: Update footprints for parts with mismatched CAD->tape rotation.
Adjust a few layer choice and line thickness bits.
* PCB: Got cold feet, switched back to rectangular pads.
* PCB: Add Eco layers to be visible and Gerber output.
* PCB: Use aux origin for plotting, for tidier coordinates.
* PCB: Output Gerber job file, because why not?
* Schematic: Correct footprints for two reference-related components.
* Schematic: Remove manfuacturer and part number for DNP component.
* Schematic: Specify resistor value, manufacturer, part number for reference oscillator series termination.
* PCB: Update netlist and footprints from schematic.
* Netlist: Updated component values, footprints.
* PCB: Nudge some components and traces to address DRC clearance violations.
* PCB: Allow KiCad to update zone timestamps (again?!).
* PCB: Generate *all* Gerber layers.
* Schematic, PCB: Update revision to 20181025.
* PCB: Adjust fab layer annotations orientation and font size.
* PCB: Hide mounting hole reference designators on silk layer.
* PCB: Shrink U1, U3 pads to get 0.2mm space between pads.
* PCB: Set pad-to-mask clearance to zero, leave up to fab. Set minimum mask web to 0.2mm for non-black options.
* PCB: Revise U1 pad shape, mask, paste, thermal drills.
Clearance is improved at corner pads.
* PCB: Tweak U3 for better thermal pad/drill/mask/paste design.
* PCB: Change solder mask color to blue.
* Schematic, PCB: Update revision to 20181029.
* PCB: Bump minimum mask web down a tiny bit because KiCad is having trouble with math.
* Update schematic
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Clock Manager: Actually store chosen clock reference
Similarly-named local was covering a member and discarding the value.
* Clock Manager: Reference type which contains source, frequency.
* Setup: Display reference source, frequency in frequency correction screen.
* LPC43xx API: Add extern "C" for use from C++.
* Use LPC43xx API for SGPIO, GPDMA, I2S initialization.
* I2S: Add BASE_AUDIO_CLK management.
* Add MOTOCON_PWM clock/reset structure.
* Serial: Fix dumb typos.
* Serial: Remove extra reference operator.
* Serial: Cut-and-paste error in structure type name.
* Move SCU structure from PAL to LPC43xx API.
It'd be nice if I gave some thought to where code should live before I commit it.
* VAA power: Move code to HackRF board file
It doesn't belong in PAL.
* MAX5 CPLD: Add SAMPLE and EXTEST methods.
* Flash image: Change packing scheme to use flash more efficiently.
Application is now a single image for both M4 bootstrap and M0.
Baseband images come immediately after application binary. No need to align to large blocks (and waste lots of flash).
* Clock Manager: Remove PLL1 power down function.
* Move and rename peripherals reset function to board module.
* Remove unused peripheral/clock management.
* Clock Manager: Extract switch to IRC into separate function.
* Clock Manager: More explicit shutdown of clocks, clock generator.
* Move initialization to board module.
* ChibiOS: Rename "application" board, add "baseband" board.
There are now two ChibiOS "boards", one which runs the application and does the hardware setup. The other board, "baseband", does very little setup.
* Clock Manager: Remove unused crystal enable/disable code.
* Clock Manager: Restore clock configuration to SPIFI bootloader state before app shutdown.
* Reset peripherals on app shutdown.
Be careful not to reset M0APP (the core we're running on) or GPIO (which is holding the hardware in a stable state).
* M4/baseband hal_lld_init: use IDIVA, which is configured earlier by M0.
This was causing problems during restart into HackRF mode. Baseband hal_lld_init changed M4 clock from IDIVA (set by M0) to PLL1, which was unceremoniously turned off during shutdown.
* Audio app: Stop audio PLL on shutdown.
* M4 HAL: Make LPC43XX_M4_CLK_SRC optional.
This was changing the BASE_M4_CLK when a baseband was run.
* LPC43xx C++ layer: Fix IDIVx constructor IDIV narrow field width.
* Application board: hide the peripherals_reset function, as it isn't useful except during hardware init.
* Consolidate hardware init code to some degree.
ClockManager is super-overloaded and murky in its purpose.
Migrate audio from IDIVC to IDIVD, to more closely resemble initial clock scheme, so it's simpler to get back to it during shutdown.
* Migrate some startup code to application board.
* Si5351: Use correct methods for reset().
update_output_enable_control() doesn't reset the enabled outputs to the reset state, unless the object is freshly initialized, which it isn't when performing firmware shutdown.
For similar reasons, use set_clock_control() instead of setting internal state and then using the update function.
* GPIO: Set SPIFI CS pin to match input buffer state coming out of bootloader.
* Change application board.c to .cpp, with required dependent changes
* Board: Clean up SCU configuration code/data.
* I2S: Add shutdown code and use it.
* LPC43xx: Consolidate a bunch of structures that had been scattered all over.
...because I'm an undisciplined coder.
* I2S: Fix ordering of branch and base clock disable.
Core was hanging, presumably because the register interface on the branch/peripheral was unresponsive after the base clock was disabled.
* Controls: Save and expose raw navigation wheel switch state
I need to do some work on debouncing and ignoring simultaneous key presses.
* Controls: Add debug view for switches state.
* Controls: Ignore all key presses until all keys are released.
This should address some mechanical quirks of the navigation wheel used on the PortaPack.
* Clock Manager: Wait for only the necessary PLL to lock.
Wasn't working on PortaPacks without a built-in clock reference, as that uses the other PLL.
TODO: Switching PLLs may be kind of pointless now...
* CMake: Pull HackRF project from GitHub and build.
* CMake: Remove commented code.
* CMake: Clone HackRF via HTTPS, not SSH.
* CMake: Extra pause for slow post-DFU firmware boot-up.
* CMake: TODO to fix SVF/XSVF file source.
* CMake: Ask HackRF hackrf_usb to make DFU binary.
* Travis-CI: Add dfu-util, now that HackRF firmware is being built for inclusion.
* Travis-CI: Update build environment to Ubuntu xenial
Previously Trusty.
* Travis-CI: Incorrectly structured my request for dfu-util package.
I'm soooo talented.
* ldscript: Mark flash, ram with correct R/W/X flags.
* ldscript: Enlarge M0 flash region to 1Mbyte, the size of the HackRF SPI flash.
* Receiver: Hide PPM adjustment if clock source is not HackRF crystal.
* Documentation: Update product photos and README.
* Documentation: Add TCXO feature to README description.
* Application: Rearrange files to match HAVOC directory structure.
* Map view in AIS (#213)
* Added GeoMapView to AISRecentEntryDetailView
* Added autoupdate in AIS map
* Revert "Map view in AIS (#213)"
This reverts commit 262c030224b9ea3e56ff1c8a66246e7ecf30e41f.
This commit will be cherry-picked onto a clean branch, then re-committed after a troublesome pull request is reverted.
* Revert "Upstream merge to make new revision of PortaPack work (#206)"
This reverts commit 920b98f7c9a30371b643c42949066fb7d2441daf.
This pull request was missing some changes and was preventing firmware from functioning on older PortaPacks.
* CPLD: Pull bitstream from HackRF project.
* SGPIO: Identify pins on CPLD by their new functions. Pull down HOST_SYNC_EN.
* CPLD: Don't load HackRF CPLD bitstream into RAM.
Trying to converge CPLD implementations, so this shouldn't be necesssary. HOWEVER, it would be good to *check* the CPLD contents and provide a way to update, if necessary.
* CPLD: Tweak clock generator config to match CPLD timing changes in HackRF.
* PinConfig: Drive CPLD pins correctly.
* CMake: Use jboone/hackrf master branch, now that CPLD fixes are there.
* CMake: Fix HackRF CPLD SVF dependency.
Build would break on the first pass, but work if you restarted make.
* CMake: Fix my misuse of the HackRF CMake configuration -- was building from too deep in the directory tree
* CMake: Work-around for CMake 3.5 not supporting ExternalProject_Add SOURCE_SUBDIR.
* CMake: Choose a CMP0005 policy to quiet CMake warnings.
* Settings: Show active clock reference. Only show PPM adjustment for HackRF source.
* Setup: Format clock reference frequency in MHz, not Hz.
* Radio Settings: Change reference clock text color.
Make consistent color with other un-editable text.
TODO: This is a bit of a hack to get ui::Text objects to support custom colors, like the Label structures used elsewhere.
* Pin config: VREGMODE=1, add other pins for completeness, comment detail
* Pin setup: More useful comments.
* Pin setup: Change some defaults, only set up PortaPack pins if detected.
* Pin setup: Disable LPC pull-ups on PP CPLD data bus, as CPLD is pulling up.
* Baseband: Allow larger HackRF firmware image.
* HackRF: Remove USER_INTERFACE CMake variable.
* CPLD: Make use of HackRF CPLD tool to generate code.
* Release: Add generation of MD5SUMS, SHA256SUMS during "make release"
* Clock generator: Match clock output currents to HackRF firmware.
Someday, we will share a code base again...
* CMake: Make "firmware" target part of the "all" target.
So now an unqualified "make" will make the firmware binary.
* CMake: Change how HackRF firmware is incorporated into binary.
Use the separate HackRF "RAM" binary. Get rid of the strip-dfu utility, since there's no longer a need to extract the binary from the DFU.
* CMake: Renamed GIT_REVISION* -> GIT_VERSION* to match HackRF build env.
* CMake: Bring git version handling closer to HackRF for code reuse.
* Travis-CI: Rework CI release artifact output.
* Travis-CI: Don't assign PROJECT_NAME within deploy-nightly.sh
* Travis-CI: Oops, don't include distro package for compiler...
...when also installing it from a third-party PPA.
* Travis-CI: Update GCC package, old one seems "retired"?
* Travis-CI: OK, the gcc-arm-none-eabi package is NOT current. Undoing...
* Travis-CI: Path oopsies.
* Travis-CI: More path confusion. I think this will do it. *touch wood*
* Travis-CI: Update build message sent to FreeNode #portapack IRC.
* Travis-CI: Break out BUILD_DATE from BUILD_NAME.
* Travis-CI: Introduce build directories, include MD5 and SHA256 hashes.
* Travis-CI: Fix MD5SUMS/SHA256SUMS paths.
* Travis-CI: Fix typo generating name for binary links.
* Power: Keep 1V8 off until after VAA is brought up.
* Power: Bring up VAA in several steps to keep voltage swing small.
* About: Show longer commit/tag version string.
* Versioning: Report non-CI builds with "local-" version prefix.
* Travis-CI: Report new nightly build site in IRC notification.
* Change use of GIT_VERSION to VERSION_STRING
Required by prior merge.
* Git: add "hackrf" submodule.
* CMake: Use hackrf submodule for build, stop pulling during build.
* Travis: Fix build paths due to CMake submodule changes.
* Travis: Explicitly update submodules recursively
* Revert "Travis: Explicitly update submodules recursively"
This reverts commit b246438d805f431e727e01b7407540e932e89ee1.
* Travis: Try to sort out hackrf submodule output paths...
* Travis: I don't know what I'm doing.
* CMake: "make firmware" problem due to target vs. path used for dependency.
* HackRF: Incorporate YAML security fix.
* CMake: Fix more places where targets should be used...
...instead of paths to outputs.
* CMake: Add DFU file to "make firmware" outputs
* HackRF: Update submodule for CMake m0_bin.s path fix.
* added encoder support to alphanum
* added encoder support to freq-keypad
* UI Redesign -
added BtnGrid & NewButton widgets and created a new button-based
layout, with both encoder and touchscreen are supported.
* Scanner changes:
- using SCANNER.TXT for frequencies, ranges also supported. file
format is the same as any other frequency file, thus can be edited
via the Frequency Manager.
- add nfm bw selector & time-to-wait to the UI
- add SCANNER.TXT to sdcard dir
orignal idea & scanner file adopted from user 'bicurico'
* small changes to scanner
* remember last category on frequency manager
* fix: cast int16_t instead of uint16_t (although i doubt we will
have more than 32767 buttons in the array...)
* added a missing last_category_id on freq manager
2019-10-29 23:53:54 +02:00
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}
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void NewButton::set_bitmap(const Bitmap* bitmap) {
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2023-05-19 08:16:05 +12:00
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bitmap_ = bitmap;
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set_dirty();
|
UI Redesign for Portapack-Havoc (#268)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* PCB: Change PCB stackup, Tg, clarify solder mask color, use more metric.
* PCB: Move HackRF header P9 to B.CrtYd layer.
* PCB: Change a Tg reference I missed.
* PCB: Update footprints for parts with mismatched CAD->tape rotation.
Adjust a few layer choice and line thickness bits.
* PCB: Got cold feet, switched back to rectangular pads.
* PCB: Add Eco layers to be visible and Gerber output.
* PCB: Use aux origin for plotting, for tidier coordinates.
* PCB: Output Gerber job file, because why not?
* Schematic: Correct footprints for two reference-related components.
* Schematic: Remove manfuacturer and part number for DNP component.
* Schematic: Specify resistor value, manufacturer, part number for reference oscillator series termination.
* PCB: Update netlist and footprints from schematic.
* Netlist: Updated component values, footprints.
* PCB: Nudge some components and traces to address DRC clearance violations.
* PCB: Allow KiCad to update zone timestamps (again?!).
* PCB: Generate *all* Gerber layers.
* Schematic, PCB: Update revision to 20181025.
* PCB: Adjust fab layer annotations orientation and font size.
* PCB: Hide mounting hole reference designators on silk layer.
* PCB: Shrink U1, U3 pads to get 0.2mm space between pads.
* PCB: Set pad-to-mask clearance to zero, leave up to fab. Set minimum mask web to 0.2mm for non-black options.
* PCB: Revise U1 pad shape, mask, paste, thermal drills.
Clearance is improved at corner pads.
* PCB: Tweak U3 for better thermal pad/drill/mask/paste design.
* PCB: Change solder mask color to blue.
* Schematic, PCB: Update revision to 20181029.
* PCB: Bump minimum mask web down a tiny bit because KiCad is having trouble with math.
* Update schematic
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Clock Manager: Actually store chosen clock reference
Similarly-named local was covering a member and discarding the value.
* Clock Manager: Reference type which contains source, frequency.
* Setup: Display reference source, frequency in frequency correction screen.
* LPC43xx API: Add extern "C" for use from C++.
* Use LPC43xx API for SGPIO, GPDMA, I2S initialization.
* I2S: Add BASE_AUDIO_CLK management.
* Add MOTOCON_PWM clock/reset structure.
* Serial: Fix dumb typos.
* Serial: Remove extra reference operator.
* Serial: Cut-and-paste error in structure type name.
* Move SCU structure from PAL to LPC43xx API.
It'd be nice if I gave some thought to where code should live before I commit it.
* VAA power: Move code to HackRF board file
It doesn't belong in PAL.
* MAX5 CPLD: Add SAMPLE and EXTEST methods.
* Flash image: Change packing scheme to use flash more efficiently.
Application is now a single image for both M4 bootstrap and M0.
Baseband images come immediately after application binary. No need to align to large blocks (and waste lots of flash).
* Clock Manager: Remove PLL1 power down function.
* Move and rename peripherals reset function to board module.
* Remove unused peripheral/clock management.
* Clock Manager: Extract switch to IRC into separate function.
* Clock Manager: More explicit shutdown of clocks, clock generator.
* Move initialization to board module.
* ChibiOS: Rename "application" board, add "baseband" board.
There are now two ChibiOS "boards", one which runs the application and does the hardware setup. The other board, "baseband", does very little setup.
* Clock Manager: Remove unused crystal enable/disable code.
* Clock Manager: Restore clock configuration to SPIFI bootloader state before app shutdown.
* Reset peripherals on app shutdown.
Be careful not to reset M0APP (the core we're running on) or GPIO (which is holding the hardware in a stable state).
* M4/baseband hal_lld_init: use IDIVA, which is configured earlier by M0.
This was causing problems during restart into HackRF mode. Baseband hal_lld_init changed M4 clock from IDIVA (set by M0) to PLL1, which was unceremoniously turned off during shutdown.
* Audio app: Stop audio PLL on shutdown.
* M4 HAL: Make LPC43XX_M4_CLK_SRC optional.
This was changing the BASE_M4_CLK when a baseband was run.
* LPC43xx C++ layer: Fix IDIVx constructor IDIV narrow field width.
* Application board: hide the peripherals_reset function, as it isn't useful except during hardware init.
* Consolidate hardware init code to some degree.
ClockManager is super-overloaded and murky in its purpose.
Migrate audio from IDIVC to IDIVD, to more closely resemble initial clock scheme, so it's simpler to get back to it during shutdown.
* Migrate some startup code to application board.
* Si5351: Use correct methods for reset().
update_output_enable_control() doesn't reset the enabled outputs to the reset state, unless the object is freshly initialized, which it isn't when performing firmware shutdown.
For similar reasons, use set_clock_control() instead of setting internal state and then using the update function.
* GPIO: Set SPIFI CS pin to match input buffer state coming out of bootloader.
* Change application board.c to .cpp, with required dependent changes
* Board: Clean up SCU configuration code/data.
* I2S: Add shutdown code and use it.
* LPC43xx: Consolidate a bunch of structures that had been scattered all over.
...because I'm an undisciplined coder.
* I2S: Fix ordering of branch and base clock disable.
Core was hanging, presumably because the register interface on the branch/peripheral was unresponsive after the base clock was disabled.
* Controls: Save and expose raw navigation wheel switch state
I need to do some work on debouncing and ignoring simultaneous key presses.
* Controls: Add debug view for switches state.
* Controls: Ignore all key presses until all keys are released.
This should address some mechanical quirks of the navigation wheel used on the PortaPack.
* Clock Manager: Wait for only the necessary PLL to lock.
Wasn't working on PortaPacks without a built-in clock reference, as that uses the other PLL.
TODO: Switching PLLs may be kind of pointless now...
* CMake: Pull HackRF project from GitHub and build.
* CMake: Remove commented code.
* CMake: Clone HackRF via HTTPS, not SSH.
* CMake: Extra pause for slow post-DFU firmware boot-up.
* CMake: TODO to fix SVF/XSVF file source.
* CMake: Ask HackRF hackrf_usb to make DFU binary.
* Travis-CI: Add dfu-util, now that HackRF firmware is being built for inclusion.
* Travis-CI: Update build environment to Ubuntu xenial
Previously Trusty.
* Travis-CI: Incorrectly structured my request for dfu-util package.
I'm soooo talented.
* ldscript: Mark flash, ram with correct R/W/X flags.
* ldscript: Enlarge M0 flash region to 1Mbyte, the size of the HackRF SPI flash.
* Receiver: Hide PPM adjustment if clock source is not HackRF crystal.
* Documentation: Update product photos and README.
* Documentation: Add TCXO feature to README description.
* Application: Rearrange files to match HAVOC directory structure.
* Map view in AIS (#213)
* Added GeoMapView to AISRecentEntryDetailView
* Added autoupdate in AIS map
* Revert "Map view in AIS (#213)"
This reverts commit 262c030224b9ea3e56ff1c8a66246e7ecf30e41f.
This commit will be cherry-picked onto a clean branch, then re-committed after a troublesome pull request is reverted.
* Revert "Upstream merge to make new revision of PortaPack work (#206)"
This reverts commit 920b98f7c9a30371b643c42949066fb7d2441daf.
This pull request was missing some changes and was preventing firmware from functioning on older PortaPacks.
* CPLD: Pull bitstream from HackRF project.
* SGPIO: Identify pins on CPLD by their new functions. Pull down HOST_SYNC_EN.
* CPLD: Don't load HackRF CPLD bitstream into RAM.
Trying to converge CPLD implementations, so this shouldn't be necesssary. HOWEVER, it would be good to *check* the CPLD contents and provide a way to update, if necessary.
* CPLD: Tweak clock generator config to match CPLD timing changes in HackRF.
* PinConfig: Drive CPLD pins correctly.
* CMake: Use jboone/hackrf master branch, now that CPLD fixes are there.
* CMake: Fix HackRF CPLD SVF dependency.
Build would break on the first pass, but work if you restarted make.
* CMake: Fix my misuse of the HackRF CMake configuration -- was building from too deep in the directory tree
* CMake: Work-around for CMake 3.5 not supporting ExternalProject_Add SOURCE_SUBDIR.
* CMake: Choose a CMP0005 policy to quiet CMake warnings.
* Settings: Show active clock reference. Only show PPM adjustment for HackRF source.
* Setup: Format clock reference frequency in MHz, not Hz.
* Radio Settings: Change reference clock text color.
Make consistent color with other un-editable text.
TODO: This is a bit of a hack to get ui::Text objects to support custom colors, like the Label structures used elsewhere.
* Pin config: VREGMODE=1, add other pins for completeness, comment detail
* Pin setup: More useful comments.
* Pin setup: Change some defaults, only set up PortaPack pins if detected.
* Pin setup: Disable LPC pull-ups on PP CPLD data bus, as CPLD is pulling up.
* Baseband: Allow larger HackRF firmware image.
* HackRF: Remove USER_INTERFACE CMake variable.
* CPLD: Make use of HackRF CPLD tool to generate code.
* Release: Add generation of MD5SUMS, SHA256SUMS during "make release"
* Clock generator: Match clock output currents to HackRF firmware.
Someday, we will share a code base again...
* CMake: Make "firmware" target part of the "all" target.
So now an unqualified "make" will make the firmware binary.
* CMake: Change how HackRF firmware is incorporated into binary.
Use the separate HackRF "RAM" binary. Get rid of the strip-dfu utility, since there's no longer a need to extract the binary from the DFU.
* CMake: Renamed GIT_REVISION* -> GIT_VERSION* to match HackRF build env.
* CMake: Bring git version handling closer to HackRF for code reuse.
* Travis-CI: Rework CI release artifact output.
* Travis-CI: Don't assign PROJECT_NAME within deploy-nightly.sh
* Travis-CI: Oops, don't include distro package for compiler...
...when also installing it from a third-party PPA.
* Travis-CI: Update GCC package, old one seems "retired"?
* Travis-CI: OK, the gcc-arm-none-eabi package is NOT current. Undoing...
* Travis-CI: Path oopsies.
* Travis-CI: More path confusion. I think this will do it. *touch wood*
* Travis-CI: Update build message sent to FreeNode #portapack IRC.
* Travis-CI: Break out BUILD_DATE from BUILD_NAME.
* Travis-CI: Introduce build directories, include MD5 and SHA256 hashes.
* Travis-CI: Fix MD5SUMS/SHA256SUMS paths.
* Travis-CI: Fix typo generating name for binary links.
* Power: Keep 1V8 off until after VAA is brought up.
* Power: Bring up VAA in several steps to keep voltage swing small.
* About: Show longer commit/tag version string.
* Versioning: Report non-CI builds with "local-" version prefix.
* Travis-CI: Report new nightly build site in IRC notification.
* Change use of GIT_VERSION to VERSION_STRING
Required by prior merge.
* Git: add "hackrf" submodule.
* CMake: Use hackrf submodule for build, stop pulling during build.
* Travis: Fix build paths due to CMake submodule changes.
* Travis: Explicitly update submodules recursively
* Revert "Travis: Explicitly update submodules recursively"
This reverts commit b246438d805f431e727e01b7407540e932e89ee1.
* Travis: Try to sort out hackrf submodule output paths...
* Travis: I don't know what I'm doing.
* CMake: "make firmware" problem due to target vs. path used for dependency.
* HackRF: Incorporate YAML security fix.
* CMake: Fix more places where targets should be used...
...instead of paths to outputs.
* CMake: Add DFU file to "make firmware" outputs
* HackRF: Update submodule for CMake m0_bin.s path fix.
* added encoder support to alphanum
* added encoder support to freq-keypad
* UI Redesign -
added BtnGrid & NewButton widgets and created a new button-based
layout, with both encoder and touchscreen are supported.
* Scanner changes:
- using SCANNER.TXT for frequencies, ranges also supported. file
format is the same as any other frequency file, thus can be edited
via the Frequency Manager.
- add nfm bw selector & time-to-wait to the UI
- add SCANNER.TXT to sdcard dir
orignal idea & scanner file adopted from user 'bicurico'
* small changes to scanner
* remember last category on frequency manager
* fix: cast int16_t instead of uint16_t (although i doubt we will
have more than 32767 buttons in the array...)
* added a missing last_category_id on freq manager
2019-10-29 23:53:54 +02:00
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}
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const Bitmap* NewButton::bitmap() {
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2023-05-19 08:16:05 +12:00
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return bitmap_;
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UI Redesign for Portapack-Havoc (#268)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* PCB: Change PCB stackup, Tg, clarify solder mask color, use more metric.
* PCB: Move HackRF header P9 to B.CrtYd layer.
* PCB: Change a Tg reference I missed.
* PCB: Update footprints for parts with mismatched CAD->tape rotation.
Adjust a few layer choice and line thickness bits.
* PCB: Got cold feet, switched back to rectangular pads.
* PCB: Add Eco layers to be visible and Gerber output.
* PCB: Use aux origin for plotting, for tidier coordinates.
* PCB: Output Gerber job file, because why not?
* Schematic: Correct footprints for two reference-related components.
* Schematic: Remove manfuacturer and part number for DNP component.
* Schematic: Specify resistor value, manufacturer, part number for reference oscillator series termination.
* PCB: Update netlist and footprints from schematic.
* Netlist: Updated component values, footprints.
* PCB: Nudge some components and traces to address DRC clearance violations.
* PCB: Allow KiCad to update zone timestamps (again?!).
* PCB: Generate *all* Gerber layers.
* Schematic, PCB: Update revision to 20181025.
* PCB: Adjust fab layer annotations orientation and font size.
* PCB: Hide mounting hole reference designators on silk layer.
* PCB: Shrink U1, U3 pads to get 0.2mm space between pads.
* PCB: Set pad-to-mask clearance to zero, leave up to fab. Set minimum mask web to 0.2mm for non-black options.
* PCB: Revise U1 pad shape, mask, paste, thermal drills.
Clearance is improved at corner pads.
* PCB: Tweak U3 for better thermal pad/drill/mask/paste design.
* PCB: Change solder mask color to blue.
* Schematic, PCB: Update revision to 20181029.
* PCB: Bump minimum mask web down a tiny bit because KiCad is having trouble with math.
* Update schematic
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Clock Manager: Actually store chosen clock reference
Similarly-named local was covering a member and discarding the value.
* Clock Manager: Reference type which contains source, frequency.
* Setup: Display reference source, frequency in frequency correction screen.
* LPC43xx API: Add extern "C" for use from C++.
* Use LPC43xx API for SGPIO, GPDMA, I2S initialization.
* I2S: Add BASE_AUDIO_CLK management.
* Add MOTOCON_PWM clock/reset structure.
* Serial: Fix dumb typos.
* Serial: Remove extra reference operator.
* Serial: Cut-and-paste error in structure type name.
* Move SCU structure from PAL to LPC43xx API.
It'd be nice if I gave some thought to where code should live before I commit it.
* VAA power: Move code to HackRF board file
It doesn't belong in PAL.
* MAX5 CPLD: Add SAMPLE and EXTEST methods.
* Flash image: Change packing scheme to use flash more efficiently.
Application is now a single image for both M4 bootstrap and M0.
Baseband images come immediately after application binary. No need to align to large blocks (and waste lots of flash).
* Clock Manager: Remove PLL1 power down function.
* Move and rename peripherals reset function to board module.
* Remove unused peripheral/clock management.
* Clock Manager: Extract switch to IRC into separate function.
* Clock Manager: More explicit shutdown of clocks, clock generator.
* Move initialization to board module.
* ChibiOS: Rename "application" board, add "baseband" board.
There are now two ChibiOS "boards", one which runs the application and does the hardware setup. The other board, "baseband", does very little setup.
* Clock Manager: Remove unused crystal enable/disable code.
* Clock Manager: Restore clock configuration to SPIFI bootloader state before app shutdown.
* Reset peripherals on app shutdown.
Be careful not to reset M0APP (the core we're running on) or GPIO (which is holding the hardware in a stable state).
* M4/baseband hal_lld_init: use IDIVA, which is configured earlier by M0.
This was causing problems during restart into HackRF mode. Baseband hal_lld_init changed M4 clock from IDIVA (set by M0) to PLL1, which was unceremoniously turned off during shutdown.
* Audio app: Stop audio PLL on shutdown.
* M4 HAL: Make LPC43XX_M4_CLK_SRC optional.
This was changing the BASE_M4_CLK when a baseband was run.
* LPC43xx C++ layer: Fix IDIVx constructor IDIV narrow field width.
* Application board: hide the peripherals_reset function, as it isn't useful except during hardware init.
* Consolidate hardware init code to some degree.
ClockManager is super-overloaded and murky in its purpose.
Migrate audio from IDIVC to IDIVD, to more closely resemble initial clock scheme, so it's simpler to get back to it during shutdown.
* Migrate some startup code to application board.
* Si5351: Use correct methods for reset().
update_output_enable_control() doesn't reset the enabled outputs to the reset state, unless the object is freshly initialized, which it isn't when performing firmware shutdown.
For similar reasons, use set_clock_control() instead of setting internal state and then using the update function.
* GPIO: Set SPIFI CS pin to match input buffer state coming out of bootloader.
* Change application board.c to .cpp, with required dependent changes
* Board: Clean up SCU configuration code/data.
* I2S: Add shutdown code and use it.
* LPC43xx: Consolidate a bunch of structures that had been scattered all over.
...because I'm an undisciplined coder.
* I2S: Fix ordering of branch and base clock disable.
Core was hanging, presumably because the register interface on the branch/peripheral was unresponsive after the base clock was disabled.
* Controls: Save and expose raw navigation wheel switch state
I need to do some work on debouncing and ignoring simultaneous key presses.
* Controls: Add debug view for switches state.
* Controls: Ignore all key presses until all keys are released.
This should address some mechanical quirks of the navigation wheel used on the PortaPack.
* Clock Manager: Wait for only the necessary PLL to lock.
Wasn't working on PortaPacks without a built-in clock reference, as that uses the other PLL.
TODO: Switching PLLs may be kind of pointless now...
* CMake: Pull HackRF project from GitHub and build.
* CMake: Remove commented code.
* CMake: Clone HackRF via HTTPS, not SSH.
* CMake: Extra pause for slow post-DFU firmware boot-up.
* CMake: TODO to fix SVF/XSVF file source.
* CMake: Ask HackRF hackrf_usb to make DFU binary.
* Travis-CI: Add dfu-util, now that HackRF firmware is being built for inclusion.
* Travis-CI: Update build environment to Ubuntu xenial
Previously Trusty.
* Travis-CI: Incorrectly structured my request for dfu-util package.
I'm soooo talented.
* ldscript: Mark flash, ram with correct R/W/X flags.
* ldscript: Enlarge M0 flash region to 1Mbyte, the size of the HackRF SPI flash.
* Receiver: Hide PPM adjustment if clock source is not HackRF crystal.
* Documentation: Update product photos and README.
* Documentation: Add TCXO feature to README description.
* Application: Rearrange files to match HAVOC directory structure.
* Map view in AIS (#213)
* Added GeoMapView to AISRecentEntryDetailView
* Added autoupdate in AIS map
* Revert "Map view in AIS (#213)"
This reverts commit 262c030224b9ea3e56ff1c8a66246e7ecf30e41f.
This commit will be cherry-picked onto a clean branch, then re-committed after a troublesome pull request is reverted.
* Revert "Upstream merge to make new revision of PortaPack work (#206)"
This reverts commit 920b98f7c9a30371b643c42949066fb7d2441daf.
This pull request was missing some changes and was preventing firmware from functioning on older PortaPacks.
* CPLD: Pull bitstream from HackRF project.
* SGPIO: Identify pins on CPLD by their new functions. Pull down HOST_SYNC_EN.
* CPLD: Don't load HackRF CPLD bitstream into RAM.
Trying to converge CPLD implementations, so this shouldn't be necesssary. HOWEVER, it would be good to *check* the CPLD contents and provide a way to update, if necessary.
* CPLD: Tweak clock generator config to match CPLD timing changes in HackRF.
* PinConfig: Drive CPLD pins correctly.
* CMake: Use jboone/hackrf master branch, now that CPLD fixes are there.
* CMake: Fix HackRF CPLD SVF dependency.
Build would break on the first pass, but work if you restarted make.
* CMake: Fix my misuse of the HackRF CMake configuration -- was building from too deep in the directory tree
* CMake: Work-around for CMake 3.5 not supporting ExternalProject_Add SOURCE_SUBDIR.
* CMake: Choose a CMP0005 policy to quiet CMake warnings.
* Settings: Show active clock reference. Only show PPM adjustment for HackRF source.
* Setup: Format clock reference frequency in MHz, not Hz.
* Radio Settings: Change reference clock text color.
Make consistent color with other un-editable text.
TODO: This is a bit of a hack to get ui::Text objects to support custom colors, like the Label structures used elsewhere.
* Pin config: VREGMODE=1, add other pins for completeness, comment detail
* Pin setup: More useful comments.
* Pin setup: Change some defaults, only set up PortaPack pins if detected.
* Pin setup: Disable LPC pull-ups on PP CPLD data bus, as CPLD is pulling up.
* Baseband: Allow larger HackRF firmware image.
* HackRF: Remove USER_INTERFACE CMake variable.
* CPLD: Make use of HackRF CPLD tool to generate code.
* Release: Add generation of MD5SUMS, SHA256SUMS during "make release"
* Clock generator: Match clock output currents to HackRF firmware.
Someday, we will share a code base again...
* CMake: Make "firmware" target part of the "all" target.
So now an unqualified "make" will make the firmware binary.
* CMake: Change how HackRF firmware is incorporated into binary.
Use the separate HackRF "RAM" binary. Get rid of the strip-dfu utility, since there's no longer a need to extract the binary from the DFU.
* CMake: Renamed GIT_REVISION* -> GIT_VERSION* to match HackRF build env.
* CMake: Bring git version handling closer to HackRF for code reuse.
* Travis-CI: Rework CI release artifact output.
* Travis-CI: Don't assign PROJECT_NAME within deploy-nightly.sh
* Travis-CI: Oops, don't include distro package for compiler...
...when also installing it from a third-party PPA.
* Travis-CI: Update GCC package, old one seems "retired"?
* Travis-CI: OK, the gcc-arm-none-eabi package is NOT current. Undoing...
* Travis-CI: Path oopsies.
* Travis-CI: More path confusion. I think this will do it. *touch wood*
* Travis-CI: Update build message sent to FreeNode #portapack IRC.
* Travis-CI: Break out BUILD_DATE from BUILD_NAME.
* Travis-CI: Introduce build directories, include MD5 and SHA256 hashes.
* Travis-CI: Fix MD5SUMS/SHA256SUMS paths.
* Travis-CI: Fix typo generating name for binary links.
* Power: Keep 1V8 off until after VAA is brought up.
* Power: Bring up VAA in several steps to keep voltage swing small.
* About: Show longer commit/tag version string.
* Versioning: Report non-CI builds with "local-" version prefix.
* Travis-CI: Report new nightly build site in IRC notification.
* Change use of GIT_VERSION to VERSION_STRING
Required by prior merge.
* Git: add "hackrf" submodule.
* CMake: Use hackrf submodule for build, stop pulling during build.
* Travis: Fix build paths due to CMake submodule changes.
* Travis: Explicitly update submodules recursively
* Revert "Travis: Explicitly update submodules recursively"
This reverts commit b246438d805f431e727e01b7407540e932e89ee1.
* Travis: Try to sort out hackrf submodule output paths...
* Travis: I don't know what I'm doing.
* CMake: "make firmware" problem due to target vs. path used for dependency.
* HackRF: Incorporate YAML security fix.
* CMake: Fix more places where targets should be used...
...instead of paths to outputs.
* CMake: Add DFU file to "make firmware" outputs
* HackRF: Update submodule for CMake m0_bin.s path fix.
* added encoder support to alphanum
* added encoder support to freq-keypad
* UI Redesign -
added BtnGrid & NewButton widgets and created a new button-based
layout, with both encoder and touchscreen are supported.
* Scanner changes:
- using SCANNER.TXT for frequencies, ranges also supported. file
format is the same as any other frequency file, thus can be edited
via the Frequency Manager.
- add nfm bw selector & time-to-wait to the UI
- add SCANNER.TXT to sdcard dir
orignal idea & scanner file adopted from user 'bicurico'
* small changes to scanner
* remember last category on frequency manager
* fix: cast int16_t instead of uint16_t (although i doubt we will
have more than 32767 buttons in the array...)
* added a missing last_category_id on freq manager
2019-10-29 23:53:54 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
void NewButton::set_color(Color color) {
|
2023-05-19 08:16:05 +12:00
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|
color_ = color;
|
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|
set_dirty();
|
UI Redesign for Portapack-Havoc (#268)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* PCB: Change PCB stackup, Tg, clarify solder mask color, use more metric.
* PCB: Move HackRF header P9 to B.CrtYd layer.
* PCB: Change a Tg reference I missed.
* PCB: Update footprints for parts with mismatched CAD->tape rotation.
Adjust a few layer choice and line thickness bits.
* PCB: Got cold feet, switched back to rectangular pads.
* PCB: Add Eco layers to be visible and Gerber output.
* PCB: Use aux origin for plotting, for tidier coordinates.
* PCB: Output Gerber job file, because why not?
* Schematic: Correct footprints for two reference-related components.
* Schematic: Remove manfuacturer and part number for DNP component.
* Schematic: Specify resistor value, manufacturer, part number for reference oscillator series termination.
* PCB: Update netlist and footprints from schematic.
* Netlist: Updated component values, footprints.
* PCB: Nudge some components and traces to address DRC clearance violations.
* PCB: Allow KiCad to update zone timestamps (again?!).
* PCB: Generate *all* Gerber layers.
* Schematic, PCB: Update revision to 20181025.
* PCB: Adjust fab layer annotations orientation and font size.
* PCB: Hide mounting hole reference designators on silk layer.
* PCB: Shrink U1, U3 pads to get 0.2mm space between pads.
* PCB: Set pad-to-mask clearance to zero, leave up to fab. Set minimum mask web to 0.2mm for non-black options.
* PCB: Revise U1 pad shape, mask, paste, thermal drills.
Clearance is improved at corner pads.
* PCB: Tweak U3 for better thermal pad/drill/mask/paste design.
* PCB: Change solder mask color to blue.
* Schematic, PCB: Update revision to 20181029.
* PCB: Bump minimum mask web down a tiny bit because KiCad is having trouble with math.
* Update schematic
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Clock Manager: Actually store chosen clock reference
Similarly-named local was covering a member and discarding the value.
* Clock Manager: Reference type which contains source, frequency.
* Setup: Display reference source, frequency in frequency correction screen.
* LPC43xx API: Add extern "C" for use from C++.
* Use LPC43xx API for SGPIO, GPDMA, I2S initialization.
* I2S: Add BASE_AUDIO_CLK management.
* Add MOTOCON_PWM clock/reset structure.
* Serial: Fix dumb typos.
* Serial: Remove extra reference operator.
* Serial: Cut-and-paste error in structure type name.
* Move SCU structure from PAL to LPC43xx API.
It'd be nice if I gave some thought to where code should live before I commit it.
* VAA power: Move code to HackRF board file
It doesn't belong in PAL.
* MAX5 CPLD: Add SAMPLE and EXTEST methods.
* Flash image: Change packing scheme to use flash more efficiently.
Application is now a single image for both M4 bootstrap and M0.
Baseband images come immediately after application binary. No need to align to large blocks (and waste lots of flash).
* Clock Manager: Remove PLL1 power down function.
* Move and rename peripherals reset function to board module.
* Remove unused peripheral/clock management.
* Clock Manager: Extract switch to IRC into separate function.
* Clock Manager: More explicit shutdown of clocks, clock generator.
* Move initialization to board module.
* ChibiOS: Rename "application" board, add "baseband" board.
There are now two ChibiOS "boards", one which runs the application and does the hardware setup. The other board, "baseband", does very little setup.
* Clock Manager: Remove unused crystal enable/disable code.
* Clock Manager: Restore clock configuration to SPIFI bootloader state before app shutdown.
* Reset peripherals on app shutdown.
Be careful not to reset M0APP (the core we're running on) or GPIO (which is holding the hardware in a stable state).
* M4/baseband hal_lld_init: use IDIVA, which is configured earlier by M0.
This was causing problems during restart into HackRF mode. Baseband hal_lld_init changed M4 clock from IDIVA (set by M0) to PLL1, which was unceremoniously turned off during shutdown.
* Audio app: Stop audio PLL on shutdown.
* M4 HAL: Make LPC43XX_M4_CLK_SRC optional.
This was changing the BASE_M4_CLK when a baseband was run.
* LPC43xx C++ layer: Fix IDIVx constructor IDIV narrow field width.
* Application board: hide the peripherals_reset function, as it isn't useful except during hardware init.
* Consolidate hardware init code to some degree.
ClockManager is super-overloaded and murky in its purpose.
Migrate audio from IDIVC to IDIVD, to more closely resemble initial clock scheme, so it's simpler to get back to it during shutdown.
* Migrate some startup code to application board.
* Si5351: Use correct methods for reset().
update_output_enable_control() doesn't reset the enabled outputs to the reset state, unless the object is freshly initialized, which it isn't when performing firmware shutdown.
For similar reasons, use set_clock_control() instead of setting internal state and then using the update function.
* GPIO: Set SPIFI CS pin to match input buffer state coming out of bootloader.
* Change application board.c to .cpp, with required dependent changes
* Board: Clean up SCU configuration code/data.
* I2S: Add shutdown code and use it.
* LPC43xx: Consolidate a bunch of structures that had been scattered all over.
...because I'm an undisciplined coder.
* I2S: Fix ordering of branch and base clock disable.
Core was hanging, presumably because the register interface on the branch/peripheral was unresponsive after the base clock was disabled.
* Controls: Save and expose raw navigation wheel switch state
I need to do some work on debouncing and ignoring simultaneous key presses.
* Controls: Add debug view for switches state.
* Controls: Ignore all key presses until all keys are released.
This should address some mechanical quirks of the navigation wheel used on the PortaPack.
* Clock Manager: Wait for only the necessary PLL to lock.
Wasn't working on PortaPacks without a built-in clock reference, as that uses the other PLL.
TODO: Switching PLLs may be kind of pointless now...
* CMake: Pull HackRF project from GitHub and build.
* CMake: Remove commented code.
* CMake: Clone HackRF via HTTPS, not SSH.
* CMake: Extra pause for slow post-DFU firmware boot-up.
* CMake: TODO to fix SVF/XSVF file source.
* CMake: Ask HackRF hackrf_usb to make DFU binary.
* Travis-CI: Add dfu-util, now that HackRF firmware is being built for inclusion.
* Travis-CI: Update build environment to Ubuntu xenial
Previously Trusty.
* Travis-CI: Incorrectly structured my request for dfu-util package.
I'm soooo talented.
* ldscript: Mark flash, ram with correct R/W/X flags.
* ldscript: Enlarge M0 flash region to 1Mbyte, the size of the HackRF SPI flash.
* Receiver: Hide PPM adjustment if clock source is not HackRF crystal.
* Documentation: Update product photos and README.
* Documentation: Add TCXO feature to README description.
* Application: Rearrange files to match HAVOC directory structure.
* Map view in AIS (#213)
* Added GeoMapView to AISRecentEntryDetailView
* Added autoupdate in AIS map
* Revert "Map view in AIS (#213)"
This reverts commit 262c030224b9ea3e56ff1c8a66246e7ecf30e41f.
This commit will be cherry-picked onto a clean branch, then re-committed after a troublesome pull request is reverted.
* Revert "Upstream merge to make new revision of PortaPack work (#206)"
This reverts commit 920b98f7c9a30371b643c42949066fb7d2441daf.
This pull request was missing some changes and was preventing firmware from functioning on older PortaPacks.
* CPLD: Pull bitstream from HackRF project.
* SGPIO: Identify pins on CPLD by their new functions. Pull down HOST_SYNC_EN.
* CPLD: Don't load HackRF CPLD bitstream into RAM.
Trying to converge CPLD implementations, so this shouldn't be necesssary. HOWEVER, it would be good to *check* the CPLD contents and provide a way to update, if necessary.
* CPLD: Tweak clock generator config to match CPLD timing changes in HackRF.
* PinConfig: Drive CPLD pins correctly.
* CMake: Use jboone/hackrf master branch, now that CPLD fixes are there.
* CMake: Fix HackRF CPLD SVF dependency.
Build would break on the first pass, but work if you restarted make.
* CMake: Fix my misuse of the HackRF CMake configuration -- was building from too deep in the directory tree
* CMake: Work-around for CMake 3.5 not supporting ExternalProject_Add SOURCE_SUBDIR.
* CMake: Choose a CMP0005 policy to quiet CMake warnings.
* Settings: Show active clock reference. Only show PPM adjustment for HackRF source.
* Setup: Format clock reference frequency in MHz, not Hz.
* Radio Settings: Change reference clock text color.
Make consistent color with other un-editable text.
TODO: This is a bit of a hack to get ui::Text objects to support custom colors, like the Label structures used elsewhere.
* Pin config: VREGMODE=1, add other pins for completeness, comment detail
* Pin setup: More useful comments.
* Pin setup: Change some defaults, only set up PortaPack pins if detected.
* Pin setup: Disable LPC pull-ups on PP CPLD data bus, as CPLD is pulling up.
* Baseband: Allow larger HackRF firmware image.
* HackRF: Remove USER_INTERFACE CMake variable.
* CPLD: Make use of HackRF CPLD tool to generate code.
* Release: Add generation of MD5SUMS, SHA256SUMS during "make release"
* Clock generator: Match clock output currents to HackRF firmware.
Someday, we will share a code base again...
* CMake: Make "firmware" target part of the "all" target.
So now an unqualified "make" will make the firmware binary.
* CMake: Change how HackRF firmware is incorporated into binary.
Use the separate HackRF "RAM" binary. Get rid of the strip-dfu utility, since there's no longer a need to extract the binary from the DFU.
* CMake: Renamed GIT_REVISION* -> GIT_VERSION* to match HackRF build env.
* CMake: Bring git version handling closer to HackRF for code reuse.
* Travis-CI: Rework CI release artifact output.
* Travis-CI: Don't assign PROJECT_NAME within deploy-nightly.sh
* Travis-CI: Oops, don't include distro package for compiler...
...when also installing it from a third-party PPA.
* Travis-CI: Update GCC package, old one seems "retired"?
* Travis-CI: OK, the gcc-arm-none-eabi package is NOT current. Undoing...
* Travis-CI: Path oopsies.
* Travis-CI: More path confusion. I think this will do it. *touch wood*
* Travis-CI: Update build message sent to FreeNode #portapack IRC.
* Travis-CI: Break out BUILD_DATE from BUILD_NAME.
* Travis-CI: Introduce build directories, include MD5 and SHA256 hashes.
* Travis-CI: Fix MD5SUMS/SHA256SUMS paths.
* Travis-CI: Fix typo generating name for binary links.
* Power: Keep 1V8 off until after VAA is brought up.
* Power: Bring up VAA in several steps to keep voltage swing small.
* About: Show longer commit/tag version string.
* Versioning: Report non-CI builds with "local-" version prefix.
* Travis-CI: Report new nightly build site in IRC notification.
* Change use of GIT_VERSION to VERSION_STRING
Required by prior merge.
* Git: add "hackrf" submodule.
* CMake: Use hackrf submodule for build, stop pulling during build.
* Travis: Fix build paths due to CMake submodule changes.
* Travis: Explicitly update submodules recursively
* Revert "Travis: Explicitly update submodules recursively"
This reverts commit b246438d805f431e727e01b7407540e932e89ee1.
* Travis: Try to sort out hackrf submodule output paths...
* Travis: I don't know what I'm doing.
* CMake: "make firmware" problem due to target vs. path used for dependency.
* HackRF: Incorporate YAML security fix.
* CMake: Fix more places where targets should be used...
...instead of paths to outputs.
* CMake: Add DFU file to "make firmware" outputs
* HackRF: Update submodule for CMake m0_bin.s path fix.
* added encoder support to alphanum
* added encoder support to freq-keypad
* UI Redesign -
added BtnGrid & NewButton widgets and created a new button-based
layout, with both encoder and touchscreen are supported.
* Scanner changes:
- using SCANNER.TXT for frequencies, ranges also supported. file
format is the same as any other frequency file, thus can be edited
via the Frequency Manager.
- add nfm bw selector & time-to-wait to the UI
- add SCANNER.TXT to sdcard dir
orignal idea & scanner file adopted from user 'bicurico'
* small changes to scanner
* remember last category on frequency manager
* fix: cast int16_t instead of uint16_t (although i doubt we will
have more than 32767 buttons in the array...)
* added a missing last_category_id on freq manager
2019-10-29 23:53:54 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
ui::Color NewButton::color() {
|
2023-05-19 08:16:05 +12:00
|
|
|
return color_;
|
UI Redesign for Portapack-Havoc (#268)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* PCB: Change PCB stackup, Tg, clarify solder mask color, use more metric.
* PCB: Move HackRF header P9 to B.CrtYd layer.
* PCB: Change a Tg reference I missed.
* PCB: Update footprints for parts with mismatched CAD->tape rotation.
Adjust a few layer choice and line thickness bits.
* PCB: Got cold feet, switched back to rectangular pads.
* PCB: Add Eco layers to be visible and Gerber output.
* PCB: Use aux origin for plotting, for tidier coordinates.
* PCB: Output Gerber job file, because why not?
* Schematic: Correct footprints for two reference-related components.
* Schematic: Remove manfuacturer and part number for DNP component.
* Schematic: Specify resistor value, manufacturer, part number for reference oscillator series termination.
* PCB: Update netlist and footprints from schematic.
* Netlist: Updated component values, footprints.
* PCB: Nudge some components and traces to address DRC clearance violations.
* PCB: Allow KiCad to update zone timestamps (again?!).
* PCB: Generate *all* Gerber layers.
* Schematic, PCB: Update revision to 20181025.
* PCB: Adjust fab layer annotations orientation and font size.
* PCB: Hide mounting hole reference designators on silk layer.
* PCB: Shrink U1, U3 pads to get 0.2mm space between pads.
* PCB: Set pad-to-mask clearance to zero, leave up to fab. Set minimum mask web to 0.2mm for non-black options.
* PCB: Revise U1 pad shape, mask, paste, thermal drills.
Clearance is improved at corner pads.
* PCB: Tweak U3 for better thermal pad/drill/mask/paste design.
* PCB: Change solder mask color to blue.
* Schematic, PCB: Update revision to 20181029.
* PCB: Bump minimum mask web down a tiny bit because KiCad is having trouble with math.
* Update schematic
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Clock Manager: Actually store chosen clock reference
Similarly-named local was covering a member and discarding the value.
* Clock Manager: Reference type which contains source, frequency.
* Setup: Display reference source, frequency in frequency correction screen.
* LPC43xx API: Add extern "C" for use from C++.
* Use LPC43xx API for SGPIO, GPDMA, I2S initialization.
* I2S: Add BASE_AUDIO_CLK management.
* Add MOTOCON_PWM clock/reset structure.
* Serial: Fix dumb typos.
* Serial: Remove extra reference operator.
* Serial: Cut-and-paste error in structure type name.
* Move SCU structure from PAL to LPC43xx API.
It'd be nice if I gave some thought to where code should live before I commit it.
* VAA power: Move code to HackRF board file
It doesn't belong in PAL.
* MAX5 CPLD: Add SAMPLE and EXTEST methods.
* Flash image: Change packing scheme to use flash more efficiently.
Application is now a single image for both M4 bootstrap and M0.
Baseband images come immediately after application binary. No need to align to large blocks (and waste lots of flash).
* Clock Manager: Remove PLL1 power down function.
* Move and rename peripherals reset function to board module.
* Remove unused peripheral/clock management.
* Clock Manager: Extract switch to IRC into separate function.
* Clock Manager: More explicit shutdown of clocks, clock generator.
* Move initialization to board module.
* ChibiOS: Rename "application" board, add "baseband" board.
There are now two ChibiOS "boards", one which runs the application and does the hardware setup. The other board, "baseband", does very little setup.
* Clock Manager: Remove unused crystal enable/disable code.
* Clock Manager: Restore clock configuration to SPIFI bootloader state before app shutdown.
* Reset peripherals on app shutdown.
Be careful not to reset M0APP (the core we're running on) or GPIO (which is holding the hardware in a stable state).
* M4/baseband hal_lld_init: use IDIVA, which is configured earlier by M0.
This was causing problems during restart into HackRF mode. Baseband hal_lld_init changed M4 clock from IDIVA (set by M0) to PLL1, which was unceremoniously turned off during shutdown.
* Audio app: Stop audio PLL on shutdown.
* M4 HAL: Make LPC43XX_M4_CLK_SRC optional.
This was changing the BASE_M4_CLK when a baseband was run.
* LPC43xx C++ layer: Fix IDIVx constructor IDIV narrow field width.
* Application board: hide the peripherals_reset function, as it isn't useful except during hardware init.
* Consolidate hardware init code to some degree.
ClockManager is super-overloaded and murky in its purpose.
Migrate audio from IDIVC to IDIVD, to more closely resemble initial clock scheme, so it's simpler to get back to it during shutdown.
* Migrate some startup code to application board.
* Si5351: Use correct methods for reset().
update_output_enable_control() doesn't reset the enabled outputs to the reset state, unless the object is freshly initialized, which it isn't when performing firmware shutdown.
For similar reasons, use set_clock_control() instead of setting internal state and then using the update function.
* GPIO: Set SPIFI CS pin to match input buffer state coming out of bootloader.
* Change application board.c to .cpp, with required dependent changes
* Board: Clean up SCU configuration code/data.
* I2S: Add shutdown code and use it.
* LPC43xx: Consolidate a bunch of structures that had been scattered all over.
...because I'm an undisciplined coder.
* I2S: Fix ordering of branch and base clock disable.
Core was hanging, presumably because the register interface on the branch/peripheral was unresponsive after the base clock was disabled.
* Controls: Save and expose raw navigation wheel switch state
I need to do some work on debouncing and ignoring simultaneous key presses.
* Controls: Add debug view for switches state.
* Controls: Ignore all key presses until all keys are released.
This should address some mechanical quirks of the navigation wheel used on the PortaPack.
* Clock Manager: Wait for only the necessary PLL to lock.
Wasn't working on PortaPacks without a built-in clock reference, as that uses the other PLL.
TODO: Switching PLLs may be kind of pointless now...
* CMake: Pull HackRF project from GitHub and build.
* CMake: Remove commented code.
* CMake: Clone HackRF via HTTPS, not SSH.
* CMake: Extra pause for slow post-DFU firmware boot-up.
* CMake: TODO to fix SVF/XSVF file source.
* CMake: Ask HackRF hackrf_usb to make DFU binary.
* Travis-CI: Add dfu-util, now that HackRF firmware is being built for inclusion.
* Travis-CI: Update build environment to Ubuntu xenial
Previously Trusty.
* Travis-CI: Incorrectly structured my request for dfu-util package.
I'm soooo talented.
* ldscript: Mark flash, ram with correct R/W/X flags.
* ldscript: Enlarge M0 flash region to 1Mbyte, the size of the HackRF SPI flash.
* Receiver: Hide PPM adjustment if clock source is not HackRF crystal.
* Documentation: Update product photos and README.
* Documentation: Add TCXO feature to README description.
* Application: Rearrange files to match HAVOC directory structure.
* Map view in AIS (#213)
* Added GeoMapView to AISRecentEntryDetailView
* Added autoupdate in AIS map
* Revert "Map view in AIS (#213)"
This reverts commit 262c030224b9ea3e56ff1c8a66246e7ecf30e41f.
This commit will be cherry-picked onto a clean branch, then re-committed after a troublesome pull request is reverted.
* Revert "Upstream merge to make new revision of PortaPack work (#206)"
This reverts commit 920b98f7c9a30371b643c42949066fb7d2441daf.
This pull request was missing some changes and was preventing firmware from functioning on older PortaPacks.
* CPLD: Pull bitstream from HackRF project.
* SGPIO: Identify pins on CPLD by their new functions. Pull down HOST_SYNC_EN.
* CPLD: Don't load HackRF CPLD bitstream into RAM.
Trying to converge CPLD implementations, so this shouldn't be necesssary. HOWEVER, it would be good to *check* the CPLD contents and provide a way to update, if necessary.
* CPLD: Tweak clock generator config to match CPLD timing changes in HackRF.
* PinConfig: Drive CPLD pins correctly.
* CMake: Use jboone/hackrf master branch, now that CPLD fixes are there.
* CMake: Fix HackRF CPLD SVF dependency.
Build would break on the first pass, but work if you restarted make.
* CMake: Fix my misuse of the HackRF CMake configuration -- was building from too deep in the directory tree
* CMake: Work-around for CMake 3.5 not supporting ExternalProject_Add SOURCE_SUBDIR.
* CMake: Choose a CMP0005 policy to quiet CMake warnings.
* Settings: Show active clock reference. Only show PPM adjustment for HackRF source.
* Setup: Format clock reference frequency in MHz, not Hz.
* Radio Settings: Change reference clock text color.
Make consistent color with other un-editable text.
TODO: This is a bit of a hack to get ui::Text objects to support custom colors, like the Label structures used elsewhere.
* Pin config: VREGMODE=1, add other pins for completeness, comment detail
* Pin setup: More useful comments.
* Pin setup: Change some defaults, only set up PortaPack pins if detected.
* Pin setup: Disable LPC pull-ups on PP CPLD data bus, as CPLD is pulling up.
* Baseband: Allow larger HackRF firmware image.
* HackRF: Remove USER_INTERFACE CMake variable.
* CPLD: Make use of HackRF CPLD tool to generate code.
* Release: Add generation of MD5SUMS, SHA256SUMS during "make release"
* Clock generator: Match clock output currents to HackRF firmware.
Someday, we will share a code base again...
* CMake: Make "firmware" target part of the "all" target.
So now an unqualified "make" will make the firmware binary.
* CMake: Change how HackRF firmware is incorporated into binary.
Use the separate HackRF "RAM" binary. Get rid of the strip-dfu utility, since there's no longer a need to extract the binary from the DFU.
* CMake: Renamed GIT_REVISION* -> GIT_VERSION* to match HackRF build env.
* CMake: Bring git version handling closer to HackRF for code reuse.
* Travis-CI: Rework CI release artifact output.
* Travis-CI: Don't assign PROJECT_NAME within deploy-nightly.sh
* Travis-CI: Oops, don't include distro package for compiler...
...when also installing it from a third-party PPA.
* Travis-CI: Update GCC package, old one seems "retired"?
* Travis-CI: OK, the gcc-arm-none-eabi package is NOT current. Undoing...
* Travis-CI: Path oopsies.
* Travis-CI: More path confusion. I think this will do it. *touch wood*
* Travis-CI: Update build message sent to FreeNode #portapack IRC.
* Travis-CI: Break out BUILD_DATE from BUILD_NAME.
* Travis-CI: Introduce build directories, include MD5 and SHA256 hashes.
* Travis-CI: Fix MD5SUMS/SHA256SUMS paths.
* Travis-CI: Fix typo generating name for binary links.
* Power: Keep 1V8 off until after VAA is brought up.
* Power: Bring up VAA in several steps to keep voltage swing small.
* About: Show longer commit/tag version string.
* Versioning: Report non-CI builds with "local-" version prefix.
* Travis-CI: Report new nightly build site in IRC notification.
* Change use of GIT_VERSION to VERSION_STRING
Required by prior merge.
* Git: add "hackrf" submodule.
* CMake: Use hackrf submodule for build, stop pulling during build.
* Travis: Fix build paths due to CMake submodule changes.
* Travis: Explicitly update submodules recursively
* Revert "Travis: Explicitly update submodules recursively"
This reverts commit b246438d805f431e727e01b7407540e932e89ee1.
* Travis: Try to sort out hackrf submodule output paths...
* Travis: I don't know what I'm doing.
* CMake: "make firmware" problem due to target vs. path used for dependency.
* HackRF: Incorporate YAML security fix.
* CMake: Fix more places where targets should be used...
...instead of paths to outputs.
* CMake: Add DFU file to "make firmware" outputs
* HackRF: Update submodule for CMake m0_bin.s path fix.
* added encoder support to alphanum
* added encoder support to freq-keypad
* UI Redesign -
added BtnGrid & NewButton widgets and created a new button-based
layout, with both encoder and touchscreen are supported.
* Scanner changes:
- using SCANNER.TXT for frequencies, ranges also supported. file
format is the same as any other frequency file, thus can be edited
via the Frequency Manager.
- add nfm bw selector & time-to-wait to the UI
- add SCANNER.TXT to sdcard dir
orignal idea & scanner file adopted from user 'bicurico'
* small changes to scanner
* remember last category on frequency manager
* fix: cast int16_t instead of uint16_t (although i doubt we will
have more than 32767 buttons in the array...)
* added a missing last_category_id on freq manager
2019-10-29 23:53:54 +02:00
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}
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void NewButton::paint(Painter& painter) {
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2023-05-19 08:16:05 +12:00
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if (!bitmap_ && text_.empty())
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return;
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Color bg, fg;
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const auto r = screen_rect();
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if (has_focus() || highlighted()) {
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bg = style().foreground;
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fg = Color::black();
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} else {
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bg = Color::grey();
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fg = style().foreground;
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}
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const Style paint_style = {style().font, bg, fg};
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painter.draw_rectangle({r.location(), {r.size().width(), 1}}, Color::light_grey());
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painter.draw_rectangle({r.location().x(), r.location().y() + r.size().height() - 1, r.size().width(), 1}, Color::dark_grey());
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painter.draw_rectangle({r.location().x() + r.size().width() - 1, r.location().y(), 1, r.size().height()}, Color::dark_grey());
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painter.fill_rectangle(
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{r.location().x(), r.location().y() + 1, r.size().width() - 1, r.size().height() - 2},
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paint_style.background);
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int y = r.location().y();
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if (bitmap_) {
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painter.draw_bitmap(
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{r.location().x() + (r.size().width() / 2) - 8, r.location().y() + 6},
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*bitmap_,
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color_, // Color::green(), //fg,
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bg);
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y += 10;
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}
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const auto label_r = paint_style.font.size_of(text_);
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painter.draw_string(
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{r.location().x() + (r.size().width() - label_r.width()) / 2, y + (r.size().height() - label_r.height()) / 2},
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paint_style,
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text_);
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UI Redesign for Portapack-Havoc (#268)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* PCB: Change PCB stackup, Tg, clarify solder mask color, use more metric.
* PCB: Move HackRF header P9 to B.CrtYd layer.
* PCB: Change a Tg reference I missed.
* PCB: Update footprints for parts with mismatched CAD->tape rotation.
Adjust a few layer choice and line thickness bits.
* PCB: Got cold feet, switched back to rectangular pads.
* PCB: Add Eco layers to be visible and Gerber output.
* PCB: Use aux origin for plotting, for tidier coordinates.
* PCB: Output Gerber job file, because why not?
* Schematic: Correct footprints for two reference-related components.
* Schematic: Remove manfuacturer and part number for DNP component.
* Schematic: Specify resistor value, manufacturer, part number for reference oscillator series termination.
* PCB: Update netlist and footprints from schematic.
* Netlist: Updated component values, footprints.
* PCB: Nudge some components and traces to address DRC clearance violations.
* PCB: Allow KiCad to update zone timestamps (again?!).
* PCB: Generate *all* Gerber layers.
* Schematic, PCB: Update revision to 20181025.
* PCB: Adjust fab layer annotations orientation and font size.
* PCB: Hide mounting hole reference designators on silk layer.
* PCB: Shrink U1, U3 pads to get 0.2mm space between pads.
* PCB: Set pad-to-mask clearance to zero, leave up to fab. Set minimum mask web to 0.2mm for non-black options.
* PCB: Revise U1 pad shape, mask, paste, thermal drills.
Clearance is improved at corner pads.
* PCB: Tweak U3 for better thermal pad/drill/mask/paste design.
* PCB: Change solder mask color to blue.
* Schematic, PCB: Update revision to 20181029.
* PCB: Bump minimum mask web down a tiny bit because KiCad is having trouble with math.
* Update schematic
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Clock Manager: Actually store chosen clock reference
Similarly-named local was covering a member and discarding the value.
* Clock Manager: Reference type which contains source, frequency.
* Setup: Display reference source, frequency in frequency correction screen.
* LPC43xx API: Add extern "C" for use from C++.
* Use LPC43xx API for SGPIO, GPDMA, I2S initialization.
* I2S: Add BASE_AUDIO_CLK management.
* Add MOTOCON_PWM clock/reset structure.
* Serial: Fix dumb typos.
* Serial: Remove extra reference operator.
* Serial: Cut-and-paste error in structure type name.
* Move SCU structure from PAL to LPC43xx API.
It'd be nice if I gave some thought to where code should live before I commit it.
* VAA power: Move code to HackRF board file
It doesn't belong in PAL.
* MAX5 CPLD: Add SAMPLE and EXTEST methods.
* Flash image: Change packing scheme to use flash more efficiently.
Application is now a single image for both M4 bootstrap and M0.
Baseband images come immediately after application binary. No need to align to large blocks (and waste lots of flash).
* Clock Manager: Remove PLL1 power down function.
* Move and rename peripherals reset function to board module.
* Remove unused peripheral/clock management.
* Clock Manager: Extract switch to IRC into separate function.
* Clock Manager: More explicit shutdown of clocks, clock generator.
* Move initialization to board module.
* ChibiOS: Rename "application" board, add "baseband" board.
There are now two ChibiOS "boards", one which runs the application and does the hardware setup. The other board, "baseband", does very little setup.
* Clock Manager: Remove unused crystal enable/disable code.
* Clock Manager: Restore clock configuration to SPIFI bootloader state before app shutdown.
* Reset peripherals on app shutdown.
Be careful not to reset M0APP (the core we're running on) or GPIO (which is holding the hardware in a stable state).
* M4/baseband hal_lld_init: use IDIVA, which is configured earlier by M0.
This was causing problems during restart into HackRF mode. Baseband hal_lld_init changed M4 clock from IDIVA (set by M0) to PLL1, which was unceremoniously turned off during shutdown.
* Audio app: Stop audio PLL on shutdown.
* M4 HAL: Make LPC43XX_M4_CLK_SRC optional.
This was changing the BASE_M4_CLK when a baseband was run.
* LPC43xx C++ layer: Fix IDIVx constructor IDIV narrow field width.
* Application board: hide the peripherals_reset function, as it isn't useful except during hardware init.
* Consolidate hardware init code to some degree.
ClockManager is super-overloaded and murky in its purpose.
Migrate audio from IDIVC to IDIVD, to more closely resemble initial clock scheme, so it's simpler to get back to it during shutdown.
* Migrate some startup code to application board.
* Si5351: Use correct methods for reset().
update_output_enable_control() doesn't reset the enabled outputs to the reset state, unless the object is freshly initialized, which it isn't when performing firmware shutdown.
For similar reasons, use set_clock_control() instead of setting internal state and then using the update function.
* GPIO: Set SPIFI CS pin to match input buffer state coming out of bootloader.
* Change application board.c to .cpp, with required dependent changes
* Board: Clean up SCU configuration code/data.
* I2S: Add shutdown code and use it.
* LPC43xx: Consolidate a bunch of structures that had been scattered all over.
...because I'm an undisciplined coder.
* I2S: Fix ordering of branch and base clock disable.
Core was hanging, presumably because the register interface on the branch/peripheral was unresponsive after the base clock was disabled.
* Controls: Save and expose raw navigation wheel switch state
I need to do some work on debouncing and ignoring simultaneous key presses.
* Controls: Add debug view for switches state.
* Controls: Ignore all key presses until all keys are released.
This should address some mechanical quirks of the navigation wheel used on the PortaPack.
* Clock Manager: Wait for only the necessary PLL to lock.
Wasn't working on PortaPacks without a built-in clock reference, as that uses the other PLL.
TODO: Switching PLLs may be kind of pointless now...
* CMake: Pull HackRF project from GitHub and build.
* CMake: Remove commented code.
* CMake: Clone HackRF via HTTPS, not SSH.
* CMake: Extra pause for slow post-DFU firmware boot-up.
* CMake: TODO to fix SVF/XSVF file source.
* CMake: Ask HackRF hackrf_usb to make DFU binary.
* Travis-CI: Add dfu-util, now that HackRF firmware is being built for inclusion.
* Travis-CI: Update build environment to Ubuntu xenial
Previously Trusty.
* Travis-CI: Incorrectly structured my request for dfu-util package.
I'm soooo talented.
* ldscript: Mark flash, ram with correct R/W/X flags.
* ldscript: Enlarge M0 flash region to 1Mbyte, the size of the HackRF SPI flash.
* Receiver: Hide PPM adjustment if clock source is not HackRF crystal.
* Documentation: Update product photos and README.
* Documentation: Add TCXO feature to README description.
* Application: Rearrange files to match HAVOC directory structure.
* Map view in AIS (#213)
* Added GeoMapView to AISRecentEntryDetailView
* Added autoupdate in AIS map
* Revert "Map view in AIS (#213)"
This reverts commit 262c030224b9ea3e56ff1c8a66246e7ecf30e41f.
This commit will be cherry-picked onto a clean branch, then re-committed after a troublesome pull request is reverted.
* Revert "Upstream merge to make new revision of PortaPack work (#206)"
This reverts commit 920b98f7c9a30371b643c42949066fb7d2441daf.
This pull request was missing some changes and was preventing firmware from functioning on older PortaPacks.
* CPLD: Pull bitstream from HackRF project.
* SGPIO: Identify pins on CPLD by their new functions. Pull down HOST_SYNC_EN.
* CPLD: Don't load HackRF CPLD bitstream into RAM.
Trying to converge CPLD implementations, so this shouldn't be necesssary. HOWEVER, it would be good to *check* the CPLD contents and provide a way to update, if necessary.
* CPLD: Tweak clock generator config to match CPLD timing changes in HackRF.
* PinConfig: Drive CPLD pins correctly.
* CMake: Use jboone/hackrf master branch, now that CPLD fixes are there.
* CMake: Fix HackRF CPLD SVF dependency.
Build would break on the first pass, but work if you restarted make.
* CMake: Fix my misuse of the HackRF CMake configuration -- was building from too deep in the directory tree
* CMake: Work-around for CMake 3.5 not supporting ExternalProject_Add SOURCE_SUBDIR.
* CMake: Choose a CMP0005 policy to quiet CMake warnings.
* Settings: Show active clock reference. Only show PPM adjustment for HackRF source.
* Setup: Format clock reference frequency in MHz, not Hz.
* Radio Settings: Change reference clock text color.
Make consistent color with other un-editable text.
TODO: This is a bit of a hack to get ui::Text objects to support custom colors, like the Label structures used elsewhere.
* Pin config: VREGMODE=1, add other pins for completeness, comment detail
* Pin setup: More useful comments.
* Pin setup: Change some defaults, only set up PortaPack pins if detected.
* Pin setup: Disable LPC pull-ups on PP CPLD data bus, as CPLD is pulling up.
* Baseband: Allow larger HackRF firmware image.
* HackRF: Remove USER_INTERFACE CMake variable.
* CPLD: Make use of HackRF CPLD tool to generate code.
* Release: Add generation of MD5SUMS, SHA256SUMS during "make release"
* Clock generator: Match clock output currents to HackRF firmware.
Someday, we will share a code base again...
* CMake: Make "firmware" target part of the "all" target.
So now an unqualified "make" will make the firmware binary.
* CMake: Change how HackRF firmware is incorporated into binary.
Use the separate HackRF "RAM" binary. Get rid of the strip-dfu utility, since there's no longer a need to extract the binary from the DFU.
* CMake: Renamed GIT_REVISION* -> GIT_VERSION* to match HackRF build env.
* CMake: Bring git version handling closer to HackRF for code reuse.
* Travis-CI: Rework CI release artifact output.
* Travis-CI: Don't assign PROJECT_NAME within deploy-nightly.sh
* Travis-CI: Oops, don't include distro package for compiler...
...when also installing it from a third-party PPA.
* Travis-CI: Update GCC package, old one seems "retired"?
* Travis-CI: OK, the gcc-arm-none-eabi package is NOT current. Undoing...
* Travis-CI: Path oopsies.
* Travis-CI: More path confusion. I think this will do it. *touch wood*
* Travis-CI: Update build message sent to FreeNode #portapack IRC.
* Travis-CI: Break out BUILD_DATE from BUILD_NAME.
* Travis-CI: Introduce build directories, include MD5 and SHA256 hashes.
* Travis-CI: Fix MD5SUMS/SHA256SUMS paths.
* Travis-CI: Fix typo generating name for binary links.
* Power: Keep 1V8 off until after VAA is brought up.
* Power: Bring up VAA in several steps to keep voltage swing small.
* About: Show longer commit/tag version string.
* Versioning: Report non-CI builds with "local-" version prefix.
* Travis-CI: Report new nightly build site in IRC notification.
* Change use of GIT_VERSION to VERSION_STRING
Required by prior merge.
* Git: add "hackrf" submodule.
* CMake: Use hackrf submodule for build, stop pulling during build.
* Travis: Fix build paths due to CMake submodule changes.
* Travis: Explicitly update submodules recursively
* Revert "Travis: Explicitly update submodules recursively"
This reverts commit b246438d805f431e727e01b7407540e932e89ee1.
* Travis: Try to sort out hackrf submodule output paths...
* Travis: I don't know what I'm doing.
* CMake: "make firmware" problem due to target vs. path used for dependency.
* HackRF: Incorporate YAML security fix.
* CMake: Fix more places where targets should be used...
...instead of paths to outputs.
* CMake: Add DFU file to "make firmware" outputs
* HackRF: Update submodule for CMake m0_bin.s path fix.
* added encoder support to alphanum
* added encoder support to freq-keypad
* UI Redesign -
added BtnGrid & NewButton widgets and created a new button-based
layout, with both encoder and touchscreen are supported.
* Scanner changes:
- using SCANNER.TXT for frequencies, ranges also supported. file
format is the same as any other frequency file, thus can be edited
via the Frequency Manager.
- add nfm bw selector & time-to-wait to the UI
- add SCANNER.TXT to sdcard dir
orignal idea & scanner file adopted from user 'bicurico'
* small changes to scanner
* remember last category on frequency manager
* fix: cast int16_t instead of uint16_t (although i doubt we will
have more than 32767 buttons in the array...)
* added a missing last_category_id on freq manager
2019-10-29 23:53:54 +02:00
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}
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void NewButton::on_focus() {
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2023-05-19 08:16:05 +12:00
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if (on_highlight)
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on_highlight(*this);
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UI Redesign for Portapack-Havoc (#268)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* PCB: Change PCB stackup, Tg, clarify solder mask color, use more metric.
* PCB: Move HackRF header P9 to B.CrtYd layer.
* PCB: Change a Tg reference I missed.
* PCB: Update footprints for parts with mismatched CAD->tape rotation.
Adjust a few layer choice and line thickness bits.
* PCB: Got cold feet, switched back to rectangular pads.
* PCB: Add Eco layers to be visible and Gerber output.
* PCB: Use aux origin for plotting, for tidier coordinates.
* PCB: Output Gerber job file, because why not?
* Schematic: Correct footprints for two reference-related components.
* Schematic: Remove manfuacturer and part number for DNP component.
* Schematic: Specify resistor value, manufacturer, part number for reference oscillator series termination.
* PCB: Update netlist and footprints from schematic.
* Netlist: Updated component values, footprints.
* PCB: Nudge some components and traces to address DRC clearance violations.
* PCB: Allow KiCad to update zone timestamps (again?!).
* PCB: Generate *all* Gerber layers.
* Schematic, PCB: Update revision to 20181025.
* PCB: Adjust fab layer annotations orientation and font size.
* PCB: Hide mounting hole reference designators on silk layer.
* PCB: Shrink U1, U3 pads to get 0.2mm space between pads.
* PCB: Set pad-to-mask clearance to zero, leave up to fab. Set minimum mask web to 0.2mm for non-black options.
* PCB: Revise U1 pad shape, mask, paste, thermal drills.
Clearance is improved at corner pads.
* PCB: Tweak U3 for better thermal pad/drill/mask/paste design.
* PCB: Change solder mask color to blue.
* Schematic, PCB: Update revision to 20181029.
* PCB: Bump minimum mask web down a tiny bit because KiCad is having trouble with math.
* Update schematic
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Clock Manager: Actually store chosen clock reference
Similarly-named local was covering a member and discarding the value.
* Clock Manager: Reference type which contains source, frequency.
* Setup: Display reference source, frequency in frequency correction screen.
* LPC43xx API: Add extern "C" for use from C++.
* Use LPC43xx API for SGPIO, GPDMA, I2S initialization.
* I2S: Add BASE_AUDIO_CLK management.
* Add MOTOCON_PWM clock/reset structure.
* Serial: Fix dumb typos.
* Serial: Remove extra reference operator.
* Serial: Cut-and-paste error in structure type name.
* Move SCU structure from PAL to LPC43xx API.
It'd be nice if I gave some thought to where code should live before I commit it.
* VAA power: Move code to HackRF board file
It doesn't belong in PAL.
* MAX5 CPLD: Add SAMPLE and EXTEST methods.
* Flash image: Change packing scheme to use flash more efficiently.
Application is now a single image for both M4 bootstrap and M0.
Baseband images come immediately after application binary. No need to align to large blocks (and waste lots of flash).
* Clock Manager: Remove PLL1 power down function.
* Move and rename peripherals reset function to board module.
* Remove unused peripheral/clock management.
* Clock Manager: Extract switch to IRC into separate function.
* Clock Manager: More explicit shutdown of clocks, clock generator.
* Move initialization to board module.
* ChibiOS: Rename "application" board, add "baseband" board.
There are now two ChibiOS "boards", one which runs the application and does the hardware setup. The other board, "baseband", does very little setup.
* Clock Manager: Remove unused crystal enable/disable code.
* Clock Manager: Restore clock configuration to SPIFI bootloader state before app shutdown.
* Reset peripherals on app shutdown.
Be careful not to reset M0APP (the core we're running on) or GPIO (which is holding the hardware in a stable state).
* M4/baseband hal_lld_init: use IDIVA, which is configured earlier by M0.
This was causing problems during restart into HackRF mode. Baseband hal_lld_init changed M4 clock from IDIVA (set by M0) to PLL1, which was unceremoniously turned off during shutdown.
* Audio app: Stop audio PLL on shutdown.
* M4 HAL: Make LPC43XX_M4_CLK_SRC optional.
This was changing the BASE_M4_CLK when a baseband was run.
* LPC43xx C++ layer: Fix IDIVx constructor IDIV narrow field width.
* Application board: hide the peripherals_reset function, as it isn't useful except during hardware init.
* Consolidate hardware init code to some degree.
ClockManager is super-overloaded and murky in its purpose.
Migrate audio from IDIVC to IDIVD, to more closely resemble initial clock scheme, so it's simpler to get back to it during shutdown.
* Migrate some startup code to application board.
* Si5351: Use correct methods for reset().
update_output_enable_control() doesn't reset the enabled outputs to the reset state, unless the object is freshly initialized, which it isn't when performing firmware shutdown.
For similar reasons, use set_clock_control() instead of setting internal state and then using the update function.
* GPIO: Set SPIFI CS pin to match input buffer state coming out of bootloader.
* Change application board.c to .cpp, with required dependent changes
* Board: Clean up SCU configuration code/data.
* I2S: Add shutdown code and use it.
* LPC43xx: Consolidate a bunch of structures that had been scattered all over.
...because I'm an undisciplined coder.
* I2S: Fix ordering of branch and base clock disable.
Core was hanging, presumably because the register interface on the branch/peripheral was unresponsive after the base clock was disabled.
* Controls: Save and expose raw navigation wheel switch state
I need to do some work on debouncing and ignoring simultaneous key presses.
* Controls: Add debug view for switches state.
* Controls: Ignore all key presses until all keys are released.
This should address some mechanical quirks of the navigation wheel used on the PortaPack.
* Clock Manager: Wait for only the necessary PLL to lock.
Wasn't working on PortaPacks without a built-in clock reference, as that uses the other PLL.
TODO: Switching PLLs may be kind of pointless now...
* CMake: Pull HackRF project from GitHub and build.
* CMake: Remove commented code.
* CMake: Clone HackRF via HTTPS, not SSH.
* CMake: Extra pause for slow post-DFU firmware boot-up.
* CMake: TODO to fix SVF/XSVF file source.
* CMake: Ask HackRF hackrf_usb to make DFU binary.
* Travis-CI: Add dfu-util, now that HackRF firmware is being built for inclusion.
* Travis-CI: Update build environment to Ubuntu xenial
Previously Trusty.
* Travis-CI: Incorrectly structured my request for dfu-util package.
I'm soooo talented.
* ldscript: Mark flash, ram with correct R/W/X flags.
* ldscript: Enlarge M0 flash region to 1Mbyte, the size of the HackRF SPI flash.
* Receiver: Hide PPM adjustment if clock source is not HackRF crystal.
* Documentation: Update product photos and README.
* Documentation: Add TCXO feature to README description.
* Application: Rearrange files to match HAVOC directory structure.
* Map view in AIS (#213)
* Added GeoMapView to AISRecentEntryDetailView
* Added autoupdate in AIS map
* Revert "Map view in AIS (#213)"
This reverts commit 262c030224b9ea3e56ff1c8a66246e7ecf30e41f.
This commit will be cherry-picked onto a clean branch, then re-committed after a troublesome pull request is reverted.
* Revert "Upstream merge to make new revision of PortaPack work (#206)"
This reverts commit 920b98f7c9a30371b643c42949066fb7d2441daf.
This pull request was missing some changes and was preventing firmware from functioning on older PortaPacks.
* CPLD: Pull bitstream from HackRF project.
* SGPIO: Identify pins on CPLD by their new functions. Pull down HOST_SYNC_EN.
* CPLD: Don't load HackRF CPLD bitstream into RAM.
Trying to converge CPLD implementations, so this shouldn't be necesssary. HOWEVER, it would be good to *check* the CPLD contents and provide a way to update, if necessary.
* CPLD: Tweak clock generator config to match CPLD timing changes in HackRF.
* PinConfig: Drive CPLD pins correctly.
* CMake: Use jboone/hackrf master branch, now that CPLD fixes are there.
* CMake: Fix HackRF CPLD SVF dependency.
Build would break on the first pass, but work if you restarted make.
* CMake: Fix my misuse of the HackRF CMake configuration -- was building from too deep in the directory tree
* CMake: Work-around for CMake 3.5 not supporting ExternalProject_Add SOURCE_SUBDIR.
* CMake: Choose a CMP0005 policy to quiet CMake warnings.
* Settings: Show active clock reference. Only show PPM adjustment for HackRF source.
* Setup: Format clock reference frequency in MHz, not Hz.
* Radio Settings: Change reference clock text color.
Make consistent color with other un-editable text.
TODO: This is a bit of a hack to get ui::Text objects to support custom colors, like the Label structures used elsewhere.
* Pin config: VREGMODE=1, add other pins for completeness, comment detail
* Pin setup: More useful comments.
* Pin setup: Change some defaults, only set up PortaPack pins if detected.
* Pin setup: Disable LPC pull-ups on PP CPLD data bus, as CPLD is pulling up.
* Baseband: Allow larger HackRF firmware image.
* HackRF: Remove USER_INTERFACE CMake variable.
* CPLD: Make use of HackRF CPLD tool to generate code.
* Release: Add generation of MD5SUMS, SHA256SUMS during "make release"
* Clock generator: Match clock output currents to HackRF firmware.
Someday, we will share a code base again...
* CMake: Make "firmware" target part of the "all" target.
So now an unqualified "make" will make the firmware binary.
* CMake: Change how HackRF firmware is incorporated into binary.
Use the separate HackRF "RAM" binary. Get rid of the strip-dfu utility, since there's no longer a need to extract the binary from the DFU.
* CMake: Renamed GIT_REVISION* -> GIT_VERSION* to match HackRF build env.
* CMake: Bring git version handling closer to HackRF for code reuse.
* Travis-CI: Rework CI release artifact output.
* Travis-CI: Don't assign PROJECT_NAME within deploy-nightly.sh
* Travis-CI: Oops, don't include distro package for compiler...
...when also installing it from a third-party PPA.
* Travis-CI: Update GCC package, old one seems "retired"?
* Travis-CI: OK, the gcc-arm-none-eabi package is NOT current. Undoing...
* Travis-CI: Path oopsies.
* Travis-CI: More path confusion. I think this will do it. *touch wood*
* Travis-CI: Update build message sent to FreeNode #portapack IRC.
* Travis-CI: Break out BUILD_DATE from BUILD_NAME.
* Travis-CI: Introduce build directories, include MD5 and SHA256 hashes.
* Travis-CI: Fix MD5SUMS/SHA256SUMS paths.
* Travis-CI: Fix typo generating name for binary links.
* Power: Keep 1V8 off until after VAA is brought up.
* Power: Bring up VAA in several steps to keep voltage swing small.
* About: Show longer commit/tag version string.
* Versioning: Report non-CI builds with "local-" version prefix.
* Travis-CI: Report new nightly build site in IRC notification.
* Change use of GIT_VERSION to VERSION_STRING
Required by prior merge.
* Git: add "hackrf" submodule.
* CMake: Use hackrf submodule for build, stop pulling during build.
* Travis: Fix build paths due to CMake submodule changes.
* Travis: Explicitly update submodules recursively
* Revert "Travis: Explicitly update submodules recursively"
This reverts commit b246438d805f431e727e01b7407540e932e89ee1.
* Travis: Try to sort out hackrf submodule output paths...
* Travis: I don't know what I'm doing.
* CMake: "make firmware" problem due to target vs. path used for dependency.
* HackRF: Incorporate YAML security fix.
* CMake: Fix more places where targets should be used...
...instead of paths to outputs.
* CMake: Add DFU file to "make firmware" outputs
* HackRF: Update submodule for CMake m0_bin.s path fix.
* added encoder support to alphanum
* added encoder support to freq-keypad
* UI Redesign -
added BtnGrid & NewButton widgets and created a new button-based
layout, with both encoder and touchscreen are supported.
* Scanner changes:
- using SCANNER.TXT for frequencies, ranges also supported. file
format is the same as any other frequency file, thus can be edited
via the Frequency Manager.
- add nfm bw selector & time-to-wait to the UI
- add SCANNER.TXT to sdcard dir
orignal idea & scanner file adopted from user 'bicurico'
* small changes to scanner
* remember last category on frequency manager
* fix: cast int16_t instead of uint16_t (although i doubt we will
have more than 32767 buttons in the array...)
* added a missing last_category_id on freq manager
2019-10-29 23:53:54 +02:00
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}
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bool NewButton::on_key(const KeyEvent key) {
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2023-05-19 08:16:05 +12:00
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if (key == KeyEvent::Select) {
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if (on_select) {
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on_select();
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return true;
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}
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} else {
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if (on_dir) {
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return on_dir(*this, key);
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}
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}
|
UI Redesign for Portapack-Havoc (#268)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* PCB: Change PCB stackup, Tg, clarify solder mask color, use more metric.
* PCB: Move HackRF header P9 to B.CrtYd layer.
* PCB: Change a Tg reference I missed.
* PCB: Update footprints for parts with mismatched CAD->tape rotation.
Adjust a few layer choice and line thickness bits.
* PCB: Got cold feet, switched back to rectangular pads.
* PCB: Add Eco layers to be visible and Gerber output.
* PCB: Use aux origin for plotting, for tidier coordinates.
* PCB: Output Gerber job file, because why not?
* Schematic: Correct footprints for two reference-related components.
* Schematic: Remove manfuacturer and part number for DNP component.
* Schematic: Specify resistor value, manufacturer, part number for reference oscillator series termination.
* PCB: Update netlist and footprints from schematic.
* Netlist: Updated component values, footprints.
* PCB: Nudge some components and traces to address DRC clearance violations.
* PCB: Allow KiCad to update zone timestamps (again?!).
* PCB: Generate *all* Gerber layers.
* Schematic, PCB: Update revision to 20181025.
* PCB: Adjust fab layer annotations orientation and font size.
* PCB: Hide mounting hole reference designators on silk layer.
* PCB: Shrink U1, U3 pads to get 0.2mm space between pads.
* PCB: Set pad-to-mask clearance to zero, leave up to fab. Set minimum mask web to 0.2mm for non-black options.
* PCB: Revise U1 pad shape, mask, paste, thermal drills.
Clearance is improved at corner pads.
* PCB: Tweak U3 for better thermal pad/drill/mask/paste design.
* PCB: Change solder mask color to blue.
* Schematic, PCB: Update revision to 20181029.
* PCB: Bump minimum mask web down a tiny bit because KiCad is having trouble with math.
* Update schematic
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Clock Manager: Actually store chosen clock reference
Similarly-named local was covering a member and discarding the value.
* Clock Manager: Reference type which contains source, frequency.
* Setup: Display reference source, frequency in frequency correction screen.
* LPC43xx API: Add extern "C" for use from C++.
* Use LPC43xx API for SGPIO, GPDMA, I2S initialization.
* I2S: Add BASE_AUDIO_CLK management.
* Add MOTOCON_PWM clock/reset structure.
* Serial: Fix dumb typos.
* Serial: Remove extra reference operator.
* Serial: Cut-and-paste error in structure type name.
* Move SCU structure from PAL to LPC43xx API.
It'd be nice if I gave some thought to where code should live before I commit it.
* VAA power: Move code to HackRF board file
It doesn't belong in PAL.
* MAX5 CPLD: Add SAMPLE and EXTEST methods.
* Flash image: Change packing scheme to use flash more efficiently.
Application is now a single image for both M4 bootstrap and M0.
Baseband images come immediately after application binary. No need to align to large blocks (and waste lots of flash).
* Clock Manager: Remove PLL1 power down function.
* Move and rename peripherals reset function to board module.
* Remove unused peripheral/clock management.
* Clock Manager: Extract switch to IRC into separate function.
* Clock Manager: More explicit shutdown of clocks, clock generator.
* Move initialization to board module.
* ChibiOS: Rename "application" board, add "baseband" board.
There are now two ChibiOS "boards", one which runs the application and does the hardware setup. The other board, "baseband", does very little setup.
* Clock Manager: Remove unused crystal enable/disable code.
* Clock Manager: Restore clock configuration to SPIFI bootloader state before app shutdown.
* Reset peripherals on app shutdown.
Be careful not to reset M0APP (the core we're running on) or GPIO (which is holding the hardware in a stable state).
* M4/baseband hal_lld_init: use IDIVA, which is configured earlier by M0.
This was causing problems during restart into HackRF mode. Baseband hal_lld_init changed M4 clock from IDIVA (set by M0) to PLL1, which was unceremoniously turned off during shutdown.
* Audio app: Stop audio PLL on shutdown.
* M4 HAL: Make LPC43XX_M4_CLK_SRC optional.
This was changing the BASE_M4_CLK when a baseband was run.
* LPC43xx C++ layer: Fix IDIVx constructor IDIV narrow field width.
* Application board: hide the peripherals_reset function, as it isn't useful except during hardware init.
* Consolidate hardware init code to some degree.
ClockManager is super-overloaded and murky in its purpose.
Migrate audio from IDIVC to IDIVD, to more closely resemble initial clock scheme, so it's simpler to get back to it during shutdown.
* Migrate some startup code to application board.
* Si5351: Use correct methods for reset().
update_output_enable_control() doesn't reset the enabled outputs to the reset state, unless the object is freshly initialized, which it isn't when performing firmware shutdown.
For similar reasons, use set_clock_control() instead of setting internal state and then using the update function.
* GPIO: Set SPIFI CS pin to match input buffer state coming out of bootloader.
* Change application board.c to .cpp, with required dependent changes
* Board: Clean up SCU configuration code/data.
* I2S: Add shutdown code and use it.
* LPC43xx: Consolidate a bunch of structures that had been scattered all over.
...because I'm an undisciplined coder.
* I2S: Fix ordering of branch and base clock disable.
Core was hanging, presumably because the register interface on the branch/peripheral was unresponsive after the base clock was disabled.
* Controls: Save and expose raw navigation wheel switch state
I need to do some work on debouncing and ignoring simultaneous key presses.
* Controls: Add debug view for switches state.
* Controls: Ignore all key presses until all keys are released.
This should address some mechanical quirks of the navigation wheel used on the PortaPack.
* Clock Manager: Wait for only the necessary PLL to lock.
Wasn't working on PortaPacks without a built-in clock reference, as that uses the other PLL.
TODO: Switching PLLs may be kind of pointless now...
* CMake: Pull HackRF project from GitHub and build.
* CMake: Remove commented code.
* CMake: Clone HackRF via HTTPS, not SSH.
* CMake: Extra pause for slow post-DFU firmware boot-up.
* CMake: TODO to fix SVF/XSVF file source.
* CMake: Ask HackRF hackrf_usb to make DFU binary.
* Travis-CI: Add dfu-util, now that HackRF firmware is being built for inclusion.
* Travis-CI: Update build environment to Ubuntu xenial
Previously Trusty.
* Travis-CI: Incorrectly structured my request for dfu-util package.
I'm soooo talented.
* ldscript: Mark flash, ram with correct R/W/X flags.
* ldscript: Enlarge M0 flash region to 1Mbyte, the size of the HackRF SPI flash.
* Receiver: Hide PPM adjustment if clock source is not HackRF crystal.
* Documentation: Update product photos and README.
* Documentation: Add TCXO feature to README description.
* Application: Rearrange files to match HAVOC directory structure.
* Map view in AIS (#213)
* Added GeoMapView to AISRecentEntryDetailView
* Added autoupdate in AIS map
* Revert "Map view in AIS (#213)"
This reverts commit 262c030224b9ea3e56ff1c8a66246e7ecf30e41f.
This commit will be cherry-picked onto a clean branch, then re-committed after a troublesome pull request is reverted.
* Revert "Upstream merge to make new revision of PortaPack work (#206)"
This reverts commit 920b98f7c9a30371b643c42949066fb7d2441daf.
This pull request was missing some changes and was preventing firmware from functioning on older PortaPacks.
* CPLD: Pull bitstream from HackRF project.
* SGPIO: Identify pins on CPLD by their new functions. Pull down HOST_SYNC_EN.
* CPLD: Don't load HackRF CPLD bitstream into RAM.
Trying to converge CPLD implementations, so this shouldn't be necesssary. HOWEVER, it would be good to *check* the CPLD contents and provide a way to update, if necessary.
* CPLD: Tweak clock generator config to match CPLD timing changes in HackRF.
* PinConfig: Drive CPLD pins correctly.
* CMake: Use jboone/hackrf master branch, now that CPLD fixes are there.
* CMake: Fix HackRF CPLD SVF dependency.
Build would break on the first pass, but work if you restarted make.
* CMake: Fix my misuse of the HackRF CMake configuration -- was building from too deep in the directory tree
* CMake: Work-around for CMake 3.5 not supporting ExternalProject_Add SOURCE_SUBDIR.
* CMake: Choose a CMP0005 policy to quiet CMake warnings.
* Settings: Show active clock reference. Only show PPM adjustment for HackRF source.
* Setup: Format clock reference frequency in MHz, not Hz.
* Radio Settings: Change reference clock text color.
Make consistent color with other un-editable text.
TODO: This is a bit of a hack to get ui::Text objects to support custom colors, like the Label structures used elsewhere.
* Pin config: VREGMODE=1, add other pins for completeness, comment detail
* Pin setup: More useful comments.
* Pin setup: Change some defaults, only set up PortaPack pins if detected.
* Pin setup: Disable LPC pull-ups on PP CPLD data bus, as CPLD is pulling up.
* Baseband: Allow larger HackRF firmware image.
* HackRF: Remove USER_INTERFACE CMake variable.
* CPLD: Make use of HackRF CPLD tool to generate code.
* Release: Add generation of MD5SUMS, SHA256SUMS during "make release"
* Clock generator: Match clock output currents to HackRF firmware.
Someday, we will share a code base again...
* CMake: Make "firmware" target part of the "all" target.
So now an unqualified "make" will make the firmware binary.
* CMake: Change how HackRF firmware is incorporated into binary.
Use the separate HackRF "RAM" binary. Get rid of the strip-dfu utility, since there's no longer a need to extract the binary from the DFU.
* CMake: Renamed GIT_REVISION* -> GIT_VERSION* to match HackRF build env.
* CMake: Bring git version handling closer to HackRF for code reuse.
* Travis-CI: Rework CI release artifact output.
* Travis-CI: Don't assign PROJECT_NAME within deploy-nightly.sh
* Travis-CI: Oops, don't include distro package for compiler...
...when also installing it from a third-party PPA.
* Travis-CI: Update GCC package, old one seems "retired"?
* Travis-CI: OK, the gcc-arm-none-eabi package is NOT current. Undoing...
* Travis-CI: Path oopsies.
* Travis-CI: More path confusion. I think this will do it. *touch wood*
* Travis-CI: Update build message sent to FreeNode #portapack IRC.
* Travis-CI: Break out BUILD_DATE from BUILD_NAME.
* Travis-CI: Introduce build directories, include MD5 and SHA256 hashes.
* Travis-CI: Fix MD5SUMS/SHA256SUMS paths.
* Travis-CI: Fix typo generating name for binary links.
* Power: Keep 1V8 off until after VAA is brought up.
* Power: Bring up VAA in several steps to keep voltage swing small.
* About: Show longer commit/tag version string.
* Versioning: Report non-CI builds with "local-" version prefix.
* Travis-CI: Report new nightly build site in IRC notification.
* Change use of GIT_VERSION to VERSION_STRING
Required by prior merge.
* Git: add "hackrf" submodule.
* CMake: Use hackrf submodule for build, stop pulling during build.
* Travis: Fix build paths due to CMake submodule changes.
* Travis: Explicitly update submodules recursively
* Revert "Travis: Explicitly update submodules recursively"
This reverts commit b246438d805f431e727e01b7407540e932e89ee1.
* Travis: Try to sort out hackrf submodule output paths...
* Travis: I don't know what I'm doing.
* CMake: "make firmware" problem due to target vs. path used for dependency.
* HackRF: Incorporate YAML security fix.
* CMake: Fix more places where targets should be used...
...instead of paths to outputs.
* CMake: Add DFU file to "make firmware" outputs
* HackRF: Update submodule for CMake m0_bin.s path fix.
* added encoder support to alphanum
* added encoder support to freq-keypad
* UI Redesign -
added BtnGrid & NewButton widgets and created a new button-based
layout, with both encoder and touchscreen are supported.
* Scanner changes:
- using SCANNER.TXT for frequencies, ranges also supported. file
format is the same as any other frequency file, thus can be edited
via the Frequency Manager.
- add nfm bw selector & time-to-wait to the UI
- add SCANNER.TXT to sdcard dir
orignal idea & scanner file adopted from user 'bicurico'
* small changes to scanner
* remember last category on frequency manager
* fix: cast int16_t instead of uint16_t (although i doubt we will
have more than 32767 buttons in the array...)
* added a missing last_category_id on freq manager
2019-10-29 23:53:54 +02:00
|
|
|
|
2023-05-19 08:16:05 +12:00
|
|
|
return false;
|
UI Redesign for Portapack-Havoc (#268)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* PCB: Change PCB stackup, Tg, clarify solder mask color, use more metric.
* PCB: Move HackRF header P9 to B.CrtYd layer.
* PCB: Change a Tg reference I missed.
* PCB: Update footprints for parts with mismatched CAD->tape rotation.
Adjust a few layer choice and line thickness bits.
* PCB: Got cold feet, switched back to rectangular pads.
* PCB: Add Eco layers to be visible and Gerber output.
* PCB: Use aux origin for plotting, for tidier coordinates.
* PCB: Output Gerber job file, because why not?
* Schematic: Correct footprints for two reference-related components.
* Schematic: Remove manfuacturer and part number for DNP component.
* Schematic: Specify resistor value, manufacturer, part number for reference oscillator series termination.
* PCB: Update netlist and footprints from schematic.
* Netlist: Updated component values, footprints.
* PCB: Nudge some components and traces to address DRC clearance violations.
* PCB: Allow KiCad to update zone timestamps (again?!).
* PCB: Generate *all* Gerber layers.
* Schematic, PCB: Update revision to 20181025.
* PCB: Adjust fab layer annotations orientation and font size.
* PCB: Hide mounting hole reference designators on silk layer.
* PCB: Shrink U1, U3 pads to get 0.2mm space between pads.
* PCB: Set pad-to-mask clearance to zero, leave up to fab. Set minimum mask web to 0.2mm for non-black options.
* PCB: Revise U1 pad shape, mask, paste, thermal drills.
Clearance is improved at corner pads.
* PCB: Tweak U3 for better thermal pad/drill/mask/paste design.
* PCB: Change solder mask color to blue.
* Schematic, PCB: Update revision to 20181029.
* PCB: Bump minimum mask web down a tiny bit because KiCad is having trouble with math.
* Update schematic
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Clock Manager: Actually store chosen clock reference
Similarly-named local was covering a member and discarding the value.
* Clock Manager: Reference type which contains source, frequency.
* Setup: Display reference source, frequency in frequency correction screen.
* LPC43xx API: Add extern "C" for use from C++.
* Use LPC43xx API for SGPIO, GPDMA, I2S initialization.
* I2S: Add BASE_AUDIO_CLK management.
* Add MOTOCON_PWM clock/reset structure.
* Serial: Fix dumb typos.
* Serial: Remove extra reference operator.
* Serial: Cut-and-paste error in structure type name.
* Move SCU structure from PAL to LPC43xx API.
It'd be nice if I gave some thought to where code should live before I commit it.
* VAA power: Move code to HackRF board file
It doesn't belong in PAL.
* MAX5 CPLD: Add SAMPLE and EXTEST methods.
* Flash image: Change packing scheme to use flash more efficiently.
Application is now a single image for both M4 bootstrap and M0.
Baseband images come immediately after application binary. No need to align to large blocks (and waste lots of flash).
* Clock Manager: Remove PLL1 power down function.
* Move and rename peripherals reset function to board module.
* Remove unused peripheral/clock management.
* Clock Manager: Extract switch to IRC into separate function.
* Clock Manager: More explicit shutdown of clocks, clock generator.
* Move initialization to board module.
* ChibiOS: Rename "application" board, add "baseband" board.
There are now two ChibiOS "boards", one which runs the application and does the hardware setup. The other board, "baseband", does very little setup.
* Clock Manager: Remove unused crystal enable/disable code.
* Clock Manager: Restore clock configuration to SPIFI bootloader state before app shutdown.
* Reset peripherals on app shutdown.
Be careful not to reset M0APP (the core we're running on) or GPIO (which is holding the hardware in a stable state).
* M4/baseband hal_lld_init: use IDIVA, which is configured earlier by M0.
This was causing problems during restart into HackRF mode. Baseband hal_lld_init changed M4 clock from IDIVA (set by M0) to PLL1, which was unceremoniously turned off during shutdown.
* Audio app: Stop audio PLL on shutdown.
* M4 HAL: Make LPC43XX_M4_CLK_SRC optional.
This was changing the BASE_M4_CLK when a baseband was run.
* LPC43xx C++ layer: Fix IDIVx constructor IDIV narrow field width.
* Application board: hide the peripherals_reset function, as it isn't useful except during hardware init.
* Consolidate hardware init code to some degree.
ClockManager is super-overloaded and murky in its purpose.
Migrate audio from IDIVC to IDIVD, to more closely resemble initial clock scheme, so it's simpler to get back to it during shutdown.
* Migrate some startup code to application board.
* Si5351: Use correct methods for reset().
update_output_enable_control() doesn't reset the enabled outputs to the reset state, unless the object is freshly initialized, which it isn't when performing firmware shutdown.
For similar reasons, use set_clock_control() instead of setting internal state and then using the update function.
* GPIO: Set SPIFI CS pin to match input buffer state coming out of bootloader.
* Change application board.c to .cpp, with required dependent changes
* Board: Clean up SCU configuration code/data.
* I2S: Add shutdown code and use it.
* LPC43xx: Consolidate a bunch of structures that had been scattered all over.
...because I'm an undisciplined coder.
* I2S: Fix ordering of branch and base clock disable.
Core was hanging, presumably because the register interface on the branch/peripheral was unresponsive after the base clock was disabled.
* Controls: Save and expose raw navigation wheel switch state
I need to do some work on debouncing and ignoring simultaneous key presses.
* Controls: Add debug view for switches state.
* Controls: Ignore all key presses until all keys are released.
This should address some mechanical quirks of the navigation wheel used on the PortaPack.
* Clock Manager: Wait for only the necessary PLL to lock.
Wasn't working on PortaPacks without a built-in clock reference, as that uses the other PLL.
TODO: Switching PLLs may be kind of pointless now...
* CMake: Pull HackRF project from GitHub and build.
* CMake: Remove commented code.
* CMake: Clone HackRF via HTTPS, not SSH.
* CMake: Extra pause for slow post-DFU firmware boot-up.
* CMake: TODO to fix SVF/XSVF file source.
* CMake: Ask HackRF hackrf_usb to make DFU binary.
* Travis-CI: Add dfu-util, now that HackRF firmware is being built for inclusion.
* Travis-CI: Update build environment to Ubuntu xenial
Previously Trusty.
* Travis-CI: Incorrectly structured my request for dfu-util package.
I'm soooo talented.
* ldscript: Mark flash, ram with correct R/W/X flags.
* ldscript: Enlarge M0 flash region to 1Mbyte, the size of the HackRF SPI flash.
* Receiver: Hide PPM adjustment if clock source is not HackRF crystal.
* Documentation: Update product photos and README.
* Documentation: Add TCXO feature to README description.
* Application: Rearrange files to match HAVOC directory structure.
* Map view in AIS (#213)
* Added GeoMapView to AISRecentEntryDetailView
* Added autoupdate in AIS map
* Revert "Map view in AIS (#213)"
This reverts commit 262c030224b9ea3e56ff1c8a66246e7ecf30e41f.
This commit will be cherry-picked onto a clean branch, then re-committed after a troublesome pull request is reverted.
* Revert "Upstream merge to make new revision of PortaPack work (#206)"
This reverts commit 920b98f7c9a30371b643c42949066fb7d2441daf.
This pull request was missing some changes and was preventing firmware from functioning on older PortaPacks.
* CPLD: Pull bitstream from HackRF project.
* SGPIO: Identify pins on CPLD by their new functions. Pull down HOST_SYNC_EN.
* CPLD: Don't load HackRF CPLD bitstream into RAM.
Trying to converge CPLD implementations, so this shouldn't be necesssary. HOWEVER, it would be good to *check* the CPLD contents and provide a way to update, if necessary.
* CPLD: Tweak clock generator config to match CPLD timing changes in HackRF.
* PinConfig: Drive CPLD pins correctly.
* CMake: Use jboone/hackrf master branch, now that CPLD fixes are there.
* CMake: Fix HackRF CPLD SVF dependency.
Build would break on the first pass, but work if you restarted make.
* CMake: Fix my misuse of the HackRF CMake configuration -- was building from too deep in the directory tree
* CMake: Work-around for CMake 3.5 not supporting ExternalProject_Add SOURCE_SUBDIR.
* CMake: Choose a CMP0005 policy to quiet CMake warnings.
* Settings: Show active clock reference. Only show PPM adjustment for HackRF source.
* Setup: Format clock reference frequency in MHz, not Hz.
* Radio Settings: Change reference clock text color.
Make consistent color with other un-editable text.
TODO: This is a bit of a hack to get ui::Text objects to support custom colors, like the Label structures used elsewhere.
* Pin config: VREGMODE=1, add other pins for completeness, comment detail
* Pin setup: More useful comments.
* Pin setup: Change some defaults, only set up PortaPack pins if detected.
* Pin setup: Disable LPC pull-ups on PP CPLD data bus, as CPLD is pulling up.
* Baseband: Allow larger HackRF firmware image.
* HackRF: Remove USER_INTERFACE CMake variable.
* CPLD: Make use of HackRF CPLD tool to generate code.
* Release: Add generation of MD5SUMS, SHA256SUMS during "make release"
* Clock generator: Match clock output currents to HackRF firmware.
Someday, we will share a code base again...
* CMake: Make "firmware" target part of the "all" target.
So now an unqualified "make" will make the firmware binary.
* CMake: Change how HackRF firmware is incorporated into binary.
Use the separate HackRF "RAM" binary. Get rid of the strip-dfu utility, since there's no longer a need to extract the binary from the DFU.
* CMake: Renamed GIT_REVISION* -> GIT_VERSION* to match HackRF build env.
* CMake: Bring git version handling closer to HackRF for code reuse.
* Travis-CI: Rework CI release artifact output.
* Travis-CI: Don't assign PROJECT_NAME within deploy-nightly.sh
* Travis-CI: Oops, don't include distro package for compiler...
...when also installing it from a third-party PPA.
* Travis-CI: Update GCC package, old one seems "retired"?
* Travis-CI: OK, the gcc-arm-none-eabi package is NOT current. Undoing...
* Travis-CI: Path oopsies.
* Travis-CI: More path confusion. I think this will do it. *touch wood*
* Travis-CI: Update build message sent to FreeNode #portapack IRC.
* Travis-CI: Break out BUILD_DATE from BUILD_NAME.
* Travis-CI: Introduce build directories, include MD5 and SHA256 hashes.
* Travis-CI: Fix MD5SUMS/SHA256SUMS paths.
* Travis-CI: Fix typo generating name for binary links.
* Power: Keep 1V8 off until after VAA is brought up.
* Power: Bring up VAA in several steps to keep voltage swing small.
* About: Show longer commit/tag version string.
* Versioning: Report non-CI builds with "local-" version prefix.
* Travis-CI: Report new nightly build site in IRC notification.
* Change use of GIT_VERSION to VERSION_STRING
Required by prior merge.
* Git: add "hackrf" submodule.
* CMake: Use hackrf submodule for build, stop pulling during build.
* Travis: Fix build paths due to CMake submodule changes.
* Travis: Explicitly update submodules recursively
* Revert "Travis: Explicitly update submodules recursively"
This reverts commit b246438d805f431e727e01b7407540e932e89ee1.
* Travis: Try to sort out hackrf submodule output paths...
* Travis: I don't know what I'm doing.
* CMake: "make firmware" problem due to target vs. path used for dependency.
* HackRF: Incorporate YAML security fix.
* CMake: Fix more places where targets should be used...
...instead of paths to outputs.
* CMake: Add DFU file to "make firmware" outputs
* HackRF: Update submodule for CMake m0_bin.s path fix.
* added encoder support to alphanum
* added encoder support to freq-keypad
* UI Redesign -
added BtnGrid & NewButton widgets and created a new button-based
layout, with both encoder and touchscreen are supported.
* Scanner changes:
- using SCANNER.TXT for frequencies, ranges also supported. file
format is the same as any other frequency file, thus can be edited
via the Frequency Manager.
- add nfm bw selector & time-to-wait to the UI
- add SCANNER.TXT to sdcard dir
orignal idea & scanner file adopted from user 'bicurico'
* small changes to scanner
* remember last category on frequency manager
* fix: cast int16_t instead of uint16_t (although i doubt we will
have more than 32767 buttons in the array...)
* added a missing last_category_id on freq manager
2019-10-29 23:53:54 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
bool NewButton::on_touch(const TouchEvent event) {
|
2023-05-19 08:16:05 +12:00
|
|
|
switch (event.type) {
|
|
|
|
case TouchEvent::Type::Start:
|
|
|
|
set_highlighted(true);
|
|
|
|
set_dirty();
|
|
|
|
return true;
|
UI Redesign for Portapack-Havoc (#268)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* PCB: Change PCB stackup, Tg, clarify solder mask color, use more metric.
* PCB: Move HackRF header P9 to B.CrtYd layer.
* PCB: Change a Tg reference I missed.
* PCB: Update footprints for parts with mismatched CAD->tape rotation.
Adjust a few layer choice and line thickness bits.
* PCB: Got cold feet, switched back to rectangular pads.
* PCB: Add Eco layers to be visible and Gerber output.
* PCB: Use aux origin for plotting, for tidier coordinates.
* PCB: Output Gerber job file, because why not?
* Schematic: Correct footprints for two reference-related components.
* Schematic: Remove manfuacturer and part number for DNP component.
* Schematic: Specify resistor value, manufacturer, part number for reference oscillator series termination.
* PCB: Update netlist and footprints from schematic.
* Netlist: Updated component values, footprints.
* PCB: Nudge some components and traces to address DRC clearance violations.
* PCB: Allow KiCad to update zone timestamps (again?!).
* PCB: Generate *all* Gerber layers.
* Schematic, PCB: Update revision to 20181025.
* PCB: Adjust fab layer annotations orientation and font size.
* PCB: Hide mounting hole reference designators on silk layer.
* PCB: Shrink U1, U3 pads to get 0.2mm space between pads.
* PCB: Set pad-to-mask clearance to zero, leave up to fab. Set minimum mask web to 0.2mm for non-black options.
* PCB: Revise U1 pad shape, mask, paste, thermal drills.
Clearance is improved at corner pads.
* PCB: Tweak U3 for better thermal pad/drill/mask/paste design.
* PCB: Change solder mask color to blue.
* Schematic, PCB: Update revision to 20181029.
* PCB: Bump minimum mask web down a tiny bit because KiCad is having trouble with math.
* Update schematic
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Clock Manager: Actually store chosen clock reference
Similarly-named local was covering a member and discarding the value.
* Clock Manager: Reference type which contains source, frequency.
* Setup: Display reference source, frequency in frequency correction screen.
* LPC43xx API: Add extern "C" for use from C++.
* Use LPC43xx API for SGPIO, GPDMA, I2S initialization.
* I2S: Add BASE_AUDIO_CLK management.
* Add MOTOCON_PWM clock/reset structure.
* Serial: Fix dumb typos.
* Serial: Remove extra reference operator.
* Serial: Cut-and-paste error in structure type name.
* Move SCU structure from PAL to LPC43xx API.
It'd be nice if I gave some thought to where code should live before I commit it.
* VAA power: Move code to HackRF board file
It doesn't belong in PAL.
* MAX5 CPLD: Add SAMPLE and EXTEST methods.
* Flash image: Change packing scheme to use flash more efficiently.
Application is now a single image for both M4 bootstrap and M0.
Baseband images come immediately after application binary. No need to align to large blocks (and waste lots of flash).
* Clock Manager: Remove PLL1 power down function.
* Move and rename peripherals reset function to board module.
* Remove unused peripheral/clock management.
* Clock Manager: Extract switch to IRC into separate function.
* Clock Manager: More explicit shutdown of clocks, clock generator.
* Move initialization to board module.
* ChibiOS: Rename "application" board, add "baseband" board.
There are now two ChibiOS "boards", one which runs the application and does the hardware setup. The other board, "baseband", does very little setup.
* Clock Manager: Remove unused crystal enable/disable code.
* Clock Manager: Restore clock configuration to SPIFI bootloader state before app shutdown.
* Reset peripherals on app shutdown.
Be careful not to reset M0APP (the core we're running on) or GPIO (which is holding the hardware in a stable state).
* M4/baseband hal_lld_init: use IDIVA, which is configured earlier by M0.
This was causing problems during restart into HackRF mode. Baseband hal_lld_init changed M4 clock from IDIVA (set by M0) to PLL1, which was unceremoniously turned off during shutdown.
* Audio app: Stop audio PLL on shutdown.
* M4 HAL: Make LPC43XX_M4_CLK_SRC optional.
This was changing the BASE_M4_CLK when a baseband was run.
* LPC43xx C++ layer: Fix IDIVx constructor IDIV narrow field width.
* Application board: hide the peripherals_reset function, as it isn't useful except during hardware init.
* Consolidate hardware init code to some degree.
ClockManager is super-overloaded and murky in its purpose.
Migrate audio from IDIVC to IDIVD, to more closely resemble initial clock scheme, so it's simpler to get back to it during shutdown.
* Migrate some startup code to application board.
* Si5351: Use correct methods for reset().
update_output_enable_control() doesn't reset the enabled outputs to the reset state, unless the object is freshly initialized, which it isn't when performing firmware shutdown.
For similar reasons, use set_clock_control() instead of setting internal state and then using the update function.
* GPIO: Set SPIFI CS pin to match input buffer state coming out of bootloader.
* Change application board.c to .cpp, with required dependent changes
* Board: Clean up SCU configuration code/data.
* I2S: Add shutdown code and use it.
* LPC43xx: Consolidate a bunch of structures that had been scattered all over.
...because I'm an undisciplined coder.
* I2S: Fix ordering of branch and base clock disable.
Core was hanging, presumably because the register interface on the branch/peripheral was unresponsive after the base clock was disabled.
* Controls: Save and expose raw navigation wheel switch state
I need to do some work on debouncing and ignoring simultaneous key presses.
* Controls: Add debug view for switches state.
* Controls: Ignore all key presses until all keys are released.
This should address some mechanical quirks of the navigation wheel used on the PortaPack.
* Clock Manager: Wait for only the necessary PLL to lock.
Wasn't working on PortaPacks without a built-in clock reference, as that uses the other PLL.
TODO: Switching PLLs may be kind of pointless now...
* CMake: Pull HackRF project from GitHub and build.
* CMake: Remove commented code.
* CMake: Clone HackRF via HTTPS, not SSH.
* CMake: Extra pause for slow post-DFU firmware boot-up.
* CMake: TODO to fix SVF/XSVF file source.
* CMake: Ask HackRF hackrf_usb to make DFU binary.
* Travis-CI: Add dfu-util, now that HackRF firmware is being built for inclusion.
* Travis-CI: Update build environment to Ubuntu xenial
Previously Trusty.
* Travis-CI: Incorrectly structured my request for dfu-util package.
I'm soooo talented.
* ldscript: Mark flash, ram with correct R/W/X flags.
* ldscript: Enlarge M0 flash region to 1Mbyte, the size of the HackRF SPI flash.
* Receiver: Hide PPM adjustment if clock source is not HackRF crystal.
* Documentation: Update product photos and README.
* Documentation: Add TCXO feature to README description.
* Application: Rearrange files to match HAVOC directory structure.
* Map view in AIS (#213)
* Added GeoMapView to AISRecentEntryDetailView
* Added autoupdate in AIS map
* Revert "Map view in AIS (#213)"
This reverts commit 262c030224b9ea3e56ff1c8a66246e7ecf30e41f.
This commit will be cherry-picked onto a clean branch, then re-committed after a troublesome pull request is reverted.
* Revert "Upstream merge to make new revision of PortaPack work (#206)"
This reverts commit 920b98f7c9a30371b643c42949066fb7d2441daf.
This pull request was missing some changes and was preventing firmware from functioning on older PortaPacks.
* CPLD: Pull bitstream from HackRF project.
* SGPIO: Identify pins on CPLD by their new functions. Pull down HOST_SYNC_EN.
* CPLD: Don't load HackRF CPLD bitstream into RAM.
Trying to converge CPLD implementations, so this shouldn't be necesssary. HOWEVER, it would be good to *check* the CPLD contents and provide a way to update, if necessary.
* CPLD: Tweak clock generator config to match CPLD timing changes in HackRF.
* PinConfig: Drive CPLD pins correctly.
* CMake: Use jboone/hackrf master branch, now that CPLD fixes are there.
* CMake: Fix HackRF CPLD SVF dependency.
Build would break on the first pass, but work if you restarted make.
* CMake: Fix my misuse of the HackRF CMake configuration -- was building from too deep in the directory tree
* CMake: Work-around for CMake 3.5 not supporting ExternalProject_Add SOURCE_SUBDIR.
* CMake: Choose a CMP0005 policy to quiet CMake warnings.
* Settings: Show active clock reference. Only show PPM adjustment for HackRF source.
* Setup: Format clock reference frequency in MHz, not Hz.
* Radio Settings: Change reference clock text color.
Make consistent color with other un-editable text.
TODO: This is a bit of a hack to get ui::Text objects to support custom colors, like the Label structures used elsewhere.
* Pin config: VREGMODE=1, add other pins for completeness, comment detail
* Pin setup: More useful comments.
* Pin setup: Change some defaults, only set up PortaPack pins if detected.
* Pin setup: Disable LPC pull-ups on PP CPLD data bus, as CPLD is pulling up.
* Baseband: Allow larger HackRF firmware image.
* HackRF: Remove USER_INTERFACE CMake variable.
* CPLD: Make use of HackRF CPLD tool to generate code.
* Release: Add generation of MD5SUMS, SHA256SUMS during "make release"
* Clock generator: Match clock output currents to HackRF firmware.
Someday, we will share a code base again...
* CMake: Make "firmware" target part of the "all" target.
So now an unqualified "make" will make the firmware binary.
* CMake: Change how HackRF firmware is incorporated into binary.
Use the separate HackRF "RAM" binary. Get rid of the strip-dfu utility, since there's no longer a need to extract the binary from the DFU.
* CMake: Renamed GIT_REVISION* -> GIT_VERSION* to match HackRF build env.
* CMake: Bring git version handling closer to HackRF for code reuse.
* Travis-CI: Rework CI release artifact output.
* Travis-CI: Don't assign PROJECT_NAME within deploy-nightly.sh
* Travis-CI: Oops, don't include distro package for compiler...
...when also installing it from a third-party PPA.
* Travis-CI: Update GCC package, old one seems "retired"?
* Travis-CI: OK, the gcc-arm-none-eabi package is NOT current. Undoing...
* Travis-CI: Path oopsies.
* Travis-CI: More path confusion. I think this will do it. *touch wood*
* Travis-CI: Update build message sent to FreeNode #portapack IRC.
* Travis-CI: Break out BUILD_DATE from BUILD_NAME.
* Travis-CI: Introduce build directories, include MD5 and SHA256 hashes.
* Travis-CI: Fix MD5SUMS/SHA256SUMS paths.
* Travis-CI: Fix typo generating name for binary links.
* Power: Keep 1V8 off until after VAA is brought up.
* Power: Bring up VAA in several steps to keep voltage swing small.
* About: Show longer commit/tag version string.
* Versioning: Report non-CI builds with "local-" version prefix.
* Travis-CI: Report new nightly build site in IRC notification.
* Change use of GIT_VERSION to VERSION_STRING
Required by prior merge.
* Git: add "hackrf" submodule.
* CMake: Use hackrf submodule for build, stop pulling during build.
* Travis: Fix build paths due to CMake submodule changes.
* Travis: Explicitly update submodules recursively
* Revert "Travis: Explicitly update submodules recursively"
This reverts commit b246438d805f431e727e01b7407540e932e89ee1.
* Travis: Try to sort out hackrf submodule output paths...
* Travis: I don't know what I'm doing.
* CMake: "make firmware" problem due to target vs. path used for dependency.
* HackRF: Incorporate YAML security fix.
* CMake: Fix more places where targets should be used...
...instead of paths to outputs.
* CMake: Add DFU file to "make firmware" outputs
* HackRF: Update submodule for CMake m0_bin.s path fix.
* added encoder support to alphanum
* added encoder support to freq-keypad
* UI Redesign -
added BtnGrid & NewButton widgets and created a new button-based
layout, with both encoder and touchscreen are supported.
* Scanner changes:
- using SCANNER.TXT for frequencies, ranges also supported. file
format is the same as any other frequency file, thus can be edited
via the Frequency Manager.
- add nfm bw selector & time-to-wait to the UI
- add SCANNER.TXT to sdcard dir
orignal idea & scanner file adopted from user 'bicurico'
* small changes to scanner
* remember last category on frequency manager
* fix: cast int16_t instead of uint16_t (although i doubt we will
have more than 32767 buttons in the array...)
* added a missing last_category_id on freq manager
2019-10-29 23:53:54 +02:00
|
|
|
|
2023-05-19 08:16:05 +12:00
|
|
|
case TouchEvent::Type::End:
|
|
|
|
set_highlighted(false);
|
|
|
|
set_dirty();
|
|
|
|
if (on_select) {
|
|
|
|
on_select();
|
|
|
|
}
|
|
|
|
return true;
|
UI Redesign for Portapack-Havoc (#268)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* PCB: Change PCB stackup, Tg, clarify solder mask color, use more metric.
* PCB: Move HackRF header P9 to B.CrtYd layer.
* PCB: Change a Tg reference I missed.
* PCB: Update footprints for parts with mismatched CAD->tape rotation.
Adjust a few layer choice and line thickness bits.
* PCB: Got cold feet, switched back to rectangular pads.
* PCB: Add Eco layers to be visible and Gerber output.
* PCB: Use aux origin for plotting, for tidier coordinates.
* PCB: Output Gerber job file, because why not?
* Schematic: Correct footprints for two reference-related components.
* Schematic: Remove manfuacturer and part number for DNP component.
* Schematic: Specify resistor value, manufacturer, part number for reference oscillator series termination.
* PCB: Update netlist and footprints from schematic.
* Netlist: Updated component values, footprints.
* PCB: Nudge some components and traces to address DRC clearance violations.
* PCB: Allow KiCad to update zone timestamps (again?!).
* PCB: Generate *all* Gerber layers.
* Schematic, PCB: Update revision to 20181025.
* PCB: Adjust fab layer annotations orientation and font size.
* PCB: Hide mounting hole reference designators on silk layer.
* PCB: Shrink U1, U3 pads to get 0.2mm space between pads.
* PCB: Set pad-to-mask clearance to zero, leave up to fab. Set minimum mask web to 0.2mm for non-black options.
* PCB: Revise U1 pad shape, mask, paste, thermal drills.
Clearance is improved at corner pads.
* PCB: Tweak U3 for better thermal pad/drill/mask/paste design.
* PCB: Change solder mask color to blue.
* Schematic, PCB: Update revision to 20181029.
* PCB: Bump minimum mask web down a tiny bit because KiCad is having trouble with math.
* Update schematic
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Clock Manager: Actually store chosen clock reference
Similarly-named local was covering a member and discarding the value.
* Clock Manager: Reference type which contains source, frequency.
* Setup: Display reference source, frequency in frequency correction screen.
* LPC43xx API: Add extern "C" for use from C++.
* Use LPC43xx API for SGPIO, GPDMA, I2S initialization.
* I2S: Add BASE_AUDIO_CLK management.
* Add MOTOCON_PWM clock/reset structure.
* Serial: Fix dumb typos.
* Serial: Remove extra reference operator.
* Serial: Cut-and-paste error in structure type name.
* Move SCU structure from PAL to LPC43xx API.
It'd be nice if I gave some thought to where code should live before I commit it.
* VAA power: Move code to HackRF board file
It doesn't belong in PAL.
* MAX5 CPLD: Add SAMPLE and EXTEST methods.
* Flash image: Change packing scheme to use flash more efficiently.
Application is now a single image for both M4 bootstrap and M0.
Baseband images come immediately after application binary. No need to align to large blocks (and waste lots of flash).
* Clock Manager: Remove PLL1 power down function.
* Move and rename peripherals reset function to board module.
* Remove unused peripheral/clock management.
* Clock Manager: Extract switch to IRC into separate function.
* Clock Manager: More explicit shutdown of clocks, clock generator.
* Move initialization to board module.
* ChibiOS: Rename "application" board, add "baseband" board.
There are now two ChibiOS "boards", one which runs the application and does the hardware setup. The other board, "baseband", does very little setup.
* Clock Manager: Remove unused crystal enable/disable code.
* Clock Manager: Restore clock configuration to SPIFI bootloader state before app shutdown.
* Reset peripherals on app shutdown.
Be careful not to reset M0APP (the core we're running on) or GPIO (which is holding the hardware in a stable state).
* M4/baseband hal_lld_init: use IDIVA, which is configured earlier by M0.
This was causing problems during restart into HackRF mode. Baseband hal_lld_init changed M4 clock from IDIVA (set by M0) to PLL1, which was unceremoniously turned off during shutdown.
* Audio app: Stop audio PLL on shutdown.
* M4 HAL: Make LPC43XX_M4_CLK_SRC optional.
This was changing the BASE_M4_CLK when a baseband was run.
* LPC43xx C++ layer: Fix IDIVx constructor IDIV narrow field width.
* Application board: hide the peripherals_reset function, as it isn't useful except during hardware init.
* Consolidate hardware init code to some degree.
ClockManager is super-overloaded and murky in its purpose.
Migrate audio from IDIVC to IDIVD, to more closely resemble initial clock scheme, so it's simpler to get back to it during shutdown.
* Migrate some startup code to application board.
* Si5351: Use correct methods for reset().
update_output_enable_control() doesn't reset the enabled outputs to the reset state, unless the object is freshly initialized, which it isn't when performing firmware shutdown.
For similar reasons, use set_clock_control() instead of setting internal state and then using the update function.
* GPIO: Set SPIFI CS pin to match input buffer state coming out of bootloader.
* Change application board.c to .cpp, with required dependent changes
* Board: Clean up SCU configuration code/data.
* I2S: Add shutdown code and use it.
* LPC43xx: Consolidate a bunch of structures that had been scattered all over.
...because I'm an undisciplined coder.
* I2S: Fix ordering of branch and base clock disable.
Core was hanging, presumably because the register interface on the branch/peripheral was unresponsive after the base clock was disabled.
* Controls: Save and expose raw navigation wheel switch state
I need to do some work on debouncing and ignoring simultaneous key presses.
* Controls: Add debug view for switches state.
* Controls: Ignore all key presses until all keys are released.
This should address some mechanical quirks of the navigation wheel used on the PortaPack.
* Clock Manager: Wait for only the necessary PLL to lock.
Wasn't working on PortaPacks without a built-in clock reference, as that uses the other PLL.
TODO: Switching PLLs may be kind of pointless now...
* CMake: Pull HackRF project from GitHub and build.
* CMake: Remove commented code.
* CMake: Clone HackRF via HTTPS, not SSH.
* CMake: Extra pause for slow post-DFU firmware boot-up.
* CMake: TODO to fix SVF/XSVF file source.
* CMake: Ask HackRF hackrf_usb to make DFU binary.
* Travis-CI: Add dfu-util, now that HackRF firmware is being built for inclusion.
* Travis-CI: Update build environment to Ubuntu xenial
Previously Trusty.
* Travis-CI: Incorrectly structured my request for dfu-util package.
I'm soooo talented.
* ldscript: Mark flash, ram with correct R/W/X flags.
* ldscript: Enlarge M0 flash region to 1Mbyte, the size of the HackRF SPI flash.
* Receiver: Hide PPM adjustment if clock source is not HackRF crystal.
* Documentation: Update product photos and README.
* Documentation: Add TCXO feature to README description.
* Application: Rearrange files to match HAVOC directory structure.
* Map view in AIS (#213)
* Added GeoMapView to AISRecentEntryDetailView
* Added autoupdate in AIS map
* Revert "Map view in AIS (#213)"
This reverts commit 262c030224b9ea3e56ff1c8a66246e7ecf30e41f.
This commit will be cherry-picked onto a clean branch, then re-committed after a troublesome pull request is reverted.
* Revert "Upstream merge to make new revision of PortaPack work (#206)"
This reverts commit 920b98f7c9a30371b643c42949066fb7d2441daf.
This pull request was missing some changes and was preventing firmware from functioning on older PortaPacks.
* CPLD: Pull bitstream from HackRF project.
* SGPIO: Identify pins on CPLD by their new functions. Pull down HOST_SYNC_EN.
* CPLD: Don't load HackRF CPLD bitstream into RAM.
Trying to converge CPLD implementations, so this shouldn't be necesssary. HOWEVER, it would be good to *check* the CPLD contents and provide a way to update, if necessary.
* CPLD: Tweak clock generator config to match CPLD timing changes in HackRF.
* PinConfig: Drive CPLD pins correctly.
* CMake: Use jboone/hackrf master branch, now that CPLD fixes are there.
* CMake: Fix HackRF CPLD SVF dependency.
Build would break on the first pass, but work if you restarted make.
* CMake: Fix my misuse of the HackRF CMake configuration -- was building from too deep in the directory tree
* CMake: Work-around for CMake 3.5 not supporting ExternalProject_Add SOURCE_SUBDIR.
* CMake: Choose a CMP0005 policy to quiet CMake warnings.
* Settings: Show active clock reference. Only show PPM adjustment for HackRF source.
* Setup: Format clock reference frequency in MHz, not Hz.
* Radio Settings: Change reference clock text color.
Make consistent color with other un-editable text.
TODO: This is a bit of a hack to get ui::Text objects to support custom colors, like the Label structures used elsewhere.
* Pin config: VREGMODE=1, add other pins for completeness, comment detail
* Pin setup: More useful comments.
* Pin setup: Change some defaults, only set up PortaPack pins if detected.
* Pin setup: Disable LPC pull-ups on PP CPLD data bus, as CPLD is pulling up.
* Baseband: Allow larger HackRF firmware image.
* HackRF: Remove USER_INTERFACE CMake variable.
* CPLD: Make use of HackRF CPLD tool to generate code.
* Release: Add generation of MD5SUMS, SHA256SUMS during "make release"
* Clock generator: Match clock output currents to HackRF firmware.
Someday, we will share a code base again...
* CMake: Make "firmware" target part of the "all" target.
So now an unqualified "make" will make the firmware binary.
* CMake: Change how HackRF firmware is incorporated into binary.
Use the separate HackRF "RAM" binary. Get rid of the strip-dfu utility, since there's no longer a need to extract the binary from the DFU.
* CMake: Renamed GIT_REVISION* -> GIT_VERSION* to match HackRF build env.
* CMake: Bring git version handling closer to HackRF for code reuse.
* Travis-CI: Rework CI release artifact output.
* Travis-CI: Don't assign PROJECT_NAME within deploy-nightly.sh
* Travis-CI: Oops, don't include distro package for compiler...
...when also installing it from a third-party PPA.
* Travis-CI: Update GCC package, old one seems "retired"?
* Travis-CI: OK, the gcc-arm-none-eabi package is NOT current. Undoing...
* Travis-CI: Path oopsies.
* Travis-CI: More path confusion. I think this will do it. *touch wood*
* Travis-CI: Update build message sent to FreeNode #portapack IRC.
* Travis-CI: Break out BUILD_DATE from BUILD_NAME.
* Travis-CI: Introduce build directories, include MD5 and SHA256 hashes.
* Travis-CI: Fix MD5SUMS/SHA256SUMS paths.
* Travis-CI: Fix typo generating name for binary links.
* Power: Keep 1V8 off until after VAA is brought up.
* Power: Bring up VAA in several steps to keep voltage swing small.
* About: Show longer commit/tag version string.
* Versioning: Report non-CI builds with "local-" version prefix.
* Travis-CI: Report new nightly build site in IRC notification.
* Change use of GIT_VERSION to VERSION_STRING
Required by prior merge.
* Git: add "hackrf" submodule.
* CMake: Use hackrf submodule for build, stop pulling during build.
* Travis: Fix build paths due to CMake submodule changes.
* Travis: Explicitly update submodules recursively
* Revert "Travis: Explicitly update submodules recursively"
This reverts commit b246438d805f431e727e01b7407540e932e89ee1.
* Travis: Try to sort out hackrf submodule output paths...
* Travis: I don't know what I'm doing.
* CMake: "make firmware" problem due to target vs. path used for dependency.
* HackRF: Incorporate YAML security fix.
* CMake: Fix more places where targets should be used...
...instead of paths to outputs.
* CMake: Add DFU file to "make firmware" outputs
* HackRF: Update submodule for CMake m0_bin.s path fix.
* added encoder support to alphanum
* added encoder support to freq-keypad
* UI Redesign -
added BtnGrid & NewButton widgets and created a new button-based
layout, with both encoder and touchscreen are supported.
* Scanner changes:
- using SCANNER.TXT for frequencies, ranges also supported. file
format is the same as any other frequency file, thus can be edited
via the Frequency Manager.
- add nfm bw selector & time-to-wait to the UI
- add SCANNER.TXT to sdcard dir
orignal idea & scanner file adopted from user 'bicurico'
* small changes to scanner
* remember last category on frequency manager
* fix: cast int16_t instead of uint16_t (although i doubt we will
have more than 32767 buttons in the array...)
* added a missing last_category_id on freq manager
2019-10-29 23:53:54 +02:00
|
|
|
|
2023-05-19 08:16:05 +12:00
|
|
|
default:
|
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|
return false;
|
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|
|
}
|
UI Redesign for Portapack-Havoc (#268)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* PCB: Change PCB stackup, Tg, clarify solder mask color, use more metric.
* PCB: Move HackRF header P9 to B.CrtYd layer.
* PCB: Change a Tg reference I missed.
* PCB: Update footprints for parts with mismatched CAD->tape rotation.
Adjust a few layer choice and line thickness bits.
* PCB: Got cold feet, switched back to rectangular pads.
* PCB: Add Eco layers to be visible and Gerber output.
* PCB: Use aux origin for plotting, for tidier coordinates.
* PCB: Output Gerber job file, because why not?
* Schematic: Correct footprints for two reference-related components.
* Schematic: Remove manfuacturer and part number for DNP component.
* Schematic: Specify resistor value, manufacturer, part number for reference oscillator series termination.
* PCB: Update netlist and footprints from schematic.
* Netlist: Updated component values, footprints.
* PCB: Nudge some components and traces to address DRC clearance violations.
* PCB: Allow KiCad to update zone timestamps (again?!).
* PCB: Generate *all* Gerber layers.
* Schematic, PCB: Update revision to 20181025.
* PCB: Adjust fab layer annotations orientation and font size.
* PCB: Hide mounting hole reference designators on silk layer.
* PCB: Shrink U1, U3 pads to get 0.2mm space between pads.
* PCB: Set pad-to-mask clearance to zero, leave up to fab. Set minimum mask web to 0.2mm for non-black options.
* PCB: Revise U1 pad shape, mask, paste, thermal drills.
Clearance is improved at corner pads.
* PCB: Tweak U3 for better thermal pad/drill/mask/paste design.
* PCB: Change solder mask color to blue.
* Schematic, PCB: Update revision to 20181029.
* PCB: Bump minimum mask web down a tiny bit because KiCad is having trouble with math.
* Update schematic
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Clock Manager: Actually store chosen clock reference
Similarly-named local was covering a member and discarding the value.
* Clock Manager: Reference type which contains source, frequency.
* Setup: Display reference source, frequency in frequency correction screen.
* LPC43xx API: Add extern "C" for use from C++.
* Use LPC43xx API for SGPIO, GPDMA, I2S initialization.
* I2S: Add BASE_AUDIO_CLK management.
* Add MOTOCON_PWM clock/reset structure.
* Serial: Fix dumb typos.
* Serial: Remove extra reference operator.
* Serial: Cut-and-paste error in structure type name.
* Move SCU structure from PAL to LPC43xx API.
It'd be nice if I gave some thought to where code should live before I commit it.
* VAA power: Move code to HackRF board file
It doesn't belong in PAL.
* MAX5 CPLD: Add SAMPLE and EXTEST methods.
* Flash image: Change packing scheme to use flash more efficiently.
Application is now a single image for both M4 bootstrap and M0.
Baseband images come immediately after application binary. No need to align to large blocks (and waste lots of flash).
* Clock Manager: Remove PLL1 power down function.
* Move and rename peripherals reset function to board module.
* Remove unused peripheral/clock management.
* Clock Manager: Extract switch to IRC into separate function.
* Clock Manager: More explicit shutdown of clocks, clock generator.
* Move initialization to board module.
* ChibiOS: Rename "application" board, add "baseband" board.
There are now two ChibiOS "boards", one which runs the application and does the hardware setup. The other board, "baseband", does very little setup.
* Clock Manager: Remove unused crystal enable/disable code.
* Clock Manager: Restore clock configuration to SPIFI bootloader state before app shutdown.
* Reset peripherals on app shutdown.
Be careful not to reset M0APP (the core we're running on) or GPIO (which is holding the hardware in a stable state).
* M4/baseband hal_lld_init: use IDIVA, which is configured earlier by M0.
This was causing problems during restart into HackRF mode. Baseband hal_lld_init changed M4 clock from IDIVA (set by M0) to PLL1, which was unceremoniously turned off during shutdown.
* Audio app: Stop audio PLL on shutdown.
* M4 HAL: Make LPC43XX_M4_CLK_SRC optional.
This was changing the BASE_M4_CLK when a baseband was run.
* LPC43xx C++ layer: Fix IDIVx constructor IDIV narrow field width.
* Application board: hide the peripherals_reset function, as it isn't useful except during hardware init.
* Consolidate hardware init code to some degree.
ClockManager is super-overloaded and murky in its purpose.
Migrate audio from IDIVC to IDIVD, to more closely resemble initial clock scheme, so it's simpler to get back to it during shutdown.
* Migrate some startup code to application board.
* Si5351: Use correct methods for reset().
update_output_enable_control() doesn't reset the enabled outputs to the reset state, unless the object is freshly initialized, which it isn't when performing firmware shutdown.
For similar reasons, use set_clock_control() instead of setting internal state and then using the update function.
* GPIO: Set SPIFI CS pin to match input buffer state coming out of bootloader.
* Change application board.c to .cpp, with required dependent changes
* Board: Clean up SCU configuration code/data.
* I2S: Add shutdown code and use it.
* LPC43xx: Consolidate a bunch of structures that had been scattered all over.
...because I'm an undisciplined coder.
* I2S: Fix ordering of branch and base clock disable.
Core was hanging, presumably because the register interface on the branch/peripheral was unresponsive after the base clock was disabled.
* Controls: Save and expose raw navigation wheel switch state
I need to do some work on debouncing and ignoring simultaneous key presses.
* Controls: Add debug view for switches state.
* Controls: Ignore all key presses until all keys are released.
This should address some mechanical quirks of the navigation wheel used on the PortaPack.
* Clock Manager: Wait for only the necessary PLL to lock.
Wasn't working on PortaPacks without a built-in clock reference, as that uses the other PLL.
TODO: Switching PLLs may be kind of pointless now...
* CMake: Pull HackRF project from GitHub and build.
* CMake: Remove commented code.
* CMake: Clone HackRF via HTTPS, not SSH.
* CMake: Extra pause for slow post-DFU firmware boot-up.
* CMake: TODO to fix SVF/XSVF file source.
* CMake: Ask HackRF hackrf_usb to make DFU binary.
* Travis-CI: Add dfu-util, now that HackRF firmware is being built for inclusion.
* Travis-CI: Update build environment to Ubuntu xenial
Previously Trusty.
* Travis-CI: Incorrectly structured my request for dfu-util package.
I'm soooo talented.
* ldscript: Mark flash, ram with correct R/W/X flags.
* ldscript: Enlarge M0 flash region to 1Mbyte, the size of the HackRF SPI flash.
* Receiver: Hide PPM adjustment if clock source is not HackRF crystal.
* Documentation: Update product photos and README.
* Documentation: Add TCXO feature to README description.
* Application: Rearrange files to match HAVOC directory structure.
* Map view in AIS (#213)
* Added GeoMapView to AISRecentEntryDetailView
* Added autoupdate in AIS map
* Revert "Map view in AIS (#213)"
This reverts commit 262c030224b9ea3e56ff1c8a66246e7ecf30e41f.
This commit will be cherry-picked onto a clean branch, then re-committed after a troublesome pull request is reverted.
* Revert "Upstream merge to make new revision of PortaPack work (#206)"
This reverts commit 920b98f7c9a30371b643c42949066fb7d2441daf.
This pull request was missing some changes and was preventing firmware from functioning on older PortaPacks.
* CPLD: Pull bitstream from HackRF project.
* SGPIO: Identify pins on CPLD by their new functions. Pull down HOST_SYNC_EN.
* CPLD: Don't load HackRF CPLD bitstream into RAM.
Trying to converge CPLD implementations, so this shouldn't be necesssary. HOWEVER, it would be good to *check* the CPLD contents and provide a way to update, if necessary.
* CPLD: Tweak clock generator config to match CPLD timing changes in HackRF.
* PinConfig: Drive CPLD pins correctly.
* CMake: Use jboone/hackrf master branch, now that CPLD fixes are there.
* CMake: Fix HackRF CPLD SVF dependency.
Build would break on the first pass, but work if you restarted make.
* CMake: Fix my misuse of the HackRF CMake configuration -- was building from too deep in the directory tree
* CMake: Work-around for CMake 3.5 not supporting ExternalProject_Add SOURCE_SUBDIR.
* CMake: Choose a CMP0005 policy to quiet CMake warnings.
* Settings: Show active clock reference. Only show PPM adjustment for HackRF source.
* Setup: Format clock reference frequency in MHz, not Hz.
* Radio Settings: Change reference clock text color.
Make consistent color with other un-editable text.
TODO: This is a bit of a hack to get ui::Text objects to support custom colors, like the Label structures used elsewhere.
* Pin config: VREGMODE=1, add other pins for completeness, comment detail
* Pin setup: More useful comments.
* Pin setup: Change some defaults, only set up PortaPack pins if detected.
* Pin setup: Disable LPC pull-ups on PP CPLD data bus, as CPLD is pulling up.
* Baseband: Allow larger HackRF firmware image.
* HackRF: Remove USER_INTERFACE CMake variable.
* CPLD: Make use of HackRF CPLD tool to generate code.
* Release: Add generation of MD5SUMS, SHA256SUMS during "make release"
* Clock generator: Match clock output currents to HackRF firmware.
Someday, we will share a code base again...
* CMake: Make "firmware" target part of the "all" target.
So now an unqualified "make" will make the firmware binary.
* CMake: Change how HackRF firmware is incorporated into binary.
Use the separate HackRF "RAM" binary. Get rid of the strip-dfu utility, since there's no longer a need to extract the binary from the DFU.
* CMake: Renamed GIT_REVISION* -> GIT_VERSION* to match HackRF build env.
* CMake: Bring git version handling closer to HackRF for code reuse.
* Travis-CI: Rework CI release artifact output.
* Travis-CI: Don't assign PROJECT_NAME within deploy-nightly.sh
* Travis-CI: Oops, don't include distro package for compiler...
...when also installing it from a third-party PPA.
* Travis-CI: Update GCC package, old one seems "retired"?
* Travis-CI: OK, the gcc-arm-none-eabi package is NOT current. Undoing...
* Travis-CI: Path oopsies.
* Travis-CI: More path confusion. I think this will do it. *touch wood*
* Travis-CI: Update build message sent to FreeNode #portapack IRC.
* Travis-CI: Break out BUILD_DATE from BUILD_NAME.
* Travis-CI: Introduce build directories, include MD5 and SHA256 hashes.
* Travis-CI: Fix MD5SUMS/SHA256SUMS paths.
* Travis-CI: Fix typo generating name for binary links.
* Power: Keep 1V8 off until after VAA is brought up.
* Power: Bring up VAA in several steps to keep voltage swing small.
* About: Show longer commit/tag version string.
* Versioning: Report non-CI builds with "local-" version prefix.
* Travis-CI: Report new nightly build site in IRC notification.
* Change use of GIT_VERSION to VERSION_STRING
Required by prior merge.
* Git: add "hackrf" submodule.
* CMake: Use hackrf submodule for build, stop pulling during build.
* Travis: Fix build paths due to CMake submodule changes.
* Travis: Explicitly update submodules recursively
* Revert "Travis: Explicitly update submodules recursively"
This reverts commit b246438d805f431e727e01b7407540e932e89ee1.
* Travis: Try to sort out hackrf submodule output paths...
* Travis: I don't know what I'm doing.
* CMake: "make firmware" problem due to target vs. path used for dependency.
* HackRF: Incorporate YAML security fix.
* CMake: Fix more places where targets should be used...
...instead of paths to outputs.
* CMake: Add DFU file to "make firmware" outputs
* HackRF: Update submodule for CMake m0_bin.s path fix.
* added encoder support to alphanum
* added encoder support to freq-keypad
* UI Redesign -
added BtnGrid & NewButton widgets and created a new button-based
layout, with both encoder and touchscreen are supported.
* Scanner changes:
- using SCANNER.TXT for frequencies, ranges also supported. file
format is the same as any other frequency file, thus can be edited
via the Frequency Manager.
- add nfm bw selector & time-to-wait to the UI
- add SCANNER.TXT to sdcard dir
orignal idea & scanner file adopted from user 'bicurico'
* small changes to scanner
* remember last category on frequency manager
* fix: cast int16_t instead of uint16_t (although i doubt we will
have more than 32767 buttons in the array...)
* added a missing last_category_id on freq manager
2019-10-29 23:53:54 +02:00
|
|
|
}
|
|
|
|
|
2016-02-04 10:27:53 +01:00
|
|
|
/* Image *****************************************************************/
|
|
|
|
|
2023-05-19 08:16:05 +12:00
|
|
|
Image::Image()
|
|
|
|
: Image{{}, nullptr, Color::white(), Color::black()} {
|
2016-02-04 10:27:53 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
Image::Image(
|
2023-05-19 08:16:05 +12:00
|
|
|
const Rect parent_rect,
|
|
|
|
const Bitmap* bitmap,
|
|
|
|
const Color foreground,
|
|
|
|
const Color background)
|
|
|
|
: Widget{parent_rect},
|
|
|
|
bitmap_{bitmap},
|
|
|
|
foreground_{foreground},
|
|
|
|
background_{background} {
|
2016-02-04 10:27:53 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
void Image::set_bitmap(const Bitmap* bitmap) {
|
2023-05-19 08:16:05 +12:00
|
|
|
bitmap_ = bitmap;
|
|
|
|
set_dirty();
|
2016-02-04 10:27:53 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
void Image::set_foreground(const Color color) {
|
2023-05-19 08:16:05 +12:00
|
|
|
foreground_ = color;
|
|
|
|
set_dirty();
|
2016-02-04 10:27:53 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
void Image::set_background(const Color color) {
|
2023-05-19 08:16:05 +12:00
|
|
|
background_ = color;
|
|
|
|
set_dirty();
|
2016-02-04 10:27:53 +01:00
|
|
|
}
|
|
|
|
|
2016-07-28 05:25:33 +02:00
|
|
|
void Image::invert_colors() {
|
2023-05-19 08:16:05 +12:00
|
|
|
Color temp;
|
|
|
|
|
|
|
|
temp = background_;
|
|
|
|
background_ = foreground_;
|
|
|
|
foreground_ = temp;
|
|
|
|
set_dirty();
|
2016-07-28 05:25:33 +02:00
|
|
|
}
|
|
|
|
|
2016-02-04 10:27:53 +01:00
|
|
|
void Image::paint(Painter& painter) {
|
2023-05-19 08:16:05 +12:00
|
|
|
if (bitmap_) {
|
|
|
|
// Code also handles ImageButton behavior.
|
|
|
|
const bool selected = (has_focus() || highlighted());
|
|
|
|
painter.draw_bitmap(
|
|
|
|
screen_pos(),
|
|
|
|
*bitmap_,
|
|
|
|
selected ? background_ : foreground_,
|
|
|
|
selected ? foreground_ : background_);
|
|
|
|
}
|
2016-02-04 10:27:53 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
/* ImageButton ***********************************************************/
|
|
|
|
|
|
|
|
// TODO: Virtually all this code is duplicated from Button. Base class?
|
|
|
|
|
|
|
|
ImageButton::ImageButton(
|
2023-05-19 08:16:05 +12:00
|
|
|
const Rect parent_rect,
|
|
|
|
const Bitmap* bitmap,
|
|
|
|
const Color foreground,
|
|
|
|
const Color background)
|
|
|
|
: Image{parent_rect, bitmap, foreground, background} {
|
|
|
|
set_focusable(true);
|
2016-02-04 10:27:53 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
bool ImageButton::on_key(const KeyEvent key) {
|
2023-05-19 08:16:05 +12:00
|
|
|
if (key == KeyEvent::Select) {
|
|
|
|
if (on_select) {
|
|
|
|
on_select(*this);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
2016-02-04 10:27:53 +01:00
|
|
|
|
2023-05-19 08:16:05 +12:00
|
|
|
return false;
|
2016-02-04 10:27:53 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
bool ImageButton::on_touch(const TouchEvent event) {
|
2023-05-19 08:16:05 +12:00
|
|
|
switch (event.type) {
|
|
|
|
case TouchEvent::Type::Start:
|
|
|
|
set_highlighted(true);
|
|
|
|
set_dirty();
|
|
|
|
return true;
|
2016-02-04 10:27:53 +01:00
|
|
|
|
2023-05-19 08:16:05 +12:00
|
|
|
case TouchEvent::Type::End:
|
|
|
|
set_highlighted(false);
|
|
|
|
set_dirty();
|
|
|
|
if (on_select) {
|
|
|
|
on_select(*this);
|
|
|
|
}
|
|
|
|
return true;
|
2016-02-03 15:48:50 -08:00
|
|
|
|
2023-05-19 08:16:05 +12:00
|
|
|
default:
|
|
|
|
return false;
|
|
|
|
}
|
2016-02-04 10:27:53 +01:00
|
|
|
}
|
|
|
|
|
2023-06-23 16:13:39 -07:00
|
|
|
/* ImageToggle ***********************************************************/
|
|
|
|
ImageToggle::ImageToggle(
|
|
|
|
Rect parent_rect,
|
|
|
|
const Bitmap* bitmap_)
|
|
|
|
: ImageToggle{parent_rect,
|
|
|
|
bitmap_,
|
|
|
|
Color::green(),
|
|
|
|
Color::light_grey(),
|
|
|
|
Color::dark_grey()} {}
|
|
|
|
|
|
|
|
ImageToggle::ImageToggle(
|
|
|
|
Rect parent_rect,
|
|
|
|
const Bitmap* bitmap_,
|
|
|
|
Color foreground_true,
|
|
|
|
Color foreground_false,
|
|
|
|
Color background_)
|
|
|
|
: ImageToggle{parent_rect,
|
|
|
|
bitmap_,
|
|
|
|
bitmap_,
|
|
|
|
foreground_true,
|
|
|
|
background_,
|
|
|
|
foreground_false,
|
|
|
|
background_} {}
|
|
|
|
|
|
|
|
ImageToggle::ImageToggle(
|
|
|
|
Rect parent_rect,
|
|
|
|
const Bitmap* bitmap_true,
|
|
|
|
const Bitmap* bitmap_false,
|
|
|
|
Color foreground_true,
|
|
|
|
Color background_true,
|
|
|
|
Color foreground_false,
|
|
|
|
Color background_false)
|
|
|
|
: ImageButton{parent_rect, bitmap_false, foreground_false, background_false},
|
|
|
|
bitmap_true_{bitmap_true},
|
|
|
|
bitmap_false_{bitmap_false},
|
|
|
|
foreground_true_{foreground_true},
|
|
|
|
background_true_{background_true},
|
|
|
|
foreground_false_{foreground_false},
|
|
|
|
background_false_{background_false},
|
|
|
|
value_{false} {
|
|
|
|
ImageButton::on_select = [this](ImageButton&) {
|
|
|
|
set_value(!value());
|
|
|
|
};
|
|
|
|
}
|
|
|
|
|
|
|
|
bool ImageToggle::value() const {
|
|
|
|
return value_;
|
|
|
|
}
|
|
|
|
|
|
|
|
void ImageToggle::set_value(bool b) {
|
|
|
|
if (b == value_)
|
|
|
|
return;
|
|
|
|
|
|
|
|
value_ = b;
|
|
|
|
set_bitmap(b ? bitmap_true_ : bitmap_false_);
|
|
|
|
set_foreground(b ? foreground_true_ : foreground_false_);
|
|
|
|
set_background(b ? background_true_ : background_false_);
|
|
|
|
|
|
|
|
if (on_change)
|
|
|
|
on_change(b);
|
|
|
|
}
|
|
|
|
|
2016-05-27 06:48:04 +02:00
|
|
|
/* ImageOptionsField *****************************************************/
|
|
|
|
|
|
|
|
ImageOptionsField::ImageOptionsField(
|
2023-05-19 08:16:05 +12:00
|
|
|
const Rect parent_rect,
|
|
|
|
const Color foreground,
|
|
|
|
const Color background,
|
|
|
|
const options_t options)
|
|
|
|
: Widget{parent_rect},
|
|
|
|
options{options},
|
|
|
|
foreground_{foreground},
|
|
|
|
background_{background} {
|
|
|
|
set_focusable(true);
|
2016-05-27 06:48:04 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
size_t ImageOptionsField::selected_index() const {
|
2023-05-19 08:16:05 +12:00
|
|
|
return selected_index_;
|
2016-05-27 06:48:04 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
size_t ImageOptionsField::selected_index_value() const {
|
2023-05-19 08:16:05 +12:00
|
|
|
return options[selected_index_].second;
|
2016-05-27 06:48:04 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
void ImageOptionsField::set_selected_index(const size_t new_index) {
|
2023-05-19 08:16:05 +12:00
|
|
|
if (new_index < options.size()) {
|
|
|
|
if (new_index != selected_index()) {
|
|
|
|
selected_index_ = new_index;
|
|
|
|
if (on_change) {
|
|
|
|
on_change(selected_index(), options[selected_index()].second);
|
|
|
|
}
|
|
|
|
set_dirty();
|
|
|
|
}
|
|
|
|
}
|
2016-05-27 06:48:04 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
void ImageOptionsField::set_by_value(value_t v) {
|
2023-06-12 23:14:26 -07:00
|
|
|
size_t new_index = 0;
|
2023-05-19 08:16:05 +12:00
|
|
|
for (const auto& option : options) {
|
|
|
|
if (option.second == v) {
|
|
|
|
set_selected_index(new_index);
|
2023-06-11 11:47:13 -07:00
|
|
|
return;
|
2023-05-19 08:16:05 +12:00
|
|
|
}
|
2023-06-11 11:47:13 -07:00
|
|
|
|
2023-05-19 08:16:05 +12:00
|
|
|
new_index++;
|
|
|
|
}
|
2023-06-11 11:47:13 -07:00
|
|
|
|
|
|
|
// No exact match was found, default to 0.
|
|
|
|
set_selected_index(0);
|
2016-05-27 06:48:04 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
void ImageOptionsField::set_options(options_t new_options) {
|
2023-05-19 08:16:05 +12:00
|
|
|
options = new_options;
|
2023-06-11 11:47:13 -07:00
|
|
|
|
|
|
|
// Set an invalid index to force on_change.
|
|
|
|
selected_index_ = (size_t)-1;
|
2023-06-12 23:14:26 -07:00
|
|
|
set_selected_index(0);
|
2023-05-19 08:16:05 +12:00
|
|
|
set_dirty();
|
2016-05-27 06:48:04 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
void ImageOptionsField::paint(Painter& painter) {
|
2023-05-19 08:16:05 +12:00
|
|
|
const bool selected = (has_focus() || highlighted());
|
|
|
|
const auto paint_style = selected ? style().invert() : style();
|
|
|
|
|
|
|
|
painter.draw_rectangle(
|
|
|
|
{screen_rect().location(), {screen_rect().size().width() + 4, screen_rect().size().height() + 4}},
|
|
|
|
paint_style.background);
|
|
|
|
|
|
|
|
painter.draw_bitmap(
|
|
|
|
{screen_pos().x() + 2, screen_pos().y() + 2},
|
|
|
|
*options[selected_index_].first,
|
|
|
|
foreground_,
|
|
|
|
background_);
|
2016-05-27 06:48:04 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
void ImageOptionsField::on_focus() {
|
2023-05-19 08:16:05 +12:00
|
|
|
if (on_show_options) {
|
|
|
|
on_show_options();
|
|
|
|
}
|
2016-05-27 06:48:04 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
bool ImageOptionsField::on_encoder(const EncoderEvent delta) {
|
2023-05-19 08:16:05 +12:00
|
|
|
set_selected_index(selected_index() + delta);
|
|
|
|
return true;
|
2016-05-27 06:48:04 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
bool ImageOptionsField::on_touch(const TouchEvent event) {
|
2023-05-19 08:16:05 +12:00
|
|
|
if (event.type == TouchEvent::Type::Start) {
|
|
|
|
focus();
|
|
|
|
}
|
|
|
|
return true;
|
2016-05-27 06:48:04 +02:00
|
|
|
}
|
|
|
|
|
2015-07-08 08:39:24 -07:00
|
|
|
/* OptionsField **********************************************************/
|
|
|
|
|
2016-01-31 09:34:24 +01:00
|
|
|
OptionsField::OptionsField(
|
2023-05-19 08:16:05 +12:00
|
|
|
Point parent_pos,
|
|
|
|
int length,
|
|
|
|
options_t options)
|
|
|
|
: Widget{{parent_pos, {8 * length, 16}}},
|
|
|
|
length_{length},
|
|
|
|
options{options} {
|
|
|
|
set_focusable(true);
|
2016-01-31 09:34:24 +01:00
|
|
|
}
|
|
|
|
|
2015-07-08 08:39:24 -07:00
|
|
|
size_t OptionsField::selected_index() const {
|
2023-05-19 08:16:05 +12:00
|
|
|
return selected_index_;
|
2015-07-08 08:39:24 -07:00
|
|
|
}
|
|
|
|
|
2016-05-13 09:34:15 +02:00
|
|
|
size_t OptionsField::selected_index_value() const {
|
2023-05-19 08:16:05 +12:00
|
|
|
return options[selected_index_].second;
|
2016-05-13 09:34:15 +02:00
|
|
|
}
|
|
|
|
|
2021-03-07 16:05:23 -06:00
|
|
|
void OptionsField::set_selected_index(const size_t new_index, bool trigger_change) {
|
2023-05-19 08:16:05 +12:00
|
|
|
if (new_index < options.size()) {
|
|
|
|
if (new_index != selected_index() || trigger_change) {
|
|
|
|
selected_index_ = new_index;
|
|
|
|
if (on_change) {
|
|
|
|
on_change(selected_index(), options[selected_index()].second);
|
|
|
|
}
|
|
|
|
set_dirty();
|
|
|
|
}
|
|
|
|
}
|
2015-07-08 08:39:24 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
void OptionsField::set_by_value(value_t v) {
|
2023-06-11 11:47:13 -07:00
|
|
|
size_t new_index = 0;
|
2023-05-19 08:16:05 +12:00
|
|
|
for (const auto& option : options) {
|
|
|
|
if (option.second == v) {
|
|
|
|
set_selected_index(new_index);
|
2023-06-11 11:47:13 -07:00
|
|
|
return;
|
2023-05-19 08:16:05 +12:00
|
|
|
}
|
|
|
|
new_index++;
|
|
|
|
}
|
2023-06-11 11:47:13 -07:00
|
|
|
|
|
|
|
// No exact match was found, default to 0.
|
|
|
|
set_selected_index(0);
|
2015-07-08 08:39:24 -07:00
|
|
|
}
|
|
|
|
|
2023-07-04 16:26:26 -07:00
|
|
|
void OptionsField::set_by_nearest_value(value_t v) {
|
|
|
|
size_t new_index = 0;
|
|
|
|
size_t curr_index = 0;
|
|
|
|
int32_t min_diff = INT32_MAX;
|
|
|
|
|
|
|
|
for (const auto& option : options) {
|
|
|
|
auto diff = abs(v - option.second);
|
|
|
|
if (diff < min_diff) {
|
|
|
|
min_diff = diff;
|
|
|
|
new_index = curr_index;
|
|
|
|
}
|
|
|
|
|
|
|
|
curr_index++;
|
|
|
|
}
|
|
|
|
|
|
|
|
set_selected_index(new_index);
|
|
|
|
}
|
|
|
|
|
2016-02-05 17:40:14 +01:00
|
|
|
void OptionsField::set_options(options_t new_options) {
|
2023-05-19 08:16:05 +12:00
|
|
|
options = new_options;
|
2023-06-11 11:47:13 -07:00
|
|
|
|
|
|
|
// Set an invalid index to force on_change.
|
|
|
|
selected_index_ = (size_t)-1;
|
|
|
|
set_selected_index(0);
|
2023-05-19 08:16:05 +12:00
|
|
|
set_dirty();
|
2016-02-05 17:40:14 +01:00
|
|
|
}
|
|
|
|
|
2015-07-08 08:39:24 -07:00
|
|
|
void OptionsField::paint(Painter& painter) {
|
2023-05-19 08:16:05 +12:00
|
|
|
const auto paint_style = has_focus() ? style().invert() : style();
|
|
|
|
|
|
|
|
painter.fill_rectangle({screen_rect().location(), {(int)length_ * 8, 16}}, ui::Color::black());
|
|
|
|
|
|
|
|
if (selected_index() < options.size()) {
|
|
|
|
const auto text = options[selected_index()].first;
|
|
|
|
painter.draw_string(
|
|
|
|
screen_pos(),
|
|
|
|
paint_style,
|
|
|
|
text);
|
|
|
|
}
|
2015-07-08 08:39:24 -07:00
|
|
|
}
|
|
|
|
|
2016-02-04 10:27:53 +01:00
|
|
|
void OptionsField::on_focus() {
|
2023-05-19 08:16:05 +12:00
|
|
|
if (on_show_options) {
|
|
|
|
on_show_options();
|
|
|
|
}
|
2016-02-04 10:27:53 +01:00
|
|
|
}
|
|
|
|
|
2015-07-08 08:39:24 -07:00
|
|
|
bool OptionsField::on_encoder(const EncoderEvent delta) {
|
2023-06-06 11:46:08 -05:00
|
|
|
int32_t new_value = selected_index() + delta;
|
|
|
|
if (new_value < 0)
|
|
|
|
new_value = options.size() - 1;
|
|
|
|
else if ((size_t)new_value >= options.size())
|
|
|
|
new_value = 0;
|
|
|
|
|
|
|
|
set_selected_index(new_value);
|
2023-05-19 08:16:05 +12:00
|
|
|
return true;
|
2015-07-08 08:39:24 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
bool OptionsField::on_touch(const TouchEvent event) {
|
2023-05-19 08:16:05 +12:00
|
|
|
if (event.type == TouchEvent::Type::Start) {
|
|
|
|
focus();
|
|
|
|
}
|
|
|
|
return true;
|
2015-07-08 08:39:24 -07:00
|
|
|
}
|
|
|
|
|
2023-05-10 09:51:09 -07:00
|
|
|
/* TextField ***********************************************************/
|
|
|
|
|
|
|
|
TextField::TextField(
|
2023-05-19 08:16:05 +12:00
|
|
|
std::string& str,
|
|
|
|
size_t max_length,
|
|
|
|
Point position,
|
|
|
|
uint32_t length)
|
|
|
|
: Widget{{position, {8 * static_cast<int>(length), 16}}},
|
|
|
|
text_{str},
|
|
|
|
max_length_{std::max<size_t>(max_length, str.length())},
|
|
|
|
char_count_{std::max<uint32_t>(length, 1)},
|
|
|
|
cursor_pos_{text_.length()},
|
|
|
|
insert_mode_{true} {
|
|
|
|
set_focusable(true);
|
2023-05-10 09:51:09 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
const std::string& TextField::value() const {
|
2023-05-19 08:16:05 +12:00
|
|
|
return text_;
|
2023-05-10 09:51:09 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
void TextField::set_cursor(uint32_t pos) {
|
2023-05-19 08:16:05 +12:00
|
|
|
cursor_pos_ = std::min<size_t>(pos, text_.length());
|
|
|
|
set_dirty();
|
2023-05-10 09:51:09 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
void TextField::set_insert_mode() {
|
2023-05-19 08:16:05 +12:00
|
|
|
insert_mode_ = true;
|
2023-05-10 09:51:09 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
void TextField::set_overwrite_mode() {
|
2023-05-19 08:16:05 +12:00
|
|
|
insert_mode_ = false;
|
2023-05-10 09:51:09 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
void TextField::char_add(char c) {
|
2023-05-19 08:16:05 +12:00
|
|
|
// Don't add if inserting and at max_length and
|
|
|
|
// don't overwrite if past the end of the text.
|
|
|
|
if ((text_.length() >= max_length_ && insert_mode_) ||
|
|
|
|
(cursor_pos_ >= text_.length() && !insert_mode_))
|
|
|
|
return;
|
2023-05-10 09:51:09 -07:00
|
|
|
|
2023-05-19 08:16:05 +12:00
|
|
|
if (insert_mode_)
|
|
|
|
text_.insert(cursor_pos_, 1, c);
|
|
|
|
else
|
|
|
|
text_[cursor_pos_] = c;
|
2023-05-10 09:51:09 -07:00
|
|
|
|
2023-05-19 08:16:05 +12:00
|
|
|
cursor_pos_++;
|
|
|
|
set_dirty();
|
2023-05-10 09:51:09 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
void TextField::char_delete() {
|
2023-05-19 08:16:05 +12:00
|
|
|
if (cursor_pos_ == 0)
|
|
|
|
return;
|
2023-05-10 09:51:09 -07:00
|
|
|
|
2023-05-19 08:16:05 +12:00
|
|
|
cursor_pos_--;
|
|
|
|
text_.erase(cursor_pos_, 1);
|
|
|
|
set_dirty();
|
2023-05-10 09:51:09 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
void TextField::paint(Painter& painter) {
|
2023-05-19 08:16:05 +12:00
|
|
|
constexpr int char_width = 8;
|
|
|
|
|
|
|
|
auto rect = screen_rect();
|
|
|
|
auto text_style = has_focus() ? style().invert() : style();
|
|
|
|
auto offset = 0;
|
|
|
|
|
|
|
|
// Does the string need to be shifted?
|
|
|
|
if (cursor_pos_ >= char_count_)
|
|
|
|
offset = cursor_pos_ - char_count_ + 1;
|
|
|
|
|
|
|
|
// Clear the control.
|
|
|
|
painter.fill_rectangle(rect, text_style.background);
|
|
|
|
|
|
|
|
// Draw the text starting at the offset.
|
|
|
|
for (uint32_t i = 0; i < char_count_ && i + offset < text_.length(); i++) {
|
|
|
|
painter.draw_char(
|
|
|
|
{rect.location().x() + (static_cast<int>(i) * char_width), rect.location().y()},
|
|
|
|
text_style,
|
|
|
|
text_[i + offset]);
|
|
|
|
}
|
2023-05-10 09:51:09 -07:00
|
|
|
|
2023-05-19 08:16:05 +12:00
|
|
|
// Determine cursor position on screen (either the cursor position or the last char).
|
|
|
|
int32_t cursor_x = char_width * (offset > 0 ? char_count_ - 1 : cursor_pos_);
|
|
|
|
Point cursor_point{screen_pos().x() + cursor_x, screen_pos().y()};
|
|
|
|
auto cursor_style = text_style.invert();
|
2023-05-10 09:51:09 -07:00
|
|
|
|
2023-05-19 08:16:05 +12:00
|
|
|
// Invert the cursor character when in overwrite mode.
|
|
|
|
if (!insert_mode_ && (cursor_pos_) < text_.length())
|
|
|
|
painter.draw_char(cursor_point, cursor_style, text_[cursor_pos_]);
|
2023-05-10 09:51:09 -07:00
|
|
|
|
2023-05-19 08:16:05 +12:00
|
|
|
// Draw the cursor.
|
|
|
|
Rect cursor_box{cursor_point, {char_width, 16}};
|
|
|
|
painter.draw_rectangle(cursor_box, cursor_style.background);
|
2023-05-10 09:51:09 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
bool TextField::on_key(const KeyEvent key) {
|
2023-05-19 08:16:05 +12:00
|
|
|
if (key == KeyEvent::Left && cursor_pos_ > 0)
|
|
|
|
cursor_pos_--;
|
|
|
|
else if (key == KeyEvent::Right && cursor_pos_ < text_.length())
|
|
|
|
cursor_pos_++;
|
|
|
|
else if (key == KeyEvent::Select)
|
|
|
|
insert_mode_ = !insert_mode_;
|
|
|
|
else
|
|
|
|
return false;
|
2023-05-10 09:51:09 -07:00
|
|
|
|
2023-05-19 08:16:05 +12:00
|
|
|
set_dirty();
|
|
|
|
return true;
|
2023-05-10 09:51:09 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
bool TextField::on_encoder(const EncoderEvent delta) {
|
2023-05-19 08:16:05 +12:00
|
|
|
int32_t new_pos = cursor_pos_ + delta;
|
2023-05-10 09:51:09 -07:00
|
|
|
|
2023-05-19 08:16:05 +12:00
|
|
|
// Let the encoder wrap around the ends of the text.
|
|
|
|
if (new_pos < 0)
|
|
|
|
new_pos = text_.length();
|
|
|
|
else if (static_cast<size_t>(new_pos) > text_.length())
|
|
|
|
new_pos = 0;
|
2023-05-10 09:51:09 -07:00
|
|
|
|
2023-05-19 08:16:05 +12:00
|
|
|
set_cursor(new_pos);
|
|
|
|
return true;
|
2023-05-10 09:51:09 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
bool TextField::on_touch(const TouchEvent event) {
|
2023-05-19 08:16:05 +12:00
|
|
|
if (event.type == TouchEvent::Type::Start)
|
|
|
|
focus();
|
2023-05-10 09:51:09 -07:00
|
|
|
|
2023-05-19 08:16:05 +12:00
|
|
|
set_dirty();
|
|
|
|
return true;
|
2023-05-10 09:51:09 -07:00
|
|
|
}
|
|
|
|
|
2015-07-08 08:39:24 -07:00
|
|
|
/* NumberField ***********************************************************/
|
|
|
|
|
2016-01-31 09:34:24 +01:00
|
|
|
NumberField::NumberField(
|
2023-05-19 08:16:05 +12:00
|
|
|
Point parent_pos,
|
|
|
|
int length,
|
|
|
|
range_t range,
|
|
|
|
int32_t step,
|
|
|
|
char fill_char,
|
|
|
|
bool can_loop)
|
|
|
|
: Widget{{parent_pos, {8 * length, 16}}},
|
|
|
|
range{range},
|
|
|
|
step{step},
|
|
|
|
length_{length},
|
|
|
|
fill_char{fill_char},
|
|
|
|
can_loop{can_loop} {
|
|
|
|
set_focusable(true);
|
2016-01-31 09:34:24 +01:00
|
|
|
}
|
|
|
|
|
2015-07-08 08:39:24 -07:00
|
|
|
int32_t NumberField::value() const {
|
2023-05-19 08:16:05 +12:00
|
|
|
return value_;
|
2015-07-08 08:39:24 -07:00
|
|
|
}
|
|
|
|
|
2016-08-03 04:53:51 +02:00
|
|
|
void NumberField::set_value(int32_t new_value, bool trigger_change) {
|
2023-05-19 08:16:05 +12:00
|
|
|
if (can_loop) {
|
|
|
|
if (new_value >= range.first)
|
|
|
|
new_value = new_value % (range.second + 1);
|
|
|
|
else
|
|
|
|
new_value = range.second + new_value + 1;
|
|
|
|
}
|
2015-07-08 08:39:24 -07:00
|
|
|
|
2023-05-19 08:16:05 +12:00
|
|
|
new_value = clip_value(new_value);
|
|
|
|
|
|
|
|
if (new_value != value()) {
|
|
|
|
value_ = new_value;
|
|
|
|
if (on_change && trigger_change) {
|
|
|
|
on_change(value_);
|
|
|
|
}
|
|
|
|
set_dirty();
|
|
|
|
}
|
2015-07-08 08:39:24 -07:00
|
|
|
}
|
|
|
|
|
2016-08-03 04:53:51 +02:00
|
|
|
void NumberField::set_range(const int32_t min, const int32_t max) {
|
2023-05-19 08:16:05 +12:00
|
|
|
range.first = min;
|
|
|
|
range.second = max;
|
|
|
|
set_value(value(), false);
|
2016-08-03 04:53:51 +02:00
|
|
|
}
|
|
|
|
|
2017-10-15 15:53:40 +01:00
|
|
|
void NumberField::set_step(const int32_t new_step) {
|
2023-05-19 08:16:05 +12:00
|
|
|
step = new_step;
|
2017-10-15 15:53:40 +01:00
|
|
|
}
|
|
|
|
|
2015-07-08 08:39:24 -07:00
|
|
|
void NumberField::paint(Painter& painter) {
|
2023-05-19 08:16:05 +12:00
|
|
|
const auto text = to_string_dec_int(value_, length_, fill_char);
|
2015-07-08 08:39:24 -07:00
|
|
|
|
2023-05-19 08:16:05 +12:00
|
|
|
const auto paint_style = has_focus() ? style().invert() : style();
|
2015-07-08 08:39:24 -07:00
|
|
|
|
2023-05-19 08:16:05 +12:00
|
|
|
painter.draw_string(
|
|
|
|
screen_pos(),
|
|
|
|
paint_style,
|
|
|
|
text);
|
2015-07-08 08:39:24 -07:00
|
|
|
}
|
|
|
|
|
2016-07-25 16:21:27 +02:00
|
|
|
bool NumberField::on_key(const KeyEvent key) {
|
2023-05-19 08:16:05 +12:00
|
|
|
if (key == KeyEvent::Select) {
|
|
|
|
if (on_select) {
|
|
|
|
on_select(*this);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
2016-07-25 16:21:27 +02:00
|
|
|
|
2023-05-19 08:16:05 +12:00
|
|
|
return false;
|
2016-07-25 16:21:27 +02:00
|
|
|
}
|
|
|
|
|
2015-07-08 08:39:24 -07:00
|
|
|
bool NumberField::on_encoder(const EncoderEvent delta) {
|
2023-05-19 08:16:05 +12:00
|
|
|
set_value(value() + (delta * step));
|
|
|
|
return true;
|
2015-07-08 08:39:24 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
bool NumberField::on_touch(const TouchEvent event) {
|
2023-05-19 08:16:05 +12:00
|
|
|
if (event.type == TouchEvent::Type::Start) {
|
|
|
|
focus();
|
|
|
|
}
|
|
|
|
return true;
|
2015-07-08 08:39:24 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
int32_t NumberField::clip_value(int32_t value) {
|
2023-05-19 08:16:05 +12:00
|
|
|
if (value > range.second) {
|
|
|
|
value = range.second;
|
|
|
|
}
|
|
|
|
if (value < range.first) {
|
|
|
|
value = range.first;
|
|
|
|
}
|
|
|
|
return value;
|
2015-07-08 08:39:24 -07:00
|
|
|
}
|
|
|
|
|
2016-08-06 08:49:45 +02:00
|
|
|
/* SymField **************************************************************/
|
|
|
|
|
2016-12-05 12:56:41 +01:00
|
|
|
SymField::SymField(
|
2023-05-19 08:16:05 +12:00
|
|
|
Point parent_pos,
|
|
|
|
size_t length,
|
|
|
|
symfield_type type)
|
|
|
|
: Widget{{parent_pos, {static_cast<ui::Dim>(8 * length), 16}}},
|
|
|
|
length_{length},
|
|
|
|
type_{type} {
|
|
|
|
uint32_t c;
|
|
|
|
|
|
|
|
// Auto-init
|
|
|
|
if (type == SYMFIELD_OCT) {
|
|
|
|
for (c = 0; c < length; c++)
|
|
|
|
set_symbol_list(c, "01234567");
|
|
|
|
} else if (type == SYMFIELD_DEC) {
|
|
|
|
for (c = 0; c < length; c++)
|
|
|
|
set_symbol_list(c, "0123456789");
|
|
|
|
} else if (type == SYMFIELD_HEX) {
|
|
|
|
for (c = 0; c < length; c++)
|
|
|
|
set_symbol_list(c, "0123456789ABCDEF");
|
|
|
|
} else if (type == SYMFIELD_ALPHANUM) {
|
|
|
|
for (c = 0; c < length; c++)
|
|
|
|
set_symbol_list(c, " 0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZ");
|
|
|
|
}
|
|
|
|
|
|
|
|
set_focusable(true);
|
2016-12-05 12:56:41 +01:00
|
|
|
}
|
|
|
|
|
2023-03-03 23:10:58 +01:00
|
|
|
uint16_t SymField::concatenate_4_octal_u16() {
|
2023-05-19 08:16:05 +12:00
|
|
|
// input array 4 octal digits , return 12 bits, same order, trippled A4-A2-A1|B4-B2-B1|C4-C2-C1|D4-D2-D1
|
|
|
|
uint32_t mul = 1;
|
|
|
|
uint16_t v = 0;
|
|
|
|
|
|
|
|
if (type_ == SYMFIELD_OCT) {
|
|
|
|
for (uint32_t c = 0; c < length_; c++) {
|
|
|
|
v += values_[(length_ - 1 - c)] * mul;
|
|
|
|
mul *= 8; // shift 3 bits to the right every new octal squawk digit
|
|
|
|
}
|
|
|
|
return v;
|
|
|
|
} else
|
|
|
|
return 0;
|
2023-03-03 23:10:58 +01:00
|
|
|
}
|
|
|
|
|
2017-02-07 17:48:17 +00:00
|
|
|
uint32_t SymField::value_dec_u32() {
|
2023-05-19 08:16:05 +12:00
|
|
|
uint32_t mul = 1, v = 0;
|
|
|
|
|
|
|
|
if (type_ == SYMFIELD_DEC) {
|
|
|
|
for (uint32_t c = 0; c < length_; c++) {
|
|
|
|
v += values_[(length_ - 1 - c)] * mul;
|
|
|
|
mul *= 10;
|
|
|
|
}
|
|
|
|
return v;
|
|
|
|
} else
|
|
|
|
return 0;
|
2017-02-07 17:48:17 +00:00
|
|
|
}
|
|
|
|
|
2016-12-05 12:56:41 +01:00
|
|
|
uint64_t SymField::value_hex_u64() {
|
2023-05-19 08:16:05 +12:00
|
|
|
uint64_t v = 0;
|
|
|
|
|
|
|
|
if (type_ != SYMFIELD_DEF) {
|
|
|
|
for (uint32_t c = 0; c < length_; c++)
|
|
|
|
v += (uint64_t)(values_[c]) << (4 * (length_ - 1 - c));
|
|
|
|
return v;
|
|
|
|
} else
|
|
|
|
return 0;
|
2016-12-05 12:56:41 +01:00
|
|
|
}
|
2018-02-23 20:21:24 +00:00
|
|
|
|
|
|
|
std::string SymField::value_string() {
|
2023-05-19 08:16:05 +12:00
|
|
|
std::string return_string{""};
|
|
|
|
|
|
|
|
if (type_ == SYMFIELD_ALPHANUM) {
|
|
|
|
for (uint32_t c = 0; c < length_; c++) {
|
|
|
|
return_string += symbol_list_[0][values_[c]];
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return return_string;
|
2018-02-23 20:21:24 +00:00
|
|
|
}
|
2023-05-19 08:16:05 +12:00
|
|
|
|
2017-03-13 04:09:21 +00:00
|
|
|
uint32_t SymField::get_sym(const uint32_t index) {
|
2023-05-19 08:16:05 +12:00
|
|
|
if (index >= length_) return 0;
|
2016-09-27 03:06:14 +02:00
|
|
|
|
2023-05-19 08:16:05 +12:00
|
|
|
return values_[index];
|
2016-08-06 08:49:45 +02:00
|
|
|
}
|
|
|
|
|
2017-03-13 04:09:21 +00:00
|
|
|
void SymField::set_sym(const uint32_t index, const uint32_t new_value) {
|
2023-05-19 08:16:05 +12:00
|
|
|
if (index >= length_) return;
|
|
|
|
|
|
|
|
uint32_t clipped_value = clip_value(index, new_value);
|
|
|
|
|
|
|
|
if (clipped_value != values_[index]) {
|
|
|
|
values_[index] = clipped_value;
|
|
|
|
if (on_change) {
|
|
|
|
on_change();
|
|
|
|
}
|
|
|
|
set_dirty();
|
|
|
|
}
|
2016-08-06 08:49:45 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
void SymField::set_length(const uint32_t new_length) {
|
2023-05-19 08:16:05 +12:00
|
|
|
if ((new_length <= 32) && (new_length != length_)) {
|
|
|
|
prev_length_ = length_;
|
|
|
|
length_ = new_length;
|
|
|
|
|
|
|
|
// Clip eventual garbage from previous shorter word
|
|
|
|
for (size_t n = 0; n < length_; n++)
|
|
|
|
set_sym(n, values_[n]);
|
|
|
|
|
|
|
|
erase_prev_ = true;
|
|
|
|
set_dirty();
|
|
|
|
}
|
2016-08-06 08:49:45 +02:00
|
|
|
}
|
|
|
|
|
2016-09-27 03:06:14 +02:00
|
|
|
void SymField::set_symbol_list(const uint32_t index, const std::string symbol_list) {
|
2023-05-19 08:16:05 +12:00
|
|
|
if (index >= length_) return;
|
2016-09-27 03:06:14 +02:00
|
|
|
|
2023-05-19 08:16:05 +12:00
|
|
|
symbol_list_[index] = symbol_list;
|
|
|
|
|
|
|
|
// Re-clip symbol's value
|
|
|
|
set_sym(index, values_[index]);
|
2016-08-06 08:49:45 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
void SymField::paint(Painter& painter) {
|
2023-05-19 08:16:05 +12:00
|
|
|
Point pt_draw = screen_pos();
|
|
|
|
|
|
|
|
if (erase_prev_) {
|
|
|
|
painter.fill_rectangle({pt_draw, {(int)prev_length_ * 8, 16}}, Color::black());
|
|
|
|
erase_prev_ = false;
|
|
|
|
}
|
|
|
|
|
|
|
|
for (size_t n = 0; n < length_; n++) {
|
|
|
|
const auto text = symbol_list_[n].substr(values_[n], 1);
|
|
|
|
|
|
|
|
const auto paint_style = (has_focus() && (n == selected_)) ? style().invert() : style();
|
|
|
|
|
|
|
|
painter.draw_string(
|
|
|
|
pt_draw,
|
|
|
|
paint_style,
|
|
|
|
text);
|
|
|
|
|
|
|
|
pt_draw += {8, 0};
|
|
|
|
}
|
2016-08-06 08:49:45 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
bool SymField::on_key(const KeyEvent key) {
|
2023-05-19 08:16:05 +12:00
|
|
|
switch (key) {
|
|
|
|
case KeyEvent::Select:
|
|
|
|
if (on_select) {
|
|
|
|
on_select(*this);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
case KeyEvent::Left:
|
|
|
|
if (selected_ > 0) {
|
|
|
|
selected_--;
|
|
|
|
set_dirty();
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
case KeyEvent::Right:
|
|
|
|
if (selected_ < (length_ - 1)) {
|
|
|
|
selected_++;
|
|
|
|
set_dirty();
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return false;
|
2016-08-06 08:49:45 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
bool SymField::on_encoder(const EncoderEvent delta) {
|
2023-05-19 08:16:05 +12:00
|
|
|
int32_t new_value = (int)values_[selected_] + delta;
|
|
|
|
|
|
|
|
if (new_value >= 0)
|
|
|
|
set_sym(selected_, values_[selected_] + delta);
|
|
|
|
|
|
|
|
return true;
|
2016-08-06 08:49:45 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
bool SymField::on_touch(const TouchEvent event) {
|
2023-05-19 08:16:05 +12:00
|
|
|
if (event.type == TouchEvent::Type::Start) {
|
|
|
|
focus();
|
|
|
|
}
|
|
|
|
return true;
|
2016-08-06 08:49:45 +02:00
|
|
|
}
|
|
|
|
|
2016-09-27 03:06:14 +02:00
|
|
|
int32_t SymField::clip_value(const uint32_t index, const uint32_t value) {
|
2023-05-19 08:16:05 +12:00
|
|
|
size_t symbol_count = symbol_list_[index].length() - 1;
|
|
|
|
|
|
|
|
if (value > symbol_count)
|
|
|
|
return symbol_count;
|
|
|
|
else
|
|
|
|
return value;
|
2016-08-06 08:49:45 +02:00
|
|
|
}
|
|
|
|
|
2017-01-09 02:45:29 +00:00
|
|
|
/* Waveform **************************************************************/
|
|
|
|
|
|
|
|
Waveform::Waveform(
|
2023-05-19 08:16:05 +12:00
|
|
|
Rect parent_rect,
|
|
|
|
int16_t* data,
|
|
|
|
uint32_t length,
|
|
|
|
uint32_t offset,
|
|
|
|
bool digital,
|
|
|
|
Color color)
|
|
|
|
: Widget{parent_rect},
|
|
|
|
data_{data},
|
|
|
|
length_{length},
|
|
|
|
offset_{offset},
|
|
|
|
digital_{digital},
|
|
|
|
color_{color} {
|
|
|
|
// set_focusable(false);
|
|
|
|
// previous_data.resize(length_, 0);
|
2017-01-09 02:45:29 +00:00
|
|
|
}
|
|
|
|
|
2017-11-02 17:11:26 +00:00
|
|
|
void Waveform::set_cursor(const uint32_t i, const int16_t position) {
|
2023-05-19 08:16:05 +12:00
|
|
|
if (i < 2) {
|
|
|
|
if (position != cursors[i]) {
|
|
|
|
cursors[i] = position;
|
|
|
|
set_dirty();
|
|
|
|
}
|
|
|
|
show_cursors = true;
|
|
|
|
}
|
2017-11-02 17:11:26 +00:00
|
|
|
}
|
|
|
|
|
2017-01-09 02:45:29 +00:00
|
|
|
void Waveform::set_offset(const uint32_t new_offset) {
|
2023-05-19 08:16:05 +12:00
|
|
|
if (new_offset != offset_) {
|
|
|
|
offset_ = new_offset;
|
|
|
|
set_dirty();
|
|
|
|
}
|
2017-01-09 02:45:29 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void Waveform::set_length(const uint32_t new_length) {
|
2023-05-19 08:16:05 +12:00
|
|
|
if (new_length != length_) {
|
|
|
|
length_ = new_length;
|
|
|
|
set_dirty();
|
|
|
|
}
|
2017-01-09 02:45:29 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void Waveform::paint(Painter& painter) {
|
2023-05-19 08:16:05 +12:00
|
|
|
size_t n;
|
|
|
|
Coord y, y_offset = screen_rect().location().y();
|
|
|
|
Coord prev_x = screen_rect().location().x(), prev_y;
|
|
|
|
float x, x_inc;
|
|
|
|
Dim h = screen_rect().size().height();
|
|
|
|
const float y_scale = (float)(h - 1) / 65536.0;
|
|
|
|
int16_t* data_start = data_ + offset_;
|
|
|
|
|
|
|
|
if (!length_) return;
|
|
|
|
|
|
|
|
x_inc = (float)screen_rect().size().width() / length_;
|
|
|
|
|
|
|
|
// Clear
|
|
|
|
painter.fill_rectangle_unrolled8(screen_rect(), Color::black());
|
|
|
|
|
|
|
|
if (digital_) {
|
|
|
|
// Digital waveform: each value is an horizontal line
|
|
|
|
x = 0;
|
|
|
|
h--;
|
|
|
|
for (n = 0; n < length_; n++) {
|
|
|
|
y = *(data_start++) ? h : 0;
|
|
|
|
|
|
|
|
if (n) {
|
|
|
|
if (y != prev_y)
|
|
|
|
painter.draw_vline({(Coord)x, y_offset}, h, color_);
|
|
|
|
}
|
|
|
|
|
|
|
|
painter.draw_hline({(Coord)x, y_offset + y}, ceil(x_inc), color_);
|
|
|
|
|
|
|
|
prev_y = y;
|
|
|
|
x += x_inc;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
// Analog waveform: each value is a point's Y coordinate
|
|
|
|
x = prev_x + x_inc;
|
|
|
|
h /= 2;
|
|
|
|
prev_y = y_offset + h - (*(data_start++) * y_scale);
|
|
|
|
for (n = 1; n < length_; n++) {
|
|
|
|
y = y_offset + h - (*(data_start++) * y_scale);
|
|
|
|
display.draw_line({prev_x, prev_y}, {(Coord)x, y}, color_);
|
|
|
|
|
|
|
|
prev_x = x;
|
|
|
|
prev_y = y;
|
|
|
|
x += x_inc;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Cursors
|
|
|
|
if (show_cursors) {
|
|
|
|
for (n = 0; n < 2; n++) {
|
|
|
|
painter.draw_vline(
|
|
|
|
Point(std::min(screen_rect().size().width(), (int)cursors[n]), y_offset),
|
|
|
|
screen_rect().size().height(),
|
|
|
|
cursor_colors[n]);
|
|
|
|
}
|
|
|
|
}
|
2017-01-09 02:45:29 +00:00
|
|
|
}
|
|
|
|
|
2017-03-13 04:09:21 +00:00
|
|
|
/* VuMeter **************************************************************/
|
|
|
|
|
|
|
|
VuMeter::VuMeter(
|
2023-05-19 08:16:05 +12:00
|
|
|
Rect parent_rect,
|
|
|
|
uint32_t LEDs,
|
|
|
|
bool show_max)
|
|
|
|
: Widget{parent_rect},
|
|
|
|
LEDs_{LEDs},
|
|
|
|
show_max_{show_max} {
|
|
|
|
// set_focusable(false);
|
|
|
|
LED_height = std::max(1UL, parent_rect.size().height() / LEDs);
|
|
|
|
split = 256 / LEDs;
|
2017-03-13 04:09:21 +00:00
|
|
|
}
|
|
|
|
|
2017-05-18 11:06:11 +01:00
|
|
|
void VuMeter::set_value(const uint32_t new_value) {
|
2023-05-19 08:16:05 +12:00
|
|
|
if ((new_value != value_) && (new_value < 256)) {
|
|
|
|
value_ = new_value;
|
|
|
|
set_dirty();
|
|
|
|
}
|
2017-03-13 04:09:21 +00:00
|
|
|
}
|
|
|
|
|
2017-05-18 11:06:11 +01:00
|
|
|
void VuMeter::set_mark(const uint32_t new_mark) {
|
2023-05-19 08:16:05 +12:00
|
|
|
if ((new_mark != mark) && (new_mark < 256)) {
|
|
|
|
mark = new_mark;
|
|
|
|
set_dirty();
|
|
|
|
}
|
2017-03-13 04:09:21 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void VuMeter::paint(Painter& painter) {
|
2023-05-19 08:16:05 +12:00
|
|
|
uint32_t bar;
|
|
|
|
Color color;
|
|
|
|
bool lit = false;
|
|
|
|
uint32_t bar_level;
|
|
|
|
Point pos = screen_rect().location();
|
|
|
|
Dim width = screen_rect().size().width() - 4;
|
|
|
|
Dim height = screen_rect().size().height();
|
|
|
|
Dim bottom = pos.y() + height;
|
|
|
|
Coord marks_x = pos.x() + width;
|
|
|
|
|
|
|
|
if (value_ != prev_value) {
|
|
|
|
bar_level = LEDs_ - ((value_ + 1) / split);
|
|
|
|
|
|
|
|
// Draw LEDs
|
|
|
|
for (bar = 0; bar < LEDs_; bar++) {
|
|
|
|
if (bar >= bar_level)
|
|
|
|
lit = true;
|
|
|
|
|
|
|
|
if (bar == 0)
|
|
|
|
color = lit ? Color::red() : Color::dark_grey();
|
|
|
|
else if (bar == 1)
|
|
|
|
color = lit ? Color::orange() : Color::dark_grey();
|
|
|
|
else if ((bar == 2) || (bar == 3))
|
|
|
|
color = lit ? Color::yellow() : Color::dark_grey();
|
|
|
|
else
|
|
|
|
color = lit ? Color::green() : Color::dark_grey();
|
|
|
|
|
|
|
|
painter.fill_rectangle({pos.x(), pos.y() + (Coord)(bar * (LED_height + 1)), width, (Coord)LED_height}, color);
|
|
|
|
}
|
|
|
|
prev_value = value_;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Update max level
|
|
|
|
if (show_max_) {
|
|
|
|
if (value_ > max) {
|
|
|
|
max = value_;
|
|
|
|
hold_timer = 30; // 0.5s @ 60Hz
|
|
|
|
} else {
|
|
|
|
if (hold_timer) {
|
|
|
|
hold_timer--;
|
|
|
|
} else {
|
|
|
|
if (max) max--; // Let it drop
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Draw max level
|
|
|
|
if (max != prev_max) {
|
|
|
|
painter.draw_hline({marks_x, bottom - (height * prev_max) / 256}, 8, Color::black());
|
|
|
|
painter.draw_hline({marks_x, bottom - (height * max) / 256}, 8, Color::white());
|
|
|
|
if (prev_max == mark)
|
|
|
|
prev_mark = 0; // Force mark refresh
|
|
|
|
prev_max = max;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Draw mark (forced refresh)
|
|
|
|
if (mark) {
|
|
|
|
painter.draw_hline({marks_x, bottom - (height * prev_mark) / 256}, 8, Color::black());
|
|
|
|
painter.draw_hline({marks_x, bottom - (height * mark) / 256}, 8, Color::grey());
|
|
|
|
prev_mark = mark;
|
|
|
|
}
|
2017-03-13 04:09:21 +00:00
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}
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2015-07-08 08:39:24 -07:00
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} /* namespace ui */
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