mirror of
https://github.com/portapack-mayhem/mayhem-firmware.git
synced 2024-12-21 07:27:43 +00:00
301 lines
9.5 KiB
C
301 lines
9.5 KiB
C
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/*
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
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2011,2012,2013 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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---
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A special exception to the GPL can be applied should you wish to distribute
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a combined work that includes ChibiOS/RT, without being obliged to provide
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the source code for any proprietary components. See the file exception.txt
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for full details of how and when the exception can be applied.
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*/
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/**
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* @file common/ARMCMx/nvic.h
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* @brief Cortex-Mx NVIC support macros and structures.
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*
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* @addtogroup COMMON_ARMCMx_NVIC
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* @{
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*/
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#ifndef _NVIC_H_
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#define _NVIC_H_
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/**
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* @name System vector numbers
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* @{
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*/
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#define HANDLER_MEM_MANAGE 0 /**< MEM MANAGE vector id. */
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#define HANDLER_BUS_FAULT 1 /**< BUS FAULT vector id. */
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#define HANDLER_USAGE_FAULT 2 /**< USAGE FAULT vector id. */
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#define HANDLER_RESERVED_3 3
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#define HANDLER_RESERVED_4 4
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#define HANDLER_RESERVED_5 5
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#define HANDLER_RESERVED_6 6
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#define HANDLER_SVCALL 7 /**< SVCALL vector id. */
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#define HANDLER_DEBUG_MONITOR 8 /**< DEBUG MONITOR vector id. */
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#define HANDLER_RESERVED_9 9
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#define HANDLER_PENDSV 10 /**< PENDSV vector id. */
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#define HANDLER_SYSTICK 11 /**< SYS TCK vector id. */
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/** @} */
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typedef volatile uint8_t IOREG8; /**< 8 bits I/O register type. */
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typedef volatile uint32_t IOREG32; /**< 32 bits I/O register type. */
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/**
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* @brief NVIC ITCR register.
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*/
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#define NVIC_ITCR (*((IOREG32 *)0xE000E004U))
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/**
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* @brief Structure representing the SYSTICK I/O space.
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*/
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typedef struct {
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IOREG32 CSR;
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IOREG32 RVR;
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IOREG32 CVR;
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IOREG32 CBVR;
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} CMx_ST;
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/**
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* @brief SYSTICK peripheral base address.
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*/
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#define STBase ((CMx_ST *)0xE000E010U)
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#define ST_CSR (STBase->CSR)
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#define ST_RVR (STBase->RVR)
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#define ST_CVR (STBase->CVR)
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#define ST_CBVR (STBase->CBVR)
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#define CSR_ENABLE_MASK (0x1U << 0)
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#define ENABLE_OFF_BITS (0U << 0)
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#define ENABLE_ON_BITS (1U << 0)
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#define CSR_TICKINT_MASK (0x1U << 1)
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#define TICKINT_DISABLED_BITS (0U << 1)
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#define TICKINT_ENABLED_BITS (1U << 1)
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#define CSR_CLKSOURCE_MASK (0x1U << 2)
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#define CLKSOURCE_EXT_BITS (0U << 2)
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#define CLKSOURCE_CORE_BITS (1U << 2)
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#define CSR_COUNTFLAG_MASK (0x1U << 16)
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#define RVR_RELOAD_MASK (0xFFFFFFU << 0)
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#define CVR_CURRENT_MASK (0xFFFFFFU << 0)
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#define CBVR_TENMS_MASK (0xFFFFFFU << 0)
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#define CBVR_SKEW_MASK (0x1U << 30)
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#define CBVR_NOREF_MASK (0x1U << 31)
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/**
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* @brief Structure representing the NVIC I/O space.
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*/
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typedef struct {
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IOREG32 ISER[8];
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IOREG32 unused1[24];
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IOREG32 ICER[8];
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IOREG32 unused2[24];
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IOREG32 ISPR[8];
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IOREG32 unused3[24];
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IOREG32 ICPR[8];
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IOREG32 unused4[24];
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IOREG32 IABR[8];
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IOREG32 unused5[56];
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IOREG32 IPR[60];
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IOREG32 unused6[644];
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IOREG32 STIR;
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} CMx_NVIC;
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/**
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* @brief NVIC peripheral base address.
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*/
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#define NVICBase ((CMx_NVIC *)0xE000E100U)
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#define NVIC_ISER(n) (NVICBase->ISER[n])
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#define NVIC_ICER(n) (NVICBase->ICER[n])
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#define NVIC_ISPR(n) (NVICBase->ISPR[n])
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#define NVIC_ICPR(n) (NVICBase->ICPR[n])
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#define NVIC_IABR(n) (NVICBase->IABR[n])
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#define NVIC_IPR(n) (NVICBase->IPR[n])
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#define NVIC_STIR (NVICBase->STIR)
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/**
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* @brief Structure representing the System Control Block I/O space.
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*/
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typedef struct {
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IOREG32 CPUID;
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IOREG32 ICSR;
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IOREG32 VTOR;
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IOREG32 AIRCR;
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IOREG32 SCR;
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IOREG32 CCR;
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IOREG32 SHPR[3];
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IOREG32 SHCSR;
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IOREG32 CFSR;
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IOREG32 HFSR;
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IOREG32 DFSR;
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IOREG32 MMFAR;
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IOREG32 BFAR;
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IOREG32 AFSR;
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IOREG32 PFR[2];
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IOREG32 DFR;
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IOREG32 ADR;
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IOREG32 MMFR[4];
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IOREG32 SAR[5];
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IOREG32 unused1[5];
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IOREG32 CPACR;
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} CMx_SCB;
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/**
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* @brief SCB peripheral base address.
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*/
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#define SCBBase ((CMx_SCB *)0xE000ED00U)
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#define SCB_CPUID (SCBBase->CPUID)
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#define SCB_ICSR (SCBBase->ICSR)
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#define SCB_VTOR (SCBBase->VTOR)
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#define SCB_AIRCR (SCBBase->AIRCR)
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#define SCB_SCR (SCBBase->SCR)
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#define SCB_CCR (SCBBase->CCR)
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#define SCB_SHPR(n) (SCBBase->SHPR[n])
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#define SCB_SHCSR (SCBBase->SHCSR)
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#define SCB_CFSR (SCBBase->CFSR)
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#define SCB_HFSR (SCBBase->HFSR)
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#define SCB_DFSR (SCBBase->DFSR)
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#define SCB_MMFAR (SCBBase->MMFAR)
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#define SCB_BFAR (SCBBase->BFAR)
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#define SCB_AFSR (SCBBase->AFSR)
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#define SCB_PFR(n) (SCBBase->PFR[n])
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#define SCB_DFR (SCBBase->DFR)
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#define SCB_ADR (SCBBase->ADR)
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#define SCB_MMFR(n) (SCBBase->MMFR[n])
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#define SCB_SAR(n) (SCBBase->SAR[n])
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#define SCB_CPACR (SCBBase->CPACR)
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#define ICSR_VECTACTIVE_MASK (0x1FFU << 0)
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#define ICSR_RETTOBASE (0x1U << 11)
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#define ICSR_VECTPENDING_MASK (0x1FFU << 12)
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#define ICSR_ISRPENDING (0x1U << 22)
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#define ICSR_ISRPREEMPT (0x1U << 23)
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#define ICSR_PENDSTCLR (0x1U << 25)
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#define ICSR_PENDSTSET (0x1U << 26)
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#define ICSR_PENDSVCLR (0x1U << 27)
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#define ICSR_PENDSVSET (0x1U << 28)
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#define ICSR_NMIPENDSET (0x1U << 31)
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#define AIRCR_VECTKEY 0x05FA0000U
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#define AIRCR_PRIGROUP_MASK (0x7U << 8)
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#define AIRCR_PRIGROUP(n) ((n) << 8)
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/**
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* @brief Structure representing the FPU I/O space.
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*/
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typedef struct {
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IOREG32 unused1[1];
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IOREG32 FPCCR;
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IOREG32 FPCAR;
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IOREG32 FPDSCR;
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IOREG32 MVFR0;
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IOREG32 MVFR1;
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} CMx_FPU;
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/**
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* @brief FPU peripheral base address.
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*/
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#define FPUBase ((CMx_FPU *)0xE000EF30U)
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#define SCB_FPCCR (FPUBase->FPCCR)
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#define SCB_FPCAR (FPUBase->FPCAR)
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#define SCB_FPDSCR (FPUBase->FPDSCR)
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#define SCB_MVFR0 (FPUBase->MVFR0)
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#define SCB_MVFR1 (FPUBase->MVFR1)
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#define FPCCR_ASPEN (0x1U << 31)
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#define FPCCR_LSPEN (0x1U << 30)
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#define FPCCR_MONRDY (0x1U << 8)
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#define FPCCR_BFRDY (0x1U << 6)
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#define FPCCR_MMRDY (0x1U << 5)
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#define FPCCR_HFRDY (0x1U << 4)
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#define FPCCR_THREAD (0x1U << 3)
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#define FPCCR_USER (0x1U << 1)
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#define FPCCR_LSPACT (0x1U << 0)
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#define FPDSCR_AHP (0x1U << 26)
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#define FPDSCR_DN (0x1U << 25)
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#define FPDSCR_FZ (0x1U << 24)
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#define FPDSCR_RMODE(n) ((n##U) << 22)
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/**
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* @brief Structure representing the SCS I/O space.
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*/
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typedef struct {
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IOREG32 DHCSR;
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IOREG32 DCRSR;
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IOREG32 DCRDR;
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IOREG32 DEMCR;
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} CMx_SCS;
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/**
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* @brief SCS peripheral base address.
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*/
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#define SCSBase ((CMx_SCS *)0xE000EDF0U)
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#define SCS_DHCSR (SCSBase->DHCSR)
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#define SCS_DCRSR (SCSBase->DCRSR)
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#define SCS_DCRDR (SCSBase->DCRDR)
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#define SCS_DEMCR (SCSBase->DEMCR)
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#define SCS_DEMCR_TRCENA (0x1U << 24)
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/**
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* @brief Structure representing the DWT I/O space.
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*/
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typedef struct {
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IOREG32 CTRL;
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IOREG32 CYCCNT;
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IOREG32 CPICNT;
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IOREG32 EXCCNT;
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IOREG32 SLEEPCNT;
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IOREG32 LSUCNT;
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IOREG32 FOLDCNT;
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IOREG32 PCSR;
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} CMx_DWT;
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/**
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* @brief DWT peripheral base address.
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*/
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#define DWTBase ((CMx_DWT *)0xE0001000U)
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#define DWT_CTRL (DWTBase->CTRL)
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#define DWT_CYCCNT (DWTBase->CYCCNT)
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#define DWT_CPICNT (DWTBase->CPICNT)
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#define DWT_EXCCNT (DWTBase->EXCCNT)
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#define DWT_SLEEPCNT (DWTBase->SLEEPCNT)
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#define DWT_LSUCNT (DWTBase->LSUCNT)
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#define DWT_FOLDCNT (DWTBase->FOLDCNT)
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#define DWT_PCSR (DWTBase->PCSR)
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#define DWT_CTRL_CYCCNTENA (0x1U << 0)
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#ifdef __cplusplus
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extern "C" {
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#endif
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void nvicEnableVector(uint32_t n, uint32_t prio);
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void nvicDisableVector(uint32_t n);
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void nvicSetSystemHandlerPriority(uint32_t handler, uint32_t prio);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _NVIC_H_ */
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/** @} */
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