2015-07-08 08:39:24 -07:00
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/*
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* Copyright (C) 2014 Jared Boone, ShareBrained Technology, Inc.
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*
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* This file is part of PortaPack.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 51 Franklin Street,
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* Boston, MA 02110-1301, USA.
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*/
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#include "clock_manager.hpp"
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2020-10-24 00:24:05 +08:00
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#include "portapack_persistent_memory.hpp"
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Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 07:56:21 +01:00
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#include "portapack_io.hpp"
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2015-07-08 08:39:24 -07:00
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#include "hackrf_hal.hpp"
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using namespace hackrf::one;
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#include "lpc43xx_cpp.hpp"
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using namespace lpc43xx;
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constexpr uint32_t si5351_vco_f = 800000000;
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constexpr si5351::Inputs si5351_inputs {
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.f_xtal = si5351_xtal_f,
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.f_clkin = si5351_clkin_f,
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.clkin_div = 1,
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};
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static_assert(si5351_inputs.f_xtal == si5351_xtal_f, "XTAL output frequency wrong");
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static_assert(si5351_inputs.f_clkin_out() == si5351_clkin_f, "CLKIN output frequency wrong");
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2023-02-16 12:09:23 +00:00
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constexpr si5351::PLLInputSource::Type si5351c_pll_input_sources {
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2015-07-08 08:39:24 -07:00
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si5351::PLLInputSource::PLLA_Source_XTAL
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| si5351::PLLInputSource::PLLB_Source_CLKIN
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| si5351::PLLInputSource::CLKIN_Div1
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};
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2023-02-16 12:09:23 +00:00
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constexpr si5351::PLLInputSource::Type si5351a_pll_input_sources {
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si5351::PLLInputSource::PLLA_Source_XTAL
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| si5351::PLLInputSource::PLLB_Source_XTAL
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| si5351::PLLInputSource::CLKIN_Div1
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};
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2015-07-08 08:39:24 -07:00
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constexpr si5351::PLL si5351_pll_xtal_25m {
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.f_in = si5351_inputs.f_xtal,
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.a = 32,
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.b = 0,
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.c = 1,
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};
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constexpr auto si5351_pll_a_xtal_reg = si5351_pll_xtal_25m.reg(0);
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constexpr si5351::PLL si5351_pll_clkin_10m {
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.f_in = si5351_inputs.f_clkin_out(),
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.a = 80,
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.b = 0,
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.c = 1,
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};
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2023-02-16 12:09:23 +00:00
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constexpr auto si5351c_pll_b_clkin_reg = si5351_pll_clkin_10m.reg(1);
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constexpr auto si5351a_pll_a_clkin_reg = si5351_pll_clkin_10m.reg(0);
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2015-07-08 08:39:24 -07:00
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static_assert(si5351_pll_xtal_25m.f_vco() == si5351_vco_f, "PLL XTAL frequency wrong");
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static_assert(si5351_pll_xtal_25m.p1() == 3584, "PLL XTAL P1 wrong");
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static_assert(si5351_pll_xtal_25m.p2() == 0, "PLL XTAL P2 wrong");
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static_assert(si5351_pll_xtal_25m.p3() == 1, "PLL XTAL P3 wrong");
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static_assert(si5351_pll_clkin_10m.f_vco() == si5351_vco_f, "PLL CLKIN frequency wrong");
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static_assert(si5351_pll_clkin_10m.p1() == 9728, "PLL CLKIN P1 wrong");
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static_assert(si5351_pll_clkin_10m.p2() == 0, "PLL CLKIN P2 wrong");
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static_assert(si5351_pll_clkin_10m.p3() == 1, "PLL CLKIN P3 wrong");
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/*
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constexpr si5351::MultisynthFractional si5351_ms_18m432 {
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.f_src = si5351_vco_f,
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.a = 43,
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.b = 29,
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.c = 72,
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.r_div = 1,
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};
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*/
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/*
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constexpr si5351::MultisynthFractional si5351_ms_0_20m {
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.f_src = si5351_vco_f,
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.a = 20,
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.b = 0,
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.c = 1,
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.r_div = 1,
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};
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constexpr auto si5351_ms_0_20m_reg = si5351_ms_0_20m.reg(0);
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*/
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constexpr si5351::MultisynthFractional si5351_ms_0_8m {
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.f_src = si5351_vco_f,
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.a = 50,
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.b = 0,
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.c = 1,
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.r_div = 1,
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};
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2023-02-16 12:09:23 +00:00
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constexpr auto si5351c_ms_0_8m_reg = si5351_ms_0_8m.reg(clock_generator_output_og_codec);
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2015-07-08 08:39:24 -07:00
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constexpr si5351::MultisynthFractional si5351_ms_group {
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.f_src = si5351_vco_f,
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.a = 80, /* Don't care */
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.b = 0,
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.c = 1,
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.r_div = 0,
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};
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2023-02-16 12:09:23 +00:00
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constexpr auto si5351c_ms_1_group_reg = si5351_ms_group.reg(clock_generator_output_og_cpld);
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constexpr auto si5351c_ms_2_group_reg = si5351_ms_group.reg(clock_generator_output_og_sgpio);
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constexpr si5351::MultisynthFractional si5351_ms_16m {
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.f_src = si5351_vco_f,
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.a = 50,
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.b = 0,
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.c = 1,
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.r_div = 0,
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};
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constexpr auto si5351a_ms_1_sgpio_16m_reg = si5351_ms_16m.reg(clock_generator_output_r9_sgpio);
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2015-07-08 08:39:24 -07:00
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constexpr si5351::MultisynthFractional si5351_ms_10m {
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.f_src = si5351_vco_f,
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.a = 80,
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.b = 0,
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.c = 1,
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.r_div = 0,
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};
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2023-02-16 12:09:23 +00:00
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constexpr auto si5351c_ms_3_10m_reg = si5351_ms_10m.reg(3);
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constexpr auto si5351a_ms_2_mcu_10m_reg = si5351_ms_10m.reg(clock_generator_output_r9_mcu_clkin);
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2015-07-08 08:39:24 -07:00
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2015-09-02 17:45:19 -07:00
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constexpr si5351::MultisynthFractional si5351_ms_40m {
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2015-07-08 08:39:24 -07:00
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.f_src = si5351_vco_f,
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2015-09-02 17:45:19 -07:00
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.a = 20,
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2015-07-08 08:39:24 -07:00
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.b = 0,
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.c = 1,
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.r_div = 0,
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};
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2015-09-02 17:45:19 -07:00
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constexpr auto si5351_ms_rffc5072 = si5351_ms_40m;
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2023-02-16 12:09:23 +00:00
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constexpr auto si5351_ms_max283x = si5351_ms_40m;
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2015-07-08 08:39:24 -07:00
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2023-02-16 12:09:23 +00:00
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constexpr auto si5351c_ms_4_reg = si5351_ms_rffc5072.reg(clock_generator_output_og_first_if);
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constexpr auto si5351c_ms_5_reg = si5351_ms_max283x.reg(clock_generator_output_og_second_if);
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constexpr auto si5351a_ms_0_if_40m_reg = si5351_ms_40m.reg(clock_generator_output_r9_if);
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2015-07-08 08:39:24 -07:00
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static_assert(si5351_ms_10m.f_out() == 10000000, "MS 10MHz f_out wrong");
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static_assert(si5351_ms_10m.p1() == 9728, "MS 10MHz p1 wrong");
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static_assert(si5351_ms_10m.p2() == 0, "MS 10MHz p2 wrong");
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static_assert(si5351_ms_10m.p3() == 1, "MS 10MHz p3 wrong");
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static_assert(si5351_ms_rffc5072.f_out() == rffc5072_reference_f, "RFFC5072 reference f_out wrong");
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2023-02-16 12:09:23 +00:00
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static_assert(si5351_ms_max283x.f_out() == max283x_reference_f, "MAX283x reference f_out wrong");
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2015-07-08 08:39:24 -07:00
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constexpr si5351::MultisynthInteger si5351_ms_int_off {
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.f_src = si5351_vco_f,
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.a = 255,
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.r_div = 0,
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};
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2023-02-16 12:09:23 +00:00
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constexpr si5351::MultisynthInteger si5351_ms_int_40m {
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2015-07-08 08:39:24 -07:00
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.f_src = si5351_vco_f,
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.a = 20,
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.r_div = 0,
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};
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2023-02-16 12:09:23 +00:00
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constexpr si5351::MultisynthInteger si5351_ms_int_10m {
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.f_src = si5351_vco_f,
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.a = 80,
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.r_div = 0,
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};
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constexpr auto si5351c_ms_int_mcu_clkin = si5351_ms_int_40m;
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constexpr auto si5351a_ms_int_mcu_clkin = si5351_ms_int_10m;
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constexpr auto si5351c_ms6_7_off_mcu_clkin_reg = si5351::ms6_7_reg(si5351_ms_int_off, si5351c_ms_int_mcu_clkin);
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constexpr auto si5351a_ms6_7_off_reg = si5351::ms6_7_reg(si5351_ms_int_off, si5351_ms_int_off);
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2015-07-08 08:39:24 -07:00
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static_assert(si5351_ms_int_off.f_out() == 3137254, "MS int off f_out wrong");
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static_assert(si5351_ms_int_off.p1() == 255, "MS int off P1 wrong");
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2023-02-16 12:09:23 +00:00
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static_assert(si5351c_ms_int_mcu_clkin.f_out() == mcu_clkin_og_f, "MS int MCU CLKIN OG f_out wrong");
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static_assert(si5351a_ms_int_mcu_clkin.f_out() == mcu_clkin_r9_f, "MS int MCU CLKIN r9 f_out wrong");
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2015-07-08 08:39:24 -07:00
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using namespace si5351;
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2023-02-16 12:09:23 +00:00
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static constexpr ClockControl::MultiSynthSource get_si5351c_reference_clock_generator_pll(const ClockManager::ReferenceSource reference_source) {
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Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 07:56:21 +01:00
|
|
|
return (reference_source == ClockManager::ReferenceSource::Xtal)
|
|
|
|
|
? ClockControl::MultiSynthSource::PLLA
|
|
|
|
|
: ClockControl::MultiSynthSource::PLLB
|
|
|
|
|
;
|
|
|
|
|
}
|
2015-07-08 08:39:24 -07:00
|
|
|
|
2023-02-16 12:09:23 +00:00
|
|
|
constexpr ClockControls si5351c_clock_control_common { {
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|
{ ClockControl::ClockCurrentDrive::_8mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, get_si5351c_reference_clock_generator_pll(ClockManager::ReferenceSource::Xtal), ClockControl::MultiSynthMode::Fractional, ClockControl::ClockPowerDown::Power_Off },
|
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|
|
|
{ ClockControl::ClockCurrentDrive::_2mA, ClockControl::ClockSource::MS_Group, ClockControl::ClockInvert::Invert, get_si5351c_reference_clock_generator_pll(ClockManager::ReferenceSource::Xtal), ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off },
|
|
|
|
|
{ ClockControl::ClockCurrentDrive::_2mA, ClockControl::ClockSource::MS_Group, ClockControl::ClockInvert::Normal, get_si5351c_reference_clock_generator_pll(ClockManager::ReferenceSource::Xtal), ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off },
|
|
|
|
|
{ ClockControl::ClockCurrentDrive::_8mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, get_si5351c_reference_clock_generator_pll(ClockManager::ReferenceSource::Xtal), ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off },
|
|
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|
|
{ ClockControl::ClockCurrentDrive::_6mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Invert, get_si5351c_reference_clock_generator_pll(ClockManager::ReferenceSource::Xtal), ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off },
|
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|
|
{ ClockControl::ClockCurrentDrive::_4mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, get_si5351c_reference_clock_generator_pll(ClockManager::ReferenceSource::Xtal), ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off },
|
|
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|
|
{ ClockControl::ClockCurrentDrive::_2mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, get_si5351c_reference_clock_generator_pll(ClockManager::ReferenceSource::Xtal), ClockControl::MultiSynthMode::Fractional, ClockControl::ClockPowerDown::Power_Off },
|
|
|
|
|
{ ClockControl::ClockCurrentDrive::_2mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, get_si5351c_reference_clock_generator_pll(ClockManager::ReferenceSource::Xtal), ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off },
|
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 07:56:21 +01:00
|
|
|
} };
|
2015-07-08 08:39:24 -07:00
|
|
|
|
2023-02-16 12:09:23 +00:00
|
|
|
constexpr ClockControls si5351a_clock_control_common { {
|
|
|
|
|
{ ClockControl::ClockCurrentDrive::_6mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, ClockControl::MultiSynthSource::PLLA, ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off },
|
|
|
|
|
{ ClockControl::ClockCurrentDrive::_4mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, ClockControl::MultiSynthSource::PLLA, ClockControl::MultiSynthMode::Fractional, ClockControl::ClockPowerDown::Power_Off },
|
|
|
|
|
{ ClockControl::ClockCurrentDrive::_8mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, ClockControl::MultiSynthSource::PLLA, ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off },
|
|
|
|
|
{ ClockControl::ClockCurrentDrive::_2mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, ClockControl::MultiSynthSource::PLLA, ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off },
|
|
|
|
|
{ ClockControl::ClockCurrentDrive::_2mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, ClockControl::MultiSynthSource::PLLA, ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off },
|
|
|
|
|
{ ClockControl::ClockCurrentDrive::_2mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, ClockControl::MultiSynthSource::PLLA, ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off },
|
|
|
|
|
{ ClockControl::ClockCurrentDrive::_2mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, ClockControl::MultiSynthSource::PLLA, ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off },
|
|
|
|
|
{ ClockControl::ClockCurrentDrive::_2mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, ClockControl::MultiSynthSource::PLLA, ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off },
|
|
|
|
|
} };
|
PortaPack Sync, take 2 (#215)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* PCB: Change PCB stackup, Tg, clarify solder mask color, use more metric.
* PCB: Move HackRF header P9 to B.CrtYd layer.
* PCB: Change a Tg reference I missed.
* PCB: Update footprints for parts with mismatched CAD->tape rotation.
Adjust a few layer choice and line thickness bits.
* PCB: Got cold feet, switched back to rectangular pads.
* PCB: Add Eco layers to be visible and Gerber output.
* PCB: Use aux origin for plotting, for tidier coordinates.
* PCB: Output Gerber job file, because why not?
* Schematic: Correct footprints for two reference-related components.
* Schematic: Remove manfuacturer and part number for DNP component.
* Schematic: Specify resistor value, manufacturer, part number for reference oscillator series termination.
* PCB: Update netlist and footprints from schematic.
* Netlist: Updated component values, footprints.
* PCB: Nudge some components and traces to address DRC clearance violations.
* PCB: Allow KiCad to update zone timestamps (again?!).
* PCB: Generate *all* Gerber layers.
* Schematic, PCB: Update revision to 20181025.
* PCB: Adjust fab layer annotations orientation and font size.
* PCB: Hide mounting hole reference designators on silk layer.
* PCB: Shrink U1, U3 pads to get 0.2mm space between pads.
* PCB: Set pad-to-mask clearance to zero, leave up to fab. Set minimum mask web to 0.2mm for non-black options.
* PCB: Revise U1 pad shape, mask, paste, thermal drills.
Clearance is improved at corner pads.
* PCB: Tweak U3 for better thermal pad/drill/mask/paste design.
* PCB: Change solder mask color to blue.
* Schematic, PCB: Update revision to 20181029.
* PCB: Bump minimum mask web down a tiny bit because KiCad is having trouble with math.
* Update schematic
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Clock Manager: Actually store chosen clock reference
Similarly-named local was covering a member and discarding the value.
* Clock Manager: Reference type which contains source, frequency.
* Setup: Display reference source, frequency in frequency correction screen.
* LPC43xx API: Add extern "C" for use from C++.
* Use LPC43xx API for SGPIO, GPDMA, I2S initialization.
* I2S: Add BASE_AUDIO_CLK management.
* Add MOTOCON_PWM clock/reset structure.
* Serial: Fix dumb typos.
* Serial: Remove extra reference operator.
* Serial: Cut-and-paste error in structure type name.
* Move SCU structure from PAL to LPC43xx API.
It'd be nice if I gave some thought to where code should live before I commit it.
* VAA power: Move code to HackRF board file
It doesn't belong in PAL.
* MAX5 CPLD: Add SAMPLE and EXTEST methods.
* Flash image: Change packing scheme to use flash more efficiently.
Application is now a single image for both M4 bootstrap and M0.
Baseband images come immediately after application binary. No need to align to large blocks (and waste lots of flash).
* Clock Manager: Remove PLL1 power down function.
* Move and rename peripherals reset function to board module.
* Remove unused peripheral/clock management.
* Clock Manager: Extract switch to IRC into separate function.
* Clock Manager: More explicit shutdown of clocks, clock generator.
* Move initialization to board module.
* ChibiOS: Rename "application" board, add "baseband" board.
There are now two ChibiOS "boards", one which runs the application and does the hardware setup. The other board, "baseband", does very little setup.
* Clock Manager: Remove unused crystal enable/disable code.
* Clock Manager: Restore clock configuration to SPIFI bootloader state before app shutdown.
* Reset peripherals on app shutdown.
Be careful not to reset M0APP (the core we're running on) or GPIO (which is holding the hardware in a stable state).
* M4/baseband hal_lld_init: use IDIVA, which is configured earlier by M0.
This was causing problems during restart into HackRF mode. Baseband hal_lld_init changed M4 clock from IDIVA (set by M0) to PLL1, which was unceremoniously turned off during shutdown.
* Audio app: Stop audio PLL on shutdown.
* M4 HAL: Make LPC43XX_M4_CLK_SRC optional.
This was changing the BASE_M4_CLK when a baseband was run.
* LPC43xx C++ layer: Fix IDIVx constructor IDIV narrow field width.
* Application board: hide the peripherals_reset function, as it isn't useful except during hardware init.
* Consolidate hardware init code to some degree.
ClockManager is super-overloaded and murky in its purpose.
Migrate audio from IDIVC to IDIVD, to more closely resemble initial clock scheme, so it's simpler to get back to it during shutdown.
* Migrate some startup code to application board.
* Si5351: Use correct methods for reset().
update_output_enable_control() doesn't reset the enabled outputs to the reset state, unless the object is freshly initialized, which it isn't when performing firmware shutdown.
For similar reasons, use set_clock_control() instead of setting internal state and then using the update function.
* GPIO: Set SPIFI CS pin to match input buffer state coming out of bootloader.
* Change application board.c to .cpp, with required dependent changes
* Board: Clean up SCU configuration code/data.
* I2S: Add shutdown code and use it.
* LPC43xx: Consolidate a bunch of structures that had been scattered all over.
...because I'm an undisciplined coder.
* I2S: Fix ordering of branch and base clock disable.
Core was hanging, presumably because the register interface on the branch/peripheral was unresponsive after the base clock was disabled.
* Controls: Save and expose raw navigation wheel switch state
I need to do some work on debouncing and ignoring simultaneous key presses.
* Controls: Add debug view for switches state.
* Controls: Ignore all key presses until all keys are released.
This should address some mechanical quirks of the navigation wheel used on the PortaPack.
* Clock Manager: Wait for only the necessary PLL to lock.
Wasn't working on PortaPacks without a built-in clock reference, as that uses the other PLL.
TODO: Switching PLLs may be kind of pointless now...
* CMake: Pull HackRF project from GitHub and build.
* CMake: Remove commented code.
* CMake: Clone HackRF via HTTPS, not SSH.
* CMake: Extra pause for slow post-DFU firmware boot-up.
* CMake: TODO to fix SVF/XSVF file source.
* CMake: Ask HackRF hackrf_usb to make DFU binary.
* Travis-CI: Add dfu-util, now that HackRF firmware is being built for inclusion.
* Travis-CI: Update build environment to Ubuntu xenial
Previously Trusty.
* Travis-CI: Incorrectly structured my request for dfu-util package.
I'm soooo talented.
* ldscript: Mark flash, ram with correct R/W/X flags.
* ldscript: Enlarge M0 flash region to 1Mbyte, the size of the HackRF SPI flash.
* Receiver: Hide PPM adjustment if clock source is not HackRF crystal.
* Documentation: Update product photos and README.
* Documentation: Add TCXO feature to README description.
* Application: Rearrange files to match HAVOC directory structure.
* Map view in AIS (#213)
* Added GeoMapView to AISRecentEntryDetailView
* Added autoupdate in AIS map
* Revert "Map view in AIS (#213)"
This reverts commit 262c030224b9ea3e56ff1c8a66246e7ecf30e41f.
This commit will be cherry-picked onto a clean branch, then re-committed after a troublesome pull request is reverted.
* Revert "Upstream merge to make new revision of PortaPack work (#206)"
This reverts commit 920b98f7c9a30371b643c42949066fb7d2441daf.
This pull request was missing some changes and was preventing firmware from functioning on older PortaPacks.
* CPLD: Pull bitstream from HackRF project.
* SGPIO: Identify pins on CPLD by their new functions. Pull down HOST_SYNC_EN.
* CPLD: Don't load HackRF CPLD bitstream into RAM.
Trying to converge CPLD implementations, so this shouldn't be necesssary. HOWEVER, it would be good to *check* the CPLD contents and provide a way to update, if necessary.
* CPLD: Tweak clock generator config to match CPLD timing changes in HackRF.
* PinConfig: Drive CPLD pins correctly.
* CMake: Use jboone/hackrf master branch, now that CPLD fixes are there.
* CMake: Fix HackRF CPLD SVF dependency.
Build would break on the first pass, but work if you restarted make.
* CMake: Fix my misuse of the HackRF CMake configuration -- was building from too deep in the directory tree
* CMake: Work-around for CMake 3.5 not supporting ExternalProject_Add SOURCE_SUBDIR.
* CMake: Choose a CMP0005 policy to quiet CMake warnings.
* Settings: Show active clock reference. Only show PPM adjustment for HackRF source.
* Radio Settings: Change reference clock text color.
Make consistent color with other un-editable text.
TODO: This is a bit of a hack to get ui::Text objects to support custom colors, like the Label structures used elsewhere.
2019-02-03 19:25:11 +01:00
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ClockManager::Reference ClockManager::get_reference() const {
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return reference;
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Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 07:56:21 +01:00
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}
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static void portapack_tcxo_enable() {
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portapack::io.reference_oscillator(true);
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2015-07-08 08:39:24 -07:00
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Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 07:56:21 +01:00
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/* Delay >10ms at 96MHz clock speed for reference oscillator to start. */
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/* Delay an additional 1ms (arbitrary) for the clock generator to detect a signal. */
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volatile uint32_t delay = 240000 + 24000;
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while(delay--);
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}
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static void portapack_tcxo_disable() {
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portapack::io.reference_oscillator(false);
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}
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#include "hackrf_gpio.hpp"
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using namespace hackrf::one;
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void ClockManager::init_clock_generator() {
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2015-07-08 08:39:24 -07:00
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clock_generator.reset();
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clock_generator.set_crystal_internal_load_capacitance(CrystalInternalLoadCapacitance::XTAL_CL_8pF);
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clock_generator.enable_fanout();
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2023-02-16 12:09:23 +00:00
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clock_generator.set_pll_input_sources(hackrf_r9
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? si5351a_pll_input_sources
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: si5351c_pll_input_sources);
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auto si5351_clock_control_common = hackrf_r9
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? si5351a_clock_control_common
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: si5351c_clock_control_common;
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auto clock_generator_output_mcu_clkin = hackrf_r9
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? clock_generator_output_r9_mcu_clkin
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: clock_generator_output_og_mcu_clkin;
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2015-07-08 08:39:24 -07:00
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Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 07:56:21 +01:00
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clock_generator.set_clock_control(
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clock_generator_output_mcu_clkin,
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2023-02-16 12:09:23 +00:00
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si5351_clock_control_common[clock_generator_output_mcu_clkin]
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.clk_src(hackrf_r9
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? ClockControl::ClockSource::Xtal
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: ClockControl::ClockSource::CLKIN)
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.clk_pdn(ClockControl::ClockPowerDown::Power_On)
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Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 07:56:21 +01:00
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);
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clock_generator.enable_output(clock_generator_output_mcu_clkin);
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2018-08-05 12:21:25 -07:00
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PortaPack Sync, take 2 (#215)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* PCB: Change PCB stackup, Tg, clarify solder mask color, use more metric.
* PCB: Move HackRF header P9 to B.CrtYd layer.
* PCB: Change a Tg reference I missed.
* PCB: Update footprints for parts with mismatched CAD->tape rotation.
Adjust a few layer choice and line thickness bits.
* PCB: Got cold feet, switched back to rectangular pads.
* PCB: Add Eco layers to be visible and Gerber output.
* PCB: Use aux origin for plotting, for tidier coordinates.
* PCB: Output Gerber job file, because why not?
* Schematic: Correct footprints for two reference-related components.
* Schematic: Remove manfuacturer and part number for DNP component.
* Schematic: Specify resistor value, manufacturer, part number for reference oscillator series termination.
* PCB: Update netlist and footprints from schematic.
* Netlist: Updated component values, footprints.
* PCB: Nudge some components and traces to address DRC clearance violations.
* PCB: Allow KiCad to update zone timestamps (again?!).
* PCB: Generate *all* Gerber layers.
* Schematic, PCB: Update revision to 20181025.
* PCB: Adjust fab layer annotations orientation and font size.
* PCB: Hide mounting hole reference designators on silk layer.
* PCB: Shrink U1, U3 pads to get 0.2mm space between pads.
* PCB: Set pad-to-mask clearance to zero, leave up to fab. Set minimum mask web to 0.2mm for non-black options.
* PCB: Revise U1 pad shape, mask, paste, thermal drills.
Clearance is improved at corner pads.
* PCB: Tweak U3 for better thermal pad/drill/mask/paste design.
* PCB: Change solder mask color to blue.
* Schematic, PCB: Update revision to 20181029.
* PCB: Bump minimum mask web down a tiny bit because KiCad is having trouble with math.
* Update schematic
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Clock Manager: Actually store chosen clock reference
Similarly-named local was covering a member and discarding the value.
* Clock Manager: Reference type which contains source, frequency.
* Setup: Display reference source, frequency in frequency correction screen.
* LPC43xx API: Add extern "C" for use from C++.
* Use LPC43xx API for SGPIO, GPDMA, I2S initialization.
* I2S: Add BASE_AUDIO_CLK management.
* Add MOTOCON_PWM clock/reset structure.
* Serial: Fix dumb typos.
* Serial: Remove extra reference operator.
* Serial: Cut-and-paste error in structure type name.
* Move SCU structure from PAL to LPC43xx API.
It'd be nice if I gave some thought to where code should live before I commit it.
* VAA power: Move code to HackRF board file
It doesn't belong in PAL.
* MAX5 CPLD: Add SAMPLE and EXTEST methods.
* Flash image: Change packing scheme to use flash more efficiently.
Application is now a single image for both M4 bootstrap and M0.
Baseband images come immediately after application binary. No need to align to large blocks (and waste lots of flash).
* Clock Manager: Remove PLL1 power down function.
* Move and rename peripherals reset function to board module.
* Remove unused peripheral/clock management.
* Clock Manager: Extract switch to IRC into separate function.
* Clock Manager: More explicit shutdown of clocks, clock generator.
* Move initialization to board module.
* ChibiOS: Rename "application" board, add "baseband" board.
There are now two ChibiOS "boards", one which runs the application and does the hardware setup. The other board, "baseband", does very little setup.
* Clock Manager: Remove unused crystal enable/disable code.
* Clock Manager: Restore clock configuration to SPIFI bootloader state before app shutdown.
* Reset peripherals on app shutdown.
Be careful not to reset M0APP (the core we're running on) or GPIO (which is holding the hardware in a stable state).
* M4/baseband hal_lld_init: use IDIVA, which is configured earlier by M0.
This was causing problems during restart into HackRF mode. Baseband hal_lld_init changed M4 clock from IDIVA (set by M0) to PLL1, which was unceremoniously turned off during shutdown.
* Audio app: Stop audio PLL on shutdown.
* M4 HAL: Make LPC43XX_M4_CLK_SRC optional.
This was changing the BASE_M4_CLK when a baseband was run.
* LPC43xx C++ layer: Fix IDIVx constructor IDIV narrow field width.
* Application board: hide the peripherals_reset function, as it isn't useful except during hardware init.
* Consolidate hardware init code to some degree.
ClockManager is super-overloaded and murky in its purpose.
Migrate audio from IDIVC to IDIVD, to more closely resemble initial clock scheme, so it's simpler to get back to it during shutdown.
* Migrate some startup code to application board.
* Si5351: Use correct methods for reset().
update_output_enable_control() doesn't reset the enabled outputs to the reset state, unless the object is freshly initialized, which it isn't when performing firmware shutdown.
For similar reasons, use set_clock_control() instead of setting internal state and then using the update function.
* GPIO: Set SPIFI CS pin to match input buffer state coming out of bootloader.
* Change application board.c to .cpp, with required dependent changes
* Board: Clean up SCU configuration code/data.
* I2S: Add shutdown code and use it.
* LPC43xx: Consolidate a bunch of structures that had been scattered all over.
...because I'm an undisciplined coder.
* I2S: Fix ordering of branch and base clock disable.
Core was hanging, presumably because the register interface on the branch/peripheral was unresponsive after the base clock was disabled.
* Controls: Save and expose raw navigation wheel switch state
I need to do some work on debouncing and ignoring simultaneous key presses.
* Controls: Add debug view for switches state.
* Controls: Ignore all key presses until all keys are released.
This should address some mechanical quirks of the navigation wheel used on the PortaPack.
* Clock Manager: Wait for only the necessary PLL to lock.
Wasn't working on PortaPacks without a built-in clock reference, as that uses the other PLL.
TODO: Switching PLLs may be kind of pointless now...
* CMake: Pull HackRF project from GitHub and build.
* CMake: Remove commented code.
* CMake: Clone HackRF via HTTPS, not SSH.
* CMake: Extra pause for slow post-DFU firmware boot-up.
* CMake: TODO to fix SVF/XSVF file source.
* CMake: Ask HackRF hackrf_usb to make DFU binary.
* Travis-CI: Add dfu-util, now that HackRF firmware is being built for inclusion.
* Travis-CI: Update build environment to Ubuntu xenial
Previously Trusty.
* Travis-CI: Incorrectly structured my request for dfu-util package.
I'm soooo talented.
* ldscript: Mark flash, ram with correct R/W/X flags.
* ldscript: Enlarge M0 flash region to 1Mbyte, the size of the HackRF SPI flash.
* Receiver: Hide PPM adjustment if clock source is not HackRF crystal.
* Documentation: Update product photos and README.
* Documentation: Add TCXO feature to README description.
* Application: Rearrange files to match HAVOC directory structure.
* Map view in AIS (#213)
* Added GeoMapView to AISRecentEntryDetailView
* Added autoupdate in AIS map
* Revert "Map view in AIS (#213)"
This reverts commit 262c030224b9ea3e56ff1c8a66246e7ecf30e41f.
This commit will be cherry-picked onto a clean branch, then re-committed after a troublesome pull request is reverted.
* Revert "Upstream merge to make new revision of PortaPack work (#206)"
This reverts commit 920b98f7c9a30371b643c42949066fb7d2441daf.
This pull request was missing some changes and was preventing firmware from functioning on older PortaPacks.
* CPLD: Pull bitstream from HackRF project.
* SGPIO: Identify pins on CPLD by their new functions. Pull down HOST_SYNC_EN.
* CPLD: Don't load HackRF CPLD bitstream into RAM.
Trying to converge CPLD implementations, so this shouldn't be necesssary. HOWEVER, it would be good to *check* the CPLD contents and provide a way to update, if necessary.
* CPLD: Tweak clock generator config to match CPLD timing changes in HackRF.
* PinConfig: Drive CPLD pins correctly.
* CMake: Use jboone/hackrf master branch, now that CPLD fixes are there.
* CMake: Fix HackRF CPLD SVF dependency.
Build would break on the first pass, but work if you restarted make.
* CMake: Fix my misuse of the HackRF CMake configuration -- was building from too deep in the directory tree
* CMake: Work-around for CMake 3.5 not supporting ExternalProject_Add SOURCE_SUBDIR.
* CMake: Choose a CMP0005 policy to quiet CMake warnings.
* Settings: Show active clock reference. Only show PPM adjustment for HackRF source.
* Radio Settings: Change reference clock text color.
Make consistent color with other un-editable text.
TODO: This is a bit of a hack to get ui::Text objects to support custom colors, like the Label structures used elsewhere.
2019-02-03 19:25:11 +01:00
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reference = choose_reference();
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2018-08-05 12:21:25 -07:00
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Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 07:56:21 +01:00
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clock_generator.disable_output(clock_generator_output_mcu_clkin);
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2018-08-05 12:21:25 -07:00
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2023-02-16 12:09:23 +00:00
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const auto ref_pll = hackrf_r9
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? ClockControl::MultiSynthSource::PLLA
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: get_si5351c_reference_clock_generator_pll(reference.source);
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Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 07:56:21 +01:00
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const ClockControls si5351_clock_control = ClockControls { {
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si5351_clock_control_common[0].ms_src(ref_pll),
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si5351_clock_control_common[1].ms_src(ref_pll),
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si5351_clock_control_common[2].ms_src(ref_pll),
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si5351_clock_control_common[3].ms_src(ref_pll),
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si5351_clock_control_common[4].ms_src(ref_pll),
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si5351_clock_control_common[5].ms_src(ref_pll),
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si5351_clock_control_common[6].ms_src(ref_pll),
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si5351_clock_control_common[7].ms_src(ref_pll),
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} };
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clock_generator.set_clock_control(si5351_clock_control);
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2015-07-08 08:39:24 -07:00
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2023-02-16 12:09:23 +00:00
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if (hackrf_r9) {
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const PLLReg pll_reg = (reference.source == ReferenceSource::Xtal)
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? si5351_pll_a_xtal_reg
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: si5351a_pll_a_clkin_reg;
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clock_generator.write(pll_reg);
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clock_generator.write(si5351a_ms_0_if_40m_reg);
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clock_generator.write(si5351a_ms_1_sgpio_16m_reg);
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clock_generator.write(si5351a_ms_2_mcu_10m_reg);
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clock_generator.write(si5351a_ms6_7_off_reg);
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} else {
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clock_generator.write(si5351_pll_a_xtal_reg);
|
|
|
|
|
clock_generator.write(si5351c_pll_b_clkin_reg);
|
|
|
|
|
clock_generator.write(si5351c_ms_0_8m_reg);
|
|
|
|
|
clock_generator.write(si5351c_ms_1_group_reg);
|
|
|
|
|
clock_generator.write(si5351c_ms_2_group_reg);
|
|
|
|
|
clock_generator.write(si5351c_ms_3_10m_reg);
|
|
|
|
|
clock_generator.write(si5351c_ms_4_reg);
|
|
|
|
|
clock_generator.write(si5351c_ms_5_reg);
|
|
|
|
|
clock_generator.write(si5351c_ms6_7_off_mcu_clkin_reg);
|
|
|
|
|
}
|
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 07:56:21 +01:00
|
|
|
|
2015-07-08 08:39:24 -07:00
|
|
|
clock_generator.reset_plls();
|
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 07:56:21 +01:00
|
|
|
|
2023-02-16 12:09:23 +00:00
|
|
|
// Wait for PLL(s) to lock.
|
|
|
|
|
uint8_t device_status_mask = hackrf_r9
|
|
|
|
|
? 0x20
|
|
|
|
|
: (ref_pll == ClockControl::MultiSynthSource::PLLB)
|
|
|
|
|
? 0x40
|
|
|
|
|
: 0x20;
|
PortaPack Sync, take 2 (#215)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* PCB: Change PCB stackup, Tg, clarify solder mask color, use more metric.
* PCB: Move HackRF header P9 to B.CrtYd layer.
* PCB: Change a Tg reference I missed.
* PCB: Update footprints for parts with mismatched CAD->tape rotation.
Adjust a few layer choice and line thickness bits.
* PCB: Got cold feet, switched back to rectangular pads.
* PCB: Add Eco layers to be visible and Gerber output.
* PCB: Use aux origin for plotting, for tidier coordinates.
* PCB: Output Gerber job file, because why not?
* Schematic: Correct footprints for two reference-related components.
* Schematic: Remove manfuacturer and part number for DNP component.
* Schematic: Specify resistor value, manufacturer, part number for reference oscillator series termination.
* PCB: Update netlist and footprints from schematic.
* Netlist: Updated component values, footprints.
* PCB: Nudge some components and traces to address DRC clearance violations.
* PCB: Allow KiCad to update zone timestamps (again?!).
* PCB: Generate *all* Gerber layers.
* Schematic, PCB: Update revision to 20181025.
* PCB: Adjust fab layer annotations orientation and font size.
* PCB: Hide mounting hole reference designators on silk layer.
* PCB: Shrink U1, U3 pads to get 0.2mm space between pads.
* PCB: Set pad-to-mask clearance to zero, leave up to fab. Set minimum mask web to 0.2mm for non-black options.
* PCB: Revise U1 pad shape, mask, paste, thermal drills.
Clearance is improved at corner pads.
* PCB: Tweak U3 for better thermal pad/drill/mask/paste design.
* PCB: Change solder mask color to blue.
* Schematic, PCB: Update revision to 20181029.
* PCB: Bump minimum mask web down a tiny bit because KiCad is having trouble with math.
* Update schematic
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Clock Manager: Actually store chosen clock reference
Similarly-named local was covering a member and discarding the value.
* Clock Manager: Reference type which contains source, frequency.
* Setup: Display reference source, frequency in frequency correction screen.
* LPC43xx API: Add extern "C" for use from C++.
* Use LPC43xx API for SGPIO, GPDMA, I2S initialization.
* I2S: Add BASE_AUDIO_CLK management.
* Add MOTOCON_PWM clock/reset structure.
* Serial: Fix dumb typos.
* Serial: Remove extra reference operator.
* Serial: Cut-and-paste error in structure type name.
* Move SCU structure from PAL to LPC43xx API.
It'd be nice if I gave some thought to where code should live before I commit it.
* VAA power: Move code to HackRF board file
It doesn't belong in PAL.
* MAX5 CPLD: Add SAMPLE and EXTEST methods.
* Flash image: Change packing scheme to use flash more efficiently.
Application is now a single image for both M4 bootstrap and M0.
Baseband images come immediately after application binary. No need to align to large blocks (and waste lots of flash).
* Clock Manager: Remove PLL1 power down function.
* Move and rename peripherals reset function to board module.
* Remove unused peripheral/clock management.
* Clock Manager: Extract switch to IRC into separate function.
* Clock Manager: More explicit shutdown of clocks, clock generator.
* Move initialization to board module.
* ChibiOS: Rename "application" board, add "baseband" board.
There are now two ChibiOS "boards", one which runs the application and does the hardware setup. The other board, "baseband", does very little setup.
* Clock Manager: Remove unused crystal enable/disable code.
* Clock Manager: Restore clock configuration to SPIFI bootloader state before app shutdown.
* Reset peripherals on app shutdown.
Be careful not to reset M0APP (the core we're running on) or GPIO (which is holding the hardware in a stable state).
* M4/baseband hal_lld_init: use IDIVA, which is configured earlier by M0.
This was causing problems during restart into HackRF mode. Baseband hal_lld_init changed M4 clock from IDIVA (set by M0) to PLL1, which was unceremoniously turned off during shutdown.
* Audio app: Stop audio PLL on shutdown.
* M4 HAL: Make LPC43XX_M4_CLK_SRC optional.
This was changing the BASE_M4_CLK when a baseband was run.
* LPC43xx C++ layer: Fix IDIVx constructor IDIV narrow field width.
* Application board: hide the peripherals_reset function, as it isn't useful except during hardware init.
* Consolidate hardware init code to some degree.
ClockManager is super-overloaded and murky in its purpose.
Migrate audio from IDIVC to IDIVD, to more closely resemble initial clock scheme, so it's simpler to get back to it during shutdown.
* Migrate some startup code to application board.
* Si5351: Use correct methods for reset().
update_output_enable_control() doesn't reset the enabled outputs to the reset state, unless the object is freshly initialized, which it isn't when performing firmware shutdown.
For similar reasons, use set_clock_control() instead of setting internal state and then using the update function.
* GPIO: Set SPIFI CS pin to match input buffer state coming out of bootloader.
* Change application board.c to .cpp, with required dependent changes
* Board: Clean up SCU configuration code/data.
* I2S: Add shutdown code and use it.
* LPC43xx: Consolidate a bunch of structures that had been scattered all over.
...because I'm an undisciplined coder.
* I2S: Fix ordering of branch and base clock disable.
Core was hanging, presumably because the register interface on the branch/peripheral was unresponsive after the base clock was disabled.
* Controls: Save and expose raw navigation wheel switch state
I need to do some work on debouncing and ignoring simultaneous key presses.
* Controls: Add debug view for switches state.
* Controls: Ignore all key presses until all keys are released.
This should address some mechanical quirks of the navigation wheel used on the PortaPack.
* Clock Manager: Wait for only the necessary PLL to lock.
Wasn't working on PortaPacks without a built-in clock reference, as that uses the other PLL.
TODO: Switching PLLs may be kind of pointless now...
* CMake: Pull HackRF project from GitHub and build.
* CMake: Remove commented code.
* CMake: Clone HackRF via HTTPS, not SSH.
* CMake: Extra pause for slow post-DFU firmware boot-up.
* CMake: TODO to fix SVF/XSVF file source.
* CMake: Ask HackRF hackrf_usb to make DFU binary.
* Travis-CI: Add dfu-util, now that HackRF firmware is being built for inclusion.
* Travis-CI: Update build environment to Ubuntu xenial
Previously Trusty.
* Travis-CI: Incorrectly structured my request for dfu-util package.
I'm soooo talented.
* ldscript: Mark flash, ram with correct R/W/X flags.
* ldscript: Enlarge M0 flash region to 1Mbyte, the size of the HackRF SPI flash.
* Receiver: Hide PPM adjustment if clock source is not HackRF crystal.
* Documentation: Update product photos and README.
* Documentation: Add TCXO feature to README description.
* Application: Rearrange files to match HAVOC directory structure.
* Map view in AIS (#213)
* Added GeoMapView to AISRecentEntryDetailView
* Added autoupdate in AIS map
* Revert "Map view in AIS (#213)"
This reverts commit 262c030224b9ea3e56ff1c8a66246e7ecf30e41f.
This commit will be cherry-picked onto a clean branch, then re-committed after a troublesome pull request is reverted.
* Revert "Upstream merge to make new revision of PortaPack work (#206)"
This reverts commit 920b98f7c9a30371b643c42949066fb7d2441daf.
This pull request was missing some changes and was preventing firmware from functioning on older PortaPacks.
* CPLD: Pull bitstream from HackRF project.
* SGPIO: Identify pins on CPLD by their new functions. Pull down HOST_SYNC_EN.
* CPLD: Don't load HackRF CPLD bitstream into RAM.
Trying to converge CPLD implementations, so this shouldn't be necesssary. HOWEVER, it would be good to *check* the CPLD contents and provide a way to update, if necessary.
* CPLD: Tweak clock generator config to match CPLD timing changes in HackRF.
* PinConfig: Drive CPLD pins correctly.
* CMake: Use jboone/hackrf master branch, now that CPLD fixes are there.
* CMake: Fix HackRF CPLD SVF dependency.
Build would break on the first pass, but work if you restarted make.
* CMake: Fix my misuse of the HackRF CMake configuration -- was building from too deep in the directory tree
* CMake: Work-around for CMake 3.5 not supporting ExternalProject_Add SOURCE_SUBDIR.
* CMake: Choose a CMP0005 policy to quiet CMake warnings.
* Settings: Show active clock reference. Only show PPM adjustment for HackRF source.
* Radio Settings: Change reference clock text color.
Make consistent color with other un-editable text.
TODO: This is a bit of a hack to get ui::Text objects to support custom colors, like the Label structures used elsewhere.
2019-02-03 19:25:11 +01:00
|
|
|
while((clock_generator.device_status() & device_status_mask) != 0);
|
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 07:56:21 +01:00
|
|
|
|
|
|
|
|
clock_generator.set_clock_control(
|
|
|
|
|
clock_generator_output_mcu_clkin,
|
|
|
|
|
si5351_clock_control_common[clock_generator_output_mcu_clkin].ms_src(ref_pll).clk_pdn(ClockControl::ClockPowerDown::Power_On)
|
|
|
|
|
);
|
|
|
|
|
clock_generator.enable_output(clock_generator_output_mcu_clkin);
|
2015-07-08 08:39:24 -07:00
|
|
|
}
|
|
|
|
|
|
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 07:56:21 +01:00
|
|
|
uint32_t ClockManager::measure_gp_clkin_frequency() {
|
|
|
|
|
// Measure Si5351B CLKIN frequency against LPC43xx IRC oscillator
|
|
|
|
|
start_frequency_monitor_measurement(cgu::CLK_SEL::GP_CLKIN);
|
|
|
|
|
wait_For_frequency_monitor_measurement_done();
|
|
|
|
|
return get_frequency_monitor_measurement_in_hertz();
|
|
|
|
|
}
|
|
|
|
|
|
2023-02-16 12:09:23 +00:00
|
|
|
bool ClockManager::loss_of_signal() {
|
|
|
|
|
return hackrf_r9
|
|
|
|
|
? clock_generator.plla_loss_of_signal()
|
|
|
|
|
: clock_generator.clkin_loss_of_signal();
|
|
|
|
|
}
|
|
|
|
|
|
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 07:56:21 +01:00
|
|
|
ClockManager::ReferenceSource ClockManager::detect_reference_source() {
|
2023-02-16 12:09:23 +00:00
|
|
|
if(loss_of_signal()) {
|
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 07:56:21 +01:00
|
|
|
// No external reference. Turn on PortaPack reference (if present).
|
|
|
|
|
portapack_tcxo_enable();
|
|
|
|
|
|
2023-02-16 12:09:23 +00:00
|
|
|
if(loss_of_signal()) {
|
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 07:56:21 +01:00
|
|
|
// No PortaPack reference was detected. Choose the HackRF crystal as the reference.
|
|
|
|
|
return ReferenceSource::Xtal;
|
|
|
|
|
} else {
|
|
|
|
|
return ReferenceSource::PortaPack;
|
|
|
|
|
}
|
|
|
|
|
} else {
|
|
|
|
|
return ReferenceSource::External;
|
|
|
|
|
}
|
2015-08-01 13:43:58 -07:00
|
|
|
}
|
|
|
|
|
|
PortaPack Sync, take 2 (#215)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* PCB: Change PCB stackup, Tg, clarify solder mask color, use more metric.
* PCB: Move HackRF header P9 to B.CrtYd layer.
* PCB: Change a Tg reference I missed.
* PCB: Update footprints for parts with mismatched CAD->tape rotation.
Adjust a few layer choice and line thickness bits.
* PCB: Got cold feet, switched back to rectangular pads.
* PCB: Add Eco layers to be visible and Gerber output.
* PCB: Use aux origin for plotting, for tidier coordinates.
* PCB: Output Gerber job file, because why not?
* Schematic: Correct footprints for two reference-related components.
* Schematic: Remove manfuacturer and part number for DNP component.
* Schematic: Specify resistor value, manufacturer, part number for reference oscillator series termination.
* PCB: Update netlist and footprints from schematic.
* Netlist: Updated component values, footprints.
* PCB: Nudge some components and traces to address DRC clearance violations.
* PCB: Allow KiCad to update zone timestamps (again?!).
* PCB: Generate *all* Gerber layers.
* Schematic, PCB: Update revision to 20181025.
* PCB: Adjust fab layer annotations orientation and font size.
* PCB: Hide mounting hole reference designators on silk layer.
* PCB: Shrink U1, U3 pads to get 0.2mm space between pads.
* PCB: Set pad-to-mask clearance to zero, leave up to fab. Set minimum mask web to 0.2mm for non-black options.
* PCB: Revise U1 pad shape, mask, paste, thermal drills.
Clearance is improved at corner pads.
* PCB: Tweak U3 for better thermal pad/drill/mask/paste design.
* PCB: Change solder mask color to blue.
* Schematic, PCB: Update revision to 20181029.
* PCB: Bump minimum mask web down a tiny bit because KiCad is having trouble with math.
* Update schematic
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Clock Manager: Actually store chosen clock reference
Similarly-named local was covering a member and discarding the value.
* Clock Manager: Reference type which contains source, frequency.
* Setup: Display reference source, frequency in frequency correction screen.
* LPC43xx API: Add extern "C" for use from C++.
* Use LPC43xx API for SGPIO, GPDMA, I2S initialization.
* I2S: Add BASE_AUDIO_CLK management.
* Add MOTOCON_PWM clock/reset structure.
* Serial: Fix dumb typos.
* Serial: Remove extra reference operator.
* Serial: Cut-and-paste error in structure type name.
* Move SCU structure from PAL to LPC43xx API.
It'd be nice if I gave some thought to where code should live before I commit it.
* VAA power: Move code to HackRF board file
It doesn't belong in PAL.
* MAX5 CPLD: Add SAMPLE and EXTEST methods.
* Flash image: Change packing scheme to use flash more efficiently.
Application is now a single image for both M4 bootstrap and M0.
Baseband images come immediately after application binary. No need to align to large blocks (and waste lots of flash).
* Clock Manager: Remove PLL1 power down function.
* Move and rename peripherals reset function to board module.
* Remove unused peripheral/clock management.
* Clock Manager: Extract switch to IRC into separate function.
* Clock Manager: More explicit shutdown of clocks, clock generator.
* Move initialization to board module.
* ChibiOS: Rename "application" board, add "baseband" board.
There are now two ChibiOS "boards", one which runs the application and does the hardware setup. The other board, "baseband", does very little setup.
* Clock Manager: Remove unused crystal enable/disable code.
* Clock Manager: Restore clock configuration to SPIFI bootloader state before app shutdown.
* Reset peripherals on app shutdown.
Be careful not to reset M0APP (the core we're running on) or GPIO (which is holding the hardware in a stable state).
* M4/baseband hal_lld_init: use IDIVA, which is configured earlier by M0.
This was causing problems during restart into HackRF mode. Baseband hal_lld_init changed M4 clock from IDIVA (set by M0) to PLL1, which was unceremoniously turned off during shutdown.
* Audio app: Stop audio PLL on shutdown.
* M4 HAL: Make LPC43XX_M4_CLK_SRC optional.
This was changing the BASE_M4_CLK when a baseband was run.
* LPC43xx C++ layer: Fix IDIVx constructor IDIV narrow field width.
* Application board: hide the peripherals_reset function, as it isn't useful except during hardware init.
* Consolidate hardware init code to some degree.
ClockManager is super-overloaded and murky in its purpose.
Migrate audio from IDIVC to IDIVD, to more closely resemble initial clock scheme, so it's simpler to get back to it during shutdown.
* Migrate some startup code to application board.
* Si5351: Use correct methods for reset().
update_output_enable_control() doesn't reset the enabled outputs to the reset state, unless the object is freshly initialized, which it isn't when performing firmware shutdown.
For similar reasons, use set_clock_control() instead of setting internal state and then using the update function.
* GPIO: Set SPIFI CS pin to match input buffer state coming out of bootloader.
* Change application board.c to .cpp, with required dependent changes
* Board: Clean up SCU configuration code/data.
* I2S: Add shutdown code and use it.
* LPC43xx: Consolidate a bunch of structures that had been scattered all over.
...because I'm an undisciplined coder.
* I2S: Fix ordering of branch and base clock disable.
Core was hanging, presumably because the register interface on the branch/peripheral was unresponsive after the base clock was disabled.
* Controls: Save and expose raw navigation wheel switch state
I need to do some work on debouncing and ignoring simultaneous key presses.
* Controls: Add debug view for switches state.
* Controls: Ignore all key presses until all keys are released.
This should address some mechanical quirks of the navigation wheel used on the PortaPack.
* Clock Manager: Wait for only the necessary PLL to lock.
Wasn't working on PortaPacks without a built-in clock reference, as that uses the other PLL.
TODO: Switching PLLs may be kind of pointless now...
* CMake: Pull HackRF project from GitHub and build.
* CMake: Remove commented code.
* CMake: Clone HackRF via HTTPS, not SSH.
* CMake: Extra pause for slow post-DFU firmware boot-up.
* CMake: TODO to fix SVF/XSVF file source.
* CMake: Ask HackRF hackrf_usb to make DFU binary.
* Travis-CI: Add dfu-util, now that HackRF firmware is being built for inclusion.
* Travis-CI: Update build environment to Ubuntu xenial
Previously Trusty.
* Travis-CI: Incorrectly structured my request for dfu-util package.
I'm soooo talented.
* ldscript: Mark flash, ram with correct R/W/X flags.
* ldscript: Enlarge M0 flash region to 1Mbyte, the size of the HackRF SPI flash.
* Receiver: Hide PPM adjustment if clock source is not HackRF crystal.
* Documentation: Update product photos and README.
* Documentation: Add TCXO feature to README description.
* Application: Rearrange files to match HAVOC directory structure.
* Map view in AIS (#213)
* Added GeoMapView to AISRecentEntryDetailView
* Added autoupdate in AIS map
* Revert "Map view in AIS (#213)"
This reverts commit 262c030224b9ea3e56ff1c8a66246e7ecf30e41f.
This commit will be cherry-picked onto a clean branch, then re-committed after a troublesome pull request is reverted.
* Revert "Upstream merge to make new revision of PortaPack work (#206)"
This reverts commit 920b98f7c9a30371b643c42949066fb7d2441daf.
This pull request was missing some changes and was preventing firmware from functioning on older PortaPacks.
* CPLD: Pull bitstream from HackRF project.
* SGPIO: Identify pins on CPLD by their new functions. Pull down HOST_SYNC_EN.
* CPLD: Don't load HackRF CPLD bitstream into RAM.
Trying to converge CPLD implementations, so this shouldn't be necesssary. HOWEVER, it would be good to *check* the CPLD contents and provide a way to update, if necessary.
* CPLD: Tweak clock generator config to match CPLD timing changes in HackRF.
* PinConfig: Drive CPLD pins correctly.
* CMake: Use jboone/hackrf master branch, now that CPLD fixes are there.
* CMake: Fix HackRF CPLD SVF dependency.
Build would break on the first pass, but work if you restarted make.
* CMake: Fix my misuse of the HackRF CMake configuration -- was building from too deep in the directory tree
* CMake: Work-around for CMake 3.5 not supporting ExternalProject_Add SOURCE_SUBDIR.
* CMake: Choose a CMP0005 policy to quiet CMake warnings.
* Settings: Show active clock reference. Only show PPM adjustment for HackRF source.
* Radio Settings: Change reference clock text color.
Make consistent color with other un-editable text.
TODO: This is a bit of a hack to get ui::Text objects to support custom colors, like the Label structures used elsewhere.
2019-02-03 19:25:11 +01:00
|
|
|
ClockManager::Reference ClockManager::choose_reference() {
|
2023-02-16 12:09:23 +00:00
|
|
|
if (hackrf_r9) {
|
|
|
|
|
gpio_r9_clkin_en.write(1);
|
|
|
|
|
volatile uint32_t delay = 240000 + 24000;
|
|
|
|
|
while(delay--);
|
|
|
|
|
}
|
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 07:56:21 +01:00
|
|
|
const auto detected_reference = detect_reference_source();
|
|
|
|
|
|
|
|
|
|
if( (detected_reference == ReferenceSource::External) ||
|
|
|
|
|
(detected_reference == ReferenceSource::PortaPack) ) {
|
|
|
|
|
const auto frequency = measure_gp_clkin_frequency();
|
|
|
|
|
if( (frequency >= 9850000) && (frequency <= 10150000) ) {
|
PortaPack Sync, take 2 (#215)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* PCB: Change PCB stackup, Tg, clarify solder mask color, use more metric.
* PCB: Move HackRF header P9 to B.CrtYd layer.
* PCB: Change a Tg reference I missed.
* PCB: Update footprints for parts with mismatched CAD->tape rotation.
Adjust a few layer choice and line thickness bits.
* PCB: Got cold feet, switched back to rectangular pads.
* PCB: Add Eco layers to be visible and Gerber output.
* PCB: Use aux origin for plotting, for tidier coordinates.
* PCB: Output Gerber job file, because why not?
* Schematic: Correct footprints for two reference-related components.
* Schematic: Remove manfuacturer and part number for DNP component.
* Schematic: Specify resistor value, manufacturer, part number for reference oscillator series termination.
* PCB: Update netlist and footprints from schematic.
* Netlist: Updated component values, footprints.
* PCB: Nudge some components and traces to address DRC clearance violations.
* PCB: Allow KiCad to update zone timestamps (again?!).
* PCB: Generate *all* Gerber layers.
* Schematic, PCB: Update revision to 20181025.
* PCB: Adjust fab layer annotations orientation and font size.
* PCB: Hide mounting hole reference designators on silk layer.
* PCB: Shrink U1, U3 pads to get 0.2mm space between pads.
* PCB: Set pad-to-mask clearance to zero, leave up to fab. Set minimum mask web to 0.2mm for non-black options.
* PCB: Revise U1 pad shape, mask, paste, thermal drills.
Clearance is improved at corner pads.
* PCB: Tweak U3 for better thermal pad/drill/mask/paste design.
* PCB: Change solder mask color to blue.
* Schematic, PCB: Update revision to 20181029.
* PCB: Bump minimum mask web down a tiny bit because KiCad is having trouble with math.
* Update schematic
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Clock Manager: Actually store chosen clock reference
Similarly-named local was covering a member and discarding the value.
* Clock Manager: Reference type which contains source, frequency.
* Setup: Display reference source, frequency in frequency correction screen.
* LPC43xx API: Add extern "C" for use from C++.
* Use LPC43xx API for SGPIO, GPDMA, I2S initialization.
* I2S: Add BASE_AUDIO_CLK management.
* Add MOTOCON_PWM clock/reset structure.
* Serial: Fix dumb typos.
* Serial: Remove extra reference operator.
* Serial: Cut-and-paste error in structure type name.
* Move SCU structure from PAL to LPC43xx API.
It'd be nice if I gave some thought to where code should live before I commit it.
* VAA power: Move code to HackRF board file
It doesn't belong in PAL.
* MAX5 CPLD: Add SAMPLE and EXTEST methods.
* Flash image: Change packing scheme to use flash more efficiently.
Application is now a single image for both M4 bootstrap and M0.
Baseband images come immediately after application binary. No need to align to large blocks (and waste lots of flash).
* Clock Manager: Remove PLL1 power down function.
* Move and rename peripherals reset function to board module.
* Remove unused peripheral/clock management.
* Clock Manager: Extract switch to IRC into separate function.
* Clock Manager: More explicit shutdown of clocks, clock generator.
* Move initialization to board module.
* ChibiOS: Rename "application" board, add "baseband" board.
There are now two ChibiOS "boards", one which runs the application and does the hardware setup. The other board, "baseband", does very little setup.
* Clock Manager: Remove unused crystal enable/disable code.
* Clock Manager: Restore clock configuration to SPIFI bootloader state before app shutdown.
* Reset peripherals on app shutdown.
Be careful not to reset M0APP (the core we're running on) or GPIO (which is holding the hardware in a stable state).
* M4/baseband hal_lld_init: use IDIVA, which is configured earlier by M0.
This was causing problems during restart into HackRF mode. Baseband hal_lld_init changed M4 clock from IDIVA (set by M0) to PLL1, which was unceremoniously turned off during shutdown.
* Audio app: Stop audio PLL on shutdown.
* M4 HAL: Make LPC43XX_M4_CLK_SRC optional.
This was changing the BASE_M4_CLK when a baseband was run.
* LPC43xx C++ layer: Fix IDIVx constructor IDIV narrow field width.
* Application board: hide the peripherals_reset function, as it isn't useful except during hardware init.
* Consolidate hardware init code to some degree.
ClockManager is super-overloaded and murky in its purpose.
Migrate audio from IDIVC to IDIVD, to more closely resemble initial clock scheme, so it's simpler to get back to it during shutdown.
* Migrate some startup code to application board.
* Si5351: Use correct methods for reset().
update_output_enable_control() doesn't reset the enabled outputs to the reset state, unless the object is freshly initialized, which it isn't when performing firmware shutdown.
For similar reasons, use set_clock_control() instead of setting internal state and then using the update function.
* GPIO: Set SPIFI CS pin to match input buffer state coming out of bootloader.
* Change application board.c to .cpp, with required dependent changes
* Board: Clean up SCU configuration code/data.
* I2S: Add shutdown code and use it.
* LPC43xx: Consolidate a bunch of structures that had been scattered all over.
...because I'm an undisciplined coder.
* I2S: Fix ordering of branch and base clock disable.
Core was hanging, presumably because the register interface on the branch/peripheral was unresponsive after the base clock was disabled.
* Controls: Save and expose raw navigation wheel switch state
I need to do some work on debouncing and ignoring simultaneous key presses.
* Controls: Add debug view for switches state.
* Controls: Ignore all key presses until all keys are released.
This should address some mechanical quirks of the navigation wheel used on the PortaPack.
* Clock Manager: Wait for only the necessary PLL to lock.
Wasn't working on PortaPacks without a built-in clock reference, as that uses the other PLL.
TODO: Switching PLLs may be kind of pointless now...
* CMake: Pull HackRF project from GitHub and build.
* CMake: Remove commented code.
* CMake: Clone HackRF via HTTPS, not SSH.
* CMake: Extra pause for slow post-DFU firmware boot-up.
* CMake: TODO to fix SVF/XSVF file source.
* CMake: Ask HackRF hackrf_usb to make DFU binary.
* Travis-CI: Add dfu-util, now that HackRF firmware is being built for inclusion.
* Travis-CI: Update build environment to Ubuntu xenial
Previously Trusty.
* Travis-CI: Incorrectly structured my request for dfu-util package.
I'm soooo talented.
* ldscript: Mark flash, ram with correct R/W/X flags.
* ldscript: Enlarge M0 flash region to 1Mbyte, the size of the HackRF SPI flash.
* Receiver: Hide PPM adjustment if clock source is not HackRF crystal.
* Documentation: Update product photos and README.
* Documentation: Add TCXO feature to README description.
* Application: Rearrange files to match HAVOC directory structure.
* Map view in AIS (#213)
* Added GeoMapView to AISRecentEntryDetailView
* Added autoupdate in AIS map
* Revert "Map view in AIS (#213)"
This reverts commit 262c030224b9ea3e56ff1c8a66246e7ecf30e41f.
This commit will be cherry-picked onto a clean branch, then re-committed after a troublesome pull request is reverted.
* Revert "Upstream merge to make new revision of PortaPack work (#206)"
This reverts commit 920b98f7c9a30371b643c42949066fb7d2441daf.
This pull request was missing some changes and was preventing firmware from functioning on older PortaPacks.
* CPLD: Pull bitstream from HackRF project.
* SGPIO: Identify pins on CPLD by their new functions. Pull down HOST_SYNC_EN.
* CPLD: Don't load HackRF CPLD bitstream into RAM.
Trying to converge CPLD implementations, so this shouldn't be necesssary. HOWEVER, it would be good to *check* the CPLD contents and provide a way to update, if necessary.
* CPLD: Tweak clock generator config to match CPLD timing changes in HackRF.
* PinConfig: Drive CPLD pins correctly.
* CMake: Use jboone/hackrf master branch, now that CPLD fixes are there.
* CMake: Fix HackRF CPLD SVF dependency.
Build would break on the first pass, but work if you restarted make.
* CMake: Fix my misuse of the HackRF CMake configuration -- was building from too deep in the directory tree
* CMake: Work-around for CMake 3.5 not supporting ExternalProject_Add SOURCE_SUBDIR.
* CMake: Choose a CMP0005 policy to quiet CMake warnings.
* Settings: Show active clock reference. Only show PPM adjustment for HackRF source.
* Radio Settings: Change reference clock text color.
Make consistent color with other un-editable text.
TODO: This is a bit of a hack to get ui::Text objects to support custom colors, like the Label structures used elsewhere.
2019-02-03 19:25:11 +01:00
|
|
|
|
|
|
|
|
return { detected_reference, 10000000 };
|
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 07:56:21 +01:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2023-02-16 12:09:23 +00:00
|
|
|
if (hackrf_r9) {
|
|
|
|
|
gpio_r9_clkin_en.write(0);
|
|
|
|
|
}
|
|
|
|
|
|
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 07:56:21 +01:00
|
|
|
portapack_tcxo_disable();
|
2023-02-16 12:09:23 +00:00
|
|
|
return { ReferenceSource::Xtal, 25000000 };
|
2015-07-08 08:39:24 -07:00
|
|
|
}
|
|
|
|
|
|
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 07:56:21 +01:00
|
|
|
void ClockManager::shutdown() {
|
|
|
|
|
clock_generator.reset();
|
2015-07-08 08:39:24 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void ClockManager::enable_codec_clocks() {
|
2023-02-16 12:09:23 +00:00
|
|
|
if (hackrf_r9) {
|
|
|
|
|
clock_generator.enable_clock(clock_generator_output_r9_sgpio);
|
|
|
|
|
} else {
|
|
|
|
|
clock_generator.enable_clock(clock_generator_output_og_codec);
|
|
|
|
|
clock_generator.enable_clock(clock_generator_output_og_cpld);
|
|
|
|
|
clock_generator.enable_clock(clock_generator_output_og_sgpio);
|
|
|
|
|
}
|
2015-07-08 08:39:24 -07:00
|
|
|
/* Turn on all outputs at the same time. This probably doesn't ensure
|
|
|
|
|
* their phase relationships. For example, clocks that output frequencies
|
|
|
|
|
* in a 2:1 relationship may start with the slower clock high or low?
|
|
|
|
|
*/
|
2023-02-16 12:09:23 +00:00
|
|
|
if (hackrf_r9) {
|
|
|
|
|
clock_generator.enable_output_mask(1U << clock_generator_output_r9_sgpio);
|
|
|
|
|
} else {
|
|
|
|
|
clock_generator.enable_output_mask(
|
|
|
|
|
(1U << clock_generator_output_og_codec)
|
|
|
|
|
| (1U << clock_generator_output_og_cpld)
|
|
|
|
|
| (1U << clock_generator_output_og_sgpio)
|
|
|
|
|
);
|
|
|
|
|
}
|
2015-07-08 08:39:24 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void ClockManager::disable_codec_clocks() {
|
|
|
|
|
/* Turn off outputs before disabling clocks. It seems the clock needs to
|
|
|
|
|
* be enabled for the output to come to rest at the state specified by
|
|
|
|
|
* CLKx_DISABLE_STATE.
|
|
|
|
|
*/
|
2023-02-16 12:09:23 +00:00
|
|
|
if (hackrf_r9) {
|
|
|
|
|
clock_generator.disable_output_mask(1U << clock_generator_output_r9_sgpio);
|
|
|
|
|
clock_generator.disable_clock(clock_generator_output_r9_sgpio);
|
|
|
|
|
} else {
|
|
|
|
|
clock_generator.disable_output_mask(
|
|
|
|
|
(1U << clock_generator_output_og_codec)
|
|
|
|
|
| (1U << clock_generator_output_og_cpld)
|
|
|
|
|
| (1U << clock_generator_output_og_sgpio)
|
|
|
|
|
);
|
|
|
|
|
clock_generator.disable_clock(clock_generator_output_og_codec);
|
|
|
|
|
clock_generator.disable_clock(clock_generator_output_og_cpld);
|
|
|
|
|
clock_generator.disable_clock(clock_generator_output_og_sgpio);
|
|
|
|
|
}
|
2015-07-08 08:39:24 -07:00
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
2023-02-16 12:09:23 +00:00
|
|
|
void ClockManager::enable_if_clocks() {
|
|
|
|
|
if (hackrf_r9) {
|
|
|
|
|
clock_generator.enable_clock(clock_generator_output_r9_if);
|
|
|
|
|
clock_generator.enable_output_mask(1U << clock_generator_output_r9_if);
|
|
|
|
|
} else {
|
|
|
|
|
clock_generator.enable_clock(clock_generator_output_og_first_if);
|
|
|
|
|
clock_generator.enable_output_mask(1U << clock_generator_output_og_first_if);
|
|
|
|
|
clock_generator.enable_clock(clock_generator_output_og_second_if);
|
|
|
|
|
clock_generator.enable_output_mask(1U << clock_generator_output_og_second_if);
|
2015-07-08 08:39:24 -07:00
|
|
|
|
2023-02-16 12:09:23 +00:00
|
|
|
}
|
2015-07-08 08:39:24 -07:00
|
|
|
}
|
|
|
|
|
|
2023-02-16 12:09:23 +00:00
|
|
|
void ClockManager::disable_if_clocks() {
|
|
|
|
|
if (hackrf_r9) {
|
|
|
|
|
clock_generator.disable_output_mask(1U << clock_generator_output_r9_if);
|
|
|
|
|
clock_generator.disable_clock(clock_generator_output_r9_if);
|
|
|
|
|
} else {
|
|
|
|
|
clock_generator.disable_output_mask(1U << clock_generator_output_og_first_if);
|
|
|
|
|
clock_generator.disable_clock(clock_generator_output_og_first_if);
|
|
|
|
|
clock_generator.disable_output_mask(1U << clock_generator_output_og_second_if);
|
|
|
|
|
clock_generator.disable_clock(clock_generator_output_og_second_if);
|
|
|
|
|
}
|
2015-07-08 08:39:24 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void ClockManager::set_sampling_frequency(const uint32_t frequency) {
|
|
|
|
|
/* Codec clock is at sampling frequency, CPLD and SGPIO clocks are at
|
|
|
|
|
* twice the frequency, and derived from the MS0 synth. So it's only
|
|
|
|
|
* necessary to change the MS0 synth frequency, and ensure the output
|
|
|
|
|
* is divided by two.
|
|
|
|
|
*/
|
2023-02-16 12:09:23 +00:00
|
|
|
if (hackrf_r9) {
|
|
|
|
|
clock_generator.set_ms_frequency(clock_generator_output_r9_sgpio, frequency * 2, si5351_vco_f, 0);
|
|
|
|
|
} else {
|
|
|
|
|
clock_generator.set_ms_frequency(clock_generator_output_og_codec, frequency * 2, si5351_vco_f, 1);
|
|
|
|
|
}
|
2015-07-08 08:39:24 -07:00
|
|
|
}
|
|
|
|
|
|
2015-08-24 12:09:11 -07:00
|
|
|
void ClockManager::set_reference_ppb(const int32_t ppb) {
|
2023-02-16 12:09:23 +00:00
|
|
|
/* NOTE: This adjustment only affects PLLA when it is derived from the 25MHz crystal.
|
|
|
|
|
* It is assumed an external clock coming in to CLKIN/PLLB is sufficiently accurate as to not need adjustment.
|
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 07:56:21 +01:00
|
|
|
* TODO: Revisit the above policy. It may be good to allow adjustment of the external reference too.
|
|
|
|
|
*/
|
2023-02-16 12:09:23 +00:00
|
|
|
if (hackrf_r9 && reference.source != ReferenceSource::Xtal) {
|
|
|
|
|
return;
|
|
|
|
|
}
|
2015-08-24 12:09:11 -07:00
|
|
|
constexpr uint32_t pll_multiplier = si5351_pll_xtal_25m.a;
|
2015-08-25 17:56:03 -07:00
|
|
|
constexpr uint32_t denominator = 1000000 / pll_multiplier;
|
2015-08-24 12:09:11 -07:00
|
|
|
const uint32_t new_a = (ppb >= 0) ? pll_multiplier : (pll_multiplier - 1);
|
2015-08-25 17:56:03 -07:00
|
|
|
const uint32_t new_b = (ppb >= 0) ? (ppb / 1000) : (denominator + (ppb / 1000));
|
|
|
|
|
const uint32_t new_c = (ppb == 0) ? 1 : denominator;
|
2015-08-24 12:09:11 -07:00
|
|
|
|
|
|
|
|
const si5351::PLL pll {
|
|
|
|
|
.f_in = si5351_inputs.f_xtal,
|
|
|
|
|
.a = new_a,
|
|
|
|
|
.b = new_b,
|
|
|
|
|
.c = new_c,
|
|
|
|
|
};
|
|
|
|
|
const auto pll_a_reg = pll.reg(0);
|
|
|
|
|
clock_generator.write(pll_a_reg);
|
|
|
|
|
}
|
|
|
|
|
|
2018-08-05 12:19:41 -07:00
|
|
|
void ClockManager::start_frequency_monitor_measurement(const cgu::CLK_SEL clk_sel) {
|
|
|
|
|
// Measure a clock input for 480 cycles of the LPC43xx IRC.
|
|
|
|
|
LPC_CGU->FREQ_MON = LPC_CGU_FREQ_MON_Type {
|
|
|
|
|
.RCNT = 480,
|
|
|
|
|
.FCNT = 0,
|
|
|
|
|
.MEAS = 0,
|
|
|
|
|
.CLK_SEL = toUType(clk_sel),
|
|
|
|
|
.RESERVED0 = 0
|
|
|
|
|
};
|
|
|
|
|
LPC_CGU->FREQ_MON.MEAS = 1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void ClockManager::wait_For_frequency_monitor_measurement_done() {
|
|
|
|
|
// FREQ_MON mechanism fails to finish if there's no clock present on selected input?!
|
|
|
|
|
while(LPC_CGU->FREQ_MON.MEAS == 1);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
uint32_t ClockManager::get_frequency_monitor_measurement_in_hertz() {
|
|
|
|
|
// Measurement is only as accurate as the LPC43xx IRC oscillator,
|
|
|
|
|
// which is +/- 1.5%. Measurement is for 480 IRC clcocks. Scale
|
|
|
|
|
// the cycle count to get a value in Hertz.
|
|
|
|
|
return LPC_CGU->FREQ_MON.FCNT * 25000;
|
|
|
|
|
}
|
|
|
|
|
|
2015-07-08 08:39:24 -07:00
|
|
|
void ClockManager::start_audio_pll() {
|
|
|
|
|
cgu::pll0audio::ctrl({
|
|
|
|
|
.pd = 1,
|
|
|
|
|
.bypass = 0,
|
|
|
|
|
.directi = 0,
|
|
|
|
|
.directo = 0,
|
|
|
|
|
.clken = 0,
|
|
|
|
|
.frm = 0,
|
|
|
|
|
.autoblock = 1,
|
|
|
|
|
.pllfract_req = 0,
|
|
|
|
|
.sel_ext = 1,
|
|
|
|
|
.mod_pd = 1,
|
|
|
|
|
.clk_sel = cgu::CLK_SEL::GP_CLKIN,
|
|
|
|
|
});
|
|
|
|
|
|
|
|
|
|
/* For 40MHz clock source, 48kHz audio rate, 256Fs MCLK:
|
|
|
|
|
* Fout=12.288MHz, Fcco=491.52MHz
|
2023-02-16 12:09:23 +00:00
|
|
|
* OG: PSEL=20, NSEL=125, MSEL=768
|
2015-07-08 08:39:24 -07:00
|
|
|
* PDEC=31, NDEC=45, MDEC=30542
|
2023-02-16 12:09:23 +00:00
|
|
|
* r9: PSEL=20, NSEL=125, MSEL=3072
|
|
|
|
|
* PDEC=31, NDEC=45, MDEC=8308
|
2015-07-08 08:39:24 -07:00
|
|
|
*/
|
|
|
|
|
cgu::pll0audio::mdiv({
|
2023-02-16 12:09:23 +00:00
|
|
|
.mdec = hackrf_r9 ? 8308UL : 30542UL,
|
2015-07-08 08:39:24 -07:00
|
|
|
});
|
|
|
|
|
cgu::pll0audio::np_div({
|
|
|
|
|
.pdec = 31,
|
|
|
|
|
.ndec = 45,
|
|
|
|
|
});
|
|
|
|
|
|
|
|
|
|
cgu::pll0audio::frac({
|
|
|
|
|
.pllfract_ctrl = 0,
|
|
|
|
|
});
|
|
|
|
|
|
|
|
|
|
cgu::pll0audio::power_up();
|
|
|
|
|
while( !cgu::pll0audio::is_locked() );
|
|
|
|
|
cgu::pll0audio::clock_enable();
|
|
|
|
|
|
2016-01-29 15:17:05 -08:00
|
|
|
set_base_audio_clock_divider(1);
|
PortaPack Sync, take 2 (#215)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* PCB: Change PCB stackup, Tg, clarify solder mask color, use more metric.
* PCB: Move HackRF header P9 to B.CrtYd layer.
* PCB: Change a Tg reference I missed.
* PCB: Update footprints for parts with mismatched CAD->tape rotation.
Adjust a few layer choice and line thickness bits.
* PCB: Got cold feet, switched back to rectangular pads.
* PCB: Add Eco layers to be visible and Gerber output.
* PCB: Use aux origin for plotting, for tidier coordinates.
* PCB: Output Gerber job file, because why not?
* Schematic: Correct footprints for two reference-related components.
* Schematic: Remove manfuacturer and part number for DNP component.
* Schematic: Specify resistor value, manufacturer, part number for reference oscillator series termination.
* PCB: Update netlist and footprints from schematic.
* Netlist: Updated component values, footprints.
* PCB: Nudge some components and traces to address DRC clearance violations.
* PCB: Allow KiCad to update zone timestamps (again?!).
* PCB: Generate *all* Gerber layers.
* Schematic, PCB: Update revision to 20181025.
* PCB: Adjust fab layer annotations orientation and font size.
* PCB: Hide mounting hole reference designators on silk layer.
* PCB: Shrink U1, U3 pads to get 0.2mm space between pads.
* PCB: Set pad-to-mask clearance to zero, leave up to fab. Set minimum mask web to 0.2mm for non-black options.
* PCB: Revise U1 pad shape, mask, paste, thermal drills.
Clearance is improved at corner pads.
* PCB: Tweak U3 for better thermal pad/drill/mask/paste design.
* PCB: Change solder mask color to blue.
* Schematic, PCB: Update revision to 20181029.
* PCB: Bump minimum mask web down a tiny bit because KiCad is having trouble with math.
* Update schematic
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Clock Manager: Actually store chosen clock reference
Similarly-named local was covering a member and discarding the value.
* Clock Manager: Reference type which contains source, frequency.
* Setup: Display reference source, frequency in frequency correction screen.
* LPC43xx API: Add extern "C" for use from C++.
* Use LPC43xx API for SGPIO, GPDMA, I2S initialization.
* I2S: Add BASE_AUDIO_CLK management.
* Add MOTOCON_PWM clock/reset structure.
* Serial: Fix dumb typos.
* Serial: Remove extra reference operator.
* Serial: Cut-and-paste error in structure type name.
* Move SCU structure from PAL to LPC43xx API.
It'd be nice if I gave some thought to where code should live before I commit it.
* VAA power: Move code to HackRF board file
It doesn't belong in PAL.
* MAX5 CPLD: Add SAMPLE and EXTEST methods.
* Flash image: Change packing scheme to use flash more efficiently.
Application is now a single image for both M4 bootstrap and M0.
Baseband images come immediately after application binary. No need to align to large blocks (and waste lots of flash).
* Clock Manager: Remove PLL1 power down function.
* Move and rename peripherals reset function to board module.
* Remove unused peripheral/clock management.
* Clock Manager: Extract switch to IRC into separate function.
* Clock Manager: More explicit shutdown of clocks, clock generator.
* Move initialization to board module.
* ChibiOS: Rename "application" board, add "baseband" board.
There are now two ChibiOS "boards", one which runs the application and does the hardware setup. The other board, "baseband", does very little setup.
* Clock Manager: Remove unused crystal enable/disable code.
* Clock Manager: Restore clock configuration to SPIFI bootloader state before app shutdown.
* Reset peripherals on app shutdown.
Be careful not to reset M0APP (the core we're running on) or GPIO (which is holding the hardware in a stable state).
* M4/baseband hal_lld_init: use IDIVA, which is configured earlier by M0.
This was causing problems during restart into HackRF mode. Baseband hal_lld_init changed M4 clock from IDIVA (set by M0) to PLL1, which was unceremoniously turned off during shutdown.
* Audio app: Stop audio PLL on shutdown.
* M4 HAL: Make LPC43XX_M4_CLK_SRC optional.
This was changing the BASE_M4_CLK when a baseband was run.
* LPC43xx C++ layer: Fix IDIVx constructor IDIV narrow field width.
* Application board: hide the peripherals_reset function, as it isn't useful except during hardware init.
* Consolidate hardware init code to some degree.
ClockManager is super-overloaded and murky in its purpose.
Migrate audio from IDIVC to IDIVD, to more closely resemble initial clock scheme, so it's simpler to get back to it during shutdown.
* Migrate some startup code to application board.
* Si5351: Use correct methods for reset().
update_output_enable_control() doesn't reset the enabled outputs to the reset state, unless the object is freshly initialized, which it isn't when performing firmware shutdown.
For similar reasons, use set_clock_control() instead of setting internal state and then using the update function.
* GPIO: Set SPIFI CS pin to match input buffer state coming out of bootloader.
* Change application board.c to .cpp, with required dependent changes
* Board: Clean up SCU configuration code/data.
* I2S: Add shutdown code and use it.
* LPC43xx: Consolidate a bunch of structures that had been scattered all over.
...because I'm an undisciplined coder.
* I2S: Fix ordering of branch and base clock disable.
Core was hanging, presumably because the register interface on the branch/peripheral was unresponsive after the base clock was disabled.
* Controls: Save and expose raw navigation wheel switch state
I need to do some work on debouncing and ignoring simultaneous key presses.
* Controls: Add debug view for switches state.
* Controls: Ignore all key presses until all keys are released.
This should address some mechanical quirks of the navigation wheel used on the PortaPack.
* Clock Manager: Wait for only the necessary PLL to lock.
Wasn't working on PortaPacks without a built-in clock reference, as that uses the other PLL.
TODO: Switching PLLs may be kind of pointless now...
* CMake: Pull HackRF project from GitHub and build.
* CMake: Remove commented code.
* CMake: Clone HackRF via HTTPS, not SSH.
* CMake: Extra pause for slow post-DFU firmware boot-up.
* CMake: TODO to fix SVF/XSVF file source.
* CMake: Ask HackRF hackrf_usb to make DFU binary.
* Travis-CI: Add dfu-util, now that HackRF firmware is being built for inclusion.
* Travis-CI: Update build environment to Ubuntu xenial
Previously Trusty.
* Travis-CI: Incorrectly structured my request for dfu-util package.
I'm soooo talented.
* ldscript: Mark flash, ram with correct R/W/X flags.
* ldscript: Enlarge M0 flash region to 1Mbyte, the size of the HackRF SPI flash.
* Receiver: Hide PPM adjustment if clock source is not HackRF crystal.
* Documentation: Update product photos and README.
* Documentation: Add TCXO feature to README description.
* Application: Rearrange files to match HAVOC directory structure.
* Map view in AIS (#213)
* Added GeoMapView to AISRecentEntryDetailView
* Added autoupdate in AIS map
* Revert "Map view in AIS (#213)"
This reverts commit 262c030224b9ea3e56ff1c8a66246e7ecf30e41f.
This commit will be cherry-picked onto a clean branch, then re-committed after a troublesome pull request is reverted.
* Revert "Upstream merge to make new revision of PortaPack work (#206)"
This reverts commit 920b98f7c9a30371b643c42949066fb7d2441daf.
This pull request was missing some changes and was preventing firmware from functioning on older PortaPacks.
* CPLD: Pull bitstream from HackRF project.
* SGPIO: Identify pins on CPLD by their new functions. Pull down HOST_SYNC_EN.
* CPLD: Don't load HackRF CPLD bitstream into RAM.
Trying to converge CPLD implementations, so this shouldn't be necesssary. HOWEVER, it would be good to *check* the CPLD contents and provide a way to update, if necessary.
* CPLD: Tweak clock generator config to match CPLD timing changes in HackRF.
* PinConfig: Drive CPLD pins correctly.
* CMake: Use jboone/hackrf master branch, now that CPLD fixes are there.
* CMake: Fix HackRF CPLD SVF dependency.
Build would break on the first pass, but work if you restarted make.
* CMake: Fix my misuse of the HackRF CMake configuration -- was building from too deep in the directory tree
* CMake: Work-around for CMake 3.5 not supporting ExternalProject_Add SOURCE_SUBDIR.
* CMake: Choose a CMP0005 policy to quiet CMake warnings.
* Settings: Show active clock reference. Only show PPM adjustment for HackRF source.
* Radio Settings: Change reference clock text color.
Make consistent color with other un-editable text.
TODO: This is a bit of a hack to get ui::Text objects to support custom colors, like the Label structures used elsewhere.
2019-02-03 19:25:11 +01:00
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LPC_CGU->BASE_AUDIO_CLK.AUTOBLOCK = 1;
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LPC_CGU->BASE_AUDIO_CLK.CLK_SEL = toUType(cgu::CLK_SEL::IDIVD);
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2016-01-29 15:17:05 -08:00
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}
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void ClockManager::set_base_audio_clock_divider(const size_t divisor) {
|
PortaPack Sync, take 2 (#215)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* PCB: Change PCB stackup, Tg, clarify solder mask color, use more metric.
* PCB: Move HackRF header P9 to B.CrtYd layer.
* PCB: Change a Tg reference I missed.
* PCB: Update footprints for parts with mismatched CAD->tape rotation.
Adjust a few layer choice and line thickness bits.
* PCB: Got cold feet, switched back to rectangular pads.
* PCB: Add Eco layers to be visible and Gerber output.
* PCB: Use aux origin for plotting, for tidier coordinates.
* PCB: Output Gerber job file, because why not?
* Schematic: Correct footprints for two reference-related components.
* Schematic: Remove manfuacturer and part number for DNP component.
* Schematic: Specify resistor value, manufacturer, part number for reference oscillator series termination.
* PCB: Update netlist and footprints from schematic.
* Netlist: Updated component values, footprints.
* PCB: Nudge some components and traces to address DRC clearance violations.
* PCB: Allow KiCad to update zone timestamps (again?!).
* PCB: Generate *all* Gerber layers.
* Schematic, PCB: Update revision to 20181025.
* PCB: Adjust fab layer annotations orientation and font size.
* PCB: Hide mounting hole reference designators on silk layer.
* PCB: Shrink U1, U3 pads to get 0.2mm space between pads.
* PCB: Set pad-to-mask clearance to zero, leave up to fab. Set minimum mask web to 0.2mm for non-black options.
* PCB: Revise U1 pad shape, mask, paste, thermal drills.
Clearance is improved at corner pads.
* PCB: Tweak U3 for better thermal pad/drill/mask/paste design.
* PCB: Change solder mask color to blue.
* Schematic, PCB: Update revision to 20181029.
* PCB: Bump minimum mask web down a tiny bit because KiCad is having trouble with math.
* Update schematic
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Clock Manager: Actually store chosen clock reference
Similarly-named local was covering a member and discarding the value.
* Clock Manager: Reference type which contains source, frequency.
* Setup: Display reference source, frequency in frequency correction screen.
* LPC43xx API: Add extern "C" for use from C++.
* Use LPC43xx API for SGPIO, GPDMA, I2S initialization.
* I2S: Add BASE_AUDIO_CLK management.
* Add MOTOCON_PWM clock/reset structure.
* Serial: Fix dumb typos.
* Serial: Remove extra reference operator.
* Serial: Cut-and-paste error in structure type name.
* Move SCU structure from PAL to LPC43xx API.
It'd be nice if I gave some thought to where code should live before I commit it.
* VAA power: Move code to HackRF board file
It doesn't belong in PAL.
* MAX5 CPLD: Add SAMPLE and EXTEST methods.
* Flash image: Change packing scheme to use flash more efficiently.
Application is now a single image for both M4 bootstrap and M0.
Baseband images come immediately after application binary. No need to align to large blocks (and waste lots of flash).
* Clock Manager: Remove PLL1 power down function.
* Move and rename peripherals reset function to board module.
* Remove unused peripheral/clock management.
* Clock Manager: Extract switch to IRC into separate function.
* Clock Manager: More explicit shutdown of clocks, clock generator.
* Move initialization to board module.
* ChibiOS: Rename "application" board, add "baseband" board.
There are now two ChibiOS "boards", one which runs the application and does the hardware setup. The other board, "baseband", does very little setup.
* Clock Manager: Remove unused crystal enable/disable code.
* Clock Manager: Restore clock configuration to SPIFI bootloader state before app shutdown.
* Reset peripherals on app shutdown.
Be careful not to reset M0APP (the core we're running on) or GPIO (which is holding the hardware in a stable state).
* M4/baseband hal_lld_init: use IDIVA, which is configured earlier by M0.
This was causing problems during restart into HackRF mode. Baseband hal_lld_init changed M4 clock from IDIVA (set by M0) to PLL1, which was unceremoniously turned off during shutdown.
* Audio app: Stop audio PLL on shutdown.
* M4 HAL: Make LPC43XX_M4_CLK_SRC optional.
This was changing the BASE_M4_CLK when a baseband was run.
* LPC43xx C++ layer: Fix IDIVx constructor IDIV narrow field width.
* Application board: hide the peripherals_reset function, as it isn't useful except during hardware init.
* Consolidate hardware init code to some degree.
ClockManager is super-overloaded and murky in its purpose.
Migrate audio from IDIVC to IDIVD, to more closely resemble initial clock scheme, so it's simpler to get back to it during shutdown.
* Migrate some startup code to application board.
* Si5351: Use correct methods for reset().
update_output_enable_control() doesn't reset the enabled outputs to the reset state, unless the object is freshly initialized, which it isn't when performing firmware shutdown.
For similar reasons, use set_clock_control() instead of setting internal state and then using the update function.
* GPIO: Set SPIFI CS pin to match input buffer state coming out of bootloader.
* Change application board.c to .cpp, with required dependent changes
* Board: Clean up SCU configuration code/data.
* I2S: Add shutdown code and use it.
* LPC43xx: Consolidate a bunch of structures that had been scattered all over.
...because I'm an undisciplined coder.
* I2S: Fix ordering of branch and base clock disable.
Core was hanging, presumably because the register interface on the branch/peripheral was unresponsive after the base clock was disabled.
* Controls: Save and expose raw navigation wheel switch state
I need to do some work on debouncing and ignoring simultaneous key presses.
* Controls: Add debug view for switches state.
* Controls: Ignore all key presses until all keys are released.
This should address some mechanical quirks of the navigation wheel used on the PortaPack.
* Clock Manager: Wait for only the necessary PLL to lock.
Wasn't working on PortaPacks without a built-in clock reference, as that uses the other PLL.
TODO: Switching PLLs may be kind of pointless now...
* CMake: Pull HackRF project from GitHub and build.
* CMake: Remove commented code.
* CMake: Clone HackRF via HTTPS, not SSH.
* CMake: Extra pause for slow post-DFU firmware boot-up.
* CMake: TODO to fix SVF/XSVF file source.
* CMake: Ask HackRF hackrf_usb to make DFU binary.
* Travis-CI: Add dfu-util, now that HackRF firmware is being built for inclusion.
* Travis-CI: Update build environment to Ubuntu xenial
Previously Trusty.
* Travis-CI: Incorrectly structured my request for dfu-util package.
I'm soooo talented.
* ldscript: Mark flash, ram with correct R/W/X flags.
* ldscript: Enlarge M0 flash region to 1Mbyte, the size of the HackRF SPI flash.
* Receiver: Hide PPM adjustment if clock source is not HackRF crystal.
* Documentation: Update product photos and README.
* Documentation: Add TCXO feature to README description.
* Application: Rearrange files to match HAVOC directory structure.
* Map view in AIS (#213)
* Added GeoMapView to AISRecentEntryDetailView
* Added autoupdate in AIS map
* Revert "Map view in AIS (#213)"
This reverts commit 262c030224b9ea3e56ff1c8a66246e7ecf30e41f.
This commit will be cherry-picked onto a clean branch, then re-committed after a troublesome pull request is reverted.
* Revert "Upstream merge to make new revision of PortaPack work (#206)"
This reverts commit 920b98f7c9a30371b643c42949066fb7d2441daf.
This pull request was missing some changes and was preventing firmware from functioning on older PortaPacks.
* CPLD: Pull bitstream from HackRF project.
* SGPIO: Identify pins on CPLD by their new functions. Pull down HOST_SYNC_EN.
* CPLD: Don't load HackRF CPLD bitstream into RAM.
Trying to converge CPLD implementations, so this shouldn't be necesssary. HOWEVER, it would be good to *check* the CPLD contents and provide a way to update, if necessary.
* CPLD: Tweak clock generator config to match CPLD timing changes in HackRF.
* PinConfig: Drive CPLD pins correctly.
* CMake: Use jboone/hackrf master branch, now that CPLD fixes are there.
* CMake: Fix HackRF CPLD SVF dependency.
Build would break on the first pass, but work if you restarted make.
* CMake: Fix my misuse of the HackRF CMake configuration -- was building from too deep in the directory tree
* CMake: Work-around for CMake 3.5 not supporting ExternalProject_Add SOURCE_SUBDIR.
* CMake: Choose a CMP0005 policy to quiet CMake warnings.
* Settings: Show active clock reference. Only show PPM adjustment for HackRF source.
* Radio Settings: Change reference clock text color.
Make consistent color with other un-editable text.
TODO: This is a bit of a hack to get ui::Text objects to support custom colors, like the Label structures used elsewhere.
2019-02-03 19:25:11 +01:00
|
|
|
LPC_CGU->IDIVD_CTRL.word =
|
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 07:56:21 +01:00
|
|
|
(0 << 0)
|
2016-01-29 15:17:05 -08:00
|
|
|
| ((divisor - 1) << 2)
|
|
|
|
|
| (1 << 11)
|
|
|
|
|
| (toUType(cgu::CLK_SEL::PLL0AUDIO) << 24)
|
|
|
|
|
;
|
2015-07-08 08:39:24 -07:00
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|
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}
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|
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void ClockManager::stop_audio_pll() {
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cgu::pll0audio::clock_disable();
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|
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|
cgu::pll0audio::power_down();
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|
while( cgu::pll0audio::is_locked() );
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}
|
2020-09-16 19:27:56 +08:00
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void ClockManager::enable_clock_output(bool enable) {
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if(enable) {
|
2023-02-16 12:09:23 +00:00
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|
clock_generator.enable_output(clock_generator_output_og_clkout);
|
2020-10-24 00:24:05 +08:00
|
|
|
if(portapack::persistent_memory::clkout_freq() < 1000) {
|
2023-02-16 12:09:23 +00:00
|
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clock_generator.set_ms_frequency(clock_generator_output_og_clkout, portapack::persistent_memory::clkout_freq() * 128000, si5351_vco_f, 7);
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2020-10-24 00:24:05 +08:00
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} else {
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2023-02-16 12:09:23 +00:00
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clock_generator.set_ms_frequency(clock_generator_output_og_clkout, portapack::persistent_memory::clkout_freq() * 1000, si5351_vco_f, 0);
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2020-10-24 00:24:05 +08:00
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}
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2020-09-16 19:27:56 +08:00
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} else {
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2023-02-16 12:09:23 +00:00
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clock_generator.disable_output(clock_generator_output_og_clkout);
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2020-09-16 19:27:56 +08:00
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}
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2023-02-16 12:09:23 +00:00
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auto si5351_clock_control_common = hackrf_r9
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? si5351a_clock_control_common
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: si5351c_clock_control_common;
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const auto ref_pll = hackrf_r9
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? ClockControl::MultiSynthSource::PLLA
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: get_si5351c_reference_clock_generator_pll(reference.source);
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2020-09-16 19:27:56 +08:00
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if(enable)
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2023-02-16 12:09:23 +00:00
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clock_generator.set_clock_control(clock_generator_output_og_clkout, si5351_clock_control_common[clock_generator_output_og_clkout].ms_src(ref_pll).clk_pdn(ClockControl::ClockPowerDown::Power_On));
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2020-09-16 19:27:56 +08:00
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else
|
2023-02-16 12:09:23 +00:00
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clock_generator.set_clock_control(clock_generator_output_og_clkout, ClockControl::power_off());
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2020-09-16 19:27:56 +08:00
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}
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