mirror of
https://github.com/portapack-mayhem/mayhem-firmware.git
synced 2024-12-15 12:38:11 +00:00
83 lines
2.2 KiB
C++
83 lines
2.2 KiB
C++
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/*
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* Copyright (C) 2014 Jared Boone, ShareBrained Technology, Inc.
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*
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* This file is part of PortaPack.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 51 Franklin Street,
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* Boston, MA 02110-1301, USA.
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*/
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#include "hackrf_hal.hpp"
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#include "lpc43xx_cpp.hpp"
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using namespace lpc43xx;
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namespace hackrf {
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namespace one {
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void reset() {
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/* "The reset delay is counted in IRC clock cycles. If the core frequency
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* CCLK is much higher than the IRC frequency, add a software delay of
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* fCCLK/fIRC clock cycles between resetting and accessing any of the
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* peripheral blocks."
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*/
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rgu::reset_mask(
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/* Don't reset SCU, may trip up SPIFI pins if running from SPIFI
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* memory.
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*/
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/*rgu::Reset::SCU */
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rgu::Reset::LCD
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| rgu::Reset::USB0
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| rgu::Reset::USB1
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| rgu::Reset::DMA
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| rgu::Reset::SDIO
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| rgu::Reset::EMC
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| rgu::Reset::ETHERNET
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| rgu::Reset::GPIO
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| rgu::Reset::TIMER0
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| rgu::Reset::TIMER1
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| rgu::Reset::TIMER2
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| rgu::Reset::TIMER3
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| rgu::Reset::RITIMER
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| rgu::Reset::SCT
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| rgu::Reset::MOTOCONPWM
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| rgu::Reset::QEI
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| rgu::Reset::ADC0
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| rgu::Reset::ADC1
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| rgu::Reset::DAC
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| rgu::Reset::UART0
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| rgu::Reset::UART1
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| rgu::Reset::UART2
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| rgu::Reset::UART3
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| rgu::Reset::I2C0
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| rgu::Reset::I2C1
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| rgu::Reset::SSP0
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| rgu::Reset::SSP1
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| rgu::Reset::I2S
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/* Don't reset SPIFI if running from SPIFI memory */
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/*| rgu::Reset::SPIFI*/
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| rgu::Reset::CAN1
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| rgu::Reset::CAN0
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/* Don't reset M0 if that's the core we're running on! */
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/*| rgu::Reset::M0APP */
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| rgu::Reset::SGPIO
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| rgu::Reset::SPI
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);
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}
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} /* namespace one */
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} /* namespace hackrf */
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