Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
EESchema Schematic File Version 4
2017-06-19 22:57:56 +00:00
LIBS:portapack_h1-cache
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
EELAYER 26 0
2017-06-19 22:57:56 +00:00
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
Sheet 5 6
2017-06-19 22:57:56 +00:00
Title "PortaPack H1"
PortaPack Sync, take 2 (#215)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* PCB: Change PCB stackup, Tg, clarify solder mask color, use more metric.
* PCB: Move HackRF header P9 to B.CrtYd layer.
* PCB: Change a Tg reference I missed.
* PCB: Update footprints for parts with mismatched CAD->tape rotation.
Adjust a few layer choice and line thickness bits.
* PCB: Got cold feet, switched back to rectangular pads.
* PCB: Add Eco layers to be visible and Gerber output.
* PCB: Use aux origin for plotting, for tidier coordinates.
* PCB: Output Gerber job file, because why not?
* Schematic: Correct footprints for two reference-related components.
* Schematic: Remove manfuacturer and part number for DNP component.
* Schematic: Specify resistor value, manufacturer, part number for reference oscillator series termination.
* PCB: Update netlist and footprints from schematic.
* Netlist: Updated component values, footprints.
* PCB: Nudge some components and traces to address DRC clearance violations.
* PCB: Allow KiCad to update zone timestamps (again?!).
* PCB: Generate *all* Gerber layers.
* Schematic, PCB: Update revision to 20181025.
* PCB: Adjust fab layer annotations orientation and font size.
* PCB: Hide mounting hole reference designators on silk layer.
* PCB: Shrink U1, U3 pads to get 0.2mm space between pads.
* PCB: Set pad-to-mask clearance to zero, leave up to fab. Set minimum mask web to 0.2mm for non-black options.
* PCB: Revise U1 pad shape, mask, paste, thermal drills.
Clearance is improved at corner pads.
* PCB: Tweak U3 for better thermal pad/drill/mask/paste design.
* PCB: Change solder mask color to blue.
* Schematic, PCB: Update revision to 20181029.
* PCB: Bump minimum mask web down a tiny bit because KiCad is having trouble with math.
* Update schematic
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Clock Manager: Actually store chosen clock reference
Similarly-named local was covering a member and discarding the value.
* Clock Manager: Reference type which contains source, frequency.
* Setup: Display reference source, frequency in frequency correction screen.
* LPC43xx API: Add extern "C" for use from C++.
* Use LPC43xx API for SGPIO, GPDMA, I2S initialization.
* I2S: Add BASE_AUDIO_CLK management.
* Add MOTOCON_PWM clock/reset structure.
* Serial: Fix dumb typos.
* Serial: Remove extra reference operator.
* Serial: Cut-and-paste error in structure type name.
* Move SCU structure from PAL to LPC43xx API.
It'd be nice if I gave some thought to where code should live before I commit it.
* VAA power: Move code to HackRF board file
It doesn't belong in PAL.
* MAX5 CPLD: Add SAMPLE and EXTEST methods.
* Flash image: Change packing scheme to use flash more efficiently.
Application is now a single image for both M4 bootstrap and M0.
Baseband images come immediately after application binary. No need to align to large blocks (and waste lots of flash).
* Clock Manager: Remove PLL1 power down function.
* Move and rename peripherals reset function to board module.
* Remove unused peripheral/clock management.
* Clock Manager: Extract switch to IRC into separate function.
* Clock Manager: More explicit shutdown of clocks, clock generator.
* Move initialization to board module.
* ChibiOS: Rename "application" board, add "baseband" board.
There are now two ChibiOS "boards", one which runs the application and does the hardware setup. The other board, "baseband", does very little setup.
* Clock Manager: Remove unused crystal enable/disable code.
* Clock Manager: Restore clock configuration to SPIFI bootloader state before app shutdown.
* Reset peripherals on app shutdown.
Be careful not to reset M0APP (the core we're running on) or GPIO (which is holding the hardware in a stable state).
* M4/baseband hal_lld_init: use IDIVA, which is configured earlier by M0.
This was causing problems during restart into HackRF mode. Baseband hal_lld_init changed M4 clock from IDIVA (set by M0) to PLL1, which was unceremoniously turned off during shutdown.
* Audio app: Stop audio PLL on shutdown.
* M4 HAL: Make LPC43XX_M4_CLK_SRC optional.
This was changing the BASE_M4_CLK when a baseband was run.
* LPC43xx C++ layer: Fix IDIVx constructor IDIV narrow field width.
* Application board: hide the peripherals_reset function, as it isn't useful except during hardware init.
* Consolidate hardware init code to some degree.
ClockManager is super-overloaded and murky in its purpose.
Migrate audio from IDIVC to IDIVD, to more closely resemble initial clock scheme, so it's simpler to get back to it during shutdown.
* Migrate some startup code to application board.
* Si5351: Use correct methods for reset().
update_output_enable_control() doesn't reset the enabled outputs to the reset state, unless the object is freshly initialized, which it isn't when performing firmware shutdown.
For similar reasons, use set_clock_control() instead of setting internal state and then using the update function.
* GPIO: Set SPIFI CS pin to match input buffer state coming out of bootloader.
* Change application board.c to .cpp, with required dependent changes
* Board: Clean up SCU configuration code/data.
* I2S: Add shutdown code and use it.
* LPC43xx: Consolidate a bunch of structures that had been scattered all over.
...because I'm an undisciplined coder.
* I2S: Fix ordering of branch and base clock disable.
Core was hanging, presumably because the register interface on the branch/peripheral was unresponsive after the base clock was disabled.
* Controls: Save and expose raw navigation wheel switch state
I need to do some work on debouncing and ignoring simultaneous key presses.
* Controls: Add debug view for switches state.
* Controls: Ignore all key presses until all keys are released.
This should address some mechanical quirks of the navigation wheel used on the PortaPack.
* Clock Manager: Wait for only the necessary PLL to lock.
Wasn't working on PortaPacks without a built-in clock reference, as that uses the other PLL.
TODO: Switching PLLs may be kind of pointless now...
* CMake: Pull HackRF project from GitHub and build.
* CMake: Remove commented code.
* CMake: Clone HackRF via HTTPS, not SSH.
* CMake: Extra pause for slow post-DFU firmware boot-up.
* CMake: TODO to fix SVF/XSVF file source.
* CMake: Ask HackRF hackrf_usb to make DFU binary.
* Travis-CI: Add dfu-util, now that HackRF firmware is being built for inclusion.
* Travis-CI: Update build environment to Ubuntu xenial
Previously Trusty.
* Travis-CI: Incorrectly structured my request for dfu-util package.
I'm soooo talented.
* ldscript: Mark flash, ram with correct R/W/X flags.
* ldscript: Enlarge M0 flash region to 1Mbyte, the size of the HackRF SPI flash.
* Receiver: Hide PPM adjustment if clock source is not HackRF crystal.
* Documentation: Update product photos and README.
* Documentation: Add TCXO feature to README description.
* Application: Rearrange files to match HAVOC directory structure.
* Map view in AIS (#213)
* Added GeoMapView to AISRecentEntryDetailView
* Added autoupdate in AIS map
* Revert "Map view in AIS (#213)"
This reverts commit 262c030224b9ea3e56ff1c8a66246e7ecf30e41f.
This commit will be cherry-picked onto a clean branch, then re-committed after a troublesome pull request is reverted.
* Revert "Upstream merge to make new revision of PortaPack work (#206)"
This reverts commit 920b98f7c9a30371b643c42949066fb7d2441daf.
This pull request was missing some changes and was preventing firmware from functioning on older PortaPacks.
* CPLD: Pull bitstream from HackRF project.
* SGPIO: Identify pins on CPLD by their new functions. Pull down HOST_SYNC_EN.
* CPLD: Don't load HackRF CPLD bitstream into RAM.
Trying to converge CPLD implementations, so this shouldn't be necesssary. HOWEVER, it would be good to *check* the CPLD contents and provide a way to update, if necessary.
* CPLD: Tweak clock generator config to match CPLD timing changes in HackRF.
* PinConfig: Drive CPLD pins correctly.
* CMake: Use jboone/hackrf master branch, now that CPLD fixes are there.
* CMake: Fix HackRF CPLD SVF dependency.
Build would break on the first pass, but work if you restarted make.
* CMake: Fix my misuse of the HackRF CMake configuration -- was building from too deep in the directory tree
* CMake: Work-around for CMake 3.5 not supporting ExternalProject_Add SOURCE_SUBDIR.
* CMake: Choose a CMP0005 policy to quiet CMake warnings.
* Settings: Show active clock reference. Only show PPM adjustment for HackRF source.
* Radio Settings: Change reference clock text color.
Make consistent color with other un-editable text.
TODO: This is a bit of a hack to get ui::Text objects to support custom colors, like the Label structures used elsewhere.
2019-02-03 18:25:11 +00:00
Date "2018-10-29"
Rev "20181029"
2017-06-19 22:57:56 +00:00
Comp "ShareBrained Technology, Inc."
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
Comment1 "Copyright © 2014-2018 Jared Boone"
2017-06-19 22:57:56 +00:00
Comment2 "License: GNU General Public License, version 2"
Comment3 ""
Comment4 ""
$EndDescr
Text HLabel 10450 4550 0 60 Output ~ 0
LCD_VBL
$Comp
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
L power:+3V3 #PWR077
2017-06-19 22:57:56 +00:00
U 1 1 58CFF694
P 10550 4450
F 0 "#PWR077" H 10550 4410 30 0001 C CNN
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
F 1 "+3V3" H 10550 4560 30 0000 C CNN
2017-06-19 22:57:56 +00:00
F 2 "" H 10550 4450 60 0000 C CNN
F 3 "" H 10550 4450 60 0000 C CNN
1 10550 4450
1 0 0 -1
$EndComp
Text HLabel 6300 2200 2 60 Output ~ 0
AUDIO_SVDD
Text HLabel 10450 4750 0 60 Output ~ 0
AUDIO_AVDD
Text HLabel 10450 5200 0 60 Output ~ 0
AUDIO_DVDD
Text HLabel 10450 4850 0 60 Output ~ 0
AUDIO_TVDD
$Comp
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
L power:+1V8 #PWR078
2017-06-19 22:57:56 +00:00
U 1 1 58CFF6A8
P 10550 5100
F 0 "#PWR078" H 10550 5240 20 0001 C CNN
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
F 1 "+1V8" H 10550 5210 30 0000 C CNN
2017-06-19 22:57:56 +00:00
F 2 "" H 10550 5100 60 0000 C CNN
F 3 "" H 10550 5100 60 0000 C CNN
1 10550 5100
1 0 0 -1
$EndComp
$Comp
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
L regulator:REGULATOR_SOT23_5 U2
2017-06-19 22:57:56 +00:00
U 1 1 58CFF91A
P 8400 2900
F 0 "U2" H 8400 3150 50 0000 C CNN
F 1 "TCR2EF18,LM(CT" H 8000 2650 50 0000 C CNN
F 2 "ipc_sot:IPC_SOT23-5P95_275X135L40X40N" H 8400 2900 60 0001 C CNN
F 3 "http://toshiba.semicon-storage.com/ap-en/product/linear/power-supply/detail.TCR2EF18.html" H 8400 2900 60 0001 C CNN
F 4 "Toshiba" H 8400 2900 60 0001 C CNN "Mfr"
F 5 "TCR2EF18,LM(CT" H 8400 2900 60 0001 C CNN "Part"
1 8400 2900
1 0 0 -1
$EndComp
$Comp
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
L Device:C C38
2017-06-19 22:57:56 +00:00
U 1 1 58CFF923
P 7500 3100
F 0 "C38" H 7550 3200 50 0000 L CNN
F 1 "10U" H 7550 3000 50 0000 L CNN
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
F 2 "ipc_capc:IPC_CAPC200X125X135L45N" H 7500 3100 60 0001 C CNN
2017-06-19 22:57:56 +00:00
F 3 "" H 7500 3100 60 0000 C CNN
F 4 "Murata" H 7500 3100 60 0001 C CNN "Mfr"
F 5 "GRM21BR61A106KE19" H 7500 3100 60 0001 C CNN "Part"
1 7500 3100
-1 0 0 -1
$EndComp
$Comp
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
L Device:C C40
2017-06-19 22:57:56 +00:00
U 1 1 58CFF92C
P 9300 3100
F 0 "C40" H 9350 3200 50 0000 L CNN
F 1 "10U" H 9350 3000 50 0000 L CNN
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
F 2 "ipc_capc:IPC_CAPC200X125X135L45N" H 9300 3100 60 0001 C CNN
2017-06-19 22:57:56 +00:00
F 3 "" H 9300 3100 60 0000 C CNN
F 4 "Murata" H 9300 3100 60 0001 C CNN "Mfr"
F 5 "GRM21BR61A106KE19" H 9300 3100 60 0001 C CNN "Part"
1 9300 3100
-1 0 0 -1
$EndComp
$Comp
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
L power:GND #PWR079
2017-06-19 22:57:56 +00:00
U 1 1 58CFF933
P 8400 3300
F 0 "#PWR079" H 8400 3300 30 0001 C CNN
F 1 "GND" H 8400 3230 30 0001 C CNN
F 2 "" H 8400 3300 60 0000 C CNN
F 3 "" H 8400 3300 60 0000 C CNN
1 8400 3300
1 0 0 -1
$EndComp
$Comp
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
L power:GND #PWR080
2017-06-19 22:57:56 +00:00
U 1 1 58CFF939
P 7500 3400
F 0 "#PWR080" H 7500 3400 30 0001 C CNN
F 1 "GND" H 7500 3330 30 0001 C CNN
F 2 "" H 7500 3400 60 0000 C CNN
F 3 "" H 7500 3400 60 0000 C CNN
1 7500 3400
1 0 0 -1
$EndComp
$Comp
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
L power:GND #PWR081
2017-06-19 22:57:56 +00:00
U 1 1 58CFF93F
P 9300 3400
F 0 "#PWR081" H 9300 3400 30 0001 C CNN
F 1 "GND" H 9300 3330 30 0001 C CNN
F 2 "" H 9300 3400 60 0000 C CNN
F 3 "" H 9300 3400 60 0000 C CNN
1 9300 3400
1 0 0 -1
$EndComp
$Comp
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
L Device:C C39
2017-06-19 22:57:56 +00:00
U 1 1 58CFF945
P 8900 3300
F 0 "C39" H 8950 3400 50 0000 L CNN
F 1 "R" H 8950 3200 50 0001 L CNN
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
F 2 "ipc_capc:IPC_CAPC160X80X90L35N" H 9100 3300 60 0001 C CNN
2017-06-19 22:57:56 +00:00
F 3 "" H 8900 3300 60 0000 C CNN
F 4 "DNP" H 9000 3200 50 0000 C CNN "DNP"
1 8900 3300
-1 0 0 -1
$EndComp
$Comp
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
L power:GND #PWR082
2017-06-19 22:57:56 +00:00
U 1 1 58CFF94C
P 8900 3600
F 0 "#PWR082" H 8900 3600 30 0001 C CNN
F 1 "GND" H 8900 3530 30 0001 C CNN
F 2 "" H 8900 3600 60 0000 C CNN
F 3 "" H 8900 3600 60 0000 C CNN
1 8900 3600
1 0 0 -1
$EndComp
$Comp
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
L power:+1V8 #PWR083
2017-06-19 22:57:56 +00:00
U 1 1 58CFF952
P 9300 2700
F 0 "#PWR083" H 9300 2840 20 0001 C CNN
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
F 1 "+1V8" H 9300 2810 30 0000 C CNN
2017-06-19 22:57:56 +00:00
F 2 "" H 9300 2700 60 0000 C CNN
F 3 "" H 9300 2700 60 0000 C CNN
1 9300 2700
1 0 0 -1
$EndComp
$Comp
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
L power:+3V3 #PWR084
2017-06-19 22:57:56 +00:00
U 1 1 58CFF958
P 7500 2700
F 0 "#PWR084" H 7500 2660 30 0001 C CNN
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
F 1 "+3V3" H 7500 2810 30 0000 C CNN
2017-06-19 22:57:56 +00:00
F 2 "" H 7500 2700 60 0000 C CNN
F 3 "" H 7500 2700 60 0000 C CNN
1 7500 2700
1 0 0 -1
$EndComp
Text HLabel 2800 2500 0 60 Input ~ 0
VBUS
Text HLabel 2800 3200 0 60 Output ~ 0
VBUSCTRL
Text HLabel 6300 2400 2 60 Output ~ 0
VIN
$Comp
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
L battery:BATTERY BT1
2017-06-19 22:57:56 +00:00
U 1 1 58D008D0
P 9700 1350
F 0 "BT1" V 9600 1200 50 0000 C CNN
F 1 "BATTERY" V 9800 1150 50 0001 C CNN
F 2 "bat_coin:MPD_BU2032SM-BT-G" H 9700 1350 60 0001 C CNN
F 3 "http://www.memoryprotectiondevices.com/datasheets/BU2032SM-BT-GTR-datasheet.pdf" H 9700 1350 60 0001 C CNN
F 4 "MPD" H 9700 1350 60 0001 C CNN "Mfr"
F 5 "BU2032SM-BT-GTR" H 9700 1350 60 0001 C CNN "Part"
1 9700 1350
0 1 1 0
$EndComp
$Comp
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
L power:GND #PWR085
2017-06-19 22:57:56 +00:00
U 1 1 58D008D7
P 9700 1650
F 0 "#PWR085" H 9700 1650 30 0001 C CNN
F 1 "GND" H 9700 1580 30 0001 C CNN
F 2 "" H 9700 1650 60 0000 C CNN
F 3 "" H 9700 1650 60 0000 C CNN
1 9700 1650
1 0 0 -1
$EndComp
$Comp
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
L Device:C C41
2017-06-19 22:57:56 +00:00
U 1 1 58D008E2
P 10200 1350
F 0 "C41" H 10250 1450 50 0000 L CNN
F 1 "10U" H 10250 1250 50 0001 L CNN
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
F 2 "ipc_capc:IPC_CAPC200X125X135L45N" H 10200 1350 60 0001 C CNN
2017-06-19 22:57:56 +00:00
F 3 "" H 10200 1350 60 0000 C CNN
F 4 "Murata" H 10200 1350 60 0001 C CNN "Mfr"
F 5 "GRM21BR61A106KE19" H 10200 1350 60 0001 C CNN "Part"
F 6 "DNP" H 10300 1250 50 0000 C CNN "DNP"
1 10200 1350
-1 0 0 -1
$EndComp
$Comp
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
L power:GND #PWR086
2017-06-19 22:57:56 +00:00
U 1 1 58D008E9
P 10200 1650
F 0 "#PWR086" H 10200 1650 30 0001 C CNN
F 1 "GND" H 10200 1580 30 0001 C CNN
F 2 "" H 10200 1650 60 0000 C CNN
F 3 "" H 10200 1650 60 0000 C CNN
1 10200 1650
1 0 0 -1
$EndComp
Text HLabel 10300 1050 2 60 Output ~ 0
VBAT
$Comp
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
L ti:BQ24075 U6
2017-06-19 22:57:56 +00:00
U 1 1 58F1AA75
P 4500 3100
F 0 "U6" H 4500 3150 60 0000 C CNN
F 1 "BQ24075RGT" H 4500 3050 60 0001 C CNN
F 2 "ipc_qfn:IPC_QFN17P50_300X300X100L40X25T160N" H 4600 3350 60 0001 C CNN
F 3 "http://www.ti.com/lit/ds/symlink/bq24075.pdf" H 4600 3350 60 0001 C CNN
F 4 "Texas Instruments" H 4500 3100 60 0001 C CNN "Mfr"
F 5 "BQ24075RGT" H 4500 3100 60 0001 C CNN "Part"
F 6 "DNP" H 4500 3050 50 0000 C CNN "DNP"
1 4500 3100
1 0 0 -1
$EndComp
$Comp
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
L Device:C C1
2017-06-19 22:57:56 +00:00
U 1 1 58F1AC44
P 3400 2800
F 0 "C1" H 3450 2900 50 0000 L CNN
F 1 "1U" H 3450 2700 50 0001 L CNN
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
F 2 "ipc_capc:IPC_CAPC200X125X135L45N" H 3400 2800 60 0001 C CNN
2017-06-19 22:57:56 +00:00
F 3 "" H 3400 2800 60 0000 C CNN
F 4 "Murata" H 3400 2800 60 0001 C CNN "Mfr"
F 5 "DNP" H 3500 2700 50 0000 C CNN "DNP"
F 6 ">26V" H 3250 2700 50 0000 C CNN "WVDC"
1 3400 2800
-1 0 0 -1
$EndComp
$Comp
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
L power:GND #PWR087
2017-06-19 22:57:56 +00:00
U 1 1 58F1AC96
P 3700 3000
F 0 "#PWR087" H 3700 3000 30 0001 C CNN
F 1 "GND" H 3700 2930 30 0001 C CNN
F 2 "" H 3700 3000 60 0000 C CNN
F 3 "" H 3700 3000 60 0000 C CNN
1 3700 3000
0 1 1 0
$EndComp
$Comp
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
L power:GND #PWR088
2017-06-19 22:57:56 +00:00
U 1 1 58F1ACB9
P 3700 3100
F 0 "#PWR088" H 3700 3100 30 0001 C CNN
F 1 "GND" H 3700 3030 30 0001 C CNN
F 2 "" H 3700 3100 60 0000 C CNN
F 3 "" H 3700 3100 60 0000 C CNN
1 3700 3100
0 1 1 0
$EndComp
$Comp
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
L power:GND #PWR089
2017-06-19 22:57:56 +00:00
U 1 1 58F1AD43
P 3400 3100
F 0 "#PWR089" H 3400 3100 30 0001 C CNN
F 1 "GND" H 3400 3030 30 0001 C CNN
F 2 "" H 3400 3100 60 0000 C CNN
F 3 "" H 3400 3100 60 0000 C CNN
1 3400 3100
1 0 0 -1
$EndComp
$Comp
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
L Device:C C16
2017-06-19 22:57:56 +00:00
U 1 1 58F1AE50
P 5600 2700
F 0 "C16" H 5650 2800 50 0000 L CNN
F 1 "4U7" H 5650 2600 50 0001 L CNN
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
F 2 "ipc_capc:IPC_CAPC200X125X135L45N" H 5600 2700 60 0001 C CNN
2017-06-19 22:57:56 +00:00
F 3 "" H 5600 2700 60 0000 C CNN
F 4 "Murata" H 5600 2700 60 0001 C CNN "Mfr"
F 5 "DNP" H 5700 2600 50 0000 C CNN "DNP"
1 5600 2700
-1 0 0 -1
$EndComp
$Comp
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
L power:GND #PWR090
2017-06-19 22:57:56 +00:00
U 1 1 58F1AEB9
P 5600 3000
F 0 "#PWR090" H 5600 3000 30 0001 C CNN
F 1 "GND" H 5600 2930 30 0001 C CNN
F 2 "" H 5600 3000 60 0000 C CNN
F 3 "" H 5600 3000 60 0000 C CNN
1 5600 3000
1 0 0 -1
$EndComp
$Comp
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
L Device:C C15
2017-06-19 22:57:56 +00:00
U 1 1 58F1B1AB
P 3500 4000
F 0 "C15" H 3550 4100 50 0000 L CNN
F 1 "4U7" H 3550 3900 50 0001 L CNN
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
F 2 "ipc_capc:IPC_CAPC200X125X135L45N" H 3500 4000 60 0001 C CNN
2017-06-19 22:57:56 +00:00
F 3 "" H 3500 4000 60 0000 C CNN
F 4 "Murata" H 3500 4000 60 0001 C CNN "Mfr"
F 5 "DNP" H 3600 3900 50 0000 C CNN "DNP"
1 3500 4000
-1 0 0 -1
$EndComp
$Comp
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
L power:GND #PWR091
2017-06-19 22:57:56 +00:00
U 1 1 58F1B4E6
P 3500 4300
F 0 "#PWR091" H 3500 4300 30 0001 C CNN
F 1 "GND" H 3500 4230 30 0001 C CNN
F 2 "" H 3500 4300 60 0000 C CNN
F 3 "" H 3500 4300 60 0000 C CNN
1 3500 4300
1 0 0 -1
$EndComp
Wire Wire Line
10450 4550 10550 4550
Wire Wire Line
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
10550 4450 10550 4550
2017-06-19 22:57:56 +00:00
Wire Wire Line
10550 4750 10450 4750
Connection ~ 10550 4550
Wire Wire Line
10550 4850 10450 4850
Connection ~ 10550 4750
Wire Wire Line
10450 5200 10550 5200
Wire Wire Line
10550 5200 10550 5100
Connection ~ 7900 2800
Wire Wire Line
7900 3000 7900 2800
Wire Wire Line
8000 3000 7900 3000
Connection ~ 7500 2800
Wire Wire Line
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
7500 2700 7500 2800
2017-06-19 22:57:56 +00:00
Wire Wire Line
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
7500 2800 7900 2800
2017-06-19 22:57:56 +00:00
Connection ~ 9300 2800
Wire Wire Line
8800 3000 8900 3000
Wire Wire Line
8400 3200 8400 3300
Wire Wire Line
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
9300 2700 9300 2800
2017-06-19 22:57:56 +00:00
Wire Wire Line
8800 2800 9300 2800
Wire Wire Line
9700 1550 9700 1650
Wire Wire Line
9700 1050 9700 1150
Wire Wire Line
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
9700 1050 10200 1050
2017-06-19 22:57:56 +00:00
Connection ~ 10200 1050
Wire Wire Line
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
2800 2500 3000 2500
2017-06-19 22:57:56 +00:00
Wire Wire Line
3800 3000 3700 3000
Wire Wire Line
3800 3100 3700 3100
Connection ~ 3400 2500
Wire Wire Line
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
5200 2400 5300 2400
2017-06-19 22:57:56 +00:00
Wire Wire Line
5300 2500 5200 2500
Wire Wire Line
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
5300 800 5300 2400
2017-06-19 22:57:56 +00:00
Connection ~ 5300 2400
Connection ~ 5600 2400
Wire Wire Line
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
2900 3700 3500 3700
2017-06-19 22:57:56 +00:00
Wire Wire Line
3800 3600 3700 3600
Wire Wire Line
3700 3600 3700 3700
Connection ~ 3700 3700
$Comp
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
L Device:R R1
2017-06-19 22:57:56 +00:00
U 1 1 58F1CB6B
P 4200 4550
F 0 "R1" V 4280 4550 50 0000 C CNN
F 1 "R" V 4200 4550 50 0001 C CNN
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
F 2 "ipc_resc:IPC_RESC100X50X40L25N" H 4200 4550 60 0001 C CNN
2017-06-19 22:57:56 +00:00
F 3 "" H 4200 4550 60 0000 C CNN
F 4 "Yageo" V 4200 4550 60 0001 C CNN "Mfr"
F 5 "DNP" V 4200 4550 50 0000 C CNN "DNP"
1 4200 4550
-1 0 0 -1
$EndComp
$Comp
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
L Device:R R4
2017-06-19 22:57:56 +00:00
U 1 1 58F1CBFA
P 4500 4550
F 0 "R4" V 4580 4550 50 0000 C CNN
F 1 "1K91" V 4500 4550 50 0001 C CNN
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
F 2 "ipc_resc:IPC_RESC100X50X40L25N" H 4500 4550 60 0001 C CNN
2017-06-19 22:57:56 +00:00
F 3 "" H 4500 4550 60 0000 C CNN
F 4 "Yageo" V 4500 4550 60 0001 C CNN "Mfr"
F 5 "DNP" V 4500 4550 50 0000 C CNN "DNP"
1 4500 4550
-1 0 0 -1
$EndComp
$Comp
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
L Device:R R6
2017-06-19 22:57:56 +00:00
U 1 1 58F1CC38
P 4800 4550
F 0 "R6" V 4880 4550 50 0000 C CNN
F 1 "1K8" V 4800 4550 50 0001 C CNN
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
F 2 "ipc_resc:IPC_RESC100X50X40L25N" H 4800 4550 60 0001 C CNN
2017-06-19 22:57:56 +00:00
F 3 "" H 4800 4550 60 0000 C CNN
F 4 "Yageo" V 4800 4550 60 0001 C CNN "Mfr"
F 5 "DNP" V 4800 4550 50 0000 C CNN "DNP"
1 4800 4550
-1 0 0 -1
$EndComp
$Comp
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
L power:GND #PWR092
2017-06-19 22:57:56 +00:00
U 1 1 58F1CC76
P 4800 4900
F 0 "#PWR092" H 4800 4900 30 0001 C CNN
F 1 "GND" H 4800 4830 30 0001 C CNN
F 2 "" H 4800 4900 60 0000 C CNN
F 3 "" H 4800 4900 60 0000 C CNN
1 4800 4900
1 0 0 -1
$EndComp
$Comp
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
L power:GND #PWR093
2017-06-19 22:57:56 +00:00
U 1 1 58F1CCA8
P 4500 4900
F 0 "#PWR093" H 4500 4900 30 0001 C CNN
F 1 "GND" H 4500 4830 30 0001 C CNN
F 2 "" H 4500 4900 60 0000 C CNN
F 3 "" H 4500 4900 60 0000 C CNN
1 4500 4900
1 0 0 -1
$EndComp
$Comp
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
L power:GND #PWR094
2017-06-19 22:57:56 +00:00
U 1 1 58F1CCDA
P 4200 4900
F 0 "#PWR094" H 4200 4900 30 0001 C CNN
F 1 "GND" H 4200 4830 30 0001 C CNN
F 2 "" H 4200 4900 60 0000 C CNN
F 3 "" H 4200 4900 60 0000 C CNN
1 4200 4900
1 0 0 -1
$EndComp
$Comp
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
L Device:R R3
2017-06-19 22:57:56 +00:00
U 1 1 58F1D0EB
P 4300 1150
F 0 "R3" V 4380 1150 50 0000 C CNN
F 1 "1K5" V 4300 1150 50 0001 C CNN
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
F 2 "ipc_resc:IPC_RESC100X50X40L25N" H 4300 1150 60 0001 C CNN
2017-06-19 22:57:56 +00:00
F 3 "" H 4300 1150 60 0000 C CNN
F 4 "Yageo" V 4300 1150 60 0001 C CNN "Mfr"
F 5 "DNP" V 4300 1150 50 0000 C CNN "DNP"
1 4300 1150
-1 0 0 -1
$EndComp
$Comp
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
L Device:R R5
2017-06-19 22:57:56 +00:00
U 1 1 58F1D207
P 4700 1150
F 0 "R5" V 4780 1150 50 0000 C CNN
F 1 "1K5" V 4700 1150 50 0001 C CNN
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
F 2 "ipc_resc:IPC_RESC100X50X40L25N" H 4700 1150 60 0001 C CNN
2017-06-19 22:57:56 +00:00
F 3 "" H 4700 1150 60 0000 C CNN
F 4 "Yageo" V 4700 1150 60 0001 C CNN "Mfr"
F 5 "DNP" V 4700 1150 50 0000 C CNN "DNP"
1 4700 1150
-1 0 0 -1
$EndComp
Wire Wire Line
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
4300 800 4700 800
2017-06-19 22:57:56 +00:00
Connection ~ 4700 800
Wire Wire Line
6300 2200 6100 2200
$Comp
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
L header:HEADER_1X2 J4
2017-06-19 22:57:56 +00:00
U 1 1 58F1DD77
P 2600 3750
F 0 "J4" H 2600 3950 60 0000 C CNN
F 1 "HEADER_1X2" H 2600 3550 60 0001 C CNN
F 2 "jst:JST_S2B-PH-SM4-TB" H 2600 3550 60 0001 C CNN
F 3 "http://www.jst-mfg.com/product/pdf/eng/ePH.pdf" H 2600 3550 60 0001 C CNN
F 4 "JST" H 2600 3750 60 0001 C CNN "Mfr"
F 5 "S2B-PH-SM4-TB" H 2600 3750 60 0001 C CNN "Part"
F 6 "DNP" H 2600 3750 50 0000 C CNN "DNP"
1 2600 3750
-1 0 0 -1
$EndComp
$Comp
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
L Device:R R8
2017-06-19 22:57:56 +00:00
U 1 1 58F1E372
P 3450 3400
F 0 "R8" V 3530 3400 50 0000 C CNN
F 1 "10K" V 3450 3400 50 0001 C CNN
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
F 2 "ipc_resc:IPC_RESC100X50X40L25N" H 3450 3400 60 0001 C CNN
2017-06-19 22:57:56 +00:00
F 3 "" H 3450 3400 60 0000 C CNN
F 4 "Yageo" V 3450 3400 60 0001 C CNN "Mfr"
F 5 "DNP" V 3450 3400 50 0000 C CNN "DNP"
1 3450 3400
0 1 -1 0
$EndComp
Connection ~ 3500 3700
$Comp
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
L power:GND #PWR095
2017-06-19 22:57:56 +00:00
U 1 1 58F1E667
P 3000 3900
F 0 "#PWR095" H 3000 3900 30 0001 C CNN
F 1 "GND" H 3000 3830 30 0001 C CNN
F 2 "" H 3000 3900 60 0000 C CNN
F 3 "" H 3000 3900 60 0000 C CNN
1 3000 3900
1 0 0 -1
$EndComp
Wire Wire Line
2900 3800 3000 3800
Wire Wire Line
3000 3800 3000 3900
$Comp
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
L power:GND #PWR096
2017-06-19 22:57:56 +00:00
U 1 1 58F1EA88
P 3100 3400
F 0 "#PWR096" H 3100 3400 30 0001 C CNN
F 1 "GND" H 3100 3330 30 0001 C CNN
F 2 "" H 3100 3400 60 0000 C CNN
F 3 "" H 3100 3400 60 0000 C CNN
1 3100 3400
0 1 1 0
$EndComp
Wire Wire Line
6100 2200 6100 2400
Connection ~ 6100 2400
$Comp
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
L Device:R R7
2017-06-19 22:57:56 +00:00
U 1 1 58F1F0EF
P 3000 2850
F 0 "R7" V 3080 2850 50 0000 C CNN
F 1 "0R" V 3000 2850 50 0001 C CNN
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
F 2 "ipc_resc:IPC_RESC100X50X40L25N" H 3000 2850 60 0001 C CNN
2017-06-19 22:57:56 +00:00
F 3 "" H 3000 2850 60 0000 C CNN
F 4 "Yageo" V 3000 2850 60 0001 C CNN "Mfr"
F 5 "DNP" V 3000 2850 50 0000 C CNN "DNP"
1 3000 2850
-1 0 0 -1
$EndComp
Wire Wire Line
2800 3200 3000 3200
Connection ~ 3000 2500
$Comp
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
L Device:R R9
2017-06-19 22:57:56 +00:00
U 1 1 58F443CF
P 5300 4050
F 0 "R9" V 5380 4050 50 0000 C CNN
F 1 "10K" V 5300 4050 50 0001 C CNN
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
F 2 "ipc_resc:IPC_RESC100X50X40L25N" H 5300 4050 60 0001 C CNN
2017-06-19 22:57:56 +00:00
F 3 "" H 5300 4050 60 0000 C CNN
F 4 "Yageo" V 5300 4050 60 0001 C CNN "Mfr"
F 5 "DNP" V 5300 4050 50 0000 C CNN "DNP"
1 5300 4050
-1 0 0 -1
$EndComp
$Comp
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
L power:GND #PWR097
2017-06-19 22:57:56 +00:00
U 1 1 58F4443F
P 5300 4400
F 0 "#PWR097" H 5300 4400 30 0001 C CNN
F 1 "GND" H 5300 4330 30 0001 C CNN
F 2 "" H 5300 4400 60 0000 C CNN
F 3 "" H 5300 4400 60 0000 C CNN
1 5300 4400
1 0 0 -1
$EndComp
Wire Wire Line
5200 3700 5300 3700
$Comp
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
L Device:R R10
2017-06-19 22:57:56 +00:00
U 1 1 58F44562
P 5500 4050
F 0 "R10" V 5580 4050 50 0000 C CNN
F 1 "10K" V 5500 4050 50 0001 C CNN
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
F 2 "ipc_resc:IPC_RESC100X50X40L25N" H 5500 4050 60 0001 C CNN
2017-06-19 22:57:56 +00:00
F 3 "" H 5500 4050 60 0000 C CNN
F 4 "Yageo" V 5500 4050 60 0001 C CNN "Mfr"
F 5 "DNP" V 5500 4050 50 0000 C CNN "DNP"
1 5500 4050
-1 0 0 -1
$EndComp
$Comp
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
L power:GND #PWR098
2017-06-19 22:57:56 +00:00
U 1 1 58F445B7
P 5500 4400
F 0 "#PWR098" H 5500 4400 30 0001 C CNN
F 1 "GND" H 5500 4330 30 0001 C CNN
F 2 "" H 5500 4400 60 0000 C CNN
F 3 "" H 5500 4400 60 0000 C CNN
1 5500 4400
1 0 0 -1
$EndComp
Wire Wire Line
5200 3600 5500 3600
$Comp
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
L Device:R R14
2017-06-19 22:57:56 +00:00
U 1 1 58F44903
P 5900 3750
F 0 "R14" V 5980 3750 50 0000 C CNN
F 1 "10K" V 5900 3750 50 0001 C CNN
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
F 2 "ipc_resc:IPC_RESC100X50X40L25N" H 5900 3750 60 0001 C CNN
2017-06-19 22:57:56 +00:00
F 3 "" H 5900 3750 60 0000 C CNN
F 4 "Yageo" V 5900 3750 60 0001 C CNN "Mfr"
F 5 "DNP" V 5900 3750 50 0000 C CNN "DNP"
1 5900 3750
-1 0 0 -1
$EndComp
$Comp
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
L Device:R R13
2017-06-19 22:57:56 +00:00
U 1 1 58F4495E
P 5900 2950
F 0 "R13" V 5980 2950 50 0000 C CNN
F 1 "10K" V 5900 2950 50 0001 C CNN
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
F 2 "ipc_resc:IPC_RESC100X50X40L25N" H 5900 2950 60 0001 C CNN
2017-06-19 22:57:56 +00:00
F 3 "" H 5900 2950 60 0000 C CNN
F 4 "Yageo" V 5900 2950 60 0001 C CNN "Mfr"
F 5 "DNP" V 5900 2950 50 0000 C CNN "DNP"
1 5900 2950
-1 0 0 -1
$EndComp
Wire Wire Line
5200 3300 5900 3300
Wire Wire Line
5200 3400 5900 3400
$Comp
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
L power:GND #PWR099
2017-06-19 22:57:56 +00:00
U 1 1 58F44AF6
P 5900 4100
F 0 "#PWR099" H 5900 4100 30 0001 C CNN
F 1 "GND" H 5900 4030 30 0001 C CNN
F 2 "" H 5900 4100 60 0000 C CNN
F 3 "" H 5900 4100 60 0000 C CNN
1 5900 4100
1 0 0 -1
$EndComp
Connection ~ 5900 2400
$Comp
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
L diode:LED D1
2017-06-19 22:57:56 +00:00
U 1 1 58F5B932
P 4300 1700
AR Path="/58F5B932" Ref="D1" Part="1"
AR Path="/58CFF3E3/58F5B932" Ref="D1" Part="1"
F 0 "D1" H 4300 1800 50 0000 C CNN
F 1 "LED 0603 green" H 4300 1600 50 0001 C CNN
F 2 "ipc_ledc:IPC_LEDC1608X90L40N" H 4300 1700 60 0001 C CNN
F 3 "" H 4300 1700 60 0000 C CNN
F 4 "Kingbright" H 4300 1700 60 0001 C CNN "Mfr"
F 5 "APT1608SGC" H 4300 1700 60 0001 C CNN "Part"
F 6 "DNP" H 4300 1600 50 0000 C CNN "DNP"
1 4300 1700
0 -1 1 0
$EndComp
$Comp
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
L diode:LED D2
2017-06-19 22:57:56 +00:00
U 1 1 58F5BA0B
P 4700 1700
AR Path="/58F5BA0B" Ref="D2" Part="1"
AR Path="/58CFF3E3/58F5BA0B" Ref="D2" Part="1"
F 0 "D2" H 4700 1800 50 0000 C CNN
F 1 "LED 0603 yellow" H 4700 1600 50 0001 C CNN
F 2 "ipc_ledc:IPC_LEDC1608X90L40N" H 4700 1700 60 0001 C CNN
F 3 "" H 4700 1700 60 0000 C CNN
F 4 "Kingbright" H 4700 1700 60 0001 C CNN "Mfr"
F 5 "APT1608SYCK" H 4700 1700 60 0001 C CNN "Part"
F 6 "DNP" H 4700 1600 50 0000 C CNN "DNP"
1 4700 1700
0 -1 1 0
$EndComp
Wire Wire Line
4700 2000 4700 1900
Wire Wire Line
4300 2000 4300 1900
Text Label 3100 3700 0 60 ~ 0
BBAT
Text Notes 1200 4700 0 60 ~ 0
TODO:\n\nV(ISET) indicates charge current. Monitor w/ADC.\nR3,R5=100K, remove LEDs, if monitoring status w/GPIOs.
Text Notes 5100 5200 0 60 ~ 0
ISET (fast charge current) R6=1K8 (~~500mA).\n\nR4 is required, otherwise no charging.\nILIM (input limit) R4=1K8 (~~850mA).\n\nTMR=open for default timer values.
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
Wire Wire Line
10550 4550 10550 4650
Wire Wire Line
10550 4750 10550 4850
Wire Wire Line
7900 2800 8000 2800
Wire Wire Line
10200 1050 10300 1050
Wire Wire Line
3400 2500 3800 2500
Wire Wire Line
5300 2400 5600 2400
Wire Wire Line
5300 2400 5300 2500
Wire Wire Line
5600 2400 5900 2400
Wire Wire Line
3700 3700 3800 3700
Wire Wire Line
4700 800 5300 800
Wire Wire Line
3500 3700 3700 3700
Wire Wire Line
6100 2400 6300 2400
Wire Wire Line
3000 2500 3400 2500
Wire Wire Line
5900 2400 6100 2400
Wire Wire Line
3000 2500 3000 2700
Wire Wire Line
3000 3000 3000 3200
Wire Wire Line
3400 2950 3400 3100
Wire Wire Line
3400 2500 3400 2650
Wire Wire Line
3500 3700 3500 3850
Wire Wire Line
3500 4150 3500 4300
Wire Wire Line
4200 4200 4200 4400
Wire Wire Line
4200 4700 4200 4900
Wire Wire Line
4500 4700 4500 4900
Wire Wire Line
4500 4200 4500 4400
Wire Wire Line
4800 4200 4800 4400
Wire Wire Line
4800 4700 4800 4900
Wire Wire Line
5300 4200 5300 4400
Wire Wire Line
5500 4200 5500 4400
Wire Wire Line
5300 3700 5300 3900
Wire Wire Line
5500 3600 5500 3900
Wire Wire Line
5900 3900 5900 4100
Wire Wire Line
5900 3400 5900 3600
Wire Wire Line
5900 3100 5900 3300
Wire Wire Line
5600 2850 5600 3000
Wire Wire Line
5600 2400 5600 2550
Wire Wire Line
5900 2400 5900 2800
Wire Wire Line
4700 1300 4700 1500
Wire Wire Line
4300 1300 4300 1500
Wire Wire Line
4300 800 4300 1000
Wire Wire Line
4700 800 4700 1000
Wire Wire Line
3100 3400 3300 3400
Wire Wire Line
3600 3400 3800 3400
Wire Wire Line
7500 2800 7500 2950
Wire Wire Line
7500 3250 7500 3400
Wire Wire Line
8900 3450 8900 3600
Wire Wire Line
8900 3000 8900 3150
Wire Wire Line
9300 2800 9300 2950
Wire Wire Line
9300 3250 9300 3400
Wire Wire Line
10200 1050 10200 1200
Wire Wire Line
10200 1500 10200 1650
$Comp
L osc:OSC4 X?
U 1 1 5B682C80
P 1900 6500
AR Path="/53A8C780/5B682C80" Ref="X?" Part="1"
AR Path="/58CFF3E3/5B682C80" Ref="X1" Part="1"
F 0 "X1" H 1600 6850 60 0000 L CNN
F 1 "10.00000M" H 2500 6150 60 0000 R CNN
F 2 "ipc_osccc:IPC_OSCCC320X250X110L75X100N" H 1900 6500 60 0001 C CNN
F 3 "" H 1900 6500 60 0000 C CNN
F 4 "Jauch" H 1900 6500 50 0001 C CNN "Mfr"
F 5 "O 10.0-JT32C-A-K-3.3-LF" H 1900 6500 50 0001 C CNN "Part"
1 1900 6500
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR?
U 1 1 5B682C87
P 1900 7100
AR Path="/53A8C780/5B682C87" Ref="#PWR?" Part="1"
AR Path="/58CFF3E3/5B682C87" Ref="#PWR0103" Part="1"
F 0 "#PWR0103" H 1900 7100 30 0001 C CNN
F 1 "GND" H 1900 7030 30 0001 C CNN
F 2 "" H 1900 7100 60 0000 C CNN
F 3 "" H 1900 7100 60 0000 C CNN
1 1900 7100
1 0 0 -1
$EndComp
Wire Wire Line
1900 7000 1900 7100
Wire Wire Line
1900 5800 1900 5900
$Comp
L Device:C C?
U 1 1 5B682C91
P 2150 5900
AR Path="/53A8C780/5B682C91" Ref="C?" Part="1"
AR Path="/58CFF3E3/5B682C91" Ref="C9" Part="1"
F 0 "C9" H 2200 6000 50 0000 L CNN
F 1 "100N" H 2200 5800 50 0000 L CNN
F 2 "ipc_capc:IPC_CAPC100X50X55L25N" H 2150 5900 60 0001 C CNN
F 3 "" H 2150 5900 60 0000 C CNN
F 4 "Murata" H 2150 5900 60 0001 C CNN "Mfr"
F 5 "GRM155R61A104KA01" H 2150 5900 60 0001 C CNN "Part"
1 2150 5900
0 -1 -1 0
$EndComp
Wire Wire Line
1900 5900 2000 5900
Connection ~ 1900 5900
Wire Wire Line
1900 5900 1900 6000
$Comp
L power:GND #PWR?
U 1 1 5B682C9B
P 2400 5900
AR Path="/53A8C780/5B682C9B" Ref="#PWR?" Part="1"
AR Path="/58CFF3E3/5B682C9B" Ref="#PWR0104" Part="1"
F 0 "#PWR0104" H 2400 5900 30 0001 C CNN
F 1 "GND" H 2400 5830 30 0001 C CNN
F 2 "" H 2400 5900 60 0000 C CNN
F 3 "" H 2400 5900 60 0000 C CNN
1 2400 5900
0 -1 -1 0
$EndComp
Wire Wire Line
2300 5900 2400 5900
$Comp
L Device:R R?
U 1 1 5B682CA2
P 4150 6500
AR Path="/53A8C780/5B682CA2" Ref="R?" Part="1"
AR Path="/58CFF3E3/5B682CA2" Ref="R22" Part="1"
F 0 "R22" V 4050 6500 50 0000 C CNN
F 1 "33R" V 4034 6500 50 0001 C CNN
PortaPack Sync, take 2 (#215)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* PCB: Change PCB stackup, Tg, clarify solder mask color, use more metric.
* PCB: Move HackRF header P9 to B.CrtYd layer.
* PCB: Change a Tg reference I missed.
* PCB: Update footprints for parts with mismatched CAD->tape rotation.
Adjust a few layer choice and line thickness bits.
* PCB: Got cold feet, switched back to rectangular pads.
* PCB: Add Eco layers to be visible and Gerber output.
* PCB: Use aux origin for plotting, for tidier coordinates.
* PCB: Output Gerber job file, because why not?
* Schematic: Correct footprints for two reference-related components.
* Schematic: Remove manfuacturer and part number for DNP component.
* Schematic: Specify resistor value, manufacturer, part number for reference oscillator series termination.
* PCB: Update netlist and footprints from schematic.
* Netlist: Updated component values, footprints.
* PCB: Nudge some components and traces to address DRC clearance violations.
* PCB: Allow KiCad to update zone timestamps (again?!).
* PCB: Generate *all* Gerber layers.
* Schematic, PCB: Update revision to 20181025.
* PCB: Adjust fab layer annotations orientation and font size.
* PCB: Hide mounting hole reference designators on silk layer.
* PCB: Shrink U1, U3 pads to get 0.2mm space between pads.
* PCB: Set pad-to-mask clearance to zero, leave up to fab. Set minimum mask web to 0.2mm for non-black options.
* PCB: Revise U1 pad shape, mask, paste, thermal drills.
Clearance is improved at corner pads.
* PCB: Tweak U3 for better thermal pad/drill/mask/paste design.
* PCB: Change solder mask color to blue.
* Schematic, PCB: Update revision to 20181029.
* PCB: Bump minimum mask web down a tiny bit because KiCad is having trouble with math.
* Update schematic
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Clock Manager: Actually store chosen clock reference
Similarly-named local was covering a member and discarding the value.
* Clock Manager: Reference type which contains source, frequency.
* Setup: Display reference source, frequency in frequency correction screen.
* LPC43xx API: Add extern "C" for use from C++.
* Use LPC43xx API for SGPIO, GPDMA, I2S initialization.
* I2S: Add BASE_AUDIO_CLK management.
* Add MOTOCON_PWM clock/reset structure.
* Serial: Fix dumb typos.
* Serial: Remove extra reference operator.
* Serial: Cut-and-paste error in structure type name.
* Move SCU structure from PAL to LPC43xx API.
It'd be nice if I gave some thought to where code should live before I commit it.
* VAA power: Move code to HackRF board file
It doesn't belong in PAL.
* MAX5 CPLD: Add SAMPLE and EXTEST methods.
* Flash image: Change packing scheme to use flash more efficiently.
Application is now a single image for both M4 bootstrap and M0.
Baseband images come immediately after application binary. No need to align to large blocks (and waste lots of flash).
* Clock Manager: Remove PLL1 power down function.
* Move and rename peripherals reset function to board module.
* Remove unused peripheral/clock management.
* Clock Manager: Extract switch to IRC into separate function.
* Clock Manager: More explicit shutdown of clocks, clock generator.
* Move initialization to board module.
* ChibiOS: Rename "application" board, add "baseband" board.
There are now two ChibiOS "boards", one which runs the application and does the hardware setup. The other board, "baseband", does very little setup.
* Clock Manager: Remove unused crystal enable/disable code.
* Clock Manager: Restore clock configuration to SPIFI bootloader state before app shutdown.
* Reset peripherals on app shutdown.
Be careful not to reset M0APP (the core we're running on) or GPIO (which is holding the hardware in a stable state).
* M4/baseband hal_lld_init: use IDIVA, which is configured earlier by M0.
This was causing problems during restart into HackRF mode. Baseband hal_lld_init changed M4 clock from IDIVA (set by M0) to PLL1, which was unceremoniously turned off during shutdown.
* Audio app: Stop audio PLL on shutdown.
* M4 HAL: Make LPC43XX_M4_CLK_SRC optional.
This was changing the BASE_M4_CLK when a baseband was run.
* LPC43xx C++ layer: Fix IDIVx constructor IDIV narrow field width.
* Application board: hide the peripherals_reset function, as it isn't useful except during hardware init.
* Consolidate hardware init code to some degree.
ClockManager is super-overloaded and murky in its purpose.
Migrate audio from IDIVC to IDIVD, to more closely resemble initial clock scheme, so it's simpler to get back to it during shutdown.
* Migrate some startup code to application board.
* Si5351: Use correct methods for reset().
update_output_enable_control() doesn't reset the enabled outputs to the reset state, unless the object is freshly initialized, which it isn't when performing firmware shutdown.
For similar reasons, use set_clock_control() instead of setting internal state and then using the update function.
* GPIO: Set SPIFI CS pin to match input buffer state coming out of bootloader.
* Change application board.c to .cpp, with required dependent changes
* Board: Clean up SCU configuration code/data.
* I2S: Add shutdown code and use it.
* LPC43xx: Consolidate a bunch of structures that had been scattered all over.
...because I'm an undisciplined coder.
* I2S: Fix ordering of branch and base clock disable.
Core was hanging, presumably because the register interface on the branch/peripheral was unresponsive after the base clock was disabled.
* Controls: Save and expose raw navigation wheel switch state
I need to do some work on debouncing and ignoring simultaneous key presses.
* Controls: Add debug view for switches state.
* Controls: Ignore all key presses until all keys are released.
This should address some mechanical quirks of the navigation wheel used on the PortaPack.
* Clock Manager: Wait for only the necessary PLL to lock.
Wasn't working on PortaPacks without a built-in clock reference, as that uses the other PLL.
TODO: Switching PLLs may be kind of pointless now...
* CMake: Pull HackRF project from GitHub and build.
* CMake: Remove commented code.
* CMake: Clone HackRF via HTTPS, not SSH.
* CMake: Extra pause for slow post-DFU firmware boot-up.
* CMake: TODO to fix SVF/XSVF file source.
* CMake: Ask HackRF hackrf_usb to make DFU binary.
* Travis-CI: Add dfu-util, now that HackRF firmware is being built for inclusion.
* Travis-CI: Update build environment to Ubuntu xenial
Previously Trusty.
* Travis-CI: Incorrectly structured my request for dfu-util package.
I'm soooo talented.
* ldscript: Mark flash, ram with correct R/W/X flags.
* ldscript: Enlarge M0 flash region to 1Mbyte, the size of the HackRF SPI flash.
* Receiver: Hide PPM adjustment if clock source is not HackRF crystal.
* Documentation: Update product photos and README.
* Documentation: Add TCXO feature to README description.
* Application: Rearrange files to match HAVOC directory structure.
* Map view in AIS (#213)
* Added GeoMapView to AISRecentEntryDetailView
* Added autoupdate in AIS map
* Revert "Map view in AIS (#213)"
This reverts commit 262c030224b9ea3e56ff1c8a66246e7ecf30e41f.
This commit will be cherry-picked onto a clean branch, then re-committed after a troublesome pull request is reverted.
* Revert "Upstream merge to make new revision of PortaPack work (#206)"
This reverts commit 920b98f7c9a30371b643c42949066fb7d2441daf.
This pull request was missing some changes and was preventing firmware from functioning on older PortaPacks.
* CPLD: Pull bitstream from HackRF project.
* SGPIO: Identify pins on CPLD by their new functions. Pull down HOST_SYNC_EN.
* CPLD: Don't load HackRF CPLD bitstream into RAM.
Trying to converge CPLD implementations, so this shouldn't be necesssary. HOWEVER, it would be good to *check* the CPLD contents and provide a way to update, if necessary.
* CPLD: Tweak clock generator config to match CPLD timing changes in HackRF.
* PinConfig: Drive CPLD pins correctly.
* CMake: Use jboone/hackrf master branch, now that CPLD fixes are there.
* CMake: Fix HackRF CPLD SVF dependency.
Build would break on the first pass, but work if you restarted make.
* CMake: Fix my misuse of the HackRF CMake configuration -- was building from too deep in the directory tree
* CMake: Work-around for CMake 3.5 not supporting ExternalProject_Add SOURCE_SUBDIR.
* CMake: Choose a CMP0005 policy to quiet CMake warnings.
* Settings: Show active clock reference. Only show PPM adjustment for HackRF source.
* Radio Settings: Change reference clock text color.
Make consistent color with other un-editable text.
TODO: This is a bit of a hack to get ui::Text objects to support custom colors, like the Label structures used elsewhere.
2019-02-03 18:25:11 +00:00
F 2 "ipc_resc:IPC_RESC100X50X40L25N" V 4080 6500 50 0001 C CNN
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
F 3 "~" H 4150 6500 50 0001 C CNN
F 4 "DNP" V 4150 6500 50 0000 C CNN "DNP"
1 4150 6500
0 1 1 0
$EndComp
$Comp
L Device:R R?
U 1 1 5B682CA9
P 3550 6900
AR Path="/53A8C780/5B682CA9" Ref="R?" Part="1"
AR Path="/58CFF3E3/5B682CA9" Ref="R17" Part="1"
F 0 "R17" V 3450 6900 50 0000 C CNN
F 1 "1M" V 3434 6900 50 0001 C CNN
F 2 "ipc_resc:IPC_RESC100X50X40L25N" V 3480 6900 50 0001 C CNN
F 3 "~" H 3550 6900 50 0001 C CNN
F 4 "DNP" V 3550 6900 50 0000 C CNN "DNP"
1 3550 6900
0 1 1 0
$EndComp
Wire Wire Line
3200 6500 3200 6900
Wire Wire Line
3200 6900 3400 6900
Wire Wire Line
3200 6500 3350 6500
Wire Wire Line
3700 6900 3900 6900
Wire Wire Line
3900 6900 3900 6500
Connection ~ 3900 6500
Wire Wire Line
3900 6500 4000 6500
Connection ~ 3200 6500
Wire Wire Line
2400 6500 2700 6500
$Comp
L Device:C C?
U 1 1 5B682CB9
P 2950 6500
AR Path="/53A8C780/5B682CB9" Ref="C?" Part="1"
AR Path="/58CFF3E3/5B682CB9" Ref="C17" Part="1"
F 0 "C17" H 3000 6600 50 0000 L CNN
F 1 "1N" H 3000 6400 50 0001 L CNN
F 2 "ipc_capc:IPC_CAPC100X50X55L25N" H 2950 6500 60 0001 C CNN
F 3 "" H 2950 6500 60 0000 C CNN
F 4 "DNP" H 3050 6400 50 0000 C CNN "DNP"
1 2950 6500
0 -1 -1 0
$EndComp
Wire Wire Line
3100 6500 3200 6500
Wire Wire Line
4500 6500 4400 6500
$Comp
L logic:74HC1G04GW U?
U 1 1 5B682CC3
P 3550 6500
AR Path="/53A8C780/5B682CC3" Ref="U?" Part="1"
AR Path="/58CFF3E3/5B682CC3" Ref="U7" Part="1"
F 0 "U7" H 3575 6787 60 0000 C CNN
F 1 "74HC1G04GW" H 3575 6681 60 0000 C CNN
F 2 "ipc_sot:IPC_SOT23-5P65_212X110L33X22N" H 3550 6500 60 0001 C CNN
F 3 "" H 3550 6500 60 0001 C CNN
F 4 "DNP" H 3650 6400 50 0000 C CNN "DNP"
1 3550 6500
1 0 0 -1
$EndComp
Wire Wire Line
3800 6500 3900 6500
$Comp
L passive:FBEAD FB?
U 1 1 5B682CCB
P 1900 5550
AR Path="/53A8C780/5B682CCB" Ref="FB?" Part="1"
AR Path="/58CFF3E3/5B682CCB" Ref="FB2" Part="1"
F 0 "FB2" V 1848 5631 50 0000 L CNN
F 1 "FBEAD" V 1939 5631 50 0001 L CNN
F 2 "ipc_beadc:IPC_BEADC160X80X95L40N" H 1900 5550 60 0001 C CNN
F 3 "" H 1900 5550 60 0000 C CNN
F 4 "Murata" V 1900 5550 50 0001 C CNN "Mfr"
F 5 "BLM18HE152SN1D" V 1900 5550 50 0001 C CNN "Part"
1 1900 5550
0 1 1 0
$EndComp
Wire Wire Line
1900 5300 1900 5200
$Comp
L Device:R R?
U 1 1 5B682CD3
P 3550 7200
AR Path="/53A8C780/5B682CD3" Ref="R?" Part="1"
AR Path="/58CFF3E3/5B682CD3" Ref="R21" Part="1"
F 0 "R21" V 3450 7200 50 0000 C CNN
PortaPack Sync, take 2 (#215)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* PCB: Change PCB stackup, Tg, clarify solder mask color, use more metric.
* PCB: Move HackRF header P9 to B.CrtYd layer.
* PCB: Change a Tg reference I missed.
* PCB: Update footprints for parts with mismatched CAD->tape rotation.
Adjust a few layer choice and line thickness bits.
* PCB: Got cold feet, switched back to rectangular pads.
* PCB: Add Eco layers to be visible and Gerber output.
* PCB: Use aux origin for plotting, for tidier coordinates.
* PCB: Output Gerber job file, because why not?
* Schematic: Correct footprints for two reference-related components.
* Schematic: Remove manfuacturer and part number for DNP component.
* Schematic: Specify resistor value, manufacturer, part number for reference oscillator series termination.
* PCB: Update netlist and footprints from schematic.
* Netlist: Updated component values, footprints.
* PCB: Nudge some components and traces to address DRC clearance violations.
* PCB: Allow KiCad to update zone timestamps (again?!).
* PCB: Generate *all* Gerber layers.
* Schematic, PCB: Update revision to 20181025.
* PCB: Adjust fab layer annotations orientation and font size.
* PCB: Hide mounting hole reference designators on silk layer.
* PCB: Shrink U1, U3 pads to get 0.2mm space between pads.
* PCB: Set pad-to-mask clearance to zero, leave up to fab. Set minimum mask web to 0.2mm for non-black options.
* PCB: Revise U1 pad shape, mask, paste, thermal drills.
Clearance is improved at corner pads.
* PCB: Tweak U3 for better thermal pad/drill/mask/paste design.
* PCB: Change solder mask color to blue.
* Schematic, PCB: Update revision to 20181029.
* PCB: Bump minimum mask web down a tiny bit because KiCad is having trouble with math.
* Update schematic
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Clock Manager: Actually store chosen clock reference
Similarly-named local was covering a member and discarding the value.
* Clock Manager: Reference type which contains source, frequency.
* Setup: Display reference source, frequency in frequency correction screen.
* LPC43xx API: Add extern "C" for use from C++.
* Use LPC43xx API for SGPIO, GPDMA, I2S initialization.
* I2S: Add BASE_AUDIO_CLK management.
* Add MOTOCON_PWM clock/reset structure.
* Serial: Fix dumb typos.
* Serial: Remove extra reference operator.
* Serial: Cut-and-paste error in structure type name.
* Move SCU structure from PAL to LPC43xx API.
It'd be nice if I gave some thought to where code should live before I commit it.
* VAA power: Move code to HackRF board file
It doesn't belong in PAL.
* MAX5 CPLD: Add SAMPLE and EXTEST methods.
* Flash image: Change packing scheme to use flash more efficiently.
Application is now a single image for both M4 bootstrap and M0.
Baseband images come immediately after application binary. No need to align to large blocks (and waste lots of flash).
* Clock Manager: Remove PLL1 power down function.
* Move and rename peripherals reset function to board module.
* Remove unused peripheral/clock management.
* Clock Manager: Extract switch to IRC into separate function.
* Clock Manager: More explicit shutdown of clocks, clock generator.
* Move initialization to board module.
* ChibiOS: Rename "application" board, add "baseband" board.
There are now two ChibiOS "boards", one which runs the application and does the hardware setup. The other board, "baseband", does very little setup.
* Clock Manager: Remove unused crystal enable/disable code.
* Clock Manager: Restore clock configuration to SPIFI bootloader state before app shutdown.
* Reset peripherals on app shutdown.
Be careful not to reset M0APP (the core we're running on) or GPIO (which is holding the hardware in a stable state).
* M4/baseband hal_lld_init: use IDIVA, which is configured earlier by M0.
This was causing problems during restart into HackRF mode. Baseband hal_lld_init changed M4 clock from IDIVA (set by M0) to PLL1, which was unceremoniously turned off during shutdown.
* Audio app: Stop audio PLL on shutdown.
* M4 HAL: Make LPC43XX_M4_CLK_SRC optional.
This was changing the BASE_M4_CLK when a baseband was run.
* LPC43xx C++ layer: Fix IDIVx constructor IDIV narrow field width.
* Application board: hide the peripherals_reset function, as it isn't useful except during hardware init.
* Consolidate hardware init code to some degree.
ClockManager is super-overloaded and murky in its purpose.
Migrate audio from IDIVC to IDIVD, to more closely resemble initial clock scheme, so it's simpler to get back to it during shutdown.
* Migrate some startup code to application board.
* Si5351: Use correct methods for reset().
update_output_enable_control() doesn't reset the enabled outputs to the reset state, unless the object is freshly initialized, which it isn't when performing firmware shutdown.
For similar reasons, use set_clock_control() instead of setting internal state and then using the update function.
* GPIO: Set SPIFI CS pin to match input buffer state coming out of bootloader.
* Change application board.c to .cpp, with required dependent changes
* Board: Clean up SCU configuration code/data.
* I2S: Add shutdown code and use it.
* LPC43xx: Consolidate a bunch of structures that had been scattered all over.
...because I'm an undisciplined coder.
* I2S: Fix ordering of branch and base clock disable.
Core was hanging, presumably because the register interface on the branch/peripheral was unresponsive after the base clock was disabled.
* Controls: Save and expose raw navigation wheel switch state
I need to do some work on debouncing and ignoring simultaneous key presses.
* Controls: Add debug view for switches state.
* Controls: Ignore all key presses until all keys are released.
This should address some mechanical quirks of the navigation wheel used on the PortaPack.
* Clock Manager: Wait for only the necessary PLL to lock.
Wasn't working on PortaPacks without a built-in clock reference, as that uses the other PLL.
TODO: Switching PLLs may be kind of pointless now...
* CMake: Pull HackRF project from GitHub and build.
* CMake: Remove commented code.
* CMake: Clone HackRF via HTTPS, not SSH.
* CMake: Extra pause for slow post-DFU firmware boot-up.
* CMake: TODO to fix SVF/XSVF file source.
* CMake: Ask HackRF hackrf_usb to make DFU binary.
* Travis-CI: Add dfu-util, now that HackRF firmware is being built for inclusion.
* Travis-CI: Update build environment to Ubuntu xenial
Previously Trusty.
* Travis-CI: Incorrectly structured my request for dfu-util package.
I'm soooo talented.
* ldscript: Mark flash, ram with correct R/W/X flags.
* ldscript: Enlarge M0 flash region to 1Mbyte, the size of the HackRF SPI flash.
* Receiver: Hide PPM adjustment if clock source is not HackRF crystal.
* Documentation: Update product photos and README.
* Documentation: Add TCXO feature to README description.
* Application: Rearrange files to match HAVOC directory structure.
* Map view in AIS (#213)
* Added GeoMapView to AISRecentEntryDetailView
* Added autoupdate in AIS map
* Revert "Map view in AIS (#213)"
This reverts commit 262c030224b9ea3e56ff1c8a66246e7ecf30e41f.
This commit will be cherry-picked onto a clean branch, then re-committed after a troublesome pull request is reverted.
* Revert "Upstream merge to make new revision of PortaPack work (#206)"
This reverts commit 920b98f7c9a30371b643c42949066fb7d2441daf.
This pull request was missing some changes and was preventing firmware from functioning on older PortaPacks.
* CPLD: Pull bitstream from HackRF project.
* SGPIO: Identify pins on CPLD by their new functions. Pull down HOST_SYNC_EN.
* CPLD: Don't load HackRF CPLD bitstream into RAM.
Trying to converge CPLD implementations, so this shouldn't be necesssary. HOWEVER, it would be good to *check* the CPLD contents and provide a way to update, if necessary.
* CPLD: Tweak clock generator config to match CPLD timing changes in HackRF.
* PinConfig: Drive CPLD pins correctly.
* CMake: Use jboone/hackrf master branch, now that CPLD fixes are there.
* CMake: Fix HackRF CPLD SVF dependency.
Build would break on the first pass, but work if you restarted make.
* CMake: Fix my misuse of the HackRF CMake configuration -- was building from too deep in the directory tree
* CMake: Work-around for CMake 3.5 not supporting ExternalProject_Add SOURCE_SUBDIR.
* CMake: Choose a CMP0005 policy to quiet CMake warnings.
* Settings: Show active clock reference. Only show PPM adjustment for HackRF source.
* Radio Settings: Change reference clock text color.
Make consistent color with other un-editable text.
TODO: This is a bit of a hack to get ui::Text objects to support custom colors, like the Label structures used elsewhere.
2019-02-03 18:25:11 +00:00
F 1 "100R" V 3550 7200 50 0000 C CNN
F 2 "ipc_resc:IPC_RESC100X50X40L25N" V 3480 7200 50 0001 C CNN
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
F 3 "~" H 3550 7200 50 0001 C CNN
F 4 "Yageo" V 3550 7200 50 0001 C CNN "Mfr"
PortaPack Sync, take 2 (#215)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* PCB: Change PCB stackup, Tg, clarify solder mask color, use more metric.
* PCB: Move HackRF header P9 to B.CrtYd layer.
* PCB: Change a Tg reference I missed.
* PCB: Update footprints for parts with mismatched CAD->tape rotation.
Adjust a few layer choice and line thickness bits.
* PCB: Got cold feet, switched back to rectangular pads.
* PCB: Add Eco layers to be visible and Gerber output.
* PCB: Use aux origin for plotting, for tidier coordinates.
* PCB: Output Gerber job file, because why not?
* Schematic: Correct footprints for two reference-related components.
* Schematic: Remove manfuacturer and part number for DNP component.
* Schematic: Specify resistor value, manufacturer, part number for reference oscillator series termination.
* PCB: Update netlist and footprints from schematic.
* Netlist: Updated component values, footprints.
* PCB: Nudge some components and traces to address DRC clearance violations.
* PCB: Allow KiCad to update zone timestamps (again?!).
* PCB: Generate *all* Gerber layers.
* Schematic, PCB: Update revision to 20181025.
* PCB: Adjust fab layer annotations orientation and font size.
* PCB: Hide mounting hole reference designators on silk layer.
* PCB: Shrink U1, U3 pads to get 0.2mm space between pads.
* PCB: Set pad-to-mask clearance to zero, leave up to fab. Set minimum mask web to 0.2mm for non-black options.
* PCB: Revise U1 pad shape, mask, paste, thermal drills.
Clearance is improved at corner pads.
* PCB: Tweak U3 for better thermal pad/drill/mask/paste design.
* PCB: Change solder mask color to blue.
* Schematic, PCB: Update revision to 20181029.
* PCB: Bump minimum mask web down a tiny bit because KiCad is having trouble with math.
* Update schematic
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Clock Manager: Actually store chosen clock reference
Similarly-named local was covering a member and discarding the value.
* Clock Manager: Reference type which contains source, frequency.
* Setup: Display reference source, frequency in frequency correction screen.
* LPC43xx API: Add extern "C" for use from C++.
* Use LPC43xx API for SGPIO, GPDMA, I2S initialization.
* I2S: Add BASE_AUDIO_CLK management.
* Add MOTOCON_PWM clock/reset structure.
* Serial: Fix dumb typos.
* Serial: Remove extra reference operator.
* Serial: Cut-and-paste error in structure type name.
* Move SCU structure from PAL to LPC43xx API.
It'd be nice if I gave some thought to where code should live before I commit it.
* VAA power: Move code to HackRF board file
It doesn't belong in PAL.
* MAX5 CPLD: Add SAMPLE and EXTEST methods.
* Flash image: Change packing scheme to use flash more efficiently.
Application is now a single image for both M4 bootstrap and M0.
Baseband images come immediately after application binary. No need to align to large blocks (and waste lots of flash).
* Clock Manager: Remove PLL1 power down function.
* Move and rename peripherals reset function to board module.
* Remove unused peripheral/clock management.
* Clock Manager: Extract switch to IRC into separate function.
* Clock Manager: More explicit shutdown of clocks, clock generator.
* Move initialization to board module.
* ChibiOS: Rename "application" board, add "baseband" board.
There are now two ChibiOS "boards", one which runs the application and does the hardware setup. The other board, "baseband", does very little setup.
* Clock Manager: Remove unused crystal enable/disable code.
* Clock Manager: Restore clock configuration to SPIFI bootloader state before app shutdown.
* Reset peripherals on app shutdown.
Be careful not to reset M0APP (the core we're running on) or GPIO (which is holding the hardware in a stable state).
* M4/baseband hal_lld_init: use IDIVA, which is configured earlier by M0.
This was causing problems during restart into HackRF mode. Baseband hal_lld_init changed M4 clock from IDIVA (set by M0) to PLL1, which was unceremoniously turned off during shutdown.
* Audio app: Stop audio PLL on shutdown.
* M4 HAL: Make LPC43XX_M4_CLK_SRC optional.
This was changing the BASE_M4_CLK when a baseband was run.
* LPC43xx C++ layer: Fix IDIVx constructor IDIV narrow field width.
* Application board: hide the peripherals_reset function, as it isn't useful except during hardware init.
* Consolidate hardware init code to some degree.
ClockManager is super-overloaded and murky in its purpose.
Migrate audio from IDIVC to IDIVD, to more closely resemble initial clock scheme, so it's simpler to get back to it during shutdown.
* Migrate some startup code to application board.
* Si5351: Use correct methods for reset().
update_output_enable_control() doesn't reset the enabled outputs to the reset state, unless the object is freshly initialized, which it isn't when performing firmware shutdown.
For similar reasons, use set_clock_control() instead of setting internal state and then using the update function.
* GPIO: Set SPIFI CS pin to match input buffer state coming out of bootloader.
* Change application board.c to .cpp, with required dependent changes
* Board: Clean up SCU configuration code/data.
* I2S: Add shutdown code and use it.
* LPC43xx: Consolidate a bunch of structures that had been scattered all over.
...because I'm an undisciplined coder.
* I2S: Fix ordering of branch and base clock disable.
Core was hanging, presumably because the register interface on the branch/peripheral was unresponsive after the base clock was disabled.
* Controls: Save and expose raw navigation wheel switch state
I need to do some work on debouncing and ignoring simultaneous key presses.
* Controls: Add debug view for switches state.
* Controls: Ignore all key presses until all keys are released.
This should address some mechanical quirks of the navigation wheel used on the PortaPack.
* Clock Manager: Wait for only the necessary PLL to lock.
Wasn't working on PortaPacks without a built-in clock reference, as that uses the other PLL.
TODO: Switching PLLs may be kind of pointless now...
* CMake: Pull HackRF project from GitHub and build.
* CMake: Remove commented code.
* CMake: Clone HackRF via HTTPS, not SSH.
* CMake: Extra pause for slow post-DFU firmware boot-up.
* CMake: TODO to fix SVF/XSVF file source.
* CMake: Ask HackRF hackrf_usb to make DFU binary.
* Travis-CI: Add dfu-util, now that HackRF firmware is being built for inclusion.
* Travis-CI: Update build environment to Ubuntu xenial
Previously Trusty.
* Travis-CI: Incorrectly structured my request for dfu-util package.
I'm soooo talented.
* ldscript: Mark flash, ram with correct R/W/X flags.
* ldscript: Enlarge M0 flash region to 1Mbyte, the size of the HackRF SPI flash.
* Receiver: Hide PPM adjustment if clock source is not HackRF crystal.
* Documentation: Update product photos and README.
* Documentation: Add TCXO feature to README description.
* Application: Rearrange files to match HAVOC directory structure.
* Map view in AIS (#213)
* Added GeoMapView to AISRecentEntryDetailView
* Added autoupdate in AIS map
* Revert "Map view in AIS (#213)"
This reverts commit 262c030224b9ea3e56ff1c8a66246e7ecf30e41f.
This commit will be cherry-picked onto a clean branch, then re-committed after a troublesome pull request is reverted.
* Revert "Upstream merge to make new revision of PortaPack work (#206)"
This reverts commit 920b98f7c9a30371b643c42949066fb7d2441daf.
This pull request was missing some changes and was preventing firmware from functioning on older PortaPacks.
* CPLD: Pull bitstream from HackRF project.
* SGPIO: Identify pins on CPLD by their new functions. Pull down HOST_SYNC_EN.
* CPLD: Don't load HackRF CPLD bitstream into RAM.
Trying to converge CPLD implementations, so this shouldn't be necesssary. HOWEVER, it would be good to *check* the CPLD contents and provide a way to update, if necessary.
* CPLD: Tweak clock generator config to match CPLD timing changes in HackRF.
* PinConfig: Drive CPLD pins correctly.
* CMake: Use jboone/hackrf master branch, now that CPLD fixes are there.
* CMake: Fix HackRF CPLD SVF dependency.
Build would break on the first pass, but work if you restarted make.
* CMake: Fix my misuse of the HackRF CMake configuration -- was building from too deep in the directory tree
* CMake: Work-around for CMake 3.5 not supporting ExternalProject_Add SOURCE_SUBDIR.
* CMake: Choose a CMP0005 policy to quiet CMake warnings.
* Settings: Show active clock reference. Only show PPM adjustment for HackRF source.
* Radio Settings: Change reference clock text color.
Make consistent color with other un-editable text.
TODO: This is a bit of a hack to get ui::Text objects to support custom colors, like the Label structures used elsewhere.
2019-02-03 18:25:11 +00:00
F 5 "RC0402FR-07100RL" V 3550 7200 50 0001 C CNN "Part"
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 06:56:21 +00:00
1 3550 7200
0 1 1 0
$EndComp
Wire Wire Line
4400 6500 4400 7200
Wire Wire Line
4400 7200 3700 7200
Connection ~ 4400 6500
Wire Wire Line
4400 6500 4300 6500
Wire Wire Line
2700 6500 2700 7200
Wire Wire Line
2700 7200 3400 7200
Connection ~ 2700 6500
Wire Wire Line
2700 6500 2800 6500
$Comp
L power:+3V3 #PWR?
U 1 1 5B682CE2
P 1900 5200
AR Path="/53A8C780/5B682CE2" Ref="#PWR?" Part="1"
AR Path="/58CFF3E3/5B682CE2" Ref="#PWR0102" Part="1"
F 0 "#PWR0102" H 1900 5160 30 0001 C CNN
F 1 "+3V3" H 1900 5310 30 0000 C CNN
F 2 "" H 1900 5200 60 0000 C CNN
F 3 "" H 1900 5200 60 0000 C CNN
1 1900 5200
1 0 0 -1
$EndComp
Wire Wire Line
1400 6500 1300 6500
Text HLabel 4500 6500 2 60 Output ~ 0
REF_CLK
Text HLabel 1200 6500 0 60 Input ~ 0
REF_EN
$Comp
L power:VCC #PWR0107
U 1 1 5B693D4A
P 10850 4450
F 0 "#PWR0107" H 10850 4300 50 0001 C CNN
F 1 "VCC" H 10867 4623 50 0000 C CNN
F 2 "" H 10850 4450 50 0001 C CNN
F 3 "" H 10850 4450 50 0001 C CNN
1 10850 4450
1 0 0 -1
$EndComp
Wire Wire Line
10850 4450 10850 4550
Wire Wire Line
10850 4550 10550 4550
$Comp
L Device:C C?
U 1 1 5B697E1B
P 3400 5650
AR Path="/53A8C780/5B697E1B" Ref="C?" Part="1"
AR Path="/58CFF3E3/5B697E1B" Ref="C18" Part="1"
F 0 "C18" H 3450 5750 50 0000 L CNN
F 1 "100N" H 3450 5550 50 0001 L CNN
F 2 "ipc_capc:IPC_CAPC100X50X55L25N" H 3400 5650 60 0001 C CNN
F 3 "" H 3400 5650 60 0000 C CNN
F 4 "Murata" H 3400 5650 60 0001 C CNN "Mfr"
F 5 "GRM155R61A104KA01" H 3400 5650 60 0001 C CNN "Part"
F 6 "DNP" H 3500 5550 50 0000 C CNN "DNP"
1 3400 5650
1 0 0 -1
$EndComp
$Comp
L power:VCC #PWR0105
U 1 1 5B69805A
P 3400 5400
F 0 "#PWR0105" H 3400 5250 50 0001 C CNN
F 1 "VCC" H 3417 5573 50 0000 C CNN
F 2 "" H 3400 5400 50 0001 C CNN
F 3 "" H 3400 5400 50 0001 C CNN
1 3400 5400
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR?
U 1 1 5B6980A9
P 3400 5900
AR Path="/53A8C780/5B6980A9" Ref="#PWR?" Part="1"
AR Path="/58CFF3E3/5B6980A9" Ref="#PWR0106" Part="1"
F 0 "#PWR0106" H 3400 5900 30 0001 C CNN
F 1 "GND" H 3400 5830 30 0001 C CNN
F 2 "" H 3400 5900 60 0000 C CNN
F 3 "" H 3400 5900 60 0000 C CNN
1 3400 5900
1 0 0 -1
$EndComp
Wire Wire Line
3400 5900 3400 5800
Wire Wire Line
3400 5500 3400 5400
Text Notes 900 7600 0 60 ~ 0
Clock Reference\n\nDefault is HCMOS output oscillator with tri-state output.\nAlternative is clipped-sine, running through CMOS squarer.
$Comp
L Device:R R?
U 1 1 5B6D148B
P 1300 6750
AR Path="/53A8C780/5B6D148B" Ref="R?" Part="1"
AR Path="/58CFF3E3/5B6D148B" Ref="R16" Part="1"
F 0 "R16" V 1200 6750 50 0000 C CNN
F 1 "10K" V 1184 6750 50 0001 C CNN
F 2 "ipc_resc:IPC_RESC100X50X40L25N" V 1230 6750 50 0001 C CNN
F 3 "~" H 1300 6750 50 0001 C CNN
F 4 "DNP" V 1300 6750 50 0000 C CNN "DNP"
1 1300 6750
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR?
U 1 1 5B6D1597
P 1300 7000
AR Path="/53A8C780/5B6D1597" Ref="#PWR?" Part="1"
AR Path="/58CFF3E3/5B6D1597" Ref="#PWR0100" Part="1"
F 0 "#PWR0100" H 1300 7000 30 0001 C CNN
F 1 "GND" H 1300 6930 30 0001 C CNN
F 2 "" H 1300 7000 60 0000 C CNN
F 3 "" H 1300 7000 60 0000 C CNN
1 1300 7000
1 0 0 -1
$EndComp
Wire Wire Line
1300 6500 1300 6600
Connection ~ 1300 6500
Wire Wire Line
1300 6500 1200 6500
Wire Wire Line
1300 6900 1300 7000
$Comp
L Device:R R?
U 1 1 5B6E2EB4
P 1300 6250
AR Path="/53A8C780/5B6E2EB4" Ref="R?" Part="1"
AR Path="/58CFF3E3/5B6E2EB4" Ref="R15" Part="1"
F 0 "R15" V 1200 6250 50 0000 C CNN
F 1 "10K" V 1184 6250 50 0001 C CNN
F 2 "ipc_resc:IPC_RESC100X50X40L25N" V 1230 6250 50 0001 C CNN
F 3 "~" H 1300 6250 50 0001 C CNN
F 4 "DNP" V 1300 6250 50 0000 C CNN "DNP"
1 1300 6250
1 0 0 -1
$EndComp
Wire Wire Line
1300 6000 1300 6100
Wire Wire Line
1300 6400 1300 6500
$Comp
L power:+3V3 #PWR?
U 1 1 5B62BBF5
P 1300 6000
AR Path="/53A8C780/5B62BBF5" Ref="#PWR?" Part="1"
AR Path="/58CFF3E3/5B62BBF5" Ref="#PWR0101" Part="1"
F 0 "#PWR0101" H 1300 5960 30 0001 C CNN
F 1 "+3V3" H 1300 6110 30 0000 C CNN
F 2 "" H 1300 6000 60 0000 C CNN
F 3 "" H 1300 6000 60 0000 C CNN
1 1300 6000
1 0 0 -1
$EndComp
Text Notes 5650 1700 0 60 ~ 0
TODO: Connect SYSOFF to a CPLD pin and to PGOOD#.\nIf VBUS is present, or CPLD is holding line low,\ndevice will stay on during battery operation.\nBut how to turn it on with a button press?!\n...and not leave the button "jammed" once on\n(and SYSOFF is being held low). Need a bit of\nlogic to fuse two OC active low signals into one?
Text HLabel 10450 4650 0 60 Output ~ 0
GPS_VCC
Wire Wire Line
10450 4650 10550 4650
Connection ~ 10550 4650
Wire Wire Line
10550 4650 10550 4750
2017-06-19 22:57:56 +00:00
$EndSCHEMATC
