mirror of
https://github.com/portapack-mayhem/mayhem-firmware.git
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256 lines
8.4 KiB
C
256 lines
8.4 KiB
C
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/*
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ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file STM32F1xx/hal_lld.h
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* @brief STM32F1xx HAL subsystem low level driver header.
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* @pre This module requires the following macros to be defined in the
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* @p board.h file:
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* - STM32_LSECLK.
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* - STM32_HSECLK.
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* - STM32_HSE_BYPASS (optionally).
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* .
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* One of the following macros must also be defined:
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* - STM32F10X_LD_VL for Value Line Low Density devices.
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* - STM32F10X_MD_VL for Value Line Medium Density devices.
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* - STM32F10X_LD for Performance Low Density devices.
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* - STM32F10X_MD for Performance Medium Density devices.
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* - STM32F10X_HD for Performance High Density devices.
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* - STM32F10X_XL for Performance eXtra Density devices.
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* - STM32F10X_CL for Connectivity Line devices.
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* .
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*
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* @addtogroup HAL
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* @{
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*/
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#ifndef _HAL_LLD_H_
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#define _HAL_LLD_H_
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#include "stm32.h"
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/**
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* @brief Defines the support for realtime counters in the HAL.
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*/
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#define HAL_IMPLEMENTS_COUNTERS TRUE
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/**
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* @name Internal clock sources
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* @{
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*/
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#define STM32_HSICLK 8000000 /**< High speed internal clock. */
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#define STM32_LSICLK 40000 /**< Low speed internal clock. */
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/** @} */
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/**
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* @name PWR_CR register bits definitions
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* @{
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*/
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#define STM32_PLS_MASK (7 << 5) /**< PLS bits mask. */
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#define STM32_PLS_LEV0 (0 << 5) /**< PVD level 0. */
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#define STM32_PLS_LEV1 (1 << 5) /**< PVD level 1. */
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#define STM32_PLS_LEV2 (2 << 5) /**< PVD level 2. */
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#define STM32_PLS_LEV3 (3 << 5) /**< PVD level 3. */
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#define STM32_PLS_LEV4 (4 << 5) /**< PVD level 4. */
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#define STM32_PLS_LEV5 (5 << 5) /**< PVD level 5. */
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#define STM32_PLS_LEV6 (6 << 5) /**< PVD level 6. */
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#define STM32_PLS_LEV7 (7 << 5) /**< PVD level 7. */
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/** @} */
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/*===========================================================================*/
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/* Platform capabilities. */
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/*===========================================================================*/
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/**
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* @name STM32F1xx capabilities
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* @{
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*/
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/* RTC attributes.*/
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#define STM32_HAS_RTC TRUE
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#define STM32_RTC_HAS_SUBSECONDS TRUE
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#define STM32_RTC_IS_CALENDAR FALSE
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/** @} */
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/**
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* @name Configuration options
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* @{
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*/
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/**
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* @brief Disables the PWR/RCC initialization in the HAL.
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*/
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#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__)
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#define STM32_NO_INIT FALSE
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#endif
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/**
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* @brief Enables or disables the programmable voltage detector.
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*/
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#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__)
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#define STM32_PVD_ENABLE FALSE
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#endif
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/**
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* @brief Sets voltage level for programmable voltage detector.
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*/
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#if !defined(STM32_PLS) || defined(__DOXYGEN__)
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#define STM32_PLS STM32_PLS_LEV0
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#endif
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/**
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* @brief Enables or disables the HSI clock source.
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*/
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#if !defined(STM32_HSI_ENABLED) || defined(__DOXYGEN__)
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#define STM32_HSI_ENABLED TRUE
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#endif
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/**
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* @brief Enables or disables the LSI clock source.
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*/
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#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__)
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#define STM32_LSI_ENABLED FALSE
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#endif
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/**
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* @brief Enables or disables the HSE clock source.
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*/
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#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__)
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#define STM32_HSE_ENABLED TRUE
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#endif
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/**
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* @brief Enables or disables the LSE clock source.
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*/
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#if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__)
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#define STM32_LSE_ENABLED FALSE
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#endif
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/** @} */
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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#if defined(__DOXYGEN__)
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/**
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* @name Platform identification
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* @{
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*/
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#define PLATFORM_NAME "STM32"
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/** @} */
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#elif defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \
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defined(STM32F10X_HD_VL) || defined(__DOXYGEN__)
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#include "hal_lld_f100.h"
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#elif defined(STM32F10X_LD) || defined(STM32F10X_MD) || \
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defined(STM32F10X_HD) || defined(STM32F10X_XL) || \
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defined(__DOXYGEN__)
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#include "hal_lld_f103.h"
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#elif defined(STM32F10X_CL) || defined(__DOXYGEN__)
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#include "hal_lld_f105_f107.h"
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#else
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#error "unspecified, unsupported or invalid STM32 platform"
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#endif
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/* There are differences in vector names in the various sub-families,
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normalizing.*/
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#if defined(STM32F10X_XL)
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#define TIM1_BRK_IRQn TIM1_BRK_TIM9_IRQn
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#define TIM1_UP_IRQn TIM1_UP_TIM10_IRQn
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#define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM11_IRQn
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#define TIM8_BRK_IRQn TIM8_BRK_TIM12_IRQn
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#define TIM8_UP_IRQn TIM8_UP_TIM13_IRQn
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#define TIM8_TRG_COM_IRQn TIM8_TRG_COM_TIM14_IRQn
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#elif defined(STM32F10X_LD_VL)|| defined(STM32F10X_MD_VL) || \
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defined(STM32F10X_HD_VL)
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#define TIM1_BRK_IRQn TIM1_BRK_TIM15_IRQn
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#define TIM1_UP_IRQn TIM1_UP_TIM16_IRQn
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#define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM17_IRQn
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#endif
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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/**
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* @brief Type representing a system clock frequency.
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*/
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typedef uint32_t halclock_t;
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/**
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* @brief Type of the realtime free counter value.
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*/
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typedef uint32_t halrtcnt_t;
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/*===========================================================================*/
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/* Driver macros. */
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/*===========================================================================*/
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/**
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* @brief Returns the current value of the system free running counter.
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* @note This service is implemented by returning the content of the
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* DWT_CYCCNT register.
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*
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* @return The value of the system free running counter of
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* type halrtcnt_t.
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*
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* @notapi
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*/
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#define hal_lld_get_counter_value() DWT_CYCCNT
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/**
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* @brief Realtime counter frequency.
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* @note The DWT_CYCCNT register is incremented directly by the system
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* clock so this function returns STM32_HCLK.
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*
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* @return The realtime counter frequency of type halclock_t.
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*
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* @notapi
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*/
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#define hal_lld_get_counter_frequency() STM32_HCLK
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/*===========================================================================*/
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/* External declarations. */
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/*===========================================================================*/
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/* STM32 ISR, DMA and RCC helpers.*/
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#include "stm32_isr.h"
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#include "stm32_dma.h"
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#include "stm32_rcc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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void hal_lld_init(void);
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void stm32_clock_init(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _HAL_LLD_H_ */
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/** @} */
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