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mayhem-firmware/hardware/portapack_h1/portapack_h1.kicad_pcb

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PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(kicad_pcb (version 4) (host pcbnew 4.0.5-e0-6337~52~ubuntu16.10.1)
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(general
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(links 263)
(no_connects 114)
(area 19.949999 21.275 274.000002 175.190501)
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(thickness 1.6)
Allow KiCad to update metadata.
2015-09-01 18:10:50 +00:00
(drawings 110)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(tracks 1546)
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(zones 0)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(modules 69)
(nets 121)
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
(page A4)
Add title block with copyright, license.
2015-08-31 00:12:32 +00:00
(title_block
(title "PortaPack H1")
(date 2015-08-31)
(rev 20150831)
(company "ShareBrained Technology, Inc.")
(comment 1 "License: GNU General Public License, version 2")
(comment 2 "Copyright (c) 2014, 2015 Jared Boone")
)
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(layers
Remove line in/out components and traces, microphone. Clean up traces and via stitching affected by removed components.
2015-08-24 00:23:21 +00:00
(0 1_top signal)
(1 2_pwr mixed)
(2 3_gnd mixed)
(31 4_bot signal)
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(32 B.Adhes user hide)
(33 F.Adhes user hide)
(34 B.Paste user hide)
(35 F.Paste user hide)
Change default layer visibility.
2015-09-01 17:14:36 +00:00
(36 B.SilkS user)
(37 F.SilkS user)
(38 B.Mask user hide)
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(39 F.Mask user hide)
Change default layer visibility.
2015-09-01 17:14:36 +00:00
(40 Dwgs.User user)
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(41 Cmts.User user hide)
(42 Eco1.User user hide)
(43 Eco2.User user hide)
(44 Edge.Cuts user)
Change default layer visibility.
2015-09-01 17:14:36 +00:00
(46 B.CrtYd user hide)
(47 F.CrtYd user hide)
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
(setup
(last_trace_width 0.2)
(user_trace_width 0.2)
(user_trace_width 0.3)
(user_trace_width 0.4)
(trace_clearance 0.198)
(zone_clearance 0.2)
(zone_45_only yes)
(trace_min 0.2)
(segment_width 0.1524)
(edge_width 0.1)
Change vias to 13mil, 7mil annular ring. Was 13.5mm, but why?!?
2015-08-30 05:31:29 +00:00
(via_size 0.6858)
(via_drill 0.3302)
(via_min_size 0.6858)
(via_min_drill 0.3302)
(user_via 0.6858 0.3302)
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(uvia_size 0.508)
(uvia_drill 0.127)
(uvias_allowed no)
(uvia_min_size 0.508)
(uvia_min_drill 0.127)
(pcb_text_width 0.3)
(pcb_text_size 1.5 1.5)
(mod_edge_width 0.1524)
(mod_text_size 0.6096 0.6096)
(mod_text_width 0.1524)
(pad_size 2.75 2.75)
(pad_drill 0)
(pad_to_mask_clearance 0.0762)
(solder_mask_min_width 0.0762)
(aux_axis_origin 60 175)
(grid_origin 60 100)
(visible_elements FFFEFFFF)
(pcbplotparams
Update layers exported during PCB plot.
2015-09-01 17:17:30 +00:00
(layerselection 0x011fc_80000007)
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(usegerberextensions true)
(excludeedgelayer true)
(linewidth 0.152400)
(plotframeref false)
(viasonmask false)
(mode 1)
(useauxorigin false)
(hpglpennumber 1)
(hpglpenspeed 20)
(hpglpendiameter 15)
(hpglpenoverlay 2)
(psnegative false)
(psa4output false)
(plotreference true)
(plotvalue false)
(plotinvisibletext false)
(padsonsilk false)
(subtractmaskfromsilk true)
(outputformat 1)
(mirror false)
(drillshape 0)
(scaleselection 1)
(outputdirectory gerber/))
)
(net 0 "")
(net 1 +1.8V)
(net 2 +3.3V)
(net 3 /audio/I2S0_MCLK)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 4 /audio/I2S0_RX_SDA)
(net 5 /audio/I2S0_SCK)
(net 6 /audio/I2S0_TX_SDA)
(net 7 /audio/I2S0_WS)
(net 8 /audio/LHPOUT)
(net 9 /audio/MICBIAS)
(net 10 /audio/MICIN)
(net 11 /audio/RHPOUT)
(net 12 /audio/SCL)
(net 13 /audio/SDA)
(net 14 /audio/VMID)
(net 15 /hackrf_if/LCD_BACKLIGHT)
(net 16 /hackrf_if/LCD_DB0)
(net 17 /hackrf_if/LCD_DB1)
(net 18 /hackrf_if/LCD_DB10)
(net 19 /hackrf_if/LCD_DB11)
(net 20 /hackrf_if/LCD_DB12)
(net 21 /hackrf_if/LCD_DB13)
(net 22 /hackrf_if/LCD_DB14)
(net 23 /hackrf_if/LCD_DB15)
(net 24 /hackrf_if/LCD_DB2)
(net 25 /hackrf_if/LCD_DB3)
(net 26 /hackrf_if/LCD_DB4)
(net 27 /hackrf_if/LCD_DB5)
(net 28 /hackrf_if/LCD_DB6)
(net 29 /hackrf_if/LCD_DB7)
(net 30 /hackrf_if/LCD_DB8)
(net 31 /hackrf_if/LCD_DB9)
(net 32 /hackrf_if/LCD_RD#)
(net 33 /hackrf_if/LCD_RESET#)
(net 34 /hackrf_if/LCD_RS)
(net 35 /hackrf_if/LCD_TE)
(net 36 /hackrf_if/LCD_WR#)
(net 37 /hackrf_if/P2_8)
(net 38 /hackrf_if/RESET#)
(net 39 /hackrf_if/SD_CD)
(net 40 /hackrf_if/SD_CLK)
(net 41 /hackrf_if/SD_CMD)
(net 42 /hackrf_if/SD_DAT0)
(net 43 /hackrf_if/SD_DAT1)
(net 44 /hackrf_if/SD_DAT2)
(net 45 /hackrf_if/SD_DAT3)
(net 46 /hackrf_if/SW_D)
(net 47 /hackrf_if/SW_L)
(net 48 /hackrf_if/SW_R)
(net 49 /hackrf_if/SW_ROT_A)
(net 50 /hackrf_if/SW_ROT_B)
(net 51 /hackrf_if/SW_SEL)
(net 52 /hackrf_if/SW_U)
(net 53 /hackrf_if/TP_D)
(net 54 /hackrf_if/TP_L)
(net 55 /hackrf_if/TP_R)
(net 56 /hackrf_if/TP_U)
(net 57 /hackrf_if/VBAT)
(net 58 GND)
(net 59 "Net-(C18-Pad2)")
(net 60 "Net-(C19-Pad2)")
(net 61 "Net-(C24-Pad1)")
(net 62 "Net-(C24-Pad2)")
(net 63 "Net-(C39-Pad1)")
(net 64 "Net-(J3-Pad1)")
(net 65 "Net-(L4-Pad1)")
(net 66 "Net-(L5-Pad1)")
(net 67 "Net-(L6-Pad1)")
(net 68 "Net-(L9-Pad1)")
(net 69 "Net-(P2-Pad5)")
(net 70 "Net-(P2-Pad6)")
(net 71 "Net-(P20-Pad2)")
(net 72 "Net-(P20-Pad4)")
(net 73 /hackrf_if/MCU_D1)
(net 74 /hackrf_if/MCU_D0)
(net 75 /hackrf_if/MCU_D3)
(net 76 /hackrf_if/MCU_D2)
(net 77 /hackrf_if/MCU_D5)
(net 78 /hackrf_if/MCU_D4)
(net 79 /hackrf_if/MCU_D7)
(net 80 /hackrf_if/MCU_D6)
(net 81 "Net-(P20-Pad17)")
(net 82 "Net-(P20-Pad22)")
(net 83 "Net-(P20-Pad21)")
(net 84 "Net-(P22-Pad2)")
(net 85 "Net-(P22-Pad1)")
(net 86 /hackrf_if/MCU_LCD_TE)
(net 87 /hackrf_if/MCU_LCD_RD)
(net 88 "Net-(P22-Pad8)")
(net 89 "Net-(P22-Pad7)")
(net 90 "Net-(P22-Pad9)")
(net 91 "Net-(P22-Pad12)")
(net 92 "Net-(P22-Pad14)")
(net 93 /hackrf_if/MCU_IO_STBX)
(net 94 /hackrf_if/MCU_ADDR)
(net 95 /hackrf_if/MCU_DIR)
(net 96 /hackrf_if/MCU_LCD_WR)
(net 97 "Net-(P22-Pad25)")
(net 98 /hackrf_if/PP_CPLD_TMS)
(net 99 /hackrf_if/PP_CPLD_TDO)
(net 100 "Net-(P28-Pad14)")
(net 101 "Net-(P28-Pad13)")
(net 102 "Net-(P28-Pad16)")
(net 103 "Net-(P28-Pad15)")
(net 104 "Net-(P28-Pad18)")
(net 105 /hackrf_if/H1_CPLD_TCK)
(net 106 "Net-(P28-Pad20)")
(net 107 /hackrf_if/H1_CPLD_TDI)
(net 108 "Net-(P28-Pad22)")
(net 109 "Net-(P28-Pad21)")
(net 110 "Net-(U1-Pad2)")
(net 111 "Net-(U1-Pad12)")
(net 112 "Net-(U1-Pad13)")
(net 113 "Net-(U1-Pad19)")
(net 114 "Net-(U1-Pad20)")
(net 115 "Net-(U1-Pad26)")
(net 116 "Net-(U3-Pad5)")
(net 117 "Net-(U3-Pad7)")
(net 118 "Net-(U3-Pad35)")
(net 119 "Net-(U3-Pad36)")
(net 120 "Net-(U3-Pad37)")
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(net_class Default "This is the default net class."
(clearance 0.198)
(trace_width 0.2)
Change vias to 13mil, 7mil annular ring. Was 13.5mm, but why?!?
2015-08-30 05:31:29 +00:00
(via_dia 0.6858)
(via_drill 0.3302)
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(uvia_dia 0.508)
(uvia_drill 0.127)
(add_net +1.8V)
(add_net +3.3V)
(add_net /audio/I2S0_MCLK)
(add_net /audio/I2S0_RX_SDA)
(add_net /audio/I2S0_SCK)
(add_net /audio/I2S0_TX_SDA)
(add_net /audio/I2S0_WS)
(add_net /audio/LHPOUT)
(add_net /audio/MICBIAS)
(add_net /audio/MICIN)
(add_net /audio/RHPOUT)
(add_net /audio/SCL)
(add_net /audio/SDA)
(add_net /audio/VMID)
Remove line in/out components and traces, microphone. Clean up traces and via stitching affected by removed components.
2015-08-24 00:23:21 +00:00
(add_net /hackrf_if/H1_CPLD_TCK)
(add_net /hackrf_if/H1_CPLD_TDI)
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(add_net /hackrf_if/LCD_BACKLIGHT)
(add_net /hackrf_if/LCD_DB0)
(add_net /hackrf_if/LCD_DB1)
(add_net /hackrf_if/LCD_DB10)
(add_net /hackrf_if/LCD_DB11)
(add_net /hackrf_if/LCD_DB12)
(add_net /hackrf_if/LCD_DB13)
(add_net /hackrf_if/LCD_DB14)
(add_net /hackrf_if/LCD_DB15)
(add_net /hackrf_if/LCD_DB2)
(add_net /hackrf_if/LCD_DB3)
(add_net /hackrf_if/LCD_DB4)
(add_net /hackrf_if/LCD_DB5)
(add_net /hackrf_if/LCD_DB6)
(add_net /hackrf_if/LCD_DB7)
(add_net /hackrf_if/LCD_DB8)
(add_net /hackrf_if/LCD_DB9)
(add_net /hackrf_if/LCD_RD#)
(add_net /hackrf_if/LCD_RESET#)
(add_net /hackrf_if/LCD_RS)
(add_net /hackrf_if/LCD_TE)
(add_net /hackrf_if/LCD_WR#)
Remove line in/out components and traces, microphone. Clean up traces and via stitching affected by removed components.
2015-08-24 00:23:21 +00:00
(add_net /hackrf_if/MCU_ADDR)
(add_net /hackrf_if/MCU_D0)
(add_net /hackrf_if/MCU_D1)
(add_net /hackrf_if/MCU_D2)
(add_net /hackrf_if/MCU_D3)
(add_net /hackrf_if/MCU_D4)
(add_net /hackrf_if/MCU_D5)
(add_net /hackrf_if/MCU_D6)
(add_net /hackrf_if/MCU_D7)
(add_net /hackrf_if/MCU_DIR)
(add_net /hackrf_if/MCU_IO_STBX)
(add_net /hackrf_if/MCU_LCD_RD)
(add_net /hackrf_if/MCU_LCD_TE)
(add_net /hackrf_if/MCU_LCD_WR)
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(add_net /hackrf_if/P2_8)
Remove line in/out components and traces, microphone. Clean up traces and via stitching affected by removed components.
2015-08-24 00:23:21 +00:00
(add_net /hackrf_if/PP_CPLD_TDO)
(add_net /hackrf_if/PP_CPLD_TMS)
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(add_net /hackrf_if/RESET#)
(add_net /hackrf_if/SD_CD)
(add_net /hackrf_if/SD_CLK)
(add_net /hackrf_if/SD_CMD)
(add_net /hackrf_if/SD_DAT0)
(add_net /hackrf_if/SD_DAT1)
(add_net /hackrf_if/SD_DAT2)
(add_net /hackrf_if/SD_DAT3)
(add_net /hackrf_if/SW_D)
(add_net /hackrf_if/SW_L)
(add_net /hackrf_if/SW_R)
(add_net /hackrf_if/SW_ROT_A)
(add_net /hackrf_if/SW_ROT_B)
(add_net /hackrf_if/SW_SEL)
(add_net /hackrf_if/SW_U)
(add_net /hackrf_if/TP_D)
(add_net /hackrf_if/TP_L)
(add_net /hackrf_if/TP_R)
(add_net /hackrf_if/TP_U)
(add_net /hackrf_if/VBAT)
(add_net GND)
(add_net "Net-(C18-Pad2)")
(add_net "Net-(C19-Pad2)")
(add_net "Net-(C24-Pad1)")
(add_net "Net-(C24-Pad2)")
(add_net "Net-(C39-Pad1)")
(add_net "Net-(J3-Pad1)")
(add_net "Net-(L4-Pad1)")
(add_net "Net-(L5-Pad1)")
(add_net "Net-(L6-Pad1)")
(add_net "Net-(L9-Pad1)")
Remove line in/out components and traces, microphone. Clean up traces and via stitching affected by removed components.
2015-08-24 00:23:21 +00:00
(add_net "Net-(P2-Pad5)")
(add_net "Net-(P2-Pad6)")
(add_net "Net-(P20-Pad17)")
(add_net "Net-(P20-Pad2)")
(add_net "Net-(P20-Pad21)")
(add_net "Net-(P20-Pad22)")
(add_net "Net-(P20-Pad4)")
(add_net "Net-(P22-Pad1)")
(add_net "Net-(P22-Pad12)")
(add_net "Net-(P22-Pad14)")
(add_net "Net-(P22-Pad2)")
(add_net "Net-(P22-Pad25)")
(add_net "Net-(P22-Pad7)")
(add_net "Net-(P22-Pad8)")
(add_net "Net-(P22-Pad9)")
(add_net "Net-(P28-Pad13)")
(add_net "Net-(P28-Pad14)")
(add_net "Net-(P28-Pad15)")
(add_net "Net-(P28-Pad16)")
(add_net "Net-(P28-Pad18)")
(add_net "Net-(P28-Pad20)")
(add_net "Net-(P28-Pad21)")
(add_net "Net-(P28-Pad22)")
(add_net "Net-(U1-Pad12)")
(add_net "Net-(U1-Pad13)")
(add_net "Net-(U1-Pad19)")
(add_net "Net-(U1-Pad2)")
(add_net "Net-(U1-Pad20)")
(add_net "Net-(U1-Pad26)")
(add_net "Net-(U3-Pad35)")
(add_net "Net-(U3-Pad36)")
(add_net "Net-(U3-Pad37)")
(add_net "Net-(U3-Pad5)")
(add_net "Net-(U3-Pad7)")
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
(module bat_coin:MPD_BU2032SM-BT-G locked (layer 4_bot) (tedit 53B09B28) (tstamp 53AA25F0)
(at 97 160 180)
(path /53A8C780/53A8D535)
(attr smd)
(fp_text reference BT1 (at -12.6 4.2 180) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_text value BATTERY (at 0 0 180) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -12 -5) (end -11 -5) (layer B.SilkS) (width 0.1524))
(fp_line (start -11.5 -4.5) (end -11.5 -5.5) (layer B.SilkS) (width 0.1524))
(fp_circle (center 0 0) (end 10 0) (layer Cmts.User) (width 0.1524))
(fp_arc (start 0 0) (end -7.838 -8) (angle -91.2) (layer B.SilkS) (width 0.1524))
(fp_arc (start 0 0) (end 7.838 8) (angle -91.2) (layer B.SilkS) (width 0.1524))
(fp_line (start -7.838 -8) (end 7.838 -8) (layer B.SilkS) (width 0.1524))
(fp_line (start -7.838 8) (end 7.838 8) (layer B.SilkS) (width 0.1524))
(fp_line (start 10.639 3.5) (end 14.3 3.5) (layer B.SilkS) (width 0.1524))
(fp_line (start 14.3 3.5) (end 14.3 -3.5) (layer B.SilkS) (width 0.1524))
(fp_line (start 14.3 -3.5) (end 10.639 -3.5) (layer B.SilkS) (width 0.1524))
(fp_line (start -10.639 3.5) (end -14.3 3.5) (layer B.SilkS) (width 0.1524))
(fp_line (start -14.3 3.5) (end -14.3 -3.5) (layer B.SilkS) (width 0.1524))
(fp_line (start -14.3 -3.5) (end -10.639 -3.5) (layer B.SilkS) (width 0.1524))
(pad 1 smd rect (at -14.65 0 180) (size 3.2 4.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 57 /hackrf_if/VBAT))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 2 smd rect (at 14.65 0 180) (size 3.2 4.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
(module ipc_capc:IPC_CAPC1005X55N (layer 4_bot) (tedit 53B0991D) (tstamp 53AA2604)
(at 142 119.8 180)
(path /53A8BFC3/53A8C6A5)
(attr smd)
(fp_text reference C2 (at 0.2 -1.2 180) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_text value 100N (at 0 0 180) (layer B.SilkS) hide
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_line (start 0.90932 0.45974) (end 0.90932 -0.45974) (layer B.SilkS) (width 0.1524))
(fp_line (start 0.90932 -0.45974) (end -0.90932 -0.45974) (layer B.SilkS) (width 0.1524))
(fp_line (start -0.90932 -0.45974) (end -0.90932 0.45974) (layer B.SilkS) (width 0.1524))
(fp_line (start -0.90932 0.45974) (end 0.90932 0.45974) (layer B.SilkS) (width 0.1524))
(pad 1 smd rect (at -0.44958 0 180) (size 0.61976 0.61976) (layers 4_bot B.Paste B.Mask)
(net 2 +3.3V))
(pad 2 smd rect (at 0.44958 0 180) (size 0.61976 0.61976) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
(module ipc_capc:IPC_CAPC1005X55N (layer 4_bot) (tedit 53BC270F) (tstamp 53AA260E)
(at 136.6 119.8 180)
(path /53A8BFC3/53A8C69F)
(attr smd)
(fp_text reference C3 (at 5.1 -0.7 180) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_text value 100N (at 0 0 180) (layer B.SilkS) hide
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_line (start 0.90932 0.45974) (end 0.90932 -0.45974) (layer B.SilkS) (width 0.1524))
(fp_line (start 0.90932 -0.45974) (end -0.90932 -0.45974) (layer B.SilkS) (width 0.1524))
(fp_line (start -0.90932 -0.45974) (end -0.90932 0.45974) (layer B.SilkS) (width 0.1524))
(fp_line (start -0.90932 0.45974) (end 0.90932 0.45974) (layer B.SilkS) (width 0.1524))
(pad 1 smd rect (at -0.44958 0 180) (size 0.61976 0.61976) (layers 4_bot B.Paste B.Mask)
(net 2 +3.3V))
(pad 2 smd rect (at 0.44958 0 180) (size 0.61976 0.61976) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
(module ipc_capc:IPC_CAPC1005X55N (layer 4_bot) (tedit 53BC2708) (tstamp 53AA2618)
(at 133.6 119.8)
(path /53A8BFC3/53A8C6B1)
(attr smd)
(fp_text reference C4 (at -3.9 0.7) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_text value 100N (at 0 0) (layer B.SilkS) hide
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_line (start 0.90932 0.45974) (end 0.90932 -0.45974) (layer B.SilkS) (width 0.1524))
(fp_line (start 0.90932 -0.45974) (end -0.90932 -0.45974) (layer B.SilkS) (width 0.1524))
(fp_line (start -0.90932 -0.45974) (end -0.90932 0.45974) (layer B.SilkS) (width 0.1524))
(fp_line (start -0.90932 0.45974) (end 0.90932 0.45974) (layer B.SilkS) (width 0.1524))
(pad 1 smd rect (at -0.44958 0) (size 0.61976 0.61976) (layers 4_bot B.Paste B.Mask)
(net 2 +3.3V))
(pad 2 smd rect (at 0.44958 0) (size 0.61976 0.61976) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
(module ipc_capc:IPC_CAPC1005X55N (layer 4_bot) (tedit 53B09A42) (tstamp 53AA2622)
(at 142 108.2)
(path /53A8BFC3/53A8C6AB)
(attr smd)
(fp_text reference C5 (at -11.8 0.6) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_text value 100N (at 0 0) (layer B.SilkS) hide
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_line (start 0.90932 0.45974) (end 0.90932 -0.45974) (layer B.SilkS) (width 0.1524))
(fp_line (start 0.90932 -0.45974) (end -0.90932 -0.45974) (layer B.SilkS) (width 0.1524))
(fp_line (start -0.90932 -0.45974) (end -0.90932 0.45974) (layer B.SilkS) (width 0.1524))
(fp_line (start -0.90932 0.45974) (end 0.90932 0.45974) (layer B.SilkS) (width 0.1524))
(pad 1 smd rect (at -0.44958 0) (size 0.61976 0.61976) (layers 4_bot B.Paste B.Mask)
(net 2 +3.3V))
(pad 2 smd rect (at 0.44958 0) (size 0.61976 0.61976) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
(module ipc_capc:IPC_CAPC1005X55N (layer 4_bot) (tedit 53B09A37) (tstamp 53B0A490)
(at 133.2 108.6 180)
(path /53A8BFC3/53A8C687)
(attr smd)
(fp_text reference C6 (at 8.6 -0.4 180) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_text value 100N (at 0 0 180) (layer B.SilkS) hide
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_line (start 0.90932 0.45974) (end 0.90932 -0.45974) (layer B.SilkS) (width 0.1524))
(fp_line (start 0.90932 -0.45974) (end -0.90932 -0.45974) (layer B.SilkS) (width 0.1524))
(fp_line (start -0.90932 -0.45974) (end -0.90932 0.45974) (layer B.SilkS) (width 0.1524))
(fp_line (start -0.90932 0.45974) (end 0.90932 0.45974) (layer B.SilkS) (width 0.1524))
(pad 1 smd rect (at -0.44958 0 180) (size 0.61976 0.61976) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 14 /audio/VMID))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 2 smd rect (at 0.44958 0 180) (size 0.61976 0.61976) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
(module ipc_capc:IPC_CAPC1005X55N (layer 4_bot) (tedit 53B09A3C) (tstamp 53B0A4A6)
(at 135.4 108.2)
(path /53A8BFC3/53A8C68D)
(attr smd)
(fp_text reference C10 (at -9.2 0.6) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_text value 100N (at 0 0) (layer B.SilkS) hide
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_line (start 0.90932 0.45974) (end 0.90932 -0.45974) (layer B.SilkS) (width 0.1524))
(fp_line (start 0.90932 -0.45974) (end -0.90932 -0.45974) (layer B.SilkS) (width 0.1524))
(fp_line (start -0.90932 -0.45974) (end -0.90932 0.45974) (layer B.SilkS) (width 0.1524))
(fp_line (start -0.90932 0.45974) (end 0.90932 0.45974) (layer B.SilkS) (width 0.1524))
(pad 1 smd rect (at -0.44958 0) (size 0.61976 0.61976) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 9 /audio/MICBIAS))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 2 smd rect (at 0.44958 0) (size 0.61976 0.61976) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
Footprint cleanup Remove courtyard lines from silkscreen. Round coordinates/dimensions to correct values (KiCad's old units don't convert nicely to the new units). Restore U3 refdes silkscreen visibility.
2015-08-30 00:14:06 +00:00
(module ipc_capae:IPC_CAPAE830X620N (layer 4_bot) (tedit 55E24037) (tstamp 53AA43B4)
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(at 154.2 120)
(tags "CASE E")
(path /53A8BFC3/53A8C256)
(fp_text reference C18 (at -4.4 -4) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_text value 220U (at 0 0) (layer B.SilkS)
(effects (font (thickness 0.3048)) (justify mirror))
)
Footprint cleanup Remove courtyard lines from silkscreen. Round coordinates/dimensions to correct values (KiCad's old units don't convert nicely to the new units). Restore U3 refdes silkscreen visibility.
2015-08-30 00:14:06 +00:00
(fp_line (start -4.2 2.4) (end -4.2 -2.4) (layer B.SilkS) (width 0.1524))
(fp_line (start 4.2 4.2) (end -2.4 4.2) (layer B.SilkS) (width 0.1524))
(fp_line (start -2.4 -4.2) (end 4.2 -4.2) (layer B.SilkS) (width 0.1524))
(fp_line (start -4.2 -2.4) (end -2.4 -4.2) (layer B.SilkS) (width 0.1524))
(fp_line (start -4.2 2.4) (end -2.4 4.2) (layer B.SilkS) (width 0.1524))
(fp_line (start 4.2 -4.2) (end 4.2 4.2) (layer B.SilkS) (width 0.1524))
(fp_circle (center 0 0) (end 4 0) (layer B.SilkS) (width 0.1524))
(fp_line (start -5.725 4.75) (end 5.725 4.75) (layer B.CrtYd) (width 0.1524))
(fp_line (start 5.725 4.75) (end 5.725 -4.75) (layer B.CrtYd) (width 0.1524))
(fp_line (start 5.725 -4.75) (end -5.725 -4.75) (layer B.CrtYd) (width 0.1524))
(fp_line (start -5.725 -4.75) (end -5.725 4.75) (layer B.CrtYd) (width 0.1524))
(pad 1 smd rect (at -3.15 0) (size 4.15 1.6) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 8 /audio/LHPOUT))
Footprint cleanup Remove courtyard lines from silkscreen. Round coordinates/dimensions to correct values (KiCad's old units don't convert nicely to the new units). Restore U3 refdes silkscreen visibility.
2015-08-30 00:14:06 +00:00
(pad 2 smd rect (at 3.15 0) (size 4.15 1.6) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 59 "Net-(C18-Pad2)"))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
Footprint cleanup Remove courtyard lines from silkscreen. Round coordinates/dimensions to correct values (KiCad's old units don't convert nicely to the new units). Restore U3 refdes silkscreen visibility.
2015-08-30 00:14:06 +00:00
(module ipc_capae:IPC_CAPAE830X620N (layer 4_bot) (tedit 55E24037) (tstamp 53AA26CA)
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(at 154.2 110)
(tags "CASE E")
(path /53A8BFC3/53A8C25E)
(fp_text reference C19 (at -4.4 4) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_text value 220U (at 0 0) (layer B.SilkS)
(effects (font (thickness 0.3048)) (justify mirror))
)
Footprint cleanup Remove courtyard lines from silkscreen. Round coordinates/dimensions to correct values (KiCad's old units don't convert nicely to the new units). Restore U3 refdes silkscreen visibility.
2015-08-30 00:14:06 +00:00
(fp_line (start -4.2 2.4) (end -4.2 -2.4) (layer B.SilkS) (width 0.1524))
(fp_line (start 4.2 4.2) (end -2.4 4.2) (layer B.SilkS) (width 0.1524))
(fp_line (start -2.4 -4.2) (end 4.2 -4.2) (layer B.SilkS) (width 0.1524))
(fp_line (start -4.2 -2.4) (end -2.4 -4.2) (layer B.SilkS) (width 0.1524))
(fp_line (start -4.2 2.4) (end -2.4 4.2) (layer B.SilkS) (width 0.1524))
(fp_line (start 4.2 -4.2) (end 4.2 4.2) (layer B.SilkS) (width 0.1524))
(fp_circle (center 0 0) (end 4 0) (layer B.SilkS) (width 0.1524))
(fp_line (start -5.725 4.75) (end 5.725 4.75) (layer B.CrtYd) (width 0.1524))
(fp_line (start 5.725 4.75) (end 5.725 -4.75) (layer B.CrtYd) (width 0.1524))
(fp_line (start 5.725 -4.75) (end -5.725 -4.75) (layer B.CrtYd) (width 0.1524))
(fp_line (start -5.725 -4.75) (end -5.725 4.75) (layer B.CrtYd) (width 0.1524))
(pad 1 smd rect (at -3.15 0) (size 4.15 1.6) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 11 /audio/RHPOUT))
Footprint cleanup Remove courtyard lines from silkscreen. Round coordinates/dimensions to correct values (KiCad's old units don't convert nicely to the new units). Restore U3 refdes silkscreen visibility.
2015-08-30 00:14:06 +00:00
(pad 2 smd rect (at 3.15 0) (size 4.15 1.6) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 60 "Net-(C19-Pad2)"))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
(module ipc_capc:IPC_CAPC1608X95N (layer 4_bot) (tedit 53B09A86) (tstamp 53AA26F6)
(at 162.8 120.8 90)
(tags "1608 metric, 0603 imperial")
(path /53A8BFC3/53A8C27E)
(attr smd)
(fp_text reference C22 (at -3.2 0 90) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_text value 220P (at 0 0 90) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_line (start -1.524 0.7493) (end 1.524 0.7493) (layer B.SilkS) (width 0.1524))
(fp_line (start 1.524 0.7493) (end 1.524 -0.7493) (layer B.SilkS) (width 0.1524))
(fp_line (start 1.524 -0.7493) (end -1.524 -0.7493) (layer B.SilkS) (width 0.1524))
(fp_line (start -1.524 -0.7493) (end -1.524 0.7493) (layer B.SilkS) (width 0.1524))
(pad 1 smd rect (at -0.8001 0 90) (size 0.94996 1.00076) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 2 smd rect (at 0.8001 0 90) (size 0.94996 1.00076) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 59 "Net-(C18-Pad2)"))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
(module ipc_capc:IPC_CAPC1608X95N (layer 4_bot) (tedit 53B09A77) (tstamp 53AA2700)
(at 162.8 109.2 90)
(tags "1608 metric, 0603 imperial")
(path /53A8BFC3/53A8C284)
(attr smd)
(fp_text reference C23 (at 3.2 0 90) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_text value 220P (at 0 0 90) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_line (start -1.524 0.7493) (end 1.524 0.7493) (layer B.SilkS) (width 0.1524))
(fp_line (start 1.524 0.7493) (end 1.524 -0.7493) (layer B.SilkS) (width 0.1524))
(fp_line (start 1.524 -0.7493) (end -1.524 -0.7493) (layer B.SilkS) (width 0.1524))
(fp_line (start -1.524 -0.7493) (end -1.524 0.7493) (layer B.SilkS) (width 0.1524))
(pad 1 smd rect (at -0.8001 0 90) (size 0.94996 1.00076) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 60 "Net-(C19-Pad2)"))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 2 smd rect (at 0.8001 0 90) (size 0.94996 1.00076) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
Footprint cleanup Remove courtyard lines from silkscreen. Round coordinates/dimensions to correct values (KiCad's old units don't convert nicely to the new units). Restore U3 refdes silkscreen visibility.
2015-08-30 00:14:06 +00:00
(module ipc_capae:IPC_CAPAE430X540N (layer 4_bot) (tedit 55E23F71) (tstamp 53ADFB14)
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(at 141.8 104.4 180)
(tags "CASE B")
(path /53A8BFC3/53A8C2AA)
(fp_text reference C24 (at -2.6 2.2 180) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_text value 1U (at 0 0 180) (layer B.SilkS)
(effects (font (thickness 0.3048)) (justify mirror))
)
Footprint cleanup Remove courtyard lines from silkscreen. Round coordinates/dimensions to correct values (KiCad's old units don't convert nicely to the new units). Restore U3 refdes silkscreen visibility.
2015-08-30 00:14:06 +00:00
(fp_line (start 3.525 -2.75) (end -3.525 -2.75) (layer B.CrtYd) (width 0.1524))
(fp_line (start -3.525 -2.75) (end -3.525 2.75) (layer B.CrtYd) (width 0.1524))
(fp_line (start -3.525 2.75) (end 3.525 2.75) (layer B.CrtYd) (width 0.1524))
(fp_line (start 3.525 2.75) (end 3.525 -2.75) (layer B.CrtYd) (width 0.1524))
(fp_line (start 2.15 2.15) (end -1.25 2.15) (layer B.SilkS) (width 0.1524))
(fp_line (start -2.15 -1.25) (end -2.15 1.25) (layer B.SilkS) (width 0.1524))
(fp_line (start -1.25 -2.15) (end 2.15 -2.15) (layer B.SilkS) (width 0.1524))
(fp_line (start -2.15 -1.25) (end -1.25 -2.15) (layer B.SilkS) (width 0.1524))
(fp_line (start -2.15 1.25) (end -1.25 2.15) (layer B.SilkS) (width 0.1524))
(fp_circle (center 0 0) (end 2 0) (layer B.SilkS) (width 0.1524))
(fp_line (start 2.15 2.15) (end 2.15 -2.15) (layer B.SilkS) (width 0.1524))
(pad 1 smd rect (at -1.75 0 180) (size 2.55 1.6) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 61 "Net-(C24-Pad1)"))
Footprint cleanup Remove courtyard lines from silkscreen. Round coordinates/dimensions to correct values (KiCad's old units don't convert nicely to the new units). Restore U3 refdes silkscreen visibility.
2015-08-30 00:14:06 +00:00
(pad 2 smd rect (at 1.75 0 180) (size 2.55 1.6) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 62 "Net-(C24-Pad2)"))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
(module ipc_capc:IPC_CAPC1608X95N (layer 4_bot) (tedit 53B09AB4) (tstamp 53AA271B)
(at 170.8 122.2 180)
(tags "1608 metric, 0603 imperial")
(path /53A8BFC3/53A8C2A2)
(attr smd)
(fp_text reference C25 (at -0.8 1.4 180) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_text value 220P (at 0 0 180) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_line (start -1.524 0.7493) (end 1.524 0.7493) (layer B.SilkS) (width 0.1524))
(fp_line (start 1.524 0.7493) (end 1.524 -0.7493) (layer B.SilkS) (width 0.1524))
(fp_line (start 1.524 -0.7493) (end -1.524 -0.7493) (layer B.SilkS) (width 0.1524))
(fp_line (start -1.524 -0.7493) (end -1.524 0.7493) (layer B.SilkS) (width 0.1524))
(pad 1 smd rect (at -0.8001 0 180) (size 0.94996 1.00076) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 62 "Net-(C24-Pad2)"))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 2 smd rect (at 0.8001 0 180) (size 0.94996 1.00076) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
(module ipc_capc:IPC_CAPC1005X55N (layer 4_bot) (tedit 53B0979B) (tstamp 53AA272F)
(at 72.2 122.8)
(path /53A9129D/53AA73CE)
(attr smd)
(fp_text reference C27 (at -1 1.8) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_text value 100N (at 0 0) (layer B.SilkS) hide
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_line (start 0.90932 0.45974) (end 0.90932 -0.45974) (layer B.SilkS) (width 0.1524))
(fp_line (start 0.90932 -0.45974) (end -0.90932 -0.45974) (layer B.SilkS) (width 0.1524))
(fp_line (start -0.90932 -0.45974) (end -0.90932 0.45974) (layer B.SilkS) (width 0.1524))
(fp_line (start -0.90932 0.45974) (end 0.90932 0.45974) (layer B.SilkS) (width 0.1524))
(pad 1 smd rect (at -0.44958 0) (size 0.61976 0.61976) (layers 4_bot B.Paste B.Mask)
(net 2 +3.3V))
(pad 2 smd rect (at 0.44958 0) (size 0.61976 0.61976) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
(module ipc_capc:IPC_CAPC1005X55N (layer 4_bot) (tedit 53C5B500) (tstamp 53AA2739)
(at 96 125.2 90)
(path /53A8C780/53A8D527)
(attr smd)
(fp_text reference C28 (at 0.8 -1.2 90) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_text value 100N (at 0 0 90) (layer B.SilkS) hide
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_line (start 0.90932 0.45974) (end 0.90932 -0.45974) (layer B.SilkS) (width 0.1524))
(fp_line (start 0.90932 -0.45974) (end -0.90932 -0.45974) (layer B.SilkS) (width 0.1524))
(fp_line (start -0.90932 -0.45974) (end -0.90932 0.45974) (layer B.SilkS) (width 0.1524))
(fp_line (start -0.90932 0.45974) (end 0.90932 0.45974) (layer B.SilkS) (width 0.1524))
(pad 1 smd rect (at -0.44958 0 90) (size 0.61976 0.61976) (layers 4_bot B.Paste B.Mask)
(net 2 +3.3V))
(pad 2 smd rect (at 0.44958 0 90) (size 0.61976 0.61976) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
(module ipc_capc:IPC_CAPC1005X55N (layer 4_bot) (tedit 53B097F7) (tstamp 53AB74CF)
(at 97.2 125.2 90)
(path /53A8C780/53A8D548)
(attr smd)
(fp_text reference C29 (at 0 1.8 90) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_text value 100N (at 0 0 90) (layer B.SilkS) hide
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_line (start 0.90932 0.45974) (end 0.90932 -0.45974) (layer B.SilkS) (width 0.1524))
(fp_line (start 0.90932 -0.45974) (end -0.90932 -0.45974) (layer B.SilkS) (width 0.1524))
(fp_line (start -0.90932 -0.45974) (end -0.90932 0.45974) (layer B.SilkS) (width 0.1524))
(fp_line (start -0.90932 0.45974) (end 0.90932 0.45974) (layer B.SilkS) (width 0.1524))
(pad 1 smd rect (at -0.44958 0 90) (size 0.61976 0.61976) (layers 4_bot B.Paste B.Mask)
(net 1 +1.8V))
(pad 2 smd rect (at 0.44958 0 90) (size 0.61976 0.61976) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
(module ipc_capc:IPC_CAPC1005X55N (layer 4_bot) (tedit 53B09B39) (tstamp 53AA274D)
(at 106 132.2)
(path /53A8C780/53A8D542)
(attr smd)
(fp_text reference C30 (at 0 -1.2) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_text value 100N (at 0 0) (layer B.SilkS) hide
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_line (start 0.90932 0.45974) (end 0.90932 -0.45974) (layer B.SilkS) (width 0.1524))
(fp_line (start 0.90932 -0.45974) (end -0.90932 -0.45974) (layer B.SilkS) (width 0.1524))
(fp_line (start -0.90932 -0.45974) (end -0.90932 0.45974) (layer B.SilkS) (width 0.1524))
(fp_line (start -0.90932 0.45974) (end 0.90932 0.45974) (layer B.SilkS) (width 0.1524))
(pad 1 smd rect (at -0.44958 0) (size 0.61976 0.61976) (layers 4_bot B.Paste B.Mask)
(net 2 +3.3V))
(pad 2 smd rect (at 0.44958 0) (size 0.61976 0.61976) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
(module ipc_capc:IPC_CAPC1005X55N (layer 4_bot) (tedit 53B09B82) (tstamp 53AA2757)
(at 98.6 141.2 270)
(path /53A8C780/53A8D54E)
(attr smd)
(fp_text reference C31 (at -1.8 -1.2 270) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_text value 100N (at 0 0 270) (layer B.SilkS) hide
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_line (start 0.90932 0.45974) (end 0.90932 -0.45974) (layer B.SilkS) (width 0.1524))
(fp_line (start 0.90932 -0.45974) (end -0.90932 -0.45974) (layer B.SilkS) (width 0.1524))
(fp_line (start -0.90932 -0.45974) (end -0.90932 0.45974) (layer B.SilkS) (width 0.1524))
(fp_line (start -0.90932 0.45974) (end 0.90932 0.45974) (layer B.SilkS) (width 0.1524))
(pad 1 smd rect (at -0.44958 0 270) (size 0.61976 0.61976) (layers 4_bot B.Paste B.Mask)
(net 1 +1.8V))
(pad 2 smd rect (at 0.44958 0 270) (size 0.61976 0.61976) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
(module ipc_capc:IPC_CAPC1005X55N (layer 4_bot) (tedit 53B09B7D) (tstamp 53AA276B)
(at 97 141.2 270)
(path /53A8C780/53A8D56C)
(attr smd)
(fp_text reference C33 (at -1.8 1.2 270) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_text value 100N (at 0 0 270) (layer B.SilkS) hide
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_line (start 0.90932 0.45974) (end 0.90932 -0.45974) (layer B.SilkS) (width 0.1524))
(fp_line (start 0.90932 -0.45974) (end -0.90932 -0.45974) (layer B.SilkS) (width 0.1524))
(fp_line (start -0.90932 -0.45974) (end -0.90932 0.45974) (layer B.SilkS) (width 0.1524))
(fp_line (start -0.90932 0.45974) (end 0.90932 0.45974) (layer B.SilkS) (width 0.1524))
(pad 1 smd rect (at -0.44958 0 270) (size 0.61976 0.61976) (layers 4_bot B.Paste B.Mask)
(net 1 +1.8V))
(pad 2 smd rect (at 0.44958 0 270) (size 0.61976 0.61976) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
(module ipc_capc:IPC_CAPC1005X55N (layer 4_bot) (tedit 53B097B0) (tstamp 53B30722)
(at 89.5 132.6 180)
(path /53A8C780/53A8D572)
(attr smd)
(fp_text reference C35 (at 0 1.2 180) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_text value 100N (at 0 0 180) (layer B.SilkS) hide
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_line (start 0.90932 0.45974) (end 0.90932 -0.45974) (layer B.SilkS) (width 0.1524))
(fp_line (start 0.90932 -0.45974) (end -0.90932 -0.45974) (layer B.SilkS) (width 0.1524))
(fp_line (start -0.90932 -0.45974) (end -0.90932 0.45974) (layer B.SilkS) (width 0.1524))
(fp_line (start -0.90932 0.45974) (end 0.90932 0.45974) (layer B.SilkS) (width 0.1524))
(pad 1 smd rect (at -0.44958 0 180) (size 0.61976 0.61976) (layers 4_bot B.Paste B.Mask)
(net 1 +1.8V))
(pad 2 smd rect (at 0.44958 0 180) (size 0.61976 0.61976) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
(module ipc_capc:IPC_CAPC1608X90N (layer 4_bot) (tedit 53B09B4A) (tstamp 53AA27A7)
(at 97.4 150.6)
(path /53A8C780/53A8D5AA)
(attr smd)
(fp_text reference C39 (at 2.8 0.8) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_text value DNI (at 0 0) (layer B.SilkS)
(effects (font (thickness 0.3048)) (justify mirror))
)
(fp_line (start -1.524 0.7493) (end 1.524 0.7493) (layer B.SilkS) (width 0.2032))
(fp_line (start 1.524 0.7493) (end 1.524 -0.7493) (layer B.SilkS) (width 0.2032))
(fp_line (start 1.524 -0.7493) (end -1.524 -0.7493) (layer B.SilkS) (width 0.2032))
(fp_line (start -1.524 -0.7493) (end -1.524 0.7493) (layer B.SilkS) (width 0.2032))
(pad 1 smd rect (at -0.8001 0) (size 0.94996 1.00076) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 63 "Net-(C39-Pad1)"))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 2 smd rect (at 0.8001 0) (size 0.94996 1.00076) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
(module hole:HOLE_3200UM_VIAS (layer 1_top) (tedit 53AA3E1E) (tstamp 53AA27D5)
(at 176 104)
(path /5369BBD8)
(fp_text reference H2 (at 0 0) (layer F.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)))
)
(fp_text value HOLE1 (at 0 0) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.1524)))
)
(pad 1 thru_hole circle (at 0 0) (size 5.6 5.6) (drill 3.2) (layers *.Cu *.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 1 thru_hole circle (at 0 -2.2) (size 0.6 0.6) (drill 0.381) (layers *.Cu *.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 1 thru_hole circle (at -2.2 0) (size 0.6 0.6) (drill 0.381) (layers *.Cu *.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 1 thru_hole circle (at 0 2.2) (size 0.6 0.6) (drill 0.381) (layers *.Cu *.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 1 thru_hole circle (at 2.2 0) (size 0.6 0.6) (drill 0.381) (layers *.Cu *.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 1 thru_hole circle (at 1.55 -1.55) (size 0.6 0.6) (drill 0.381) (layers *.Cu *.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 1 thru_hole circle (at -1.55 -1.55) (size 0.6 0.6) (drill 0.381) (layers *.Cu *.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 1 thru_hole circle (at -1.55 1.55) (size 0.6 0.6) (drill 0.381) (layers *.Cu *.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 1 thru_hole circle (at 1.55 1.55) (size 0.6 0.6) (drill 0.381) (layers *.Cu *.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
(module hole:HOLE_3200UM_VIAS (layer 1_top) (tedit 53AA3E1E) (tstamp 53AA27E2)
(at 176 171)
(path /5369BBEC)
(fp_text reference H3 (at 0 0) (layer F.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)))
)
(fp_text value HOLE1 (at 0 0) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.1524)))
)
(pad 1 thru_hole circle (at 0 0) (size 5.6 5.6) (drill 3.2) (layers *.Cu *.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 1 thru_hole circle (at 0 -2.2) (size 0.6 0.6) (drill 0.381) (layers *.Cu *.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 1 thru_hole circle (at -2.2 0) (size 0.6 0.6) (drill 0.381) (layers *.Cu *.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 1 thru_hole circle (at 0 2.2) (size 0.6 0.6) (drill 0.381) (layers *.Cu *.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 1 thru_hole circle (at 2.2 0) (size 0.6 0.6) (drill 0.381) (layers *.Cu *.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 1 thru_hole circle (at 1.55 -1.55) (size 0.6 0.6) (drill 0.381) (layers *.Cu *.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 1 thru_hole circle (at -1.55 -1.55) (size 0.6 0.6) (drill 0.381) (layers *.Cu *.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 1 thru_hole circle (at -1.55 1.55) (size 0.6 0.6) (drill 0.381) (layers *.Cu *.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 1 thru_hole circle (at 1.55 1.55) (size 0.6 0.6) (drill 0.381) (layers *.Cu *.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
(module hole:HOLE_3200UM_VIAS (layer 1_top) (tedit 53AA3E1E) (tstamp 53AA27EF)
(at 64 171)
(path /5369BC00)
(fp_text reference H4 (at 0 0) (layer F.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)))
)
(fp_text value HOLE1 (at 0 0) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.1524)))
)
(pad 1 thru_hole circle (at 0 0) (size 5.6 5.6) (drill 3.2) (layers *.Cu *.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 1 thru_hole circle (at 0 -2.2) (size 0.6 0.6) (drill 0.381) (layers *.Cu *.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 1 thru_hole circle (at -2.2 0) (size 0.6 0.6) (drill 0.381) (layers *.Cu *.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 1 thru_hole circle (at 0 2.2) (size 0.6 0.6) (drill 0.381) (layers *.Cu *.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 1 thru_hole circle (at 2.2 0) (size 0.6 0.6) (drill 0.381) (layers *.Cu *.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 1 thru_hole circle (at 1.55 -1.55) (size 0.6 0.6) (drill 0.381) (layers *.Cu *.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 1 thru_hole circle (at -1.55 -1.55) (size 0.6 0.6) (drill 0.381) (layers *.Cu *.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 1 thru_hole circle (at -1.55 1.55) (size 0.6 0.6) (drill 0.381) (layers *.Cu *.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 1 thru_hole circle (at 1.55 1.55) (size 0.6 0.6) (drill 0.381) (layers *.Cu *.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
(module hole:HOLE_3200UM_VIAS (layer 1_top) (tedit 53AA3E1E) (tstamp 53AA27FC)
(at 64 104)
(path /5369BC14)
(fp_text reference H5 (at 0 0) (layer F.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)))
)
(fp_text value HOLE1 (at 0 0) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.1524)))
)
(pad 1 thru_hole circle (at 0 0) (size 5.6 5.6) (drill 3.2) (layers *.Cu *.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 1 thru_hole circle (at 0 -2.2) (size 0.6 0.6) (drill 0.381) (layers *.Cu *.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 1 thru_hole circle (at -2.2 0) (size 0.6 0.6) (drill 0.381) (layers *.Cu *.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 1 thru_hole circle (at 0 2.2) (size 0.6 0.6) (drill 0.381) (layers *.Cu *.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 1 thru_hole circle (at 2.2 0) (size 0.6 0.6) (drill 0.381) (layers *.Cu *.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 1 thru_hole circle (at 1.55 -1.55) (size 0.6 0.6) (drill 0.381) (layers *.Cu *.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 1 thru_hole circle (at -1.55 -1.55) (size 0.6 0.6) (drill 0.381) (layers *.Cu *.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 1 thru_hole circle (at -1.55 1.55) (size 0.6 0.6) (drill 0.381) (layers *.Cu *.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 1 thru_hole circle (at 1.55 1.55) (size 0.6 0.6) (drill 0.381) (layers *.Cu *.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
(module molex:MOLEX_54132-40XX_LR locked (layer 4_bot) (tedit 53B09BB0) (tstamp 53AA2868)
(at 82.5 137.5 90)
(path /53A9129D/53A91651)
Tighten solder mask around LCD connector. Shooting for 4mil mask web between pads.
2015-08-30 21:35:04 +00:00
(solder_mask_margin 0.0492)
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(attr smd)
(fp_text reference J3 (at -13.1 2.1 90) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_text value KINGTECH_DW0240A2BZ_FPC (at 0 0 90) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -10.25 1.1) (end -10.25 -2.5) (layer Eco1.User) (width 0.1524))
(fp_line (start 10.25 -2.5) (end 10.25 1.1) (layer Eco1.User) (width 0.1524))
(fp_line (start -10.25 1.1) (end 10.25 1.1) (layer Eco1.User) (width 0.1524))
(fp_line (start 12.15 -3.2) (end 12.15 -2.5) (layer Eco1.User) (width 0.1524))
(fp_line (start -12.15 -3.2) (end -12.15 -2.5) (layer Eco1.User) (width 0.1524))
(fp_line (start -12.75 -2.5) (end 12.75 -2.5) (layer B.SilkS) (width 0.1524))
(fp_line (start -12.75 -2.5) (end -12.75 -1.5) (layer B.SilkS) (width 0.1524))
(fp_line (start -12.75 -1.5) (end -12.15 -1.5) (layer B.SilkS) (width 0.1524))
(fp_line (start -12.15 -1.5) (end -12.15 2.5) (layer B.SilkS) (width 0.1524))
(fp_line (start 12.75 -2.5) (end 12.75 -1.5) (layer B.SilkS) (width 0.1524))
(fp_line (start 12.75 -1.5) (end 12.15 -1.5) (layer B.SilkS) (width 0.1524))
(fp_line (start 12.15 -1.5) (end 12.15 2.5) (layer B.SilkS) (width 0.1524))
(fp_line (start 12.75 -4.2) (end 12.75 -3.2) (layer Eco1.User) (width 0.1524))
(fp_line (start -12.75 -4.2) (end -12.75 -3.2) (layer Eco1.User) (width 0.1524))
(fp_line (start -12.15 -4.2) (end -12.75 -4.2) (layer Eco1.User) (width 0.1524))
(fp_line (start -12.75 -3.2) (end -12.15 -3.2) (layer Eco1.User) (width 0.1524))
(fp_line (start 12.15 -4.2) (end 12.75 -4.2) (layer Eco1.User) (width 0.1524))
(fp_line (start 12.75 -3.2) (end 12.15 -3.2) (layer Eco1.User) (width 0.1524))
(fp_line (start 12.15 -4.2) (end -12.15 -4.2) (layer Eco1.User) (width 0.1524))
(fp_line (start -12.15 2.5) (end 12.15 2.5) (layer B.SilkS) (width 0.1524))
(pad 1 smd rect (at -9.75 2.8 90) (size 0.3 1.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 64 "Net-(J3-Pad1)"))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 2 smd rect (at -9.25 2.8 90) (size 0.3 1.2) (layers 4_bot B.Paste B.Mask)
(net 2 +3.3V))
(pad 3 smd rect (at -8.75 2.8 90) (size 0.3 1.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 4 smd rect (at -8.25 2.8 90) (size 0.3 1.2) (layers 4_bot B.Paste B.Mask)
(net 2 +3.3V))
(pad 5 smd rect (at -7.75 2.8 90) (size 0.3 1.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 33 /hackrf_if/LCD_RESET#))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 6 smd rect (at -7.25 2.8 90) (size 0.3 1.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 34 /hackrf_if/LCD_RS))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 7 smd rect (at -6.75 2.8 90) (size 0.3 1.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 32 /hackrf_if/LCD_RD#))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 8 smd rect (at -6.25 2.8 90) (size 0.3 1.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 9 smd rect (at -5.75 2.8 90) (size 0.3 1.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 10 smd rect (at -5.25 2.8 90) (size 0.3 1.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 36 /hackrf_if/LCD_WR#))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 11 smd rect (at -4.75 2.8 90) (size 0.3 1.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 12 smd rect (at -4.25 2.8 90) (size 0.3 1.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 13 smd rect (at -3.75 2.8 90) (size 0.3 1.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 14 smd rect (at -3.25 2.8 90) (size 0.3 1.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 15 smd rect (at -2.75 2.8 90) (size 0.3 1.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 16 smd rect (at -2.25 2.8 90) (size 0.3 1.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 17 smd rect (at -1.75 2.8 90) (size 0.3 1.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 18 smd rect (at -1.25 2.8 90) (size 0.3 1.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 23 /hackrf_if/LCD_DB15))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 19 smd rect (at -0.75 2.8 90) (size 0.3 1.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 22 /hackrf_if/LCD_DB14))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 20 smd rect (at -0.25 2.8 90) (size 0.3 1.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 21 /hackrf_if/LCD_DB13))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 21 smd rect (at 0.25 2.8 90) (size 0.3 1.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 20 /hackrf_if/LCD_DB12))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 22 smd rect (at 0.75 2.8 90) (size 0.3 1.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 19 /hackrf_if/LCD_DB11))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 23 smd rect (at 1.25 2.8 90) (size 0.3 1.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 18 /hackrf_if/LCD_DB10))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 24 smd rect (at 1.75 2.8 90) (size 0.3 1.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 31 /hackrf_if/LCD_DB9))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 25 smd rect (at 2.25 2.8 90) (size 0.3 1.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 30 /hackrf_if/LCD_DB8))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 26 smd rect (at 2.75 2.8 90) (size 0.3 1.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 29 /hackrf_if/LCD_DB7))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 27 smd rect (at 3.25 2.8 90) (size 0.3 1.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 28 /hackrf_if/LCD_DB6))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 28 smd rect (at 3.75 2.8 90) (size 0.3 1.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 27 /hackrf_if/LCD_DB5))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 29 smd rect (at 4.25 2.8 90) (size 0.3 1.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 26 /hackrf_if/LCD_DB4))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 30 smd rect (at 4.75 2.8 90) (size 0.3 1.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 25 /hackrf_if/LCD_DB3))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 31 smd rect (at 5.25 2.8 90) (size 0.3 1.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 24 /hackrf_if/LCD_DB2))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 32 smd rect (at 5.75 2.8 90) (size 0.3 1.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 17 /hackrf_if/LCD_DB1))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 33 smd rect (at 6.25 2.8 90) (size 0.3 1.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 16 /hackrf_if/LCD_DB0))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 34 smd rect (at 6.75 2.8 90) (size 0.3 1.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 35 /hackrf_if/LCD_TE))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 35 smd rect (at 7.25 2.8 90) (size 0.3 1.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 36 smd rect (at 7.75 2.8 90) (size 0.3 1.2) (layers 4_bot B.Paste B.Mask)
(net 1 +1.8V))
(pad 37 smd rect (at 8.25 2.8 90) (size 0.3 1.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 55 /hackrf_if/TP_R))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 38 smd rect (at 8.75 2.8 90) (size 0.3 1.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 53 /hackrf_if/TP_D))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 39 smd rect (at 9.25 2.8 90) (size 0.3 1.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 54 /hackrf_if/TP_L))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 40 smd rect (at 9.75 2.8 90) (size 0.3 1.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 56 /hackrf_if/TP_U))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad SHLD smd rect (at -11.45 0.9 90) (size 1.6 0.8) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad SHLD smd rect (at -11.85 -0.3 90) (size 2.4 1.6) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad SHLD smd rect (at 11.85 -0.3 90) (size 2.4 1.6) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad SHLD smd rect (at 11.45 0.9 90) (size 1.6 0.8) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
(module ipc_indc:IPC_INDC1608X95N (layer 4_bot) (tedit 53B30A63) (tstamp 53AA28A2)
(at 165.4 121.6 180)
(path /53A8BFC3/53A8C2E2)
(attr smd)
(fp_text reference L4 (at 0 -1.4 180) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_text value L (at 0 0 180) (layer B.SilkS) hide
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_line (start 1.524 0.7493) (end 1.524 -0.7493) (layer B.SilkS) (width 0.1524))
(fp_line (start 1.524 -0.7493) (end -1.524 -0.7493) (layer B.SilkS) (width 0.1524))
(fp_line (start -1.524 -0.7493) (end -1.524 0.7493) (layer B.SilkS) (width 0.1524))
(fp_line (start -1.524 0.7493) (end 1.524 0.7493) (layer B.SilkS) (width 0.1524))
(pad 1 smd rect (at -0.8001 0 180) (size 0.94996 0.94996) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 65 "Net-(L4-Pad1)"))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 2 smd rect (at 0.8001 0 180) (size 0.94996 0.94996) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 59 "Net-(C18-Pad2)"))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
(module ipc_indc:IPC_INDC1608X95N (layer 4_bot) (tedit 53B09A7D) (tstamp 53AA28AC)
(at 165.4 110 180)
(path /53A8BFC3/53A8C2E8)
(attr smd)
(fp_text reference L5 (at 0 1.4 180) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_text value L (at 0 0 180) (layer B.SilkS) hide
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_line (start 1.524 0.7493) (end 1.524 -0.7493) (layer B.SilkS) (width 0.1524))
(fp_line (start 1.524 -0.7493) (end -1.524 -0.7493) (layer B.SilkS) (width 0.1524))
(fp_line (start -1.524 -0.7493) (end -1.524 0.7493) (layer B.SilkS) (width 0.1524))
(fp_line (start -1.524 0.7493) (end 1.524 0.7493) (layer B.SilkS) (width 0.1524))
(pad 1 smd rect (at -0.8001 0 180) (size 0.94996 0.94996) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 66 "Net-(L5-Pad1)"))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 2 smd rect (at 0.8001 0 180) (size 0.94996 0.94996) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 60 "Net-(C19-Pad2)"))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
(module ipc_indc:IPC_INDC1608X95N (layer 4_bot) (tedit 53B09AA3) (tstamp 53AA28B6)
(at 174.8 121.6 180)
(path /53A8BFC3/53A8C2EE)
(attr smd)
(fp_text reference L6 (at -2.4 0 180) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_text value L (at 0 0 180) (layer B.SilkS) hide
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_line (start 1.524 0.7493) (end 1.524 -0.7493) (layer B.SilkS) (width 0.1524))
(fp_line (start 1.524 -0.7493) (end -1.524 -0.7493) (layer B.SilkS) (width 0.1524))
(fp_line (start -1.524 -0.7493) (end -1.524 0.7493) (layer B.SilkS) (width 0.1524))
(fp_line (start -1.524 0.7493) (end 1.524 0.7493) (layer B.SilkS) (width 0.1524))
(pad 1 smd rect (at -0.8001 0 180) (size 0.94996 0.94996) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 67 "Net-(L6-Pad1)"))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 2 smd rect (at 0.8001 0 180) (size 0.94996 0.94996) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
(module ipc_indc:IPC_INDC1608X95N (layer 4_bot) (tedit 53B09AA7) (tstamp 53AA28D4)
(at 174.2 124 180)
(path /53A8BFC3/53A8C2F4)
(attr smd)
(fp_text reference L9 (at -2.4 0 180) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_text value L (at 0 0 180) (layer B.SilkS) hide
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_line (start 1.524 0.7493) (end 1.524 -0.7493) (layer B.SilkS) (width 0.1524))
(fp_line (start 1.524 -0.7493) (end -1.524 -0.7493) (layer B.SilkS) (width 0.1524))
(fp_line (start -1.524 -0.7493) (end -1.524 0.7493) (layer B.SilkS) (width 0.1524))
(fp_line (start -1.524 0.7493) (end 1.524 0.7493) (layer B.SilkS) (width 0.1524))
(pad 1 smd rect (at -0.8001 0 180) (size 0.94996 0.94996) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 68 "Net-(L9-Pad1)"))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 2 smd rect (at 0.8001 0 180) (size 0.94996 0.94996) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 62 "Net-(C24-Pad2)"))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
(module lcd_kingtech:KINGTECH_DW0240A2BZ_PANEL locked (layer 1_top) (tedit 53C5BC95) (tstamp 53AA2904)
(at 62 137.5 270)
(path /53A9129D/53A8C752)
(attr smd)
(fp_text reference LCD1 (at 4.5 -4 270) (layer F.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)))
)
(fp_text value KINGTECH_DW0240A2BZ_PANEL (at 0 0 270) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -10.25 -18) (end 10.25 -18) (layer Eco2.User) (width 0.1524))
(fp_line (start -12.96 -10.72) (end -10.25 -13.39) (layer Eco2.User) (width 0.1524))
(fp_line (start 10.25 -22) (end -10.25 -22) (layer Eco2.User) (width 0.1524))
(fp_line (start -10.25 -22) (end -10.25 -13.39) (layer Eco2.User) (width 0.1524))
(fp_line (start 10.25 -12.5) (end 10.25 -22) (layer Eco2.User) (width 0.1524))
(fp_line (start 18.54 -12.5) (end 10.25 -12.5) (layer Eco2.User) (width 0.1524))
(fp_line (start 18.54 -0.5) (end 18.54 -12.5) (layer Eco2.User) (width 0.1524))
(fp_line (start 10.25 -0.5) (end 18.54 -0.5) (layer Eco2.User) (width 0.1524))
(fp_line (start 10.25 0) (end 10.25 1.5) (layer Eco1.User) (width 0.1524))
(fp_line (start -12.96 -0.5) (end -12.96 -10.72) (layer Eco2.User) (width 0.1524))
(fp_line (start -10.25 0) (end -10.25 1.5) (layer Eco1.User) (width 0.1524))
(fp_line (start -10.25 -0.5) (end -12.96 -0.5) (layer Eco2.User) (width 0.1524))
(fp_line (start 0 -31.83) (end 0 -33.83) (layer Cmts.User) (width 0.1524))
(fp_line (start -1 -32.83) (end 1 -32.83) (layer Cmts.User) (width 0.1524))
(fp_line (start -21.36 0) (end -22.06 0) (layer F.SilkS) (width 0.1524))
(fp_line (start -22.06 0) (end -22.06 -2.5) (layer F.SilkS) (width 0.1524))
(fp_line (start -22.06 -2.5) (end -21.36 -2.5) (layer F.SilkS) (width 0.1524))
(fp_line (start 21.36 0) (end 22.06 0) (layer F.SilkS) (width 0.1524))
(fp_line (start 22.06 0) (end 22.06 -2.5) (layer F.SilkS) (width 0.1524))
(fp_line (start 22.06 -2.5) (end 21.36 -2.5) (layer F.SilkS) (width 0.1524))
(fp_line (start 21.36 -60.26) (end 22.06 -60.26) (layer F.SilkS) (width 0.1524))
(fp_line (start 22.06 -60.26) (end 22.06 -57.76) (layer F.SilkS) (width 0.1524))
(fp_line (start 22.06 -57.76) (end 21.36 -57.76) (layer F.SilkS) (width 0.1524))
(fp_line (start -21.36 -60.26) (end -22.06 -60.26) (layer F.SilkS) (width 0.1524))
(fp_line (start -22.06 -60.26) (end -22.06 -57.76) (layer F.SilkS) (width 0.1524))
(fp_line (start -22.06 -57.76) (end -21.36 -57.76) (layer F.SilkS) (width 0.1524))
(fp_line (start -18.36 -57.31) (end 18.36 -57.31) (layer F.SilkS) (width 0.1524))
(fp_line (start 18.36 -57.31) (end 18.36 -8.35) (layer F.SilkS) (width 0.1524))
(fp_line (start 18.36 -8.35) (end -18.36 -8.35) (layer F.SilkS) (width 0.1524))
(fp_line (start -18.36 -8.35) (end -18.36 -57.31) (layer F.SilkS) (width 0.1524))
(fp_line (start 21.36 0) (end -21.36 0) (layer F.SilkS) (width 0.1524))
(fp_line (start -21.36 0) (end -21.36 -60.26) (layer F.SilkS) (width 0.1524))
(fp_line (start -21.36 -60.26) (end 21.36 -60.26) (layer F.SilkS) (width 0.1524))
(fp_line (start 21.36 -60.26) (end 21.36 0) (layer F.SilkS) (width 0.1524))
)
(module ipc_resc:IPC_RESC1608X55N (layer 4_bot) (tedit 53B09A40) (tstamp 53B0A464)
(at 139.4 108.2 180)
(tags "1608 metric, 0603 imperial")
(path /53A8BFC3/53A8C2B0)
(attr smd)
(fp_text reference R10 (at 11 -0.6 180) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
Remove line in/out components and traces, microphone. Clean up traces and via stitching affected by removed components.
2015-08-24 00:23:21 +00:00
(fp_text value 0R (at 0 0 180) (layer B.SilkS)
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_line (start -1.50114 0.7493) (end 1.50114 0.7493) (layer B.SilkS) (width 0.1524))
(fp_line (start 1.50114 0.7493) (end 1.50114 -0.7493) (layer B.SilkS) (width 0.1524))
(fp_line (start 1.50114 -0.7493) (end -1.50114 -0.7493) (layer B.SilkS) (width 0.1524))
(fp_line (start -1.50114 -0.7493) (end -1.50114 0.7493) (layer B.SilkS) (width 0.1524))
(pad 1 smd rect (at -0.8001 0 180) (size 0.89916 1.00076) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 61 "Net-(C24-Pad1)"))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 2 smd rect (at 0.8001 0 180) (size 0.89916 1.00076) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 10 /audio/MICIN))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
(module ipc_resc:IPC_RESC1608X55N (layer 4_bot) (tedit 53B09A8C) (tstamp 53AA2A28)
(at 161 120.8 90)
(tags "1608 metric, 0603 imperial")
(path /53A8BFC3/53A8C264)
(attr smd)
(fp_text reference R11 (at -3.2 0 90) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_text value 47K (at 0 0 90) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_line (start -1.50114 0.7493) (end 1.50114 0.7493) (layer B.SilkS) (width 0.1524))
(fp_line (start 1.50114 0.7493) (end 1.50114 -0.7493) (layer B.SilkS) (width 0.1524))
(fp_line (start 1.50114 -0.7493) (end -1.50114 -0.7493) (layer B.SilkS) (width 0.1524))
(fp_line (start -1.50114 -0.7493) (end -1.50114 0.7493) (layer B.SilkS) (width 0.1524))
(pad 1 smd rect (at -0.8001 0 90) (size 0.89916 1.00076) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 2 smd rect (at 0.8001 0 90) (size 0.89916 1.00076) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 59 "Net-(C18-Pad2)"))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
(module ipc_resc:IPC_RESC1608X55N (layer 4_bot) (tedit 53B09A73) (tstamp 53AA2A32)
(at 161 109.2 90)
(tags "1608 metric, 0603 imperial")
(path /53A8BFC3/53A8C26A)
(attr smd)
(fp_text reference R12 (at 3.2 0 90) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_text value 47K (at 0 0 90) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_line (start -1.50114 0.7493) (end 1.50114 0.7493) (layer B.SilkS) (width 0.1524))
(fp_line (start 1.50114 0.7493) (end 1.50114 -0.7493) (layer B.SilkS) (width 0.1524))
(fp_line (start 1.50114 -0.7493) (end -1.50114 -0.7493) (layer B.SilkS) (width 0.1524))
(fp_line (start -1.50114 -0.7493) (end -1.50114 0.7493) (layer B.SilkS) (width 0.1524))
(pad 1 smd rect (at -0.8001 0 90) (size 0.89916 1.00076) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 60 "Net-(C19-Pad2)"))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 2 smd rect (at 0.8001 0 90) (size 0.89916 1.00076) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
(module ipc_resc:IPC_RESC1608X55N (layer 4_bot) (tedit 53B09AAF) (tstamp 53AE455C)
(at 170.8 124 180)
(tags "1608 metric, 0603 imperial")
(path /53A8BFC3/53A8C296)
(attr smd)
(fp_text reference R17 (at -0.6 -1.4 180) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_text value 47K (at 0 0 180) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_line (start -1.50114 0.7493) (end 1.50114 0.7493) (layer B.SilkS) (width 0.1524))
(fp_line (start 1.50114 0.7493) (end 1.50114 -0.7493) (layer B.SilkS) (width 0.1524))
(fp_line (start 1.50114 -0.7493) (end -1.50114 -0.7493) (layer B.SilkS) (width 0.1524))
(fp_line (start -1.50114 -0.7493) (end -1.50114 0.7493) (layer B.SilkS) (width 0.1524))
(pad 1 smd rect (at -0.8001 0 180) (size 0.89916 1.00076) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 62 "Net-(C24-Pad2)"))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 2 smd rect (at 0.8001 0 180) (size 0.89916 1.00076) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
(module ipc_resc:IPC_RESC1608X55N (layer 4_bot) (tedit 53B09A2B) (tstamp 53B0A485)
(at 136.4 104.4)
(tags "1608 metric, 0603 imperial")
(path /53A8BFC3/53A8C29C)
(attr smd)
(fp_text reference R18 (at -0.6 -1.4) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_text value 680R (at 0 0) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_line (start -1.50114 0.7493) (end 1.50114 0.7493) (layer B.SilkS) (width 0.1524))
(fp_line (start 1.50114 0.7493) (end 1.50114 -0.7493) (layer B.SilkS) (width 0.1524))
(fp_line (start 1.50114 -0.7493) (end -1.50114 -0.7493) (layer B.SilkS) (width 0.1524))
(fp_line (start -1.50114 -0.7493) (end -1.50114 0.7493) (layer B.SilkS) (width 0.1524))
(pad 1 smd rect (at -0.8001 0) (size 0.89916 1.00076) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 9 /audio/MICBIAS))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 2 smd rect (at 0.8001 0) (size 0.89916 1.00076) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 62 "Net-(C24-Pad2)"))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
(module ipc_resc:IPC_RESC1608X55N (layer 4_bot) (tedit 53B09B9B) (tstamp 53AA2A78)
(at 87.8 146.4 270)
(tags "1608 metric, 0603 imperial")
(path /53A9129D/53A91657)
(attr smd)
(fp_text reference R19 (at -0.8 -1.4 270) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_text value 47K (at 0 0 270) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_line (start -1.50114 0.7493) (end 1.50114 0.7493) (layer B.SilkS) (width 0.1524))
(fp_line (start 1.50114 0.7493) (end 1.50114 -0.7493) (layer B.SilkS) (width 0.1524))
(fp_line (start 1.50114 -0.7493) (end -1.50114 -0.7493) (layer B.SilkS) (width 0.1524))
(fp_line (start -1.50114 -0.7493) (end -1.50114 0.7493) (layer B.SilkS) (width 0.1524))
(pad 1 smd rect (at -0.8001 0 270) (size 0.89916 1.00076) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 33 /hackrf_if/LCD_RESET#))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 2 smd rect (at 0.8001 0 270) (size 0.89916 1.00076) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
(module ipc_resc:IPC_RESC1608X55N (layer 4_bot) (tedit 53B09B8D) (tstamp 53AA2A82)
(at 94.6 148.3 90)
(tags "1608 metric, 0603 imperial")
(path /53A9129D/53A91635)
(attr smd)
(fp_text reference R20 (at 2.6 0 90) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_text value 47K (at 0 0 90) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_line (start -1.50114 0.7493) (end 1.50114 0.7493) (layer B.SilkS) (width 0.1524))
(fp_line (start 1.50114 0.7493) (end 1.50114 -0.7493) (layer B.SilkS) (width 0.1524))
(fp_line (start 1.50114 -0.7493) (end -1.50114 -0.7493) (layer B.SilkS) (width 0.1524))
(fp_line (start -1.50114 -0.7493) (end -1.50114 0.7493) (layer B.SilkS) (width 0.1524))
(pad 1 smd rect (at -0.8001 0 90) (size 0.89916 1.00076) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 2 smd rect (at 0.8001 0 90) (size 0.89916 1.00076) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 15 /hackrf_if/LCD_BACKLIGHT))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
(module ipc_resc:IPC_RESC1608X55N (layer 4_bot) (tedit 53B30AF0) (tstamp 53AE033F)
(at 138.5 120.9 90)
(tags "1608 metric, 0603 imperial")
(path /53A8C780/53A915E9)
(attr smd)
(fp_text reference R22 (at -1.1 1.5 90) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_text value 220R (at 0 0 90) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_line (start -1.50114 0.7493) (end 1.50114 0.7493) (layer B.SilkS) (width 0.1524))
(fp_line (start 1.50114 0.7493) (end 1.50114 -0.7493) (layer B.SilkS) (width 0.1524))
(fp_line (start 1.50114 -0.7493) (end -1.50114 -0.7493) (layer B.SilkS) (width 0.1524))
(fp_line (start -1.50114 -0.7493) (end -1.50114 0.7493) (layer B.SilkS) (width 0.1524))
(pad 1 smd rect (at -0.8001 0 90) (size 0.89916 1.00076) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 107 /hackrf_if/H1_CPLD_TDI))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 2 smd rect (at 0.8001 0 90) (size 0.89916 1.00076) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 4 /audio/I2S0_RX_SDA))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
(module ipc_capc:IPC_CAPC2012X140N (layer 4_bot) (tedit 53B108E0) (tstamp 53AA27BB)
(at 173.4 159 180)
(path /53A8C780/53A8D62C)
(attr smd)
(fp_text reference C41 (at -2.8 0 180) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
Remove line in/out components and traces, microphone. Clean up traces and via stitching affected by removed components.
2015-08-24 00:23:21 +00:00
(fp_text value DNI (at 0 0 180) (layer B.SilkS)
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(effects (font (thickness 0.3048)) (justify mirror))
)
(fp_line (start -1.72466 0.97536) (end 1.72466 0.97536) (layer B.SilkS) (width 0.1524))
(fp_line (start 1.72466 0.97536) (end 1.72466 -0.97536) (layer B.SilkS) (width 0.1524))
(fp_line (start 1.72466 -0.97536) (end -1.72466 -0.97536) (layer B.SilkS) (width 0.1524))
(fp_line (start -1.72466 -0.97536) (end -1.72466 0.97536) (layer B.SilkS) (width 0.1524))
(pad 1 smd rect (at -0.89916 0 180) (size 1.15062 1.45034) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 57 /hackrf_if/VBAT))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 2 smd rect (at 0.89916 0 180) (size 1.15062 1.45034) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
(module ipc_capc:IPC_CAPC2012X140N (layer 4_bot) (tedit 53B1092C) (tstamp 53AA27B1)
(at 97.6 144.8)
(path /53A8C780/53A8D592)
(attr smd)
(fp_text reference C40 (at 2.8 -1) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_text value 10U (at 0 0) (layer B.SilkS)
(effects (font (thickness 0.3048)) (justify mirror))
)
(fp_line (start -1.72466 0.97536) (end 1.72466 0.97536) (layer B.SilkS) (width 0.1524))
(fp_line (start 1.72466 0.97536) (end 1.72466 -0.97536) (layer B.SilkS) (width 0.1524))
(fp_line (start 1.72466 -0.97536) (end -1.72466 -0.97536) (layer B.SilkS) (width 0.1524))
(fp_line (start -1.72466 -0.97536) (end -1.72466 0.97536) (layer B.SilkS) (width 0.1524))
(pad 1 smd rect (at -0.89916 0) (size 1.15062 1.45034) (layers 4_bot B.Paste B.Mask)
(net 1 +1.8V))
(pad 2 smd rect (at 0.89916 0) (size 1.15062 1.45034) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
(module ipc_capc:IPC_CAPC2012X140N (layer 4_bot) (tedit 53B108F5) (tstamp 53AA279D)
(at 101.4 147.8 270)
(path /53A8C780/53A8D58C)
(attr smd)
(fp_text reference C38 (at 0 -2.2 270) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_text value 10U (at 0 0 270) (layer B.SilkS)
(effects (font (thickness 0.3048)) (justify mirror))
)
(fp_line (start -1.72466 0.97536) (end 1.72466 0.97536) (layer B.SilkS) (width 0.1524))
(fp_line (start 1.72466 0.97536) (end 1.72466 -0.97536) (layer B.SilkS) (width 0.1524))
(fp_line (start 1.72466 -0.97536) (end -1.72466 -0.97536) (layer B.SilkS) (width 0.1524))
(fp_line (start -1.72466 -0.97536) (end -1.72466 0.97536) (layer B.SilkS) (width 0.1524))
(pad 1 smd rect (at -0.89916 0 270) (size 1.15062 1.45034) (layers 4_bot B.Paste B.Mask)
(net 2 +3.3V))
(pad 2 smd rect (at 0.89916 0 270) (size 1.15062 1.45034) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
(module ipc_capc:IPC_CAPC2012X140N (layer 4_bot) (tedit 53B108FA) (tstamp 53AB408E)
(at 90 140.7 180)
(path /53A8C780/53A8D5E0)
(attr smd)
(fp_text reference C37 (at 0 2.1 180) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_text value 10U (at 0 0 180) (layer B.SilkS)
(effects (font (thickness 0.3048)) (justify mirror))
)
(fp_line (start -1.72466 0.97536) (end 1.72466 0.97536) (layer B.SilkS) (width 0.1524))
(fp_line (start 1.72466 0.97536) (end 1.72466 -0.97536) (layer B.SilkS) (width 0.1524))
(fp_line (start 1.72466 -0.97536) (end -1.72466 -0.97536) (layer B.SilkS) (width 0.1524))
(fp_line (start -1.72466 -0.97536) (end -1.72466 0.97536) (layer B.SilkS) (width 0.1524))
(pad 1 smd rect (at -0.89916 0 180) (size 1.15062 1.45034) (layers 4_bot B.Paste B.Mask)
(net 1 +1.8V))
(pad 2 smd rect (at 0.89916 0 180) (size 1.15062 1.45034) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
(module ipc_capc:IPC_CAPC2012X140N (layer 4_bot) (tedit 53B1089D) (tstamp 53AA2789)
(at 90 125.7 180)
(path /53A8C780/53A8D5DA)
(attr smd)
(fp_text reference C36 (at 2.8 0.9 180) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_text value 10U (at 0 0 180) (layer B.SilkS)
(effects (font (thickness 0.3048)) (justify mirror))
)
(fp_line (start -1.72466 0.97536) (end 1.72466 0.97536) (layer B.SilkS) (width 0.1524))
(fp_line (start 1.72466 0.97536) (end 1.72466 -0.97536) (layer B.SilkS) (width 0.1524))
(fp_line (start 1.72466 -0.97536) (end -1.72466 -0.97536) (layer B.SilkS) (width 0.1524))
(fp_line (start -1.72466 -0.97536) (end -1.72466 0.97536) (layer B.SilkS) (width 0.1524))
(pad 1 smd rect (at -0.89916 0 180) (size 1.15062 1.45034) (layers 4_bot B.Paste B.Mask)
(net 1 +1.8V))
(pad 2 smd rect (at 0.89916 0 180) (size 1.15062 1.45034) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
(module ipc_capc:IPC_CAPC2012X140N (layer 4_bot) (tedit 53B10916) (tstamp 53AA2775)
(at 97 121.3 180)
(path /53A8C780/53A8D5C8)
(attr smd)
(fp_text reference C34 (at -2.8 -1.1 180) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_text value 10U (at 0 0 180) (layer B.SilkS)
(effects (font (thickness 0.3048)) (justify mirror))
)
(fp_line (start -1.72466 0.97536) (end 1.72466 0.97536) (layer B.SilkS) (width 0.1524))
(fp_line (start 1.72466 0.97536) (end 1.72466 -0.97536) (layer B.SilkS) (width 0.1524))
(fp_line (start 1.72466 -0.97536) (end -1.72466 -0.97536) (layer B.SilkS) (width 0.1524))
(fp_line (start -1.72466 -0.97536) (end -1.72466 0.97536) (layer B.SilkS) (width 0.1524))
(pad 1 smd rect (at -0.89916 0 180) (size 1.15062 1.45034) (layers 4_bot B.Paste B.Mask)
(net 2 +3.3V))
(pad 2 smd rect (at 0.89916 0 180) (size 1.15062 1.45034) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
(module ipc_capc:IPC_CAPC2012X140N (layer 4_bot) (tedit 53B108EA) (tstamp 53AB19ED)
(at 123.5 158.9 180)
(path /53A8C780/53A8D5C2)
(attr smd)
(fp_text reference C32 (at 2.9 -1.1 180) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_text value 10U (at 0 0 180) (layer B.SilkS)
(effects (font (thickness 0.3048)) (justify mirror))
)
(fp_line (start -1.72466 0.97536) (end 1.72466 0.97536) (layer B.SilkS) (width 0.1524))
(fp_line (start 1.72466 0.97536) (end 1.72466 -0.97536) (layer B.SilkS) (width 0.1524))
(fp_line (start 1.72466 -0.97536) (end -1.72466 -0.97536) (layer B.SilkS) (width 0.1524))
(fp_line (start -1.72466 -0.97536) (end -1.72466 0.97536) (layer B.SilkS) (width 0.1524))
(pad 1 smd rect (at -0.89916 0 180) (size 1.15062 1.45034) (layers 4_bot B.Paste B.Mask)
(net 2 +3.3V))
(pad 2 smd rect (at 0.89916 0 180) (size 1.15062 1.45034) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
(module ipc_capc:IPC_CAPC2012X140N (layer 4_bot) (tedit 53B1089A) (tstamp 53AA2725)
(at 76.2 123.2)
(path /53A9129D/53A8C71C)
(attr smd)
(fp_text reference C26 (at 2.8 -0.8) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_text value 10U (at 0 0) (layer B.SilkS)
(effects (font (thickness 0.3048)) (justify mirror))
)
(fp_line (start -1.72466 0.97536) (end 1.72466 0.97536) (layer B.SilkS) (width 0.1524))
(fp_line (start 1.72466 0.97536) (end 1.72466 -0.97536) (layer B.SilkS) (width 0.1524))
(fp_line (start 1.72466 -0.97536) (end -1.72466 -0.97536) (layer B.SilkS) (width 0.1524))
(fp_line (start -1.72466 -0.97536) (end -1.72466 0.97536) (layer B.SilkS) (width 0.1524))
(pad 1 smd rect (at -0.89916 0) (size 1.15062 1.45034) (layers 4_bot B.Paste B.Mask)
(net 2 +3.3V))
(pad 2 smd rect (at 0.89916 0) (size 1.15062 1.45034) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
(module ipc_capc:IPC_CAPC2012X140N (layer 4_bot) (tedit 53B108C2) (tstamp 53AA2672)
(at 144.6 111.4 270)
(path /53A8BFC3/53A8C720)
(attr smd)
(fp_text reference C13 (at 0 -2.2 270) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_text value 10U (at 0 0 270) (layer B.SilkS)
(effects (font (thickness 0.3048)) (justify mirror))
)
(fp_line (start -1.72466 0.97536) (end 1.72466 0.97536) (layer B.SilkS) (width 0.1524))
(fp_line (start 1.72466 0.97536) (end 1.72466 -0.97536) (layer B.SilkS) (width 0.1524))
(fp_line (start 1.72466 -0.97536) (end -1.72466 -0.97536) (layer B.SilkS) (width 0.1524))
(fp_line (start -1.72466 -0.97536) (end -1.72466 0.97536) (layer B.SilkS) (width 0.1524))
(pad 1 smd rect (at -0.89916 0 270) (size 1.15062 1.45034) (layers 4_bot B.Paste B.Mask)
(net 2 +3.3V))
(pad 2 smd rect (at 0.89916 0 270) (size 1.15062 1.45034) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
(module ipc_capc:IPC_CAPC2012X140N (layer 4_bot) (tedit 53B108D2) (tstamp 53B0A47A)
(at 136.2 106.4)
(path /53A8BFC3/53A8C6F0)
(attr smd)
(fp_text reference C12 (at -2.6 -1.4) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_text value 10U (at 0 0) (layer B.SilkS)
(effects (font (thickness 0.3048)) (justify mirror))
)
(fp_line (start -1.72466 0.97536) (end 1.72466 0.97536) (layer B.SilkS) (width 0.1524))
(fp_line (start 1.72466 0.97536) (end 1.72466 -0.97536) (layer B.SilkS) (width 0.1524))
(fp_line (start 1.72466 -0.97536) (end -1.72466 -0.97536) (layer B.SilkS) (width 0.1524))
(fp_line (start -1.72466 -0.97536) (end -1.72466 0.97536) (layer B.SilkS) (width 0.1524))
(pad 1 smd rect (at -0.89916 0) (size 1.15062 1.45034) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 9 /audio/MICBIAS))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 2 smd rect (at 0.89916 0) (size 1.15062 1.45034) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
(module ipc_capc:IPC_CAPC2012X140N (layer 4_bot) (tedit 53B108AF) (tstamp 53AA265E)
(at 130.2 116.6 90)
(path /53A8BFC3/53A8C72C)
(attr smd)
(fp_text reference C11 (at 2.8 0 90) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_text value 10U (at 0 0 90) (layer B.SilkS)
(effects (font (thickness 0.3048)) (justify mirror))
)
(fp_line (start -1.72466 0.97536) (end 1.72466 0.97536) (layer B.SilkS) (width 0.1524))
(fp_line (start 1.72466 0.97536) (end 1.72466 -0.97536) (layer B.SilkS) (width 0.1524))
(fp_line (start 1.72466 -0.97536) (end -1.72466 -0.97536) (layer B.SilkS) (width 0.1524))
(fp_line (start -1.72466 -0.97536) (end -1.72466 0.97536) (layer B.SilkS) (width 0.1524))
(pad 1 smd rect (at -0.89916 0 90) (size 1.15062 1.45034) (layers 4_bot B.Paste B.Mask)
(net 2 +3.3V))
(pad 2 smd rect (at 0.89916 0 90) (size 1.15062 1.45034) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
(module ipc_capc:IPC_CAPC2012X140N (layer 4_bot) (tedit 53BC2715) (tstamp 53AA264A)
(at 135 122 180)
(path /53A8BFC3/53A8C708)
(attr smd)
(fp_text reference C9 (at 3.3 0 180) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_text value 10U (at 0 0 180) (layer B.SilkS)
(effects (font (thickness 0.3048)) (justify mirror))
)
(fp_line (start -1.72466 0.97536) (end 1.72466 0.97536) (layer B.SilkS) (width 0.1524))
(fp_line (start 1.72466 0.97536) (end 1.72466 -0.97536) (layer B.SilkS) (width 0.1524))
(fp_line (start 1.72466 -0.97536) (end -1.72466 -0.97536) (layer B.SilkS) (width 0.1524))
(fp_line (start -1.72466 -0.97536) (end -1.72466 0.97536) (layer B.SilkS) (width 0.1524))
(pad 1 smd rect (at -0.89916 0 180) (size 1.15062 1.45034) (layers 4_bot B.Paste B.Mask)
(net 2 +3.3V))
(pad 2 smd rect (at 0.89916 0 180) (size 1.15062 1.45034) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
(module ipc_capc:IPC_CAPC2012X140N (layer 4_bot) (tedit 53B108CA) (tstamp 53AE5118)
(at 132.4 106.8 180)
(path /53A8BFC3/53A8C6F6)
(attr smd)
(fp_text reference C8 (at 2.6 0.6 180) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_text value 10U (at 0 0 180) (layer B.SilkS)
(effects (font (thickness 0.3048)) (justify mirror))
)
(fp_line (start -1.72466 0.97536) (end 1.72466 0.97536) (layer B.SilkS) (width 0.1524))
(fp_line (start 1.72466 0.97536) (end 1.72466 -0.97536) (layer B.SilkS) (width 0.1524))
(fp_line (start 1.72466 -0.97536) (end -1.72466 -0.97536) (layer B.SilkS) (width 0.1524))
(fp_line (start -1.72466 -0.97536) (end -1.72466 0.97536) (layer B.SilkS) (width 0.1524))
(pad 1 smd rect (at -0.89916 0 180) (size 1.15062 1.45034) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 14 /audio/VMID))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 2 smd rect (at 0.89916 0 180) (size 1.15062 1.45034) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
(module ipc_capc:IPC_CAPC2012X140N (layer 4_bot) (tedit 53B108BE) (tstamp 53AA2636)
(at 144.6 116.6 90)
(path /53A8BFC3/53A8C70E)
(attr smd)
(fp_text reference C7 (at 0 2.2 90) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_text value 10U (at 0 0 90) (layer B.SilkS)
(effects (font (thickness 0.3048)) (justify mirror))
)
(fp_line (start -1.72466 0.97536) (end 1.72466 0.97536) (layer B.SilkS) (width 0.1524))
(fp_line (start 1.72466 0.97536) (end 1.72466 -0.97536) (layer B.SilkS) (width 0.1524))
(fp_line (start 1.72466 -0.97536) (end -1.72466 -0.97536) (layer B.SilkS) (width 0.1524))
(fp_line (start -1.72466 -0.97536) (end -1.72466 0.97536) (layer B.SilkS) (width 0.1524))
(pad 1 smd rect (at -0.89916 0 90) (size 1.15062 1.45034) (layers 4_bot B.Paste B.Mask)
(net 2 +3.3V))
(pad 2 smd rect (at 0.89916 0 90) (size 1.15062 1.45034) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
(module ipc_capc:IPC_CAPC2012X140N (layer 4_bot) (tedit 53B19259) (tstamp 53B19350)
(at 155.2 157.8)
(path /53A8C780/53B1911F)
(attr smd)
(fp_text reference C42 (at 2.9 1) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_text value 10U (at 0 0) (layer B.SilkS)
(effects (font (thickness 0.3048)) (justify mirror))
)
(fp_line (start -1.72466 0.97536) (end 1.72466 0.97536) (layer B.SilkS) (width 0.1524))
(fp_line (start 1.72466 0.97536) (end 1.72466 -0.97536) (layer B.SilkS) (width 0.1524))
(fp_line (start 1.72466 -0.97536) (end -1.72466 -0.97536) (layer B.SilkS) (width 0.1524))
(fp_line (start -1.72466 -0.97536) (end -1.72466 0.97536) (layer B.SilkS) (width 0.1524))
(pad 1 smd rect (at -0.89916 0) (size 1.15062 1.45034) (layers 4_bot B.Paste B.Mask)
(net 2 +3.3V))
(pad 2 smd rect (at 0.89916 0) (size 1.15062 1.45034) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
(module ipc_capc:IPC_CAPC2012X140N (layer 4_bot) (tedit 53B193EF) (tstamp 53B19576)
(at 165.2 154.4 270)
(path /53A8C780/53B1A065)
(attr smd)
(fp_text reference C43 (at 2.2 -1.6 270) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_text value 10U (at 0 0 270) (layer B.SilkS)
(effects (font (thickness 0.3048)) (justify mirror))
)
(fp_line (start -1.72466 0.97536) (end 1.72466 0.97536) (layer B.SilkS) (width 0.1524))
(fp_line (start 1.72466 0.97536) (end 1.72466 -0.97536) (layer B.SilkS) (width 0.1524))
(fp_line (start 1.72466 -0.97536) (end -1.72466 -0.97536) (layer B.SilkS) (width 0.1524))
(fp_line (start -1.72466 -0.97536) (end -1.72466 0.97536) (layer B.SilkS) (width 0.1524))
(pad 1 smd rect (at -0.89916 0 270) (size 1.15062 1.45034) (layers 4_bot B.Paste B.Mask)
(net 2 +3.3V))
(pad 2 smd rect (at 0.89916 0 270) (size 1.15062 1.45034) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
(module fiducial:FIDUCIAL_65MIL (layer 4_bot) (tedit 53B2E496) (tstamp 53B2EF36)
(at 71.2 104.2)
(path /53B309AC)
(solder_mask_margin 2.99974)
(attr smd)
(fp_text reference FID1 (at 0 0) (layer B.SilkS) hide
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_text value FIDUCIAL (at 0 0) (layer B.SilkS) hide
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(pad "" smd circle (at 0 0) (size 1.651 1.651) (layers 4_bot B.Mask)
(solder_mask_margin 0.8255) (clearance 1.0795))
)
(module fiducial:FIDUCIAL_65MIL (layer 4_bot) (tedit 53B2E496) (tstamp 53B2EF3B)
(at 168.8 104.2)
(path /53B30B4C)
(solder_mask_margin 2.99974)
(attr smd)
(fp_text reference FID2 (at 0 0) (layer B.SilkS) hide
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_text value FIDUCIAL (at 0 0) (layer B.SilkS) hide
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(pad "" smd circle (at 0 0) (size 1.651 1.651) (layers 4_bot B.Mask)
(solder_mask_margin 0.8255) (clearance 1.0795))
)
(module fiducial:FIDUCIAL_65MIL (layer 4_bot) (tedit 53B2E496) (tstamp 53B2EF40)
(at 64.2 161.2)
(path /53B30CEC)
(solder_mask_margin 2.99974)
(attr smd)
(fp_text reference FID3 (at 0 0) (layer B.SilkS) hide
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_text value FIDUCIAL (at 0 0) (layer B.SilkS) hide
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(pad "" smd circle (at 0 0) (size 1.651 1.651) (layers 4_bot B.Mask)
(solder_mask_margin 0.8255) (clearance 1.0795))
)
(module fiducial:FIDUCIAL_65MIL (layer 4_bot) (tedit 53B2E496) (tstamp 53B2EF45)
(at 175.8 163.8)
(path /53B30E8C)
(solder_mask_margin 2.99974)
(attr smd)
(fp_text reference FID4 (at 0 0) (layer B.SilkS) hide
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_text value FIDUCIAL (at 0 0) (layer B.SilkS) hide
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(pad "" smd circle (at 0 0) (size 1.651 1.651) (layers 4_bot B.Mask)
(solder_mask_margin 0.8255) (clearance 1.0795))
)
(module ck:CK_TSWB-3N-CB222_LFS (layer 1_top) (tedit 53B3003D) (tstamp 53AA2AAD)
(at 147.5 137.5 90)
(path /53A9129D/53A8C6FD)
(fp_text reference SW1 (at -0.1 -2.7 90) (layer F.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)))
)
(fp_text value CK_TSWB-3N-CB (at 0 0 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_circle (center 0 0) (end 11.45 0) (layer F.SilkS) (width 0.15))
(fp_circle (center 0 0) (end 4.05 0) (layer F.SilkS) (width 0.15))
(fp_circle (center 0 0) (end 16 0) (layer F.SilkS) (width 0.15))
(fp_circle (center 0 0) (end 17.2 0) (layer F.SilkS) (width 0.15))
(pad "" np_thru_hole circle (at -3.182 -3.182 90) (size 1.6 1.6) (drill 1.6) (layers *.Cu *.Mask)
(clearance 0.4))
(pad "" np_thru_hole circle (at 3.182 3.182 90) (size 1.6 1.6) (drill 1.6) (layers *.Cu *.Mask)
(clearance 0.4))
(pad CA thru_hole circle (at -6.548 -6.548 90) (size 2.1 2.1) (drill 1.4) (layers *.Cu *.Mask F.SilkS)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad A thru_hole circle (at 6.548 6.548 90) (size 2.1 2.1) (drill 1.4) (layers *.Cu *.Mask F.SilkS)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 49 /hackrf_if/SW_ROT_A))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad "" np_thru_hole circle (at -10.607 -10.607 90) (size 4 4) (drill 4) (layers *.Cu *.Mask)
(clearance 0.4))
(pad "" np_thru_hole circle (at 10.607 -10.607 90) (size 4 4) (drill 4) (layers *.Cu *.Mask)
(clearance 0.4))
(pad "" np_thru_hole circle (at 10.607 10.607 90) (size 4 4) (drill 4) (layers *.Cu *.Mask)
(clearance 0.4))
(pad "" np_thru_hole circle (at -10.607 10.607 90) (size 4 4) (drill 4) (layers *.Cu *.Mask)
(clearance 0.4))
(pad S1 thru_hole circle (at -1.11 1.11 90) (size 2.1 2.1) (drill 1.4) (layers *.Cu *.Mask F.SilkS)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 51 /hackrf_if/SW_SEL))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad B thru_hole circle (at 6.548 -6.548 90) (size 2.1 2.1) (drill 1.4) (layers *.Cu *.Mask F.SilkS)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 50 /hackrf_if/SW_ROT_B))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad S3 thru_hole circle (at 16.15 -3.606 90) (size 2.1 2.1) (drill 1.4) (layers *.Cu *.Mask F.SilkS)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 48 /hackrf_if/SW_R))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad S2 thru_hole circle (at 7.75 15.104 90) (size 2.1 2.1) (drill 1.4) (layers *.Cu *.Mask F.SilkS)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 46 /hackrf_if/SW_D))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad CB thru_hole circle (at -3.253 16.08 90) (size 2.1 2.1) (drill 1.4) (layers *.Cu *.Mask F.SilkS)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad S5 thru_hole circle (at -16.15 3.606 90) (size 2.1 2.1) (drill 1.4) (layers *.Cu *.Mask F.SilkS)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 47 /hackrf_if/SW_L))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad S4 thru_hole circle (at -7.75 -15.104 90) (size 2.1 2.1) (drill 1.4) (layers *.Cu *.Mask F.SilkS)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 52 /hackrf_if/SW_U))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
(module cui:CUI_SJ-43516-SMT (layer 4_bot) (tedit 53B3001C) (tstamp 53AA3C96)
(at 172.1 114.8 180)
(path /53A8BFC3/53A8C2C6)
(attr smd)
(fp_text reference P2 (at -0.5 -3.8 180) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_text value TRRS_SW_JACK (at 0 0 180) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start 8.5 -3) (end -1.5 -3) (layer B.SilkS) (width 0.1524))
(fp_line (start -1.5 -3) (end -1.5 -3.7) (layer B.SilkS) (width 0.1524))
(fp_line (start -1.5 -3.7) (end -7 -3.7) (layer B.SilkS) (width 0.1524))
(fp_line (start 8.5 3) (end 8.5 -3) (layer B.SilkS) (width 0.1524))
(fp_line (start -7 3) (end 8.5 3) (layer B.SilkS) (width 0.1524))
(fp_line (start -7 3) (end -7 -3.7) (layer B.SilkS) (width 0.1524))
(fp_line (start -7 2.5) (end -8.5 2.5) (layer B.SilkS) (width 0.1524))
(fp_line (start -8.5 2.5) (end -8.5 -2.5) (layer B.SilkS) (width 0.1524))
(fp_line (start -8.5 -2.5) (end -7 -2.5) (layer B.SilkS) (width 0.1524))
(pad 1 smd rect (at -6.4 -3.7 180) (size 2.2 2.8) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 68 "Net-(L9-Pad1)"))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 4 smd rect (at -3.6 -3.7 180) (size 2.2 2.8) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 67 "Net-(L6-Pad1)"))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 2 smd rect (at 5.8 -3.7 180) (size 2.8 2.8) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 65 "Net-(L4-Pad1)"))
Remove line in/out components and traces, microphone. Clean up traces and via stitching affected by removed components.
2015-08-24 00:23:21 +00:00
(pad 5 smd rect (at 9.9 0.75 180) (size 2.8 2.8) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 69 "Net-(P2-Pad5)"))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 3 smd rect (at -1.7 3.7 180) (size 2 2.8) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 66 "Net-(L5-Pad1)"))
Remove line in/out components and traces, microphone. Clean up traces and via stitching affected by removed components.
2015-08-24 00:23:21 +00:00
(pad 6 smd rect (at -4.5 3.7 180) (size 2 2.8) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 70 "Net-(P2-Pad6)"))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad "" np_thru_hole circle (at -2.5 0 180) (size 1.7 1.7) (drill 1.7) (layers *.Cu *.Mask B.SilkS)
(clearance 0.4))
(pad "" np_thru_hole circle (at 4.5 0 180) (size 1.7 1.7) (drill 1.7) (layers *.Cu *.Mask B.SilkS)
(clearance 0.4))
)
More footprint units cleanup.
2015-08-30 00:54:26 +00:00
(module ipc_sop:IPC_SOP65P780X200-28N (layer 4_bot) (tedit 55E2538C) (tstamp 53AA2AD7)
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(at 137.4 114 90)
(tags "JEDEC MO-150AH")
(path /53A8BFC3/53A8C66D)
Reduce solder mask margin on WM8731. Trying to squeeze some mask web in there!
2015-08-30 01:14:23 +00:00
(solder_mask_margin 0.0492)
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(fp_text reference U1 (at -5.2 6.2 90) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_text value WM8731SEDS (at 0 0 90) (layer B.SilkS)
(effects (font (thickness 0.3048)) (justify mirror))
)
(fp_circle (center -4.184 4.98602) (end -4.084 4.98602) (layer B.SilkS) (width 0.1524))
(fp_line (start -1.8 5.1) (end -1.8 -5.1) (layer B.SilkS) (width 0.1524))
More footprint units cleanup.
2015-08-30 00:54:26 +00:00
(fp_line (start -4.675 5.5) (end 4.675 5.5) (layer B.CrtYd) (width 0.1524))
(fp_line (start 4.675 5.5) (end 4.675 -5.5) (layer B.CrtYd) (width 0.1524))
(fp_line (start 4.675 -5.5) (end -4.675 -5.5) (layer B.CrtYd) (width 0.1524))
(fp_line (start -4.675 -5.5) (end -4.675 5.5) (layer B.CrtYd) (width 0.1524))
Footprint cleanup Remove courtyard lines from silkscreen. Round coordinates/dimensions to correct values (KiCad's old units don't convert nicely to the new units). Restore U3 refdes silkscreen visibility.
2015-08-30 00:14:06 +00:00
(fp_line (start -2.25 5.1) (end 2.25 5.1) (layer B.SilkS) (width 0.1524))
(fp_line (start 2.25 5.1) (end 2.25 -5.1) (layer B.SilkS) (width 0.1524))
(fp_line (start 2.25 -5.1) (end -2.25 -5.1) (layer B.SilkS) (width 0.1524))
(fp_line (start -2.25 -5.1) (end -2.25 5.1) (layer B.SilkS) (width 0.1524))
(pad 1 smd rect (at -3.5 4.225 90) (size 1.85 0.45) (layers 4_bot B.Paste B.Mask)
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(net 2 +3.3V))
Footprint cleanup Remove courtyard lines from silkscreen. Round coordinates/dimensions to correct values (KiCad's old units don't convert nicely to the new units). Restore U3 refdes silkscreen visibility.
2015-08-30 00:14:06 +00:00
(pad 2 smd rect (at -3.5 3.575 90) (size 1.85 0.45) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 110 "Net-(U1-Pad2)"))
Footprint cleanup Remove courtyard lines from silkscreen. Round coordinates/dimensions to correct values (KiCad's old units don't convert nicely to the new units). Restore U3 refdes silkscreen visibility.
2015-08-30 00:14:06 +00:00
(pad 3 smd rect (at -3.5 2.925 90) (size 1.85 0.45) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 5 /audio/I2S0_SCK))
Footprint cleanup Remove courtyard lines from silkscreen. Round coordinates/dimensions to correct values (KiCad's old units don't convert nicely to the new units). Restore U3 refdes silkscreen visibility.
2015-08-30 00:14:06 +00:00
(pad 4 smd rect (at -3.5 2.275 90) (size 1.85 0.45) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 6 /audio/I2S0_TX_SDA))
Footprint cleanup Remove courtyard lines from silkscreen. Round coordinates/dimensions to correct values (KiCad's old units don't convert nicely to the new units). Restore U3 refdes silkscreen visibility.
2015-08-30 00:14:06 +00:00
(pad 5 smd rect (at -3.5 1.625 90) (size 1.85 0.45) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 7 /audio/I2S0_WS))
Footprint cleanup Remove courtyard lines from silkscreen. Round coordinates/dimensions to correct values (KiCad's old units don't convert nicely to the new units). Restore U3 refdes silkscreen visibility.
2015-08-30 00:14:06 +00:00
(pad 6 smd rect (at -3.5 0.975 90) (size 1.85 0.45) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 4 /audio/I2S0_RX_SDA))
Footprint cleanup Remove courtyard lines from silkscreen. Round coordinates/dimensions to correct values (KiCad's old units don't convert nicely to the new units). Restore U3 refdes silkscreen visibility.
2015-08-30 00:14:06 +00:00
(pad 7 smd rect (at -3.5 0.325 90) (size 1.85 0.45) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 7 /audio/I2S0_WS))
Footprint cleanup Remove courtyard lines from silkscreen. Round coordinates/dimensions to correct values (KiCad's old units don't convert nicely to the new units). Restore U3 refdes silkscreen visibility.
2015-08-30 00:14:06 +00:00
(pad 8 smd rect (at -3.5 -0.325 90) (size 1.85 0.45) (layers 4_bot B.Paste B.Mask)
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(net 2 +3.3V))
Footprint cleanup Remove courtyard lines from silkscreen. Round coordinates/dimensions to correct values (KiCad's old units don't convert nicely to the new units). Restore U3 refdes silkscreen visibility.
2015-08-30 00:14:06 +00:00
(pad 9 smd rect (at -3.5 -0.975 90) (size 1.85 0.45) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 8 /audio/LHPOUT))
Footprint cleanup Remove courtyard lines from silkscreen. Round coordinates/dimensions to correct values (KiCad's old units don't convert nicely to the new units). Restore U3 refdes silkscreen visibility.
2015-08-30 00:14:06 +00:00
(pad 10 smd rect (at -3.5 -1.625 90) (size 1.85 0.45) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 11 /audio/RHPOUT))
Footprint cleanup Remove courtyard lines from silkscreen. Round coordinates/dimensions to correct values (KiCad's old units don't convert nicely to the new units). Restore U3 refdes silkscreen visibility.
2015-08-30 00:14:06 +00:00
(pad 11 smd rect (at -3.5 -2.275 90) (size 1.85 0.45) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Footprint cleanup Remove courtyard lines from silkscreen. Round coordinates/dimensions to correct values (KiCad's old units don't convert nicely to the new units). Restore U3 refdes silkscreen visibility.
2015-08-30 00:14:06 +00:00
(pad 12 smd rect (at -3.5 -2.925 90) (size 1.85 0.45) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 111 "Net-(U1-Pad12)"))
Footprint cleanup Remove courtyard lines from silkscreen. Round coordinates/dimensions to correct values (KiCad's old units don't convert nicely to the new units). Restore U3 refdes silkscreen visibility.
2015-08-30 00:14:06 +00:00
(pad 13 smd rect (at -3.5 -3.575 90) (size 1.85 0.45) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 112 "Net-(U1-Pad13)"))
Footprint cleanup Remove courtyard lines from silkscreen. Round coordinates/dimensions to correct values (KiCad's old units don't convert nicely to the new units). Restore U3 refdes silkscreen visibility.
2015-08-30 00:14:06 +00:00
(pad 14 smd rect (at -3.5 -4.225 90) (size 1.85 0.45) (layers 4_bot B.Paste B.Mask)
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(net 2 +3.3V))
Footprint cleanup Remove courtyard lines from silkscreen. Round coordinates/dimensions to correct values (KiCad's old units don't convert nicely to the new units). Restore U3 refdes silkscreen visibility.
2015-08-30 00:14:06 +00:00
(pad 15 smd rect (at 3.5 -4.225 90) (size 1.85 0.45) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Footprint cleanup Remove courtyard lines from silkscreen. Round coordinates/dimensions to correct values (KiCad's old units don't convert nicely to the new units). Restore U3 refdes silkscreen visibility.
2015-08-30 00:14:06 +00:00
(pad 16 smd rect (at 3.5 -3.575 90) (size 1.85 0.45) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 14 /audio/VMID))
Footprint cleanup Remove courtyard lines from silkscreen. Round coordinates/dimensions to correct values (KiCad's old units don't convert nicely to the new units). Restore U3 refdes silkscreen visibility.
2015-08-30 00:14:06 +00:00
(pad 17 smd rect (at 3.5 -2.925 90) (size 1.85 0.45) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 9 /audio/MICBIAS))
Footprint cleanup Remove courtyard lines from silkscreen. Round coordinates/dimensions to correct values (KiCad's old units don't convert nicely to the new units). Restore U3 refdes silkscreen visibility.
2015-08-30 00:14:06 +00:00
(pad 18 smd rect (at 3.5 -2.275 90) (size 1.85 0.45) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 10 /audio/MICIN))
Footprint cleanup Remove courtyard lines from silkscreen. Round coordinates/dimensions to correct values (KiCad's old units don't convert nicely to the new units). Restore U3 refdes silkscreen visibility.
2015-08-30 00:14:06 +00:00
(pad 19 smd rect (at 3.5 -1.625 90) (size 1.85 0.45) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 113 "Net-(U1-Pad19)"))
Footprint cleanup Remove courtyard lines from silkscreen. Round coordinates/dimensions to correct values (KiCad's old units don't convert nicely to the new units). Restore U3 refdes silkscreen visibility.
2015-08-30 00:14:06 +00:00
(pad 20 smd rect (at 3.5 -0.975 90) (size 1.85 0.45) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 114 "Net-(U1-Pad20)"))
Footprint cleanup Remove courtyard lines from silkscreen. Round coordinates/dimensions to correct values (KiCad's old units don't convert nicely to the new units). Restore U3 refdes silkscreen visibility.
2015-08-30 00:14:06 +00:00
(pad 21 smd rect (at 3.5 -0.325 90) (size 1.85 0.45) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Footprint cleanup Remove courtyard lines from silkscreen. Round coordinates/dimensions to correct values (KiCad's old units don't convert nicely to the new units). Restore U3 refdes silkscreen visibility.
2015-08-30 00:14:06 +00:00
(pad 22 smd rect (at 3.5 0.325 90) (size 1.85 0.45) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Footprint cleanup Remove courtyard lines from silkscreen. Round coordinates/dimensions to correct values (KiCad's old units don't convert nicely to the new units). Restore U3 refdes silkscreen visibility.
2015-08-30 00:14:06 +00:00
(pad 23 smd rect (at 3.5 0.975 90) (size 1.85 0.45) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 13 /audio/SDA))
Footprint cleanup Remove courtyard lines from silkscreen. Round coordinates/dimensions to correct values (KiCad's old units don't convert nicely to the new units). Restore U3 refdes silkscreen visibility.
2015-08-30 00:14:06 +00:00
(pad 24 smd rect (at 3.5 1.625 90) (size 1.85 0.45) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 12 /audio/SCL))
Footprint cleanup Remove courtyard lines from silkscreen. Round coordinates/dimensions to correct values (KiCad's old units don't convert nicely to the new units). Restore U3 refdes silkscreen visibility.
2015-08-30 00:14:06 +00:00
(pad 25 smd rect (at 3.5 2.275 90) (size 1.85 0.45) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 3 /audio/I2S0_MCLK))
Footprint cleanup Remove courtyard lines from silkscreen. Round coordinates/dimensions to correct values (KiCad's old units don't convert nicely to the new units). Restore U3 refdes silkscreen visibility.
2015-08-30 00:14:06 +00:00
(pad 26 smd rect (at 3.5 2.925 90) (size 1.85 0.45) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 115 "Net-(U1-Pad26)"))
Footprint cleanup Remove courtyard lines from silkscreen. Round coordinates/dimensions to correct values (KiCad's old units don't convert nicely to the new units). Restore U3 refdes silkscreen visibility.
2015-08-30 00:14:06 +00:00
(pad 27 smd rect (at 3.5 3.575 90) (size 1.85 0.45) (layers 4_bot B.Paste B.Mask)
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(net 2 +3.3V))
Footprint cleanup Remove courtyard lines from silkscreen. Round coordinates/dimensions to correct values (KiCad's old units don't convert nicely to the new units). Restore U3 refdes silkscreen visibility.
2015-08-30 00:14:06 +00:00
(pad 28 smd rect (at 3.5 4.225 90) (size 1.85 0.45) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
Footprint cleanup Remove courtyard lines from silkscreen. Round coordinates/dimensions to correct values (KiCad's old units don't convert nicely to the new units). Restore U3 refdes silkscreen visibility.
2015-08-30 00:14:06 +00:00
(module ipc_sot:IPC_SOT95P280X110-5N (layer 4_bot) (tedit 55E242AA) (tstamp 53AA2AE9)
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(at 98 147.8 180)
(path /53A8C780/53A8D586)
(fp_text reference U2 (at -2.8 2.8 180) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_text value REGULATOR_SOT23_5 (at 0 0 180) (layer B.SilkS)
(effects (font (thickness 0.3048)) (justify mirror))
)
Footprint cleanup Remove courtyard lines from silkscreen. Round coordinates/dimensions to correct values (KiCad's old units don't convert nicely to the new units). Restore U3 refdes silkscreen visibility.
2015-08-30 00:14:06 +00:00
(fp_line (start -0.475 1.45) (end 0.475 1.45) (layer B.SilkS) (width 0.1524))
(fp_line (start 0.475 1.45) (end 0.475 -1.45) (layer B.SilkS) (width 0.1524))
(fp_line (start 0.475 -1.45) (end -0.475 -1.45) (layer B.SilkS) (width 0.1524))
(fp_line (start -0.475 -1.45) (end -0.475 1.45) (layer B.SilkS) (width 0.1524))
(fp_circle (center -1.98 2.22) (end -1.88 2.22) (layer B.SilkS) (width 0.1524))
(fp_line (start -2.15 1.775) (end 2.15 1.775) (layer B.CrtYd) (width 0.1524))
(fp_line (start 2.15 1.775) (end 2.15 -1.775) (layer B.CrtYd) (width 0.1524))
(fp_line (start 2.15 -1.775) (end -2.15 -1.775) (layer B.CrtYd) (width 0.1524))
(fp_line (start -2.15 -1.775) (end -2.15 1.775) (layer B.CrtYd) (width 0.1524))
(pad 1 smd rect (at -1.35 0.95 180) (size 1.1 0.6) (layers 4_bot B.Paste B.Mask)
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(net 2 +3.3V))
Footprint cleanup Remove courtyard lines from silkscreen. Round coordinates/dimensions to correct values (KiCad's old units don't convert nicely to the new units). Restore U3 refdes silkscreen visibility.
2015-08-30 00:14:06 +00:00
(pad 2 smd rect (at -1.35 0 180) (size 1.1 0.6) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Footprint cleanup Remove courtyard lines from silkscreen. Round coordinates/dimensions to correct values (KiCad's old units don't convert nicely to the new units). Restore U3 refdes silkscreen visibility.
2015-08-30 00:14:06 +00:00
(pad 3 smd rect (at -1.35 -0.95 180) (size 1.1 0.6) (layers 4_bot B.Paste B.Mask)
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(net 2 +3.3V))
Footprint cleanup Remove courtyard lines from silkscreen. Round coordinates/dimensions to correct values (KiCad's old units don't convert nicely to the new units). Restore U3 refdes silkscreen visibility.
2015-08-30 00:14:06 +00:00
(pad 4 smd rect (at 1.35 -0.95 180) (size 1.1 0.6) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 63 "Net-(C39-Pad1)"))
Footprint cleanup Remove courtyard lines from silkscreen. Round coordinates/dimensions to correct values (KiCad's old units don't convert nicely to the new units). Restore U3 refdes silkscreen visibility.
2015-08-30 00:14:06 +00:00
(pad 5 smd rect (at 1.35 0.95 180) (size 1.1 0.6) (layers 4_bot B.Paste B.Mask)
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(net 1 +1.8V))
)
(module alps:ALPS_SCHA4B0100 (layer 4_bot) (tedit 53BC708B) (tstamp 53BC708B)
(at 68.4 114.6 90)
(path /53A9129D/53A8C6D0)
(attr smd)
(fp_text reference J2 (at -6.2 8.4 90) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_text value MICROSD_DETSW (at 0 0 90) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -5.5 -13.2) (end 3.5 -13.2) (layer Cmts.User) (width 0.1524))
(fp_line (start -5.5 -9.9) (end 3.5 -9.9) (layer Cmts.User) (width 0.1524))
(fp_line (start -5.5 -8.5) (end 3.5 -8.5) (layer Cmts.User) (width 0.1524))
(fp_line (start -1.4675 7.45) (end -1.4675 6.6) (layer Cmts.User) (width 0.1524))
(fp_line (start -1.4675 6.6) (end -2.5125 6.6) (layer Cmts.User) (width 0.1524))
(fp_line (start -2.5125 6.6) (end -2.5125 5.2) (layer Cmts.User) (width 0.1524))
(fp_line (start -2.5125 5.2) (end 1.0375 5.2) (layer Cmts.User) (width 0.1524))
(fp_line (start 1.0375 5.2) (end 1.0375 7.45) (layer Cmts.User) (width 0.1524))
(fp_line (start 1.0375 7.45) (end -1.4675 7.45) (layer Cmts.User) (width 0.1524))
(fp_line (start -6.0125 3.45) (end 2.8875 3.45) (layer Cmts.User) (width 0.1524))
(fp_line (start 2.8875 3.45) (end 2.8875 -0.95) (layer Cmts.User) (width 0.1524))
(fp_line (start 2.8875 -0.95) (end -6.0125 -0.95) (layer Cmts.User) (width 0.1524))
(fp_line (start -6.0125 -0.95) (end -6.0125 3.45) (layer Cmts.User) (width 0.1524))
(fp_line (start -6.9 -7.6) (end -6.9 7.6) (layer B.SilkS) (width 0.1524))
(fp_line (start 6.9 -7.6) (end -6.9 -7.6) (layer B.SilkS) (width 0.1524))
(fp_line (start 6.9 7.6) (end 6.9 -7.6) (layer B.SilkS) (width 0.1524))
(fp_line (start -6.9 7.6) (end 6.9 7.6) (layer B.SilkS) (width 0.1524))
(pad SH smd rect (at -4.725 7.425 90) (size 1.2 0.85) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad A smd rect (at -3.475 7.475 90) (size 0.65 0.75) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad B smd rect (at 2.875 7.475 90) (size 0.65 0.75) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 39 /hackrf_if/SD_CD))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad SH smd rect (at 6.025 7.425 90) (size 1.3 0.85) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad SH smd rect (at -6.575 -7.15 90) (size 0.95 1.1) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad SH smd rect (at 6.575 -7.25 90) (size 0.95 0.9) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 0 smd rect (at -3.275 -5.825 90) (size 0.7 0.95) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 0 smd rect (at 0.725 -5.825 90) (size 0.7 0.95) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 1 smd rect (at 2.225 -4.325 90) (size 0.7 1.05) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 44 /hackrf_if/SD_DAT2))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 2 smd rect (at 1.225 -4.325 90) (size 0.7 1.05) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 45 /hackrf_if/SD_DAT3))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 3 smd rect (at 0.225 -4.325 90) (size 0.7 1.05) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 41 /hackrf_if/SD_CMD))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 4 smd rect (at -0.775 -4.325 90) (size 0.7 1.05) (layers 4_bot B.Paste B.Mask)
(net 2 +3.3V))
(pad 5 smd rect (at -1.775 -4.325 90) (size 0.7 1.05) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 40 /hackrf_if/SD_CLK))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 6 smd rect (at -2.775 -4.325 90) (size 0.7 1.05) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 7 smd rect (at -3.775 -4.325 90) (size 0.7 1.05) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 42 /hackrf_if/SD_DAT0))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 8 smd rect (at -4.775 -4.325 90) (size 0.7 1.05) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 43 /hackrf_if/SD_DAT1))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
Footprint cleanup Remove courtyard lines from silkscreen. Round coordinates/dimensions to correct values (KiCad's old units don't convert nicely to the new units). Restore U3 refdes silkscreen visibility.
2015-08-30 00:14:06 +00:00
(module ipc_sot:IPC_SOT95P230X110-3N (layer 4_bot) (tedit 55E241DF) (tstamp 53C5B8DC)
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(at 91.6 148.4 180)
(path /53A9129D/53C5B6EB)
(fp_text reference Q1 (at -1.4 2.4 180) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_text value MOSFET_N (at 0 0 180) (layer B.SilkS)
(effects (font (thickness 0.3048)) (justify mirror))
)
Footprint cleanup Remove courtyard lines from silkscreen. Round coordinates/dimensions to correct values (KiCad's old units don't convert nicely to the new units). Restore U3 refdes silkscreen visibility.
2015-08-30 00:14:06 +00:00
(fp_line (start -1.9 1.75) (end 1.9 1.75) (layer B.CrtYd) (width 0.1524))
(fp_line (start 1.9 1.75) (end 1.9 -1.75) (layer B.CrtYd) (width 0.1524))
(fp_line (start 1.9 -1.75) (end -1.9 -1.75) (layer B.CrtYd) (width 0.1524))
(fp_line (start -1.9 -1.75) (end -1.9 1.75) (layer B.CrtYd) (width 0.1524))
(fp_line (start -0.325 1.45) (end 0.325 1.45) (layer B.SilkS) (width 0.1524))
(fp_line (start 0.325 1.45) (end 0.325 -1.45) (layer B.SilkS) (width 0.1524))
(fp_line (start 0.325 -1.45) (end -0.325 -1.45) (layer B.SilkS) (width 0.1524))
(fp_line (start -0.325 -1.45) (end -0.325 1.45) (layer B.SilkS) (width 0.1524))
(pad 1 smd rect (at -1.15 0.95 180) (size 1 0.6) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 15 /hackrf_if/LCD_BACKLIGHT))
Footprint cleanup Remove courtyard lines from silkscreen. Round coordinates/dimensions to correct values (KiCad's old units don't convert nicely to the new units). Restore U3 refdes silkscreen visibility.
2015-08-30 00:14:06 +00:00
(pad 2 smd rect (at -1.15 -0.95 180) (size 1 0.6) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Footprint cleanup Remove courtyard lines from silkscreen. Round coordinates/dimensions to correct values (KiCad's old units don't convert nicely to the new units). Restore U3 refdes silkscreen visibility.
2015-08-30 00:14:06 +00:00
(pad 3 smd rect (at 1.15 0 180) (size 1 0.6) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 64 "Net-(J3-Pad1)"))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
(module header:HEADER_13X2_REV_SM_254_AP (layer 4_bot) (tedit 53F39BE9) (tstamp 53AA297D)
(at 152.71 164.84 90)
(descr "MLE TSHSM-1")
(path /53A8C780/53A8CDB6)
(attr smd)
(fp_text reference P22 (at 4.44 16.69 90) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_text value HACKRF_ONE_P22 (at 0 0 90) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_circle (center 3.1 16.6) (end 2.9 16.6) (layer B.SilkS) (width 0.1524))
(fp_line (start -2.5 16.51) (end 2.5 16.51) (layer B.SilkS) (width 0.1524))
(fp_line (start 2.5 16.51) (end 2.5 -16.51) (layer B.SilkS) (width 0.1524))
(fp_line (start 2.5 -16.51) (end -2.5 -16.51) (layer B.SilkS) (width 0.1524))
(fp_line (start -2.5 -16.51) (end -2.5 16.51) (layer B.SilkS) (width 0.1524))
Remove line in/out components and traces, microphone. Clean up traces and via stitching affected by removed components.
2015-08-24 00:23:21 +00:00
(pad 2 smd rect (at -2.73 15.24 90) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 84 "Net-(P22-Pad2)"))
Remove line in/out components and traces, microphone. Clean up traces and via stitching affected by removed components.
2015-08-24 00:23:21 +00:00
(pad 1 smd rect (at 2.73 15.24 90) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 85 "Net-(P22-Pad1)"))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 4 smd rect (at -2.73 12.7 90) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 3 smd rect (at 2.73 12.7 90) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 38 /hackrf_if/RESET#))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 6 smd rect (at -2.73 10.16 90) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 86 /hackrf_if/MCU_LCD_TE))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 5 smd rect (at 2.73 10.16 90) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 87 /hackrf_if/MCU_LCD_RD))
Remove line in/out components and traces, microphone. Clean up traces and via stitching affected by removed components.
2015-08-24 00:23:21 +00:00
(pad 8 smd rect (at -2.73 7.62 90) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 88 "Net-(P22-Pad8)"))
Remove line in/out components and traces, microphone. Clean up traces and via stitching affected by removed components.
2015-08-24 00:23:21 +00:00
(pad 7 smd rect (at 2.73 7.62 90) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 89 "Net-(P22-Pad7)"))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 10 smd rect (at -2.73 5.08 90) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Remove line in/out components and traces, microphone. Clean up traces and via stitching affected by removed components.
2015-08-24 00:23:21 +00:00
(pad 9 smd rect (at 2.73 5.08 90) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 90 "Net-(P22-Pad9)"))
Remove line in/out components and traces, microphone. Clean up traces and via stitching affected by removed components.
2015-08-24 00:23:21 +00:00
(pad 12 smd rect (at -2.73 2.54 90) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 91 "Net-(P22-Pad12)"))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 11 smd rect (at 2.73 2.54 90) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
(net 2 +3.3V))
Remove line in/out components and traces, microphone. Clean up traces and via stitching affected by removed components.
2015-08-24 00:23:21 +00:00
(pad 14 smd rect (at -2.73 0 90) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 92 "Net-(P22-Pad14)"))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 13 smd rect (at 2.73 0 90) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 6 /audio/I2S0_TX_SDA))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 16 smd rect (at -2.73 -2.54 90) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 5 /audio/I2S0_SCK))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 15 smd rect (at 2.73 -2.54 90) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 7 /audio/I2S0_WS))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 18 smd rect (at -2.73 -5.08 90) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 17 smd rect (at 2.73 -5.08 90) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
(net 3 /audio/I2S0_MCLK))
(pad 20 smd rect (at -2.73 -7.62 90) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 93 /hackrf_if/MCU_IO_STBX))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 19 smd rect (at 2.73 -7.62 90) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 94 /hackrf_if/MCU_ADDR))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 22 smd rect (at -2.73 -10.16 90) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 95 /hackrf_if/MCU_DIR))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 21 smd rect (at 2.73 -10.16 90) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 96 /hackrf_if/MCU_LCD_WR))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 24 smd rect (at -2.73 -12.7 90) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 13 /audio/SDA))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 23 smd rect (at 2.73 -12.7 90) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 37 /hackrf_if/P2_8))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 26 smd rect (at -2.73 -15.24 90) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 12 /audio/SCL))
Remove line in/out components and traces, microphone. Clean up traces and via stitching affected by removed components.
2015-08-24 00:23:21 +00:00
(pad 25 smd rect (at 2.73 -15.24 90) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 97 "Net-(P22-Pad25)"))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad "" np_thru_hole circle (at 0 13.97 90) (size 1.8 1.8) (drill 1.8) (layers *.Cu *.Mask)
(clearance 0.4))
(pad "" np_thru_hole circle (at 0 -13.97 90) (size 1.8 1.8) (drill 1.8) (layers *.Cu *.Mask)
(clearance 0.4))
)
(module header:HEADER_11X2_REV_SM_254_AP (layer 4_bot) (tedit 53F39BE1) (tstamp 53AA299C)
(at 123.5 143.25)
(descr "MLE TSHSM-1")
(path /53A8C780/53A8CDBE)
(attr smd)
(fp_text reference P28 (at 4.5 14.15) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_text value HACKRF_ONE_P28 (at 0 0) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_circle (center 3.1 14) (end 2.9 14) (layer B.SilkS) (width 0.1524))
(fp_line (start -2.5 13.97) (end 2.5 13.97) (layer B.SilkS) (width 0.1524))
(fp_line (start 2.5 13.97) (end 2.5 -13.97) (layer B.SilkS) (width 0.1524))
(fp_line (start 2.5 -13.97) (end -2.5 -13.97) (layer B.SilkS) (width 0.1524))
(fp_line (start -2.5 -13.97) (end -2.5 13.97) (layer B.SilkS) (width 0.1524))
(pad 2 smd rect (at -2.73 12.7) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 1 smd rect (at 2.73 12.7) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
(net 2 +3.3V))
(pad 4 smd rect (at -2.73 10.16) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 45 /hackrf_if/SD_DAT3))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 3 smd rect (at 2.73 10.16) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 39 /hackrf_if/SD_CD))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 6 smd rect (at -2.73 7.62) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 43 /hackrf_if/SD_DAT1))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 5 smd rect (at 2.73 7.62) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 44 /hackrf_if/SD_DAT2))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 8 smd rect (at -2.73 5.08) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 98 /hackrf_if/PP_CPLD_TMS))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 7 smd rect (at 2.73 5.08) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 42 /hackrf_if/SD_DAT0))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 10 smd rect (at -2.73 2.54) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 99 /hackrf_if/PP_CPLD_TDO))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 9 smd rect (at 2.73 2.54) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 41 /hackrf_if/SD_CMD))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 12 smd rect (at -2.73 0) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 11 smd rect (at 2.73 0) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 40 /hackrf_if/SD_CLK))
Remove line in/out components and traces, microphone. Clean up traces and via stitching affected by removed components.
2015-08-24 00:23:21 +00:00
(pad 14 smd rect (at -2.73 -2.54) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 100 "Net-(P28-Pad14)"))
Remove line in/out components and traces, microphone. Clean up traces and via stitching affected by removed components.
2015-08-24 00:23:21 +00:00
(pad 13 smd rect (at 2.73 -2.54) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 101 "Net-(P28-Pad13)"))
Remove line in/out components and traces, microphone. Clean up traces and via stitching affected by removed components.
2015-08-24 00:23:21 +00:00
(pad 16 smd rect (at -2.73 -5.08) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 102 "Net-(P28-Pad16)"))
Remove line in/out components and traces, microphone. Clean up traces and via stitching affected by removed components.
2015-08-24 00:23:21 +00:00
(pad 15 smd rect (at 2.73 -5.08) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 103 "Net-(P28-Pad15)"))
Remove line in/out components and traces, microphone. Clean up traces and via stitching affected by removed components.
2015-08-24 00:23:21 +00:00
(pad 18 smd rect (at -2.73 -7.62) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 104 "Net-(P28-Pad18)"))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 17 smd rect (at 2.73 -7.62) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 105 /hackrf_if/H1_CPLD_TCK))
Remove line in/out components and traces, microphone. Clean up traces and via stitching affected by removed components.
2015-08-24 00:23:21 +00:00
(pad 20 smd rect (at -2.73 -10.16) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 106 "Net-(P28-Pad20)"))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 19 smd rect (at 2.73 -10.16) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 107 /hackrf_if/H1_CPLD_TDI))
Remove line in/out components and traces, microphone. Clean up traces and via stitching affected by removed components.
2015-08-24 00:23:21 +00:00
(pad 22 smd rect (at -2.73 -12.7) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 108 "Net-(P28-Pad22)"))
Remove line in/out components and traces, microphone. Clean up traces and via stitching affected by removed components.
2015-08-24 00:23:21 +00:00
(pad 21 smd rect (at 2.73 -12.7) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 109 "Net-(P28-Pad21)"))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad "" np_thru_hole circle (at 0 11.43) (size 1.8 1.8) (drill 1.8) (layers *.Cu *.Mask)
(clearance 0.4))
(pad "" np_thru_hole circle (at 0 -11.43) (size 1.8 1.8) (drill 1.8) (layers *.Cu *.Mask)
(clearance 0.4))
)
(module header:HEADER_11X2_REV_SM_254_AP (layer 4_bot) (tedit 53F39BF0) (tstamp 53AA295A)
(at 171.76 143.25)
(descr "MLE TSHSM-1")
(path /53A8C780/53A8CDAE)
(attr smd)
(fp_text reference P20 (at 4.44 14.15) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
)
(fp_text value HACKRF_ONE_P20 (at 0 0) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_circle (center 3.1 14) (end 2.9 14) (layer B.SilkS) (width 0.1524))
(fp_line (start -2.5 13.97) (end 2.5 13.97) (layer B.SilkS) (width 0.1524))
(fp_line (start 2.5 13.97) (end 2.5 -13.97) (layer B.SilkS) (width 0.1524))
(fp_line (start 2.5 -13.97) (end -2.5 -13.97) (layer B.SilkS) (width 0.1524))
(fp_line (start -2.5 -13.97) (end -2.5 13.97) (layer B.SilkS) (width 0.1524))
Remove line in/out components and traces, microphone. Clean up traces and via stitching affected by removed components.
2015-08-24 00:23:21 +00:00
(pad 2 smd rect (at -2.73 12.7) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 71 "Net-(P20-Pad2)"))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 1 smd rect (at 2.73 12.7) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 57 /hackrf_if/VBAT))
Remove line in/out components and traces, microphone. Clean up traces and via stitching affected by removed components.
2015-08-24 00:23:21 +00:00
(pad 4 smd rect (at -2.73 10.16) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 72 "Net-(P20-Pad4)"))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 3 smd rect (at 2.73 10.16) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
(net 2 +3.3V))
(pad 6 smd rect (at -2.73 7.62) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 73 /hackrf_if/MCU_D1))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 5 smd rect (at 2.73 7.62) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 74 /hackrf_if/MCU_D0))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 8 smd rect (at -2.73 5.08) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 75 /hackrf_if/MCU_D3))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 7 smd rect (at 2.73 5.08) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 76 /hackrf_if/MCU_D2))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 10 smd rect (at -2.73 2.54) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 77 /hackrf_if/MCU_D5))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 9 smd rect (at 2.73 2.54) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 78 /hackrf_if/MCU_D4))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 12 smd rect (at -2.73 0) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 79 /hackrf_if/MCU_D7))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 11 smd rect (at 2.73 0) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 80 /hackrf_if/MCU_D6))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 14 smd rect (at -2.73 -2.54) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 55 /hackrf_if/TP_R))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 13 smd rect (at 2.73 -2.54) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 16 smd rect (at -2.73 -5.08) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 53 /hackrf_if/TP_D))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 15 smd rect (at 2.73 -5.08) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 18 smd rect (at -2.73 -7.62) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 54 /hackrf_if/TP_L))
Remove line in/out components and traces, microphone. Clean up traces and via stitching affected by removed components.
2015-08-24 00:23:21 +00:00
(pad 17 smd rect (at 2.73 -7.62) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 81 "Net-(P20-Pad17)"))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 20 smd rect (at -2.73 -10.16) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 56 /hackrf_if/TP_U))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 19 smd rect (at 2.73 -10.16) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND))
Remove line in/out components and traces, microphone. Clean up traces and via stitching affected by removed components.
2015-08-24 00:23:21 +00:00
(pad 22 smd rect (at -2.73 -12.7) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 82 "Net-(P20-Pad22)"))
Remove line in/out components and traces, microphone. Clean up traces and via stitching affected by removed components.
2015-08-24 00:23:21 +00:00
(pad 21 smd rect (at 2.73 -12.7) (size 3.18 1.02) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 83 "Net-(P20-Pad21)"))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad "" np_thru_hole circle (at 0 11.43) (size 1.8 1.8) (drill 1.8) (layers *.Cu *.Mask)
(clearance 0.4))
(pad "" np_thru_hole circle (at 0 -11.43) (size 1.8 1.8) (drill 1.8) (layers *.Cu *.Mask)
(clearance 0.4))
)
Footprint cleanup Remove courtyard lines from silkscreen. Round coordinates/dimensions to correct values (KiCad's old units don't convert nicely to the new units). Restore U3 refdes silkscreen visibility.
2015-08-30 00:14:06 +00:00
(module ipc_qfp:IPC_QFP40P900X900X120-65N (layer 4_bot) (tedit 55E249FD) (tstamp 53AA699D)
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(at 97.6 132.8 270)
(path /53A8C780/53A8D11B)
Reduce mask margin on QFP pads.
2015-08-29 23:12:45 +00:00
(solder_mask_margin 0.0492)
Footprint cleanup Remove courtyard lines from silkscreen. Round coordinates/dimensions to correct values (KiCad's old units don't convert nicely to the new units). Restore U3 refdes silkscreen visibility.
2015-08-30 00:14:06 +00:00
(fp_text reference U3 (at -4.8 6 360) (layer B.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.1524)) (justify mirror))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
(fp_text value 5M40ZE64 (at 0 0 270) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_circle (center -5.6 3) (end -5.5 3) (layer B.SilkS) (width 0.15))
Footprint cleanup Remove courtyard lines from silkscreen. Round coordinates/dimensions to correct values (KiCad's old units don't convert nicely to the new units). Restore U3 refdes silkscreen visibility.
2015-08-30 00:14:06 +00:00
(fp_line (start -5.2 5.2) (end -5.2 -5.2) (layer B.CrtYd) (width 0.15))
(fp_line (start -5.2 -5.2) (end 5.2 -5.2) (layer B.CrtYd) (width 0.15))
(fp_line (start 5.2 -5.2) (end 5.2 5.2) (layer B.CrtYd) (width 0.15))
(fp_line (start 5.2 5.2) (end -5.2 5.2) (layer B.CrtYd) (width 0.15))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(fp_line (start -3.1 3.1) (end -3.1 -3.1) (layer B.SilkS) (width 0.15))
(fp_line (start -3.1 -3.1) (end 3.1 -3.1) (layer B.SilkS) (width 0.15))
(fp_line (start 3.1 -3.1) (end 3.1 3.1) (layer B.SilkS) (width 0.15))
(fp_line (start 3.1 3.1) (end -3.1 3.1) (layer B.SilkS) (width 0.15))
(pad 1 smd rect (at -4.2 3 270) (size 1.5 0.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 53 /hackrf_if/TP_D))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 2 smd rect (at -4.2 2.6 270) (size 1.5 0.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 54 /hackrf_if/TP_L))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 3 smd rect (at -4.2 2.2 270) (size 1.5 0.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 56 /hackrf_if/TP_U))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 4 smd rect (at -4.2 1.8 270) (size 1.5 0.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 15 /hackrf_if/LCD_BACKLIGHT))
Remove line in/out components and traces, microphone. Clean up traces and via stitching affected by removed components.
2015-08-24 00:23:21 +00:00
(pad 5 smd rect (at -4.2 1.4 270) (size 1.5 0.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 116 "Net-(U3-Pad5)"))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 6 smd rect (at -4.2 1 270) (size 1.5 0.2) (layers 4_bot B.Paste B.Mask)
(net 2 +3.3V))
Remove line in/out components and traces, microphone. Clean up traces and via stitching affected by removed components.
2015-08-24 00:23:21 +00:00
(pad 7 smd rect (at -4.2 0.6 270) (size 1.5 0.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 117 "Net-(U3-Pad7)"))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 8 smd rect (at -4.2 0.2 270) (size 1.5 0.2) (layers 4_bot B.Paste B.Mask)
(net 1 +1.8V))
(pad 9 smd rect (at -4.2 -0.2 270) (size 1.5 0.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 48 /hackrf_if/SW_R))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 10 smd rect (at -4.2 -0.6 270) (size 1.5 0.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 46 /hackrf_if/SW_D))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 11 smd rect (at -4.2 -1 270) (size 1.5 0.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 49 /hackrf_if/SW_ROT_A))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 12 smd rect (at -4.2 -1.4 270) (size 1.5 0.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 50 /hackrf_if/SW_ROT_B))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 13 smd rect (at -4.2 -1.8 270) (size 1.5 0.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 51 /hackrf_if/SW_SEL))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 14 smd rect (at -4.2 -2.2 270) (size 1.5 0.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 98 /hackrf_if/PP_CPLD_TMS))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 15 smd rect (at -4.2 -2.6 270) (size 1.5 0.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 107 /hackrf_if/H1_CPLD_TDI))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 16 smd rect (at -4.2 -3 270) (size 1.5 0.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 105 /hackrf_if/H1_CPLD_TCK))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 17 smd rect (at -3 -4.2 180) (size 1.5 0.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 99 /hackrf_if/PP_CPLD_TDO))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 18 smd rect (at -2.6 -4.2 180) (size 1.5 0.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 79 /hackrf_if/MCU_D7))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 19 smd rect (at -2.2 -4.2 180) (size 1.5 0.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 80 /hackrf_if/MCU_D6))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 20 smd rect (at -1.8 -4.2 180) (size 1.5 0.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 78 /hackrf_if/MCU_D4))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 21 smd rect (at -1.4 -4.2 180) (size 1.5 0.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 77 /hackrf_if/MCU_D5))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 22 smd rect (at -1 -4.2 180) (size 1.5 0.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 75 /hackrf_if/MCU_D3))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 23 smd rect (at -0.6 -4.2 180) (size 1.5 0.2) (layers 4_bot B.Paste B.Mask)
(net 2 +3.3V))
(pad 24 smd rect (at -0.2 -4.2 180) (size 1.5 0.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 76 /hackrf_if/MCU_D2))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 25 smd rect (at 0.2 -4.2 180) (size 1.5 0.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 52 /hackrf_if/SW_U))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 26 smd rect (at 0.6 -4.2 180) (size 1.5 0.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 74 /hackrf_if/MCU_D0))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 27 smd rect (at 1 -4.2 180) (size 1.5 0.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 73 /hackrf_if/MCU_D1))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 28 smd rect (at 1.4 -4.2 180) (size 1.5 0.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 47 /hackrf_if/SW_L))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 29 smd rect (at 1.8 -4.2 180) (size 1.5 0.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 38 /hackrf_if/RESET#))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 30 smd rect (at 2.2 -4.2 180) (size 1.5 0.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 87 /hackrf_if/MCU_LCD_RD))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 31 smd rect (at 2.6 -4.2 180) (size 1.5 0.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 86 /hackrf_if/MCU_LCD_TE))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 32 smd rect (at 3 -4.2 180) (size 1.5 0.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 93 /hackrf_if/MCU_IO_STBX))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 33 smd rect (at 4.2 -3 90) (size 1.5 0.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 94 /hackrf_if/MCU_ADDR))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 34 smd rect (at 4.2 -2.6 90) (size 1.5 0.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 37 /hackrf_if/P2_8))
Remove line in/out components and traces, microphone. Clean up traces and via stitching affected by removed components.
2015-08-24 00:23:21 +00:00
(pad 35 smd rect (at 4.2 -2.2 90) (size 1.5 0.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 118 "Net-(U3-Pad35)"))
Remove line in/out components and traces, microphone. Clean up traces and via stitching affected by removed components.
2015-08-24 00:23:21 +00:00
(pad 36 smd rect (at 4.2 -1.8 90) (size 1.5 0.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 119 "Net-(U3-Pad36)"))
Remove line in/out components and traces, microphone. Clean up traces and via stitching affected by removed components.
2015-08-24 00:23:21 +00:00
(pad 37 smd rect (at 4.2 -1.4 90) (size 1.5 0.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 120 "Net-(U3-Pad37)"))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 38 smd rect (at 4.2 -1 90) (size 1.5 0.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 33 /hackrf_if/LCD_RESET#))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 39 smd rect (at 4.2 -0.6 90) (size 1.5 0.2) (layers 4_bot B.Paste B.Mask)
(net 1 +1.8V))
(pad 40 smd rect (at 4.2 -0.2 90) (size 1.5 0.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 96 /hackrf_if/MCU_LCD_WR))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 41 smd rect (at 4.2 0.2 90) (size 1.5 0.2) (layers 4_bot B.Paste B.Mask)
(net 1 +1.8V))
(pad 42 smd rect (at 4.2 0.6 90) (size 1.5 0.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 95 /hackrf_if/MCU_DIR))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 43 smd rect (at 4.2 1 90) (size 1.5 0.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 34 /hackrf_if/LCD_RS))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 44 smd rect (at 4.2 1.4 90) (size 1.5 0.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 32 /hackrf_if/LCD_RD#))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 45 smd rect (at 4.2 1.8 90) (size 1.5 0.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 36 /hackrf_if/LCD_WR#))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 46 smd rect (at 4.2 2.2 90) (size 1.5 0.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 23 /hackrf_if/LCD_DB15))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 47 smd rect (at 4.2 2.6 90) (size 1.5 0.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 22 /hackrf_if/LCD_DB14))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 48 smd rect (at 4.2 3 90) (size 1.5 0.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 21 /hackrf_if/LCD_DB13))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 49 smd rect (at 3 4.2) (size 1.5 0.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 20 /hackrf_if/LCD_DB12))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 50 smd rect (at 2.6 4.2) (size 1.5 0.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 19 /hackrf_if/LCD_DB11))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 51 smd rect (at 2.2 4.2) (size 1.5 0.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 18 /hackrf_if/LCD_DB10))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 52 smd rect (at 1.8 4.2) (size 1.5 0.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 31 /hackrf_if/LCD_DB9))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 53 smd rect (at 1.4 4.2) (size 1.5 0.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 30 /hackrf_if/LCD_DB8))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 54 smd rect (at 1 4.2) (size 1.5 0.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 29 /hackrf_if/LCD_DB7))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 55 smd rect (at 0.6 4.2) (size 1.5 0.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 28 /hackrf_if/LCD_DB6))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 56 smd rect (at 0.2 4.2) (size 1.5 0.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 27 /hackrf_if/LCD_DB5))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 57 smd rect (at -0.2 4.2) (size 1.5 0.2) (layers 4_bot B.Paste B.Mask)
(net 1 +1.8V))
(pad 58 smd rect (at -0.6 4.2) (size 1.5 0.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 26 /hackrf_if/LCD_DB4))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 59 smd rect (at -1 4.2) (size 1.5 0.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 25 /hackrf_if/LCD_DB3))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 60 smd rect (at -1.4 4.2) (size 1.5 0.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 24 /hackrf_if/LCD_DB2))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 61 smd rect (at -1.8 4.2) (size 1.5 0.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 17 /hackrf_if/LCD_DB1))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 62 smd rect (at -2.2 4.2) (size 1.5 0.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 16 /hackrf_if/LCD_DB0))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 63 smd rect (at -2.6 4.2) (size 1.5 0.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 35 /hackrf_if/LCD_TE))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 64 smd rect (at -3 4.2) (size 1.5 0.2) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 55 /hackrf_if/TP_R))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 65 smd rect (at -1.375 1.375 270) (size 2.75 2.75) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND) (solder_mask_margin 0.0762) (solder_paste_margin_ratio -0.1))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 65 smd rect (at 1.375 1.375 270) (size 2.75 2.75) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND) (solder_mask_margin 0.0762) (solder_paste_margin_ratio -0.1))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 65 smd rect (at -1.375 -1.375 270) (size 2.75 2.75) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND) (solder_mask_margin 0.0762) (solder_paste_margin_ratio -0.1))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(pad 65 smd rect (at 1.375 -1.375 270) (size 2.75 2.75) (layers 4_bot B.Paste B.Mask)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(net 58 GND) (solder_mask_margin 0.0762) (solder_paste_margin_ratio -0.1))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
Board stack-up drawing clean-up.
2015-09-01 17:13:51 +00:00
(gr_text "Drills are in two files, one for PTH, one for NPTH." (at 20 61) (layer Dwgs.User)
Change drawing lines width to 0.1mm.
2015-09-01 17:02:07 +00:00
(effects (font (size 1.5 1.5) (thickness 0.1)) (justify left))
Note about separate PTH and NPTH drill files.
2015-08-31 00:23:53 +00:00
)
Add default dimension units note.
2015-08-31 00:18:14 +00:00
(gr_text "Dimensions in inches, unless otherwise specified." (at 205 168) (layer Dwgs.User)
Change drawing lines width to 0.1mm.
2015-09-01 17:02:07 +00:00
(effects (font (size 1.5 1.5) (thickness 0.1)) (justify left))
Add default dimension units note.
2015-08-31 00:18:14 +00:00
)
Add notes block.
2015-08-31 00:11:59 +00:00
(gr_text "Notes, unless otherwise specified:\n\n1. Corner radii, inside: .047 min, unless otherwise stated.\n Corner radii, outside: break all sharp edges and corners.\n\n2. Tolerances:\n Warpage: .010/inch max along longest diag.\n Etching: +/-20% of master pattern.\n\n PTH hole diameter:\n < .100 +/- .003\n > .100 +/- .005\n < .016 + .003, -(hole diameter)\n NPTH hole diameter:\n < .100 +/- .002\n > .100 +/- .003\n\n Front-to-back reg: .005 max.\n (Do not use top-to-bottom pad alignment.)\n Hole plating: .001 min, .003 max.\n Hole diameters are finished sizes.\n\n3. Material: glass-epoxy resin sheet. Refer to board\n stackup for weight of Cu. 2 sides, flame-retardant.\n NEMA grade high temp FR4, TG requirement >= 170C.\n\n4. Finish: Soldermask over bare copper using LPI mask.\n Mask thickness: .0004 min, .0013 max.\n Color: Black\n\n5. Silkscreen legend to board using non-conductive,\n epoxy paint. Remove silkscreen from pads.\n Color: White\n\n6. Acceptability based on IPC-A-600 class 2 (latest revision).\n\n7. Test all boards for opens and shorts.\n\n8. No silkscreen on pads or test points.\n\n9. Do not block mask fine pitch SMD pads.\n\n10. No solder mask on fiducials.\n\n11. No solder mask may cover any gold fingers, if applicable.\n\n12. Do not use top-to-bottom pad alignment.\n Via alignment is recommended.\n\n13. Do not modify solder mask via flooding design.\n Do not modify solder mask chimney designs for test points.\n\n14. No Gerber modifications allowed without prior written\n approval, except for impedance trace width modifications\n to meet requirements, and the addition of tear drops where\n required.\n\n15. Raw material and finished PCB must be RoHS-compliant." (at 200 90) (layer Dwgs.User)
Change drawing lines width to 0.1mm.
2015-09-01 17:02:07 +00:00
(effects (font (size 1.5 1.5) (thickness 0.1)) (justify left))
Add notes block.
2015-08-31 00:11:59 +00:00
)
Change drawing lines width to 0.1mm.
2015-09-01 17:02:07 +00:00
(dimension 75 (width 0.1) (layer Dwgs.User)
Add PCB dimensions
2015-08-30 23:24:07 +00:00
(gr_text "75.000 mm" (at 53.65 137.5 90) (layer Dwgs.User)
Change drawing lines width to 0.1mm.
2015-09-01 17:02:07 +00:00
(effects (font (size 1.5 1.5) (thickness 0.1)))
Add PCB dimensions
2015-08-30 23:24:07 +00:00
)
(feature1 (pts (xy 60 100) (xy 52.3 100)))
(feature2 (pts (xy 60 175) (xy 52.3 175)))
(crossbar (pts (xy 55 175) (xy 55 100)))
(arrow1a (pts (xy 55 100) (xy 55.586421 101.126504)))
(arrow1b (pts (xy 55 100) (xy 54.413579 101.126504)))
(arrow2a (pts (xy 55 175) (xy 55.586421 173.873496)))
(arrow2b (pts (xy 55 175) (xy 54.413579 173.873496)))
)
Change drawing lines width to 0.1mm.
2015-09-01 17:02:07 +00:00
(dimension 120 (width 0.1) (layer Dwgs.User)
Add PCB dimensions
2015-08-30 23:24:07 +00:00
(gr_text "120.000 mm" (at 120 93.65) (layer Dwgs.User)
Change drawing lines width to 0.1mm.
2015-09-01 17:02:07 +00:00
(effects (font (size 1.5 1.5) (thickness 0.1)))
Add PCB dimensions
2015-08-30 23:24:07 +00:00
)
(feature1 (pts (xy 180 100) (xy 180 92.3)))
(feature2 (pts (xy 60 100) (xy 60 92.3)))
(crossbar (pts (xy 60 95) (xy 180 95)))
(arrow1a (pts (xy 180 95) (xy 178.873496 95.586421)))
(arrow1b (pts (xy 180 95) (xy 178.873496 94.413579)))
(arrow2a (pts (xy 60 95) (xy 61.126504 95.586421)))
(arrow2b (pts (xy 60 95) (xy 61.126504 94.413579)))
)
Board stack-up drawing clean-up.
2015-09-01 17:13:51 +00:00
(gr_line (start 90.5 25) (end 101.5 25) (layer Dwgs.User) (width 0.1))
(gr_line (start 45 25) (end 54 25) (layer Dwgs.User) (width 0.1))
(gr_line (start 28 25) (end 33 25) (layer Dwgs.User) (width 0.1))
(gr_line (start 20 25) (end 24 25) (layer Dwgs.User) (width 0.1))
(gr_text "62 mil +/- 10%\nBoard Thickness" (at 107.5 41) (layer Dwgs.User)
Change drawing lines width to 0.1mm.
2015-09-01 17:02:07 +00:00
(effects (font (size 1.5 1.5) (thickness 0.1)) (justify left))
)
Board stack-up drawing clean-up.
2015-09-01 17:13:51 +00:00
(gr_line (start 105 49) (end 105.5 47.5) (layer Dwgs.User) (width 0.1))
(gr_line (start 105 49) (end 104.5 47.5) (layer Dwgs.User) (width 0.1))
(gr_line (start 105 33) (end 105.5 34.5) (layer Dwgs.User) (width 0.1))
(gr_line (start 105 33) (end 104.5 34.5) (layer Dwgs.User) (width 0.1))
(gr_line (start 105 33) (end 105 49) (layer Dwgs.User) (width 0.1))
(gr_line (start 102.5 49) (end 107.5 49) (layer Dwgs.User) (width 0.1))
(gr_line (start 102.5 33) (end 107.5 33) (layer Dwgs.User) (width 0.1))
(gr_line (start 72.5 39.7) (end 72.5 37.7) (layer Dwgs.User) (width 0.1) (tstamp 55E38A17))
(gr_line (start 72.5 38.7) (end 73.5 37.7) (layer Dwgs.User) (width 0.1) (tstamp 55E38A16))
(gr_line (start 72.5 39.7) (end 74.5 37.7) (layer Dwgs.User) (width 0.1) (tstamp 55E38A15))
(gr_line (start 73.5 39.7) (end 75.5 37.7) (layer Dwgs.User) (width 0.1) (tstamp 55E38A14))
(gr_line (start 76.5 39.7) (end 78.5 37.7) (layer Dwgs.User) (width 0.1) (tstamp 55E38A13))
(gr_line (start 75.5 39.7) (end 77.5 37.7) (layer Dwgs.User) (width 0.1) (tstamp 55E38A12))
(gr_line (start 74.5 39.7) (end 76.5 37.7) (layer Dwgs.User) (width 0.1) (tstamp 55E38A11))
(gr_line (start 72.5 39.7) (end 87.5 39.7) (layer Dwgs.User) (width 0.1) (tstamp 55E38A10))
(gr_line (start 72.5 37.7) (end 87.5 37.7) (layer Dwgs.User) (width 0.1) (tstamp 55E38A0F))
(gr_line (start 81.5 39.7) (end 83.5 37.7) (layer Dwgs.User) (width 0.1) (tstamp 55E38A0E))
(gr_line (start 80.5 39.7) (end 82.5 37.7) (layer Dwgs.User) (width 0.1) (tstamp 55E38A0D))
(gr_line (start 79.5 39.7) (end 81.5 37.7) (layer Dwgs.User) (width 0.1) (tstamp 55E38A0C))
(gr_line (start 78.5 39.7) (end 80.5 37.7) (layer Dwgs.User) (width 0.1) (tstamp 55E38A0B))
(gr_line (start 77.5 39.7) (end 79.5 37.7) (layer Dwgs.User) (width 0.1) (tstamp 55E38A0A))
(gr_line (start 87.5 39.7) (end 87.5 37.7) (layer Dwgs.User) (width 0.1) (tstamp 55E38A09))
(gr_line (start 86.5 39.7) (end 87.5 38.7) (layer Dwgs.User) (width 0.1) (tstamp 55E38A08))
(gr_line (start 85.5 39.7) (end 87.5 37.7) (layer Dwgs.User) (width 0.1) (tstamp 55E38A07))
(gr_line (start 84.5 39.7) (end 86.5 37.7) (layer Dwgs.User) (width 0.1) (tstamp 55E38A06))
(gr_line (start 83.5 39.7) (end 85.5 37.7) (layer Dwgs.User) (width 0.1) (tstamp 55E38A05))
(gr_line (start 82.5 39.7) (end 84.5 37.7) (layer Dwgs.User) (width 0.1) (tstamp 55E38A04))
(gr_line (start 86.5 44.3) (end 87.5 43.3) (layer Dwgs.User) (width 0.1))
(gr_line (start 85.5 44.3) (end 87.5 42.3) (layer Dwgs.User) (width 0.1))
(gr_line (start 84.5 44.3) (end 86.5 42.3) (layer Dwgs.User) (width 0.1))
(gr_line (start 83.5 44.3) (end 85.5 42.3) (layer Dwgs.User) (width 0.1))
(gr_line (start 82.5 44.3) (end 84.5 42.3) (layer Dwgs.User) (width 0.1))
(gr_line (start 81.5 44.3) (end 83.5 42.3) (layer Dwgs.User) (width 0.1))
(gr_line (start 80.5 44.3) (end 82.5 42.3) (layer Dwgs.User) (width 0.1))
(gr_line (start 79.5 44.3) (end 81.5 42.3) (layer Dwgs.User) (width 0.1))
(gr_line (start 78.5 44.3) (end 80.5 42.3) (layer Dwgs.User) (width 0.1))
(gr_line (start 77.5 44.3) (end 79.5 42.3) (layer Dwgs.User) (width 0.1))
(gr_line (start 76.5 44.3) (end 78.5 42.3) (layer Dwgs.User) (width 0.1))
(gr_line (start 75.5 44.3) (end 77.5 42.3) (layer Dwgs.User) (width 0.1))
(gr_line (start 74.5 44.3) (end 76.5 42.3) (layer Dwgs.User) (width 0.1))
(gr_line (start 73.5 44.3) (end 75.5 42.3) (layer Dwgs.User) (width 0.1))
(gr_line (start 72.5 44.3) (end 72.5 42.3) (layer Dwgs.User) (width 0.1))
(gr_line (start 87.5 44.3) (end 87.5 42.3) (layer Dwgs.User) (width 0.1))
(gr_line (start 82 35.2) (end 82.5 34.7) (layer Dwgs.User) (width 0.1))
(gr_line (start 81 35.2) (end 82.5 33.7) (layer Dwgs.User) (width 0.1))
(gr_line (start 80 35.2) (end 81.5 33.7) (layer Dwgs.User) (width 0.1))
(gr_line (start 79 35.2) (end 80.5 33.7) (layer Dwgs.User) (width 0.1))
(gr_line (start 78 35.2) (end 79.5 33.7) (layer Dwgs.User) (width 0.1))
(gr_line (start 77.5 34.7) (end 78.5 33.7) (layer Dwgs.User) (width 0.1))
(gr_line (start 82 48.3) (end 82.5 47.8) (layer Dwgs.User) (width 0.1))
(gr_line (start 81 48.3) (end 82.5 46.8) (layer Dwgs.User) (width 0.1))
(gr_line (start 80 48.3) (end 81.5 46.8) (layer Dwgs.User) (width 0.1))
(gr_line (start 79 48.3) (end 80.5 46.8) (layer Dwgs.User) (width 0.1))
(gr_line (start 78 48.3) (end 79.5 46.8) (layer Dwgs.User) (width 0.1))
(gr_line (start 77.5 47.8) (end 78.5 46.8) (layer Dwgs.User) (width 0.1))
(gr_line (start 72.5 44.3) (end 74.5 42.3) (layer Dwgs.User) (width 0.1))
(gr_line (start 72.5 43.3) (end 73.5 42.3) (layer Dwgs.User) (width 0.1))
(gr_line (start 72.5 51.2) (end 87.5 51.2) (layer Dwgs.User) (width 0.1) (tstamp 55E38631))
(gr_line (start 72.5 30.8) (end 87.5 30.8) (layer Dwgs.User) (width 0.1) (tstamp 55E385FB))
(gr_line (start 72.5 49) (end 87.5 49) (layer Dwgs.User) (width 0.1) (tstamp 55E38573))
(gr_line (start 77.5 48.3) (end 82.5 48.3) (layer Dwgs.User) (width 0.1) (tstamp 55E3856C))
(gr_line (start 77.5 46.8) (end 77.5 48.3) (layer Dwgs.User) (width 0.1) (tstamp 55E38565))
(gr_line (start 82.5 46.8) (end 82.5 48.3) (layer Dwgs.User) (width 0.1) (tstamp 55E38563))
(gr_line (start 72.5 46.8) (end 87.5 46.8) (layer Dwgs.User) (width 0.1) (tstamp 55E3855C))
(gr_line (start 72.5 44.3) (end 87.5 44.3) (layer Dwgs.User) (width 0.1) (tstamp 55E38536))
(gr_line (start 72.5 42.3) (end 87.5 42.3) (layer Dwgs.User) (width 0.1) (tstamp 55E38531))
(gr_line (start 72.5 33) (end 87.5 33) (layer Dwgs.User) (width 0.1) (tstamp 55E384EF))
(gr_line (start 82.5 33.7) (end 82.5 35.2) (layer Dwgs.User) (width 0.1))
(gr_line (start 77.5 33.7) (end 82.5 33.7) (layer Dwgs.User) (width 0.1))
(gr_line (start 77.5 35.2) (end 77.5 33.7) (layer Dwgs.User) (width 0.1))
(gr_line (start 72.5 35.2) (end 87.5 35.2) (layer Dwgs.User) (width 0.1))
Change PCB stack-up for vendor.
2015-09-01 17:01:39 +00:00
(gr_text "Material\n\n\nWhite\nBlack\n0.5 oz Copper + ENIG\nFR-4 TG170\n1 oz Copper\nFR-4 TG170\n1 oz Copper\nFR-4 TG170\n0.5 oz Copper + ENIG\nBlack\nWhite\n\nCenter line is finished edge\n" (at 45 40) (layer Dwgs.User) (tstamp 55E3838A)
Change drawing lines width to 0.1mm.
2015-09-01 17:02:07 +00:00
(effects (font (size 1.5 1.5) (thickness 0.1)) (justify left))
Add PCB stack data and diagram.
2015-08-30 23:23:55 +00:00
)
Board stack-up drawing clean-up.
2015-09-01 17:13:51 +00:00
(gr_text "Thickness\n\n\n\n0.8 mil\n1.7 mil\n8.0 mil\n1.4 mil\n\n1.4 mil\n8.0 mil\n1.7 mil\n0.8 mil\n\n\n\n" (at 90.5 40) (layer Dwgs.User) (tstamp 55E381F6)
Change drawing lines width to 0.1mm.
2015-09-01 17:02:07 +00:00
(effects (font (size 1.5 1.5) (thickness 0.1)) (justify left))
Add PCB stack data and diagram.
2015-08-30 23:23:55 +00:00
)
Board stack-up drawing clean-up.
2015-09-01 17:13:51 +00:00
(gr_text "Type\n\nSolder paste\nSilkscreen\nSolder mask\nSignal\nPrepreg\nPower\nCore\nPower\nPrepreg\nSignal\nSolder mask\nSilkscreen\nSolder paste\nBoard outline" (at 28 40) (layer Dwgs.User)
Change drawing lines width to 0.1mm.
2015-09-01 17:02:07 +00:00
(effects (font (size 1.5 1.5) (thickness 0.1)) (justify left))
Add PCB stack data and diagram.
2015-08-30 23:23:55 +00:00
)
(gr_text "File\n\n.GTP\n.GTO\n.GTS\n.GTL\n\n.G1\n\n.G2\n\n.GBL\n.GBS\n.GBO\n.GBP\n.GKO\n" (at 20 40) (layer Dwgs.User)
Change drawing lines width to 0.1mm.
2015-09-01 17:02:07 +00:00
(effects (font (size 1.5 1.5) (thickness 0.1)) (justify left))
Add PCB stack data and diagram.
2015-08-30 23:23:55 +00:00
)
PCB: Interim revision number/date.
2017-01-28 22:54:33 +00:00
(gr_text ???????? (at 75 164 180) (layer F.SilkS)
Add PCB stack data and diagram.
2015-08-30 23:23:55 +00:00
(effects (font (size 1.524 0.762) (thickness 0.1524)))
)
Move and shrink copper layer legend. Doesn't need to be visible after assembly. I think.
2015-08-30 17:14:36 +00:00
(gr_text 4 (at 76.5 139 90) (layer 4_bot)
(effects (font (size 1.016 1.016) (thickness 0.2032)) (justify mirror))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
Move and shrink copper layer legend. Doesn't need to be visible after assembly. I think.
2015-08-30 17:14:36 +00:00
(gr_text 3 (at 76.5 138 90) (layer 3_gnd)
(effects (font (size 1.016 1.016) (thickness 0.2032)) (justify mirror))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
Move and shrink copper layer legend. Doesn't need to be visible after assembly. I think.
2015-08-30 17:14:36 +00:00
(gr_text 2 (at 76.5 137 90) (layer 2_pwr) (tstamp 53AE501D)
(effects (font (size 1.016 1.016) (thickness 0.2032)) (justify mirror))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
Move and shrink copper layer legend. Doesn't need to be visible after assembly. I think.
2015-08-30 17:14:36 +00:00
(gr_text 1 (at 76.5 136 90) (layer 1_top) (tstamp 53AE4FEC)
(effects (font (size 1.016 1.016) (thickness 0.2032)) (justify mirror))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
(gr_line (start 60 104) (end 60 121.5) (angle 90) (layer Edge.Cuts) (width 0.381))
(gr_line (start 60 171) (end 60 159) (angle 90) (layer Edge.Cuts) (width 0.381))
(gr_line (start 62 157) (end 67 157) (angle 90) (layer Edge.Cuts) (width 0.381))
(gr_line (start 68 156) (end 68 124.5) (angle 90) (layer Edge.Cuts) (width 0.381))
(gr_line (start 62 123.5) (end 67 123.5) (angle 90) (layer Edge.Cuts) (width 0.381))
(gr_arc (start 67 156) (end 68 156) (angle 90) (layer Edge.Cuts) (width 0.381))
(gr_arc (start 67 124.5) (end 67 123.5) (angle 90) (layer Edge.Cuts) (width 0.381))
(gr_arc (start 62 159) (end 60 159) (angle 90) (layer Edge.Cuts) (width 0.381))
(gr_arc (start 62 121.5) (end 62 123.5) (angle 90) (layer Edge.Cuts) (width 0.381))
(gr_line (start 180 171) (end 180 104) (angle 90) (layer Edge.Cuts) (width 0.381))
(gr_line (start 176 100) (end 64 100) (angle 90) (layer Edge.Cuts) (width 0.381))
(gr_line (start 64 175) (end 176 175) (angle 90) (layer Edge.Cuts) (width 0.381))
(gr_arc (start 176 171) (end 180 171) (angle 90) (layer Edge.Cuts) (width 0.381))
(gr_arc (start 176 104) (end 176 100) (angle 90) (layer Edge.Cuts) (width 0.381))
(gr_arc (start 64 171) (end 64 175) (angle 90) (layer Edge.Cuts) (width 0.381))
(gr_arc (start 64 104) (end 60 104) (angle 90) (layer Edge.Cuts) (width 0.381))
(gr_line (start 87.94 126.74) (end 108.26 126.74) (layer Eco2.User) (width 0.1))
(gr_line (start 108.26 126.74) (end 108.26 131.82) (layer Eco2.User) (width 0.1))
(gr_line (start 108.26 131.82) (end 87.94 131.82) (layer Eco2.User) (width 0.1))
(gr_line (start 87.94 131.82) (end 87.94 126.74) (layer Eco2.User) (width 0.1))
(segment (start 89.94958 132.6) (end 90.6 132.6) (width 0.4) (layer 4_bot) (net 1) (status 10))
Change vias to 13mil, 7mil annular ring. Was 13.5mm, but why?!?
2015-08-30 05:31:29 +00:00
(via (at 90.6 132.6) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 1))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(segment (start 90.6 132.6) (end 93.4 132.6) (width 0.2) (layer 4_bot) (net 1) (status 20))
(segment (start 90.89916 125.7) (end 92 125.7) (width 0.4) (layer 4_bot) (net 1) (status 10))
Change vias to 13mil, 7mil annular ring. Was 13.5mm, but why?!?
2015-08-30 05:31:29 +00:00
(via (at 92 125.7) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 1))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(segment (start 90.89916 125.7) (end 90.6 125.99916) (width 0.4) (layer 4_bot) (net 1) (status 30))
Change vias to 13mil, 7mil annular ring. Was 13.5mm, but why?!?
2015-08-30 05:31:29 +00:00
(via (at 90.6 126.9) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 1))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(segment (start 90.6 125.99916) (end 90.6 126.9) (width 0.4) (layer 4_bot) (net 1) (tstamp 53B307A4) (status 10))
(segment (start 90.89916 125.7) (end 90.6 125.40084) (width 0.4) (layer 4_bot) (net 1) (status 30))
Change vias to 13mil, 7mil annular ring. Was 13.5mm, but why?!?
2015-08-30 05:31:29 +00:00
(via (at 90.6 124.5) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 1))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(segment (start 90.6 125.40084) (end 90.6 124.5) (width 0.4) (layer 4_bot) (net 1) (tstamp 53B307A0) (status 10))
(segment (start 90.89916 140.7) (end 90.6 140.99916) (width 0.4) (layer 4_bot) (net 1) (status 30))
Change vias to 13mil, 7mil annular ring. Was 13.5mm, but why?!?
2015-08-30 05:31:29 +00:00
(via (at 90.6 141.9) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 1))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(segment (start 90.6 140.99916) (end 90.6 141.9) (width 0.4) (layer 4_bot) (net 1) (tstamp 53B30742) (status 10))
(segment (start 90.89916 140.7) (end 92 140.7) (width 0.4) (layer 4_bot) (net 1) (status 10))
Change vias to 13mil, 7mil annular ring. Was 13.5mm, but why?!?
2015-08-30 05:31:29 +00:00
(via (at 92 140.7) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 1))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(segment (start 90.89916 140.7) (end 90.6 140.40084) (width 0.4) (layer 4_bot) (net 1) (status 30))
Change vias to 13mil, 7mil annular ring. Was 13.5mm, but why?!?
2015-08-30 05:31:29 +00:00
(via (at 90.6 139.5) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 1))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(segment (start 90.6 140.40084) (end 90.6 139.5) (width 0.4) (layer 4_bot) (net 1) (tstamp 53B30737) (status 10))
(segment (start 96.70084 144.8) (end 96.20084 145.3) (width 0.4) (layer 4_bot) (net 1) (status 30))
Change vias to 13mil, 7mil annular ring. Was 13.5mm, but why?!?
2015-08-30 05:31:29 +00:00
(via (at 95.7 145.3) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 1))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(segment (start 96.20084 145.3) (end 95.7 145.3) (width 0.4) (layer 4_bot) (net 1) (tstamp 53B305D4) (status 10))
(segment (start 96.70084 144.8) (end 96.20084 144.3) (width 0.4) (layer 4_bot) (net 1) (status 30))
Change vias to 13mil, 7mil annular ring. Was 13.5mm, but why?!?
2015-08-30 05:31:29 +00:00
(via (at 95.7 144.3) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 1))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(segment (start 96.20084 144.3) (end 95.7 144.3) (width 0.4) (layer 4_bot) (net 1) (tstamp 53B305CD) (status 10))
(segment (start 96.65126 146.85004) (end 96.65126 144.84958) (width 0.4) (layer 4_bot) (net 1) (status 30))
(segment (start 96.65126 144.84958) (end 96.70084 144.8) (width 0.4) (layer 4_bot) (net 1) (tstamp 53AE1EC8) (status 30))
(segment (start 97 126.4) (end 97 125.84958) (width 0.4) (layer 4_bot) (net 1) (status 20))
(segment (start 97 125.84958) (end 97.2 125.64958) (width 0.4) (layer 4_bot) (net 1) (tstamp 53AB75C2) (status 30))
(segment (start 97.4 128.6) (end 97.4 126.8) (width 0.2) (layer 4_bot) (net 1) (status 10))
Change vias to 13mil, 7mil annular ring. Was 13.5mm, but why?!?
2015-08-30 05:31:29 +00:00
(via (at 97 126.4) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 1))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(segment (start 97.4 126.8) (end 97 126.4) (width 0.2) (layer 4_bot) (net 1) (tstamp 53AB75B4))
(segment (start 85.3 129.75) (end 84.45 129.75) (width 0.3) (layer 4_bot) (net 1) (status 10))
(segment (start 84.45 129.75) (end 84.15 129.45) (width 0.3) (layer 4_bot) (net 1) (tstamp 53AA6CE3))
Change vias to 13mil, 7mil annular ring. Was 13.5mm, but why?!?
2015-08-30 05:31:29 +00:00
(via (at 84.15 129.45) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 1))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(segment (start 97 140.75042) (end 97 140) (width 0.4) (layer 4_bot) (net 1) (status 10))
(segment (start 97.4 139.6) (end 97.4 137) (width 0.2) (layer 4_bot) (net 1) (status 20))
Change vias to 13mil, 7mil annular ring. Was 13.5mm, but why?!?
2015-08-30 05:31:29 +00:00
(via (at 97 140) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 1))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(segment (start 97.4 139.6) (end 97 140) (width 0.2) (layer 4_bot) (net 1) (tstamp 53AA6BB0))
(segment (start 98.6 140.75042) (end 98.6 140) (width 0.4) (layer 4_bot) (net 1) (status 10))
(segment (start 98.2 139.6) (end 98.6 140) (width 0.2) (layer 4_bot) (net 1) (tstamp 53AA6BFB))
Change vias to 13mil, 7mil annular ring. Was 13.5mm, but why?!?
2015-08-30 05:31:29 +00:00
(via (at 98.6 140) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 1))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(segment (start 98.2 139.6) (end 98.2 137) (width 0.2) (layer 4_bot) (net 1) (status 20))
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(segment (start 126.23 155.95) (end 126.23 156.98) (width 0.4) (layer 4_bot) (net 2) (status 10))
Change vias to 13mil, 7mil annular ring. Was 13.5mm, but why?!?
2015-08-30 05:31:29 +00:00
(via (at 126.25 157) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 2))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(segment (start 126.23 156.98) (end 126.25 157) (width 0.4) (layer 4_bot) (net 2) (tstamp 53F39EBA))
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(segment (start 126.23 155.95) (end 128.4 155.95) (width 0.4) (layer 4_bot) (net 2) (status 10))
Change vias to 13mil, 7mil annular ring. Was 13.5mm, but why?!?
2015-08-30 05:31:29 +00:00
(via (at 128.4 155.95) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 2))
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(segment (start 126.23 155.95) (end 126.23 154.92) (width 0.4) (layer 4_bot) (net 2) (status 10))
Change vias to 13mil, 7mil annular ring. Was 13.5mm, but why?!?
2015-08-30 05:31:29 +00:00
(via (at 126.25 154.9) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 2))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(segment (start 126.23 154.92) (end 126.25 154.9) (width 0.4) (layer 4_bot) (net 2) (tstamp 53F39EB2))
(segment (start 174.49 153.41) (end 174.5 153.42) (width 0.4) (layer 4_bot) (net 2) (status 30))
Change vias to 13mil, 7mil annular ring. Was 13.5mm, but why?!?
2015-08-30 05:31:29 +00:00
(via (at 174.5 154.5) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 2))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(segment (start 174.5 153.42) (end 174.5 154.5) (width 0.4) (layer 4_bot) (net 2) (tstamp 53F39D02) (status 10))
(segment (start 174.49 153.41) (end 174.5 153.4) (width 0.4) (layer 4_bot) (net 2) (status 30))
(segment (start 174.5 153.4) (end 176.7 153.4) (width 0.4) (layer 4_bot) (net 2) (tstamp 53F39CFE) (status 10))
Change vias to 13mil, 7mil annular ring. Was 13.5mm, but why?!?
2015-08-30 05:31:29 +00:00
(via (at 176.7 153.4) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 2))
(via (at 174.5 152.3) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 2))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(segment (start 174.5 153.4) (end 174.5 152.3) (width 0.4) (layer 4_bot) (net 2) (tstamp 53F39CFA) (status 10))
(segment (start 155.25 162.11) (end 156.39 162.11) (width 0.4) (layer 4_bot) (net 2) (status 10))
Change vias to 13mil, 7mil annular ring. Was 13.5mm, but why?!?
2015-08-30 05:31:29 +00:00
(via (at 156.4 162.1) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 2))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(segment (start 156.39 162.11) (end 156.4 162.1) (width 0.4) (layer 4_bot) (net 2) (tstamp 53F39C36))
(segment (start 155.25 162.11) (end 154.11 162.11) (width 0.4) (layer 4_bot) (net 2) (status 10))
Change vias to 13mil, 7mil annular ring. Was 13.5mm, but why?!?
2015-08-30 05:31:29 +00:00
(via (at 154.1 162.1) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 2))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(segment (start 154.11 162.11) (end 154.1 162.1) (width 0.4) (layer 4_bot) (net 2) (tstamp 53F39C32))
(segment (start 155.25 162.11) (end 155.25 159.95) (width 0.4) (layer 4_bot) (net 2) (status 10))
Change vias to 13mil, 7mil annular ring. Was 13.5mm, but why?!?
2015-08-30 05:31:29 +00:00
(via (at 155.2 159.9) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 2))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(segment (start 155.25 159.95) (end 155.2 159.9) (width 0.4) (layer 4_bot) (net 2) (tstamp 53F39C2E))
(segment (start 85.3 146.75) (end 84.15 146.75) (width 0.3) (layer 4_bot) (net 2) (status 10))
Change vias to 13mil, 7mil annular ring. Was 13.5mm, but why?!?
2015-08-30 05:31:29 +00:00
(via (at 84.15 146.75) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 2))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(segment (start 64.075 115.375) (end 64.1 115.4) (width 0.4) (layer 4_bot) (net 2) (status 30))
Change vias to 13mil, 7mil annular ring. Was 13.5mm, but why?!?
2015-08-30 05:31:29 +00:00
(via (at 65 115.4) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 2))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(segment (start 64.1 115.4) (end 65 115.4) (width 0.4) (layer 4_bot) (net 2) (tstamp 53BC7166) (status 10))
(segment (start 64.075 115.375) (end 64.05 115.4) (width 0.4) (layer 4_bot) (net 2) (status 30))
Change vias to 13mil, 7mil annular ring. Was 13.5mm, but why?!?
2015-08-30 05:31:29 +00:00
(via (at 63.1 115.4) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 2))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(segment (start 64.05 115.4) (end 63.1 115.4) (width 0.4) (layer 4_bot) (net 2) (tstamp 53BC7164) (status 10))
(segment (start 97.89916 121.3) (end 99 121.3) (width 0.4) (layer 4_bot) (net 2) (status 10))
Change vias to 13mil, 7mil annular ring. Was 13.5mm, but why?!?
2015-08-30 05:31:29 +00:00
(via (at 99 121.3) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 2))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(segment (start 97.89916 121.3) (end 97.6 121.59916) (width 0.4) (layer 4_bot) (net 2) (status 30))
Change vias to 13mil, 7mil annular ring. Was 13.5mm, but why?!?
2015-08-30 05:31:29 +00:00
(via (at 97.6 122.5) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 2))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(segment (start 97.6 121.59916) (end 97.6 122.5) (width 0.4) (layer 4_bot) (net 2) (tstamp 53B3081C) (status 10))
(segment (start 97.89916 121.3) (end 97.6 121.00084) (width 0.4) (layer 4_bot) (net 2) (status 30))
Change vias to 13mil, 7mil annular ring. Was 13.5mm, but why?!?
2015-08-30 05:31:29 +00:00
(via (at 97.6 120.1) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 2))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(segment (start 97.6 121.00084) (end 97.6 120.1) (width 0.4) (layer 4_bot) (net 2) (tstamp 53B30818) (status 10))
(segment (start 99.34874 148.74996) (end 99.4 148.80122) (width 0.4) (layer 4_bot) (net 2) (status 30))
Change vias to 13mil, 7mil annular ring. Was 13.5mm, but why?!?
2015-08-30 05:31:29 +00:00
(via (at 99.4 149.5) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 2))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(segment (start 99.4 148.80122) (end 99.4 149.5) (width 0.4) (layer 4_bot) (net 2) (tstamp 53B30626) (status 10))
(segment (start 99.34874 146.85004) (end 99.39954 146.90084) (width 0.4) (layer 4_bot) (net 2) (status 30))
(segment (start 99.39954 146.90084) (end 101.4 146.90084) (width 0.4) (layer 4_bot) (net 2) (tstamp 53B3060D) (status 30))
(segment (start 101.4 146.90084) (end 101.69916 147.2) (width 0.4) (layer 4_bot) (net 2) (status 30))
Change vias to 13mil, 7mil annular ring. Was 13.5mm, but why?!?
2015-08-30 05:31:29 +00:00
(via (at 102.6 147.2) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 2))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(segment (start 101.69916 147.2) (end 102.6 147.2) (width 0.4) (layer 4_bot) (net 2) (tstamp 53B30601) (status 10))
(segment (start 101.4 146.90084) (end 101.4 145.9) (width 0.4) (layer 4_bot) (net 2) (status 10))
Change vias to 13mil, 7mil annular ring. Was 13.5mm, but why?!?
2015-08-30 05:31:29 +00:00
(via (at 101.4 145.9) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 2))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(segment (start 124.39916 158.9) (end 124.1 159.19916) (width 0.4) (layer 4_bot) (net 2) (status 30))
Change vias to 13mil, 7mil annular ring. Was 13.5mm, but why?!?
2015-08-30 05:31:29 +00:00
(via (at 124.1 160.1) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 2))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(segment (start 124.1 159.19916) (end 124.1 160.1) (width 0.4) (layer 4_bot) (net 2) (tstamp 53B304F6) (status 10))
(segment (start 124.39916 158.9) (end 125.5 158.9) (width 0.4) (layer 4_bot) (net 2) (status 10))
Change vias to 13mil, 7mil annular ring. Was 13.5mm, but why?!?
2015-08-30 05:31:29 +00:00
(via (at 125.5 158.9) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 2))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(segment (start 124.39916 158.9) (end 124.1 158.60084) (width 0.4) (layer 4_bot) (net 2) (status 30))
Change vias to 13mil, 7mil annular ring. Was 13.5mm, but why?!?
2015-08-30 05:31:29 +00:00
(via (at 124.1 157.7) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 2))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(segment (start 124.1 158.60084) (end 124.1 157.7) (width 0.4) (layer 4_bot) (net 2) (tstamp 53B304EC) (status 10))
(segment (start 75.30084 123.2) (end 75.6 123.49916) (width 0.4) (layer 4_bot) (net 2) (status 30))
Change vias to 13mil, 7mil annular ring. Was 13.5mm, but why?!?
2015-08-30 05:31:29 +00:00
(via (at 75.6 124.4) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 2))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(segment (start 75.6 123.49916) (end 75.6 124.4) (width 0.4) (layer 4_bot) (net 2) (tstamp 53B30349) (status 10))
(segment (start 75.30084 123.2) (end 75.6 122.90084) (width 0.4) (layer 4_bot) (net 2) (status 30))
Change vias to 13mil, 7mil annular ring. Was 13.5mm, but why?!?
2015-08-30 05:31:29 +00:00
(via (at 75.6 122) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 2))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(segment (start 75.6 122.90084) (end 75.6 122) (width 0.4) (layer 4_bot) (net 2) (tstamp 53B30345) (status 10))
(segment (start 165.2 153.50084) (end 165.2 152.4) (width 0.4) (layer 4_bot) (net 2) (status 10))
Change vias to 13mil, 7mil annular ring. Was 13.5mm, but why?!?
2015-08-30 05:31:29 +00:00
(via (at 165.2 152.4) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 2))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(segment (start 165.2 153.50084) (end 165.49916 153.8) (width 0.4) (layer 4_bot) (net 2) (status 30))
Change vias to 13mil, 7mil annular ring. Was 13.5mm, but why?!?
2015-08-30 05:31:29 +00:00
(via (at 166.4 153.8) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 2))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(segment (start 165.49916 153.8) (end 166.4 153.8) (width 0.4) (layer 4_bot) (net 2) (tstamp 53B195B1) (status 10))
(segment (start 165.2 153.50084) (end 164.90084 153.8) (width 0.4) (layer 4_bot) (net 2) (status 30))
Change vias to 13mil, 7mil annular ring. Was 13.5mm, but why?!?
2015-08-30 05:31:29 +00:00
(via (at 164 153.8) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 2))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(segment (start 164.90084 153.8) (end 164 153.8) (width 0.4) (layer 4_bot) (net 2) (tstamp 53B195AD) (status 10))
(segment (start 154.30084 157.8) (end 153.1 157.8) (width 0.4) (layer 4_bot) (net 2) (status 10))
Change vias to 13mil, 7mil annular ring. Was 13.5mm, but why?!?
2015-08-30 05:31:29 +00:00
(via (at 153.1 157.8) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 2))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(segment (start 154.30084 157.8) (end 154.6 157.50084) (width 0.4) (layer 4_bot) (net 2) (status 30))
Change vias to 13mil, 7mil annular ring. Was 13.5mm, but why?!?
2015-08-30 05:31:29 +00:00
(via (at 154.6 156.5) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 2))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(segment (start 154.6 157.50084) (end 154.6 156.5) (width 0.4) (layer 4_bot) (net 2) (tstamp 53B193C8) (status 10))
(segment (start 154.30084 157.8) (end 154.6 158.09916) (width 0.4) (layer 4_bot) (net 2) (status 30))
Change vias to 13mil, 7mil annular ring. Was 13.5mm, but why?!?
2015-08-30 05:31:29 +00:00
(via (at 154.6 159.1) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 2))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(segment (start 154.6 158.09916) (end 154.6 159.1) (width 0.4) (layer 4_bot) (net 2) (tstamp 53B193B8) (status 10))
(segment (start 105.55042 132.2) (end 104.8 132.2) (width 0.4) (layer 4_bot) (net 2) (status 10))
Change vias to 13mil, 7mil annular ring. Was 13.5mm, but why?!?
2015-08-30 05:31:29 +00:00
(via (at 104.8 132.2) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 2))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(segment (start 104.8 132.2) (end 102.4 132.2) (width 0.2) (layer 4_bot) (net 2) (status 20))
(segment (start 71.75042 122.8) (end 71.75042 123.54958) (width 0.4) (layer 4_bot) (net 2) (status 10))
Change vias to 13mil, 7mil annular ring. Was 13.5mm, but why?!?
2015-08-30 05:31:29 +00:00
(via (at 71.7 123.6) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 2))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(segment (start 71.75042 123.54958) (end 71.7 123.6) (width 0.4) (layer 4_bot) (net 2) (tstamp 53AE3577))
(segment (start 71.75042 122.8) (end 71.75042 122.05042) (width 0.4) (layer 4_bot) (net 2) (status 10))
Change vias to 13mil, 7mil annular ring. Was 13.5mm, but why?!?
2015-08-30 05:31:29 +00:00
(via (at 71.7 122) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 2))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(segment (start 71.75042 122.05042) (end 71.7 122) (width 0.4) (layer 4_bot) (net 2) (tstamp 53AE3563))
(segment (start 71.75042 122.8) (end 70.9 122.8) (width 0.4) (layer 4_bot) (net 2) (status 10))
Change vias to 13mil, 7mil annular ring. Was 13.5mm, but why?!?
2015-08-30 05:31:29 +00:00
(via (at 70.9 122.8) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 2))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(segment (start 75.30084 123.2) (end 74.2 123.2) (width 0.4) (layer 4_bot) (net 2) (status 10))
Change vias to 13mil, 7mil annular ring. Was 13.5mm, but why?!?
2015-08-30 05:31:29 +00:00
(via (at 74.2 123.2) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 2))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(segment (start 96 125.64958) (end 96 126.4) (width 0.4) (layer 4_bot) (net 2) (status 10))
(segment (start 96.6 127) (end 96.6 128.6) (width 0.2) (layer 4_bot) (net 2) (status 20))
Change vias to 13mil, 7mil annular ring. Was 13.5mm, but why?!?
2015-08-30 05:31:29 +00:00
(via (at 96 126.4) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 2))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(segment (start 96.6 127) (end 96 126.4) (width 0.2) (layer 4_bot) (net 2) (tstamp 53AB759B))
(segment (start 85.3 145.75) (end 84.15 145.75) (width 0.3) (layer 4_bot) (net 2) (status 10))
Change vias to 13mil, 7mil annular ring. Was 13.5mm, but why?!?
2015-08-30 05:31:29 +00:00
(via (at 84.15 145.75) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 2))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(segment (start 135.89916 122) (end 137 122) (width 0.4) (layer 4_bot) (net 2) (status 10))
Change vias to 13mil, 7mil annular ring. Was 13.5mm, but why?!?
2015-08-30 05:31:29 +00:00
(via (at 137 122) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 2))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(segment (start 135.89916 122) (end 135.6 121.70084) (width 0.4) (layer 4_bot) (net 2) (status 30))
Change vias to 13mil, 7mil annular ring. Was 13.5mm, but why?!?
2015-08-30 05:31:29 +00:00
(via (at 135.6 120.8) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 2))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(segment (start 135.6 121.70084) (end 135.6 120.8) (width 0.4) (layer 4_bot) (net 2) (tstamp 53B30424) (status 10))
(segment (start 133.15042 119.8) (end 133 119.64958) (width 0.4) (layer 4_bot) (net 2) (status 30))
Change vias to 13mil, 7mil annular ring. Was 13.5mm, but why?!?
2015-08-30 05:31:29 +00:00
(via (at 133 119) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 2))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(segment (start 133 119.64958) (end 133 119) (width 0.4) (layer 4_bot) (net 2) (tstamp 53B3041C) (status 10))
(segment (start 142.44958 119.8) (end 142.4 119.75042) (width 0.4) (layer 4_bot) (net 2) (status 30))
Change vias to 13mil, 7mil annular ring. Was 13.5mm, but why?!?
2015-08-30 05:31:29 +00:00
(via (at 142.4 119) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 2))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(segment (start 142.4 119.75042) (end 142.4 119) (width 0.4) (layer 4_bot) (net 2) (tstamp 53B30401) (status 10))
(segment (start 144.6 117.49916) (end 144.30084 117.2) (width 0.4) (layer 4_bot) (net 2) (status 30))
Change vias to 13mil, 7mil annular ring. Was 13.5mm, but why?!?
2015-08-30 05:31:29 +00:00
(via (at 143.4 117.2) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 2))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(segment (start 144.30084 117.2) (end 143.4 117.2) (width 0.4) (layer 4_bot) (net 2) (tstamp 53B303F7) (status 10))
(segment (start 144.6 117.49916) (end 144.89916 117.2) (width 0.4) (layer 4_bot) (net 2) (status 30))
Change vias to 13mil, 7mil annular ring. Was 13.5mm, but why?!?
2015-08-30 05:31:29 +00:00
(via (at 145.8 117.2) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 2))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(segment (start 144.89916 117.2) (end 145.8 117.2) (width 0.4) (layer 4_bot) (net 2) (tstamp 53B303F3) (status 10))
(segment (start 144.6 110.50084) (end 144.30084 110.8) (width 0.4) (layer 4_bot) (net 2) (status 30))
Change vias to 13mil, 7mil annular ring. Was 13.5mm, but why?!?
2015-08-30 05:31:29 +00:00
(via (at 143.4 110.8) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 2))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(segment (start 144.30084 110.8) (end 143.4 110.8) (width 0.4) (layer 4_bot) (net 2) (tstamp 53B303DF) (status 10))
(segment (start 144.6 110.50084) (end 144.89916 110.8) (width 0.4) (layer 4_bot) (net 2) (status 30))
Change vias to 13mil, 7mil annular ring. Was 13.5mm, but why?!?
2015-08-30 05:31:29 +00:00
(via (at 145.8 110.8) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 2))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(segment (start 144.89916 110.8) (end 145.8 110.8) (width 0.4) (layer 4_bot) (net 2) (tstamp 53B303DB) (status 10))
(segment (start 141.55042 108.2) (end 141.4 108.35042) (width 0.4) (layer 4_bot) (net 2) (status 30))
Change vias to 13mil, 7mil annular ring. Was 13.5mm, but why?!?
2015-08-30 05:31:29 +00:00
(via (at 141.4 109) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 2))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(segment (start 141.4 108.35042) (end 141.4 109) (width 0.4) (layer 4_bot) (net 2) (tstamp 53B303D0) (status 10))
(segment (start 130.2 117.49916) (end 130.49916 117.2) (width 0.4) (layer 4_bot) (net 2) (status 30))
Change vias to 13mil, 7mil annular ring. Was 13.5mm, but why?!?
2015-08-30 05:31:29 +00:00
(via (at 131.4 117.2) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 2))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(segment (start 130.49916 117.2) (end 131.4 117.2) (width 0.4) (layer 4_bot) (net 2) (tstamp 53B2F3E6) (status 10))
(segment (start 130.2 117.49916) (end 129.90084 117.2) (width 0.4) (layer 4_bot) (net 2) (status 30))
Change vias to 13mil, 7mil annular ring. Was 13.5mm, but why?!?
2015-08-30 05:31:29 +00:00
(via (at 129 117.2) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 2))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(segment (start 129.90084 117.2) (end 129 117.2) (width 0.4) (layer 4_bot) (net 2) (tstamp 53B2F3E0) (status 10))
(segment (start 130.2 117.49916) (end 130.2 118.6) (width 0.4) (layer 4_bot) (net 2) (status 10))
Change vias to 13mil, 7mil annular ring. Was 13.5mm, but why?!?
2015-08-30 05:31:29 +00:00
(via (at 130.2 118.6) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 2))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(segment (start 137.07488 117.50012) (end 137.07488 118.97488) (width 0.4) (layer 4_bot) (net 2) (status 10))
(segment (start 137.07488 118.97488) (end 137.1 119) (width 0.4) (layer 4_bot) (net 2) (tstamp 53AE215A))
Change vias to 13mil, 7mil annular ring. Was 13.5mm, but why?!?
2015-08-30 05:31:29 +00:00
(via (at 137.1 119) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 2))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(segment (start 137.04958 119.05042) (end 137.04958 119.8) (width 0.4) (layer 4_bot) (net 2) (status 20))
(segment (start 137.04958 119.05042) (end 137.1 119) (width 0.4) (layer 4_bot) (net 2) (tstamp 53ADF367))
Change vias to 13mil, 7mil annular ring. Was 13.5mm, but why?!?
2015-08-30 05:31:29 +00:00
(via (at 141 112) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 2))
(via (at 132.4 117.5) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 2))
(via (at 142.4 117.5) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 2))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(segment (start 140.97378 110.49988) (end 140.97378 111.97378) (width 0.4) (layer 4_bot) (net 2) (status 10))
(segment (start 140.97378 111.97378) (end 141 112) (width 0.4) (layer 4_bot) (net 2) (tstamp 53ADF184))
(segment (start 133.17598 117.50012) (end 132.40012 117.50012) (width 0.4) (layer 4_bot) (net 2) (status 10))
(segment (start 132.40012 117.50012) (end 132.4 117.5) (width 0.4) (layer 4_bot) (net 2) (tstamp 53ADF172))
(segment (start 141.62402 117.50012) (end 142.39988 117.50012) (width 0.4) (layer 4_bot) (net 2) (status 10))
(segment (start 142.39988 117.50012) (end 142.4 117.5) (width 0.4) (layer 4_bot) (net 2) (tstamp 53ADF16E))
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(segment (start 147.63 162.11) (end 147.63 157.03) (width 0.2) (layer 4_bot) (net 3) (status 10))
(segment (start 147.63 157.03) (end 147.1 156.5) (width 0.2) (layer 4_bot) (net 3))
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(segment (start 147.6 162.1) (end 147.63 162.11) (width 0.2) (layer 4_bot) (net 3) (tstamp 53F39CA0) (status 30))
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(segment (start 140 112) (end 140 114.5) (width 0.2) (layer 1_top) (net 3))
(segment (start 140 114.5) (end 138.9 115.6) (width 0.2) (layer 1_top) (net 3) (tstamp 53AE06E3))
(segment (start 139.67584 111.67584) (end 140 112) (width 0.2) (layer 4_bot) (net 3) (tstamp 53AE03F8))
(via (at 140 112) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 3))
(segment (start 138.9 115.6) (end 138.9 122.6) (width 0.2) (layer 1_top) (net 3) (tstamp 53AE06F0))
(segment (start 139.67584 111.67584) (end 139.67584 110.49988) (width 0.2) (layer 4_bot) (net 3) (status 20))
(segment (start 142.8 126.5) (end 138.9 122.6) (width 0.2) (layer 1_top) (net 3) (tstamp 53AE0612))
(segment (start 147.1 156.5) (end 142.8 152.2) (width 0.2) (layer 1_top) (net 3))
(via (at 147.1 156.5) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 3))
(segment (start 142.8 152.2) (end 142.8 126.5) (width 0.2) (layer 1_top) (net 3) (tstamp 53AE060C))
(segment (start 138.37536 117.50012) (end 138.37536 119.97526) (width 0.2) (layer 4_bot) (net 4) (status 30))
(segment (start 138.37536 119.97526) (end 138.5 120.0999) (width 0.2) (layer 4_bot) (net 4) (tstamp 53AE2A50) (status 30))
(segment (start 150.17 167.365) (end 150.17 165.37) (width 0.2) (layer 4_bot) (net 5) (status 10))
(segment (start 150.17 165.37) (end 148.9 164.1) (width 0.2) (layer 4_bot) (net 5))
(segment (start 148.9 164.1) (end 148.9 156.9) (width 0.2) (layer 4_bot) (net 5))
(segment (start 148.9 156.9) (end 148.5 156.5) (width 0.2) (layer 4_bot) (net 5))
(segment (start 140.3 116) (end 139.5 116.8) (width 0.2) (layer 1_top) (net 5))
(segment (start 139.5 116.8) (end 139.5 122.1) (width 0.2) (layer 1_top) (net 5) (tstamp 53AE08D2))
(segment (start 140.32608 117.50012) (end 140.32608 116.02608) (width 0.2) (layer 4_bot) (net 5) (status 10))
(via (at 140.3 116) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 5))
(segment (start 140.32608 116.02608) (end 140.3 116) (width 0.2) (layer 4_bot) (net 5) (tstamp 53AE0508))
(segment (start 139.5 122.1) (end 145.8 128.4) (width 0.2) (layer 1_top) (net 5) (tstamp 53AE05FC))
(segment (start 145.8 153.8) (end 148.5 156.5) (width 0.2) (layer 1_top) (net 5) (tstamp 53AE0607))
(segment (start 145.8 128.4) (end 145.8 153.8) (width 0.2) (layer 1_top) (net 5) (tstamp 53AE0601))
(segment (start 148.5 156.5) (end 148.5 156.4) (width 0.2) (layer 1_top) (net 5))
(via (at 148.5 156.5) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 5))
(segment (start 152.71 159.21) (end 151.5 158) (width 0.2) (layer 4_bot) (net 6))
(segment (start 151.5 158) (end 151.5 156.5) (width 0.2) (layer 4_bot) (net 6))
(segment (start 152.71 162.11) (end 152.71 159.21) (width 0.2) (layer 4_bot) (net 6) (status 10))
(segment (start 140.3 119.3) (end 141.6 120.6) (width 0.2) (layer 1_top) (net 6))
(segment (start 139.67584 118.67584) (end 139.67584 117.50012) (width 0.2) (layer 4_bot) (net 6) (status 20))
(via (at 140.3 119.3) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 6))
(segment (start 139.67584 118.67584) (end 140.3 119.3) (width 0.2) (layer 4_bot) (net 6) (tstamp 53AE0538))
(via (at 151.5 156.5) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 6))
(segment (start 153.2 154.8) (end 153.2 133.6) (width 0.2) (layer 1_top) (net 6) (tstamp 53AE081F))
(segment (start 151.5 156.5) (end 153.2 154.8) (width 0.2) (layer 1_top) (net 6))
(segment (start 141.6 122) (end 153.2 133.6) (width 0.2) (layer 1_top) (net 6) (tstamp 53AE084D))
(segment (start 141.6 120.6) (end 141.6 122) (width 0.2) (layer 1_top) (net 6) (tstamp 53AE0849))
(segment (start 150.17 162.11) (end 150.17 156.57) (width 0.2) (layer 4_bot) (net 7) (status 10))
(segment (start 150.17 156.57) (end 150.1 156.5) (width 0.2) (layer 4_bot) (net 7))
(segment (start 150.2 162.1) (end 150.17 162.11) (width 0.2) (layer 4_bot) (net 7) (tstamp 53F39C9D) (status 30))
(segment (start 149 141.8) (end 146.4 139.2) (width 0.2) (layer 1_top) (net 7) (tstamp 53AE0866))
(segment (start 139.0256 119.0256) (end 139.0256 117.50012) (width 0.2) (layer 4_bot) (net 7) (status 20))
(via (at 140.3 120.3) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 7))
(segment (start 139.0256 119.0256) (end 140.3 120.3) (width 0.2) (layer 4_bot) (net 7) (tstamp 53AE054B))
(segment (start 140.3 121.8) (end 140.3 120.3) (width 0.2) (layer 1_top) (net 7))
(segment (start 146.4 127.9) (end 140.3 121.8) (width 0.2) (layer 1_top) (net 7) (tstamp 53AE05F4))
(segment (start 146.4 139.2) (end 146.4 127.9) (width 0.2) (layer 1_top) (net 7) (tstamp 53AE0870))
(segment (start 137.72512 117.50012) (end 137.72512 116.27488) (width 0.2) (layer 4_bot) (net 7) (status 10))
(segment (start 137.72512 116.27488) (end 138 116) (width 0.2) (layer 4_bot) (net 7) (tstamp 53AE0542))
(segment (start 138 116) (end 138.7 116) (width 0.2) (layer 4_bot) (net 7) (tstamp 53AE0543))
(segment (start 138.7 116) (end 139.0256 116.3256) (width 0.2) (layer 4_bot) (net 7) (tstamp 53AE0544))
(segment (start 139.0256 116.3256) (end 139.0256 117.50012) (width 0.2) (layer 4_bot) (net 7) (tstamp 53AE0548) (status 20))
(segment (start 149 155.4) (end 149 141.8) (width 0.2) (layer 1_top) (net 7))
(segment (start 150.1 156.5) (end 149 155.4) (width 0.2) (layer 1_top) (net 7))
(segment (start 150.1 156.5) (end 150.1 156.4) (width 0.2) (layer 1_top) (net 7) (tstamp 53AE05F0))
(via (at 150.1 156.5) (size 0.6858) (drill 0.3302) (layers 1_top 4_bot) (net 7))
(segment (start 151.0504 120) (end 149.8 120) (width 0.4) (layer 4_bot) (net 8) (status 30))
(segment (start 148.5 116.7) (end 146.2 114.4) (width 0.4) (layer 4_bot) (net 8) (tstamp 53AE0081))
(segment (start 146.2 114.4) (end 137.5 114.4) (width 0.4) (layer 4_bot) (net 8) (tstamp 53AE004D))
(segment (start 137.5 114.4) (end 136.42464 115.47536) (width 0.4) (layer 4_bot) (net 8) (tstamp 53AE0050))
(segment (start 136.42464 115.47536) (end 136.42464 117.50012) (width 0.4) (layer 4_bot) (net 8) (tstamp 53AE0052) (status 20))
(segment (start 149.8 120) (end 148.5 118.7) (width 0.4) (layer 4_bot) (net 8) (tstamp 53AE0078) (status 10))
(segment (start 148.5 118.7) (end 148.5 116.7) (width 0.4) (layer 4_bot) (net 8) (tstamp 53AE007C))
(segment (start 135.5999 104.4) (end 135.5999 106.10094) (width 0.4) (layer 4_bot) (net 9) (status 30))
(segment (start 135.5999 106.10094) (end 135.30084 106.4) (width 0.4) (layer 4_bot) (net 9) (tstamp 53AE01C9) (status 30))
(segment (start 135.30084 106.4) (end 134.95042 106.75042) (width 0.4) (layer 4_bot) (net 9) (status 30))
(segment (start 134.95042 106.75042) (end 134.95042 108.2) (width 0.4) (layer 4_bot) (net 9) (tstamp 53ADF19E) (status 30))
(segment (start 134.95042 108.2) (end 134.47392 108.6765) (width 0.4) (layer 4_bot) (net 9) (status 10))
(segment (start 134.47392 108.6765) (end 134.47392 110.49988) (width 0.4) (layer 4_bot) (net 9) (tstamp 53ADF192) (status 20))
(segment (start 135.12416 110.49988) (end 135.12416 109.27584) (width 0.2) (layer 4_bot) (net 10) (status 10))
(segment (start 137.7999 109) (end 138.5999 108.2) (width 0.2) (layer 4_bot) (net 10) (tstamp 53ADF668) (status 20))
(segment (start 135.4 109) (end 137.7999 109) (width 0.2) (layer 4_bot) (net 10) (tstamp 53ADF667))
(segment (start 135.12416 109.27584) (end 135.4 109) (width 0.2) (layer 4_bot) (net 10) (tstamp 53ADF664))
(segment (start 151.0504 110) (end 149.8 110) (width 0.4) (layer 4_bot) (net 11) (status 30))
(segment (start 149.8 110) (end 146.1 113.7) (width 0.4) (layer 4_bot) (net 11) (tstamp 53AE006E) (status 10))
(segment (start 137.3 113.7) (end 135.7744 115.2256) (width 0.4) (layer 4_bot) (net 11) (tstamp 53AE0022))
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(segment (start 142.55 169.65) (end 141.9 170.3) (width 0.2) (layer 4_bot) (net 95))
(segment (start 141.9 170.3) (end 127.7 170.3) (width 0.2) (layer 4_bot) (net 95))
(segment (start 127.7 170.3) (end 101 143.6) (width 0.2) (layer 4_bot) (net 95))
(segment (start 97 137) (end 97 139) (width 0.2) (layer 4_bot) (net 95) (status 10))
(segment (start 96.2 142.6) (end 97.2 143.6) (width 0.2) (layer 4_bot) (net 95) (tstamp 53AB45A4))
(segment (start 96.2 139.8) (end 96.2 142.6) (width 0.2) (layer 4_bot) (net 95) (tstamp 53AB45A2))
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(segment (start 142.55 164.45) (end 141.3 165.7) (width 0.2) (layer 4_bot) (net 96))
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Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(zone (net 0) (net_name "") (layer 2_pwr) (tstamp 53AA1C68) (hatch edge 0.508)
(connect_pads (clearance 0.2))
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Move and shrink copper layer legend. Doesn't need to be visible after assembly. I think.
2015-08-30 17:14:36 +00:00
(xy 75.2 140) (xy 75.2 135) (xy 77.8 135) (xy 77.8 140)
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
)
)
(zone (net 0) (net_name "") (layer 3_gnd) (tstamp 53AA1C69) (hatch edge 0.508)
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Move and shrink copper layer legend. Doesn't need to be visible after assembly. I think.
2015-08-30 17:14:36 +00:00
(xy 75.2 140) (xy 75.2 135) (xy 77.8 135) (xy 77.8 140)
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
)
)
(zone (net 2) (net_name +3.3V) (layer 2_pwr) (tstamp 53AA6D6C) (hatch edge 0.508)
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PCB: Remove H1 (fifth hole).
2017-01-28 22:57:20 +00:00
(xy 62 109) (xy 66 109) (xy 69 106) (xy 69 102) (xy 171 102)
(xy 171 106) (xy 174 109) (xy 178 109) (xy 178 166) (xy 174 166)
(xy 171 169) (xy 171 173) (xy 69 173) (xy 69 169) (xy 66 166)
(xy 62 166) (xy 62 159) (xy 70 159) (xy 70 121.4) (xy 62 121.4)
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
)
)
(zone (net 1) (net_name +1.8V) (layer 2_pwr) (tstamp 53AE109F) (hatch edge 0.508)
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(xy 83.6 145.2) (xy 83.6 155.6) (xy 70 155.6)
)
)
)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(zone (net 58) (net_name GND) (layer 3_gnd) (tstamp 53AA6EAC) (hatch edge 0.508)
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(connect_pads (clearance 0.2))
(min_thickness 0.2)
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Move and shrink copper layer legend. Doesn't need to be visible after assembly. I think.
2015-08-30 17:14:36 +00:00
(xy 75.2 140) (xy 75.2 135) (xy 77.8 135) (xy 77.8 140)
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
)
)
(zone (net 0) (net_name "") (layer F.Mask) (tstamp 53B19601) (hatch edge 0.508)
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Move and shrink copper layer legend. Doesn't need to be visible after assembly. I think.
2015-08-30 17:14:36 +00:00
(xy 75.2 140) (xy 75.2 135) (xy 77.8 135) (xy 77.8 140)
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
)
)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(zone (net 58) (net_name GND) (layer 4_bot) (tstamp 53B315F1) (hatch edge 0.508)
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(connect_pads (clearance 0.2))
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(polygon
(pts
(xy 60 100) (xy 180 100) (xy 180 175) (xy 60 175)
)
)
)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(zone (net 58) (net_name GND) (layer 2_pwr) (tstamp 53B317F9) (hatch edge 0.508)
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(connect_pads (clearance 0.2))
(min_thickness 0.2)
(fill (arc_segments 16) (thermal_gap 0.2) (thermal_bridge_width 0.3))
(polygon
(pts
(xy 60 100) (xy 180 100) (xy 180 175) (xy 60 175)
)
)
)
(zone (net 0) (net_name "") (layer 1_top) (tstamp 53B3161C) (hatch edge 0.508)
(connect_pads (clearance 0.2))
(min_thickness 0.2)
(keepout (tracks allowed) (vias allowed) (copperpour not_allowed))
(fill (arc_segments 16) (thermal_gap 0.2) (thermal_bridge_width 0.3))
(polygon
(pts
PCB: Remove H1 (fifth hole).
2017-01-28 22:57:20 +00:00
(xy 69 102) (xy 171 102) (xy 171 105.8) (xy 171 106) (xy 174 109)
(xy 178 109) (xy 178 166) (xy 174 166) (xy 171 169) (xy 171 173)
(xy 69 173) (xy 69 169) (xy 66 166) (xy 62 166) (xy 62 159)
(xy 70 159) (xy 70 121.4) (xy 62 121.4) (xy 62 109) (xy 66 109)
(xy 69 106)
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
)
)
PCB: Remove series resistors. Not sure they're of much benefit.
2017-01-28 23:18:49 +00:00
(zone (net 58) (net_name GND) (layer 1_top) (tstamp 53B315F1) (hatch edge 0.508)
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
(connect_pads (clearance 0.2))
(min_thickness 0.2)
(fill (arc_segments 16) (thermal_gap 0.2) (thermal_bridge_width 0.3))
(polygon
(pts
(xy 60 100) (xy 180 100) (xy 180 175) (xy 60 175)
)
)
)
(zone (net 0) (net_name "") (layer B.SilkS) (tstamp 53C7F92D) (hatch edge 0.508)
(connect_pads (clearance 0.2))
(min_thickness 0.1524)
(fill (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
(polygon
(pts
(xy 119 172) (xy 118 173) (xy 108 173) (xy 107 172) (xy 107 168)
(xy 108 167) (xy 118 167) (xy 119 168)
)
)
)
PCB: Remove H1 (fifth hole).
2017-01-28 22:57:20 +00:00
(zone (net 0) (net_name "") (layer 4_bot) (tstamp 53B3161C) (hatch edge 0.508)
(connect_pads (clearance 0.2))
(min_thickness 0.2)
(keepout (tracks allowed) (vias allowed) (copperpour not_allowed))
(fill (arc_segments 16) (thermal_gap 0.2) (thermal_bridge_width 0.3))
(polygon
(pts
(xy 69 102) (xy 171 102) (xy 171 105.8) (xy 171 106) (xy 174 109)
(xy 178 109) (xy 178 166) (xy 174 166) (xy 171 169) (xy 171 173)
(xy 69 173) (xy 69 169) (xy 66 166) (xy 62 166) (xy 62 159)
(xy 70 159) (xy 70 121.4) (xy 62 121.4) (xy 62 109) (xy 66 109)
(xy 69 106)
)
)
)
Initial release of schematic, PCB, CPLD code.
2015-07-16 16:32:10 +00:00
)
Reference in New Issue Copy Permalink