mirror of
https://github.com/portapack-mayhem/mayhem-firmware.git
synced 2025-08-15 00:27:40 +00:00
Formatted code (#1007)
* Updated style * Updated files * fixed new line * Updated spacing * File fix WIP * Updated to clang 13 * updated comment style * Removed old comment code
This commit is contained in:
jLynx
@@ -39,177 +39,160 @@ namespace gpdma {
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*/
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constexpr size_t buffer_words(const size_t bytes, const size_t word_size) {
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return (bytes + word_size - 1) / word_size;
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return (bytes + word_size - 1) / word_size;
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}
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using TCHandler = void (*)(void);
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using ErrHandler = void (*)(void);
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enum class FlowControl {
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MemoryToMemory_DMAControl = 0x0,
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MemoryToPeripheral_DMAControl = 0x1,
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PeripheralToMemory_DMAControl = 0x2,
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SourcePeripheralToDestinationPeripheral_DMAControl = 0x3,
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SourcePeripheralToDestinationPeripheral_DestinationControl = 0x4,
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MemoryToPeripheral_PeripheralControl = 0x5,
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PeripheralToMemory_PeripheralControl = 0x6,
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SourcePeripheralToDestinationPeripheral_SourceControl = 0x7,
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MemoryToMemory_DMAControl = 0x0,
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MemoryToPeripheral_DMAControl = 0x1,
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PeripheralToMemory_DMAControl = 0x2,
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SourcePeripheralToDestinationPeripheral_DMAControl = 0x3,
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SourcePeripheralToDestinationPeripheral_DestinationControl = 0x4,
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MemoryToPeripheral_PeripheralControl = 0x5,
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PeripheralToMemory_PeripheralControl = 0x6,
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SourcePeripheralToDestinationPeripheral_SourceControl = 0x7,
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};
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static const uint_fast8_t flow_control_peripheral_source_map = 0b11011100;
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constexpr uint_fast8_t source_endpoint_type(const FlowControl flow_control) {
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return (flow_control_peripheral_source_map >> toUType(flow_control)) & 1;
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return (flow_control_peripheral_source_map >> toUType(flow_control)) & 1;
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}
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static const uint_fast8_t flow_control_peripheral_destination_map = 0b11111010;
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constexpr uint_fast8_t destination_endpoint_type(const FlowControl flow_control) {
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return (flow_control_peripheral_destination_map >> toUType(flow_control)) & 1;
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return (flow_control_peripheral_destination_map >> toUType(flow_control)) & 1;
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}
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namespace mux {
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enum class Peripheral0 {
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SPIFI = 0,
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SCT_CTOUT_2 = 1,
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SGPIO14 = 2,
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TIMER3_MATCH_1 = 3,
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SPIFI = 0,
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SCT_CTOUT_2 = 1,
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SGPIO14 = 2,
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TIMER3_MATCH_1 = 3,
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};
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enum class Peripheral1 {
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TIMER0_MATCH_0 = 0,
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USART0_TX = 1,
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TIMER0_MATCH_0 = 0,
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USART0_TX = 1,
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};
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enum class Peripheral2 {
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TIMER0_MATCH_1 = 0,
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USART0_RX = 1,
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TIMER0_MATCH_1 = 0,
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USART0_RX = 1,
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};
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enum class Peripheral3 {
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TIMER1_MATCH_0 = 0,
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UART1_TX = 1,
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I2S1_DMAREQ_1 = 2,
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SSP1_TX = 3,
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TIMER1_MATCH_0 = 0,
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UART1_TX = 1,
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I2S1_DMAREQ_1 = 2,
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SSP1_TX = 3,
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};
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enum class Peripheral4 {
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TIMER1_MATCH_1 = 0,
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UART1_RX = 1,
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I2S1_DMAREQ_2 = 2,
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SSP1_RX = 3,
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TIMER1_MATCH_1 = 0,
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UART1_RX = 1,
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I2S1_DMAREQ_2 = 2,
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SSP1_RX = 3,
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};
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enum class Peripheral5 {
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TIMER2_MATCH_0 = 0,
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USART2_TX = 1,
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SSP1_TX = 2,
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SGPIO15 = 3,
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TIMER2_MATCH_0 = 0,
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USART2_TX = 1,
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SSP1_TX = 2,
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SGPIO15 = 3,
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};
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enum class Peripheral6 {
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TIMER2_MATCH_1 = 0,
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USART2_RX = 1,
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SSP1_RX = 2,
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SGPIO14 = 3,
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TIMER2_MATCH_1 = 0,
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USART2_RX = 1,
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SSP1_RX = 2,
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SGPIO14 = 3,
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};
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enum class Peripheral7 {
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TIMER3_MATCH_0 = 0,
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USART3_TX = 1,
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SCT_DMAREQ_0 = 2,
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ADCHS_WRITE = 3,
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TIMER3_MATCH_0 = 0,
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USART3_TX = 1,
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SCT_DMAREQ_0 = 2,
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ADCHS_WRITE = 3,
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};
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enum class Peripheral8 {
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TIMER3_MATCH_1 = 0,
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USART3_RX = 1,
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SCT_DMAREQ_1 = 2,
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ADCHS_READ = 3,
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TIMER3_MATCH_1 = 0,
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USART3_RX = 1,
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SCT_DMAREQ_1 = 2,
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ADCHS_READ = 3,
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};
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enum class Peripheral9 {
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SSP0_RX = 0,
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I2S0_DMAREQ_1 = 1,
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SCT_DMAREQ_1 = 2,
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SSP0_RX = 0,
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I2S0_DMAREQ_1 = 1,
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SCT_DMAREQ_1 = 2,
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};
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enum class Peripheral10 {
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SSP0_TX = 0,
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I2S0_DMAREQ_2 = 1,
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SCT_DMAREQ_0 = 2,
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SSP0_TX = 0,
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I2S0_DMAREQ_2 = 1,
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SCT_DMAREQ_0 = 2,
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};
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enum class Peripheral11 {
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SSP1_RX = 0,
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SGPIO14 = 1,
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USART0_TX = 2,
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SSP1_RX = 0,
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SGPIO14 = 1,
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USART0_TX = 2,
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};
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enum class Peripheral12 {
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SSP1_TX = 0,
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SGPIO15 = 1,
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USART0_RX = 2,
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SSP1_TX = 0,
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SGPIO15 = 1,
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USART0_RX = 2,
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};
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enum class Peripheral13 {
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ADC0 = 0,
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SSP1_RX = 2,
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USART3_RX = 3,
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ADC0 = 0,
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SSP1_RX = 2,
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USART3_RX = 3,
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};
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enum class Peripheral14 {
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ADC1 = 0,
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SSP1_TX = 2,
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USART3_TX = 3,
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ADC1 = 0,
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SSP1_TX = 2,
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USART3_TX = 3,
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};
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enum class Peripheral15 {
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DAC = 0,
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SCT_CTOUT_3 = 1,
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SGPIO15 = 2,
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TIMER3_MATCH_0 = 3,
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DAC = 0,
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SCT_CTOUT_3 = 1,
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SGPIO15 = 2,
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TIMER3_MATCH_0 = 3,
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};
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struct MUX {
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Peripheral0 peripheral_0;
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Peripheral1 peripheral_1;
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Peripheral2 peripheral_2;
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Peripheral3 peripheral_3;
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Peripheral4 peripheral_4;
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Peripheral5 peripheral_5;
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Peripheral6 peripheral_6;
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Peripheral7 peripheral_7;
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Peripheral8 peripheral_8;
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Peripheral9 peripheral_9;
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Peripheral10 peripheral_10;
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Peripheral11 peripheral_11;
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Peripheral12 peripheral_12;
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Peripheral13 peripheral_13;
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Peripheral14 peripheral_14;
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Peripheral15 peripheral_15;
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Peripheral0 peripheral_0;
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Peripheral1 peripheral_1;
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Peripheral2 peripheral_2;
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Peripheral3 peripheral_3;
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Peripheral4 peripheral_4;
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Peripheral5 peripheral_5;
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Peripheral6 peripheral_6;
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Peripheral7 peripheral_7;
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Peripheral8 peripheral_8;
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Peripheral9 peripheral_9;
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Peripheral10 peripheral_10;
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Peripheral11 peripheral_11;
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Peripheral12 peripheral_12;
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Peripheral13 peripheral_13;
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Peripheral14 peripheral_14;
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Peripheral15 peripheral_15;
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constexpr operator uint32_t() const {
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return
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(toUType(peripheral_0 ) << 0)
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| (toUType(peripheral_1 ) << 2)
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| (toUType(peripheral_2 ) << 4)
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| (toUType(peripheral_3 ) << 6)
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| (toUType(peripheral_4 ) << 8)
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| (toUType(peripheral_5 ) << 10)
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| (toUType(peripheral_6 ) << 12)
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| (toUType(peripheral_7 ) << 14)
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| (toUType(peripheral_8 ) << 16)
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| (toUType(peripheral_9 ) << 18)
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| (toUType(peripheral_10) << 20)
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| (toUType(peripheral_11) << 22)
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| (toUType(peripheral_12) << 24)
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| (toUType(peripheral_13) << 26)
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| (toUType(peripheral_14) << 28)
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| (toUType(peripheral_15) << 30)
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;
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}
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constexpr operator uint32_t() const {
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return (toUType(peripheral_0) << 0) | (toUType(peripheral_1) << 2) | (toUType(peripheral_2) << 4) | (toUType(peripheral_3) << 6) | (toUType(peripheral_4) << 8) | (toUType(peripheral_5) << 10) | (toUType(peripheral_6) << 12) | (toUType(peripheral_7) << 14) | (toUType(peripheral_8) << 16) | (toUType(peripheral_9) << 18) | (toUType(peripheral_10) << 20) | (toUType(peripheral_11) << 22) | (toUType(peripheral_12) << 24) | (toUType(peripheral_13) << 26) | (toUType(peripheral_14) << 28) | (toUType(peripheral_15) << 30);
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}
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};
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} /* namespace mux */
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@@ -217,154 +200,131 @@ struct MUX {
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namespace channel {
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struct LLI {
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uint32_t srcaddr;
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uint32_t destaddr;
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uint32_t lli;
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uint32_t control;
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uint32_t srcaddr;
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uint32_t destaddr;
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uint32_t lli;
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uint32_t control;
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};
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struct LLIPointer {
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uint32_t lm;
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uint32_t r;
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uint32_t lli;
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uint32_t lm;
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uint32_t r;
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uint32_t lli;
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constexpr operator uint32_t() const {
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return
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((lm & 1) << 0)
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| ((r & 1) << 1)
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| (lli & 0xfffffffc)
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;
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}
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constexpr operator uint32_t() const {
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return ((lm & 1) << 0) | ((r & 1) << 1) | (lli & 0xfffffffc);
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}
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};
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struct Control {
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uint32_t transfersize;
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uint32_t sbsize;
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uint32_t dbsize;
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uint32_t swidth;
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uint32_t dwidth;
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uint32_t s;
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uint32_t d;
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uint32_t si;
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uint32_t di;
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uint32_t prot1;
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uint32_t prot2;
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uint32_t prot3;
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uint32_t i;
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uint32_t transfersize;
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uint32_t sbsize;
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uint32_t dbsize;
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uint32_t swidth;
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uint32_t dwidth;
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uint32_t s;
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uint32_t d;
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uint32_t si;
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uint32_t di;
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uint32_t prot1;
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uint32_t prot2;
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uint32_t prot3;
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uint32_t i;
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constexpr operator uint32_t() const {
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return
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((transfersize & 0xfff) << 0)
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| ((sbsize & 7) << 12)
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| ((dbsize & 7) << 15)
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| ((swidth & 7) << 18)
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| ((dwidth & 7) << 21)
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| ((s & 1) << 24)
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| ((d & 1) << 25)
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| ((si & 1) << 26)
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| ((di & 1) << 27)
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| ((prot1 & 1) << 28)
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| ((prot2 & 1) << 29)
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| ((prot3 & 1) << 30)
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| ((i & 1) << 31)
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;
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}
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constexpr operator uint32_t() const {
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return ((transfersize & 0xfff) << 0) | ((sbsize & 7) << 12) | ((dbsize & 7) << 15) | ((swidth & 7) << 18) | ((dwidth & 7) << 21) | ((s & 1) << 24) | ((d & 1) << 25) | ((si & 1) << 26) | ((di & 1) << 27) | ((prot1 & 1) << 28) | ((prot2 & 1) << 29) | ((prot3 & 1) << 30) | ((i & 1) << 31);
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}
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};
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struct Config {
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uint32_t e;
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uint32_t srcperipheral;
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uint32_t destperipheral;
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FlowControl flowcntrl;
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uint32_t ie;
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uint32_t itc;
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uint32_t l;
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uint32_t a;
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uint32_t h;
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uint32_t e;
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uint32_t srcperipheral;
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uint32_t destperipheral;
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FlowControl flowcntrl;
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uint32_t ie;
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uint32_t itc;
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uint32_t l;
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uint32_t a;
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uint32_t h;
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constexpr operator uint32_t() const {
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return
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((e & 1) << 0)
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| ((srcperipheral & 0x1f) << 1)
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| ((destperipheral & 0x1f) << 6)
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| ((toUType(flowcntrl) & 7) << 11)
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| ((ie & 1) << 14)
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| ((itc & 1) << 15)
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| ((l & 1) << 16)
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| ((a & 1) << 17)
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| ((h & 1) << 18)
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;
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}
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constexpr operator uint32_t() const {
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return ((e & 1) << 0) | ((srcperipheral & 0x1f) << 1) | ((destperipheral & 0x1f) << 6) | ((toUType(flowcntrl) & 7) << 11) | ((ie & 1) << 14) | ((itc & 1) << 15) | ((l & 1) << 16) | ((a & 1) << 17) | ((h & 1) << 18);
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}
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};
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class Channel {
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public:
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constexpr Channel(
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const size_t number
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) : number(number)
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{
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}
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public:
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constexpr Channel(
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const size_t number)
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: number(number) {
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}
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void enable() const {
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LPC_GPDMA->CH[number].CONFIG |= (1U << 0);
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}
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void enable() const {
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LPC_GPDMA->CH[number].CONFIG |= (1U << 0);
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}
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bool is_enabled() const {
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return LPC_GPDMA->CH[number].CONFIG & (1U << 0);
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}
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bool is_enabled() const {
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return LPC_GPDMA->CH[number].CONFIG & (1U << 0);
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}
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void disable() const {
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LPC_GPDMA->CH[number].CONFIG &= ~(1U << 0);
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}
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void disable() const {
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LPC_GPDMA->CH[number].CONFIG &= ~(1U << 0);
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}
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void clear_interrupts() const {
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LPC_GPDMA->INTTCCLR = (1U << number);
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LPC_GPDMA->INTERRCLR = (1U << number);
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}
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void clear_interrupts() const {
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LPC_GPDMA->INTTCCLR = (1U << number);
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LPC_GPDMA->INTERRCLR = (1U << number);
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}
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void set_handlers(const TCHandler tc_handler, const ErrHandler err_handler) const;
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void set_handlers(const TCHandler tc_handler, const ErrHandler err_handler) const;
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void configure(const LLI& first_lli, const uint32_t config) const;
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void configure(const LLI& first_lli, const uint32_t config) const;
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const LLI* next_lli() const {
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return reinterpret_cast<LLI*>(LPC_GPDMA->CH[number].LLI);
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}
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const LLI* next_lli() const {
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return reinterpret_cast<LLI*>(LPC_GPDMA->CH[number].LLI);
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}
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private:
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const size_t number;
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private:
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const size_t number;
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};
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} /* namespace channel */
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constexpr std::array<channel::Channel, 8> channels { {
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{ 0 }, { 1 }, { 2 }, { 3 },
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{ 4 }, { 5 }, { 6 }, { 7 },
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} };
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constexpr std::array<channel::Channel, 8> channels{{
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{0},
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{1},
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{2},
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{3},
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{4},
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{5},
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{6},
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{7},
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}};
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static const gpdma_resources_t gpdma_resources = {
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.base = { .clk = &LPC_CGU->BASE_M4_CLK, .stat = &LPC_CCU1->BASE_STAT, .stat_mask = (1 << 3) },
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.branch = { .cfg = &LPC_CCU1->CLK_M4_DMA_CFG, .stat = &LPC_CCU1->CLK_M4_DMA_STAT },
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.reset = { .output_index = 19 },
|
||||
.base = {.clk = &LPC_CGU->BASE_M4_CLK, .stat = &LPC_CCU1->BASE_STAT, .stat_mask = (1 << 3)},
|
||||
.branch = {.cfg = &LPC_CCU1->CLK_M4_DMA_CFG, .stat = &LPC_CCU1->CLK_M4_DMA_STAT},
|
||||
.reset = {.output_index = 19},
|
||||
};
|
||||
|
||||
class Controller {
|
||||
public:
|
||||
void enable() const {
|
||||
base_clock_enable(&gpdma_resources.base);
|
||||
branch_clock_enable(&gpdma_resources.branch);
|
||||
peripheral_reset(&gpdma_resources.reset);
|
||||
LPC_GPDMA->CONFIG |= (1U << 0);
|
||||
}
|
||||
public:
|
||||
void enable() const {
|
||||
base_clock_enable(&gpdma_resources.base);
|
||||
branch_clock_enable(&gpdma_resources.branch);
|
||||
peripheral_reset(&gpdma_resources.reset);
|
||||
LPC_GPDMA->CONFIG |= (1U << 0);
|
||||
}
|
||||
|
||||
void disable() const {
|
||||
for(const auto& channel : channels) {
|
||||
channel.disable();
|
||||
}
|
||||
LPC_GPDMA->CONFIG &= ~(1U << 0);
|
||||
peripheral_reset(&gpdma_resources.reset);
|
||||
branch_clock_disable(&gpdma_resources.branch);
|
||||
base_clock_disable(&gpdma_resources.base);
|
||||
}
|
||||
void disable() const {
|
||||
for (const auto& channel : channels) {
|
||||
channel.disable();
|
||||
}
|
||||
LPC_GPDMA->CONFIG &= ~(1U << 0);
|
||||
peripheral_reset(&gpdma_resources.reset);
|
||||
branch_clock_disable(&gpdma_resources.branch);
|
||||
base_clock_disable(&gpdma_resources.base);
|
||||
}
|
||||
};
|
||||
|
||||
constexpr Controller controller;
|
||||
@@ -372,4 +332,4 @@ constexpr Controller controller;
|
||||
} /* namespace gpdma */
|
||||
} /* namespace lpc43xx */
|
||||
|
||||
#endif/*__GPDMA_H__*/
|
||||
#endif /*__GPDMA_H__*/
|
||||
|
||||
Reference in New Issue
Block a user