First test, ghost-singal c/m to only Mic_App

firmware/common/cpld_update.cpp

@@ -114,6 +114,20 @@ bool load_sram() {
 	return ok;
 }
 
+void load_sram_no_verify() {
+	// CoolRunner II family has Hybrid memory CPLD arquitecture (SRAM+NVM) 
+	// It seems that after using TX App somehow , I do not why , the CPLD_SRAM part needs to be re_loaded to solve #637 ghost beat 
+    // load_sram() it is already called at each boot in portapack.cpp ,including verify CPLD part.
+	// Here we skipped CPLD verify part,just to be quicker (in case any CPLD problem it will be detected in the boot process).
+
+	auto jtag_target_hackrf_cpld = jtag_target_hackrf();
+	hackrf::one::cpld::CPLD hackrf_cpld { jtag_target_hackrf_cpld };
+
+ 	hackrf_cpld.write_sram(hackrf::one::cpld::verify_blocks);
+
+	return;
+}
+
 bool verify_eeprom() {
 	auto jtag_target_hackrf_cpld = jtag_target_hackrf();
 	hackrf::one::cpld::CPLD hackrf_cpld { jtag_target_hackrf_cpld };

firmware/common/cpld_update.hpp

@@ -38,6 +38,7 @@ namespace hackrf {
 namespace cpld {
 
 bool load_sram();
+void load_sram_no_verify(); // added to solve issue #637 , "ghost" signal at RX , after using any TX App
 bool verify_eeprom();
 void init_from_eeprom();