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This commit is contained in:
furrtek
2016-01-31 09:34:24 +01:00
parent 29ec87a9ad
commit 44638e504b
166 changed files with 8700 additions and 3967 deletions
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38
firmware/chibios-portapack/os/hal/platforms/LPC43xx/lpc43xx.inc
View File

@@ -1372,43 +1372,6 @@ typedef struct {
// ------------------------------------------------------------------------------------------------
#ifdef __cplusplus
#define LPC_PERIPHERAL(_t, _i) constexpr auto const LPC_ ## _i = reinterpret_cast<LPC_ ## _t ## _Type*>(LPC_ ## _i ## _BASE)
LPC_PERIPHERAL(GPDMA, GPDMA);
LPC_PERIPHERAL(SPIFI, SPIFI);
LPC_PERIPHERAL(SDMMC, SDMMC);
LPC_PERIPHERAL(CREG, CREG);
LPC_PERIPHERAL(RTC, RTC);
LPC_PERIPHERAL(CGU, CGU);
LPC_PERIPHERAL(CCU1, CCU1);
LPC_PERIPHERAL(CCU2, CCU2);
LPC_PERIPHERAL(RGU, RGU);
LPC_PERIPHERAL(USART, USART0);
LPC_PERIPHERAL(UART, UART1);
LPC_PERIPHERAL(SSPx, SSP0);
LPC_PERIPHERAL(TIMER, TIMER0);
LPC_PERIPHERAL(TIMER, TIMER1);
LPC_PERIPHERAL(SCU, SCU);
LPC_PERIPHERAL(GPIO_INT, GPIO_INT);
LPC_PERIPHERAL(I2Cx, I2C0);
LPC_PERIPHERAL(I2S, I2S0);
LPC_PERIPHERAL(I2S, I2S1);
LPC_PERIPHERAL(RITIMER, RITIMER);
LPC_PERIPHERAL(USART, USART2);
LPC_PERIPHERAL(USART, USART3);
LPC_PERIPHERAL(TIMER, TIMER2);
LPC_PERIPHERAL(TIMER, TIMER3);
LPC_PERIPHERAL(SSPx, SSP1);
LPC_PERIPHERAL(I2Cx, I2C1);
LPC_PERIPHERAL(ADCx, ADC0);
LPC_PERIPHERAL(ADCx, ADC1);
LPC_PERIPHERAL(GPIO, GPIO);
LPC_PERIPHERAL(SGPIO, SGPIO);
#else
#define LPC_GPDMA ((LPC_GPDMA_Type *) LPC_GPDMA_BASE)
#define LPC_SPIFI ((LPC_SPIFI_Type *) LPC_SPIFI_BASE)
#define LPC_SDMMC ((LPC_SDMMC_Type *) LPC_SDMMC_BASE)
@@ -1439,7 +1402,6 @@ LPC_PERIPHERAL(SGPIO, SGPIO);
#define LPC_ADC1 ((LPC_ADCx_Type *) LPC_ADC1_BASE)
#define LPC_GPIO ((LPC_GPIO_Type *) LPC_GPIO_BASE)
#define LPC_SGPIO ((LPC_SGPIO_Type *) LPC_SGPIO_BASE)
#endif
#ifdef __cplusplus
}

56
firmware/chibios-portapack/os/hal/platforms/LPC43xx_M4/lpc43xx_m4.h
View File

@@ -134,34 +134,34 @@ typedef enum IRQn {
/* Overload of __SXTB16() to add ROR argument, since using __ROR() as an
* argument to the existing __SXTB16() doesn't produce optimum/sane code.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t rm, uint32_t ror)
__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __SXTB16(uint32_t rm, uint32_t ror)
{
uint32_t rd;
int32_t rd;
__ASM volatile ("sxtb16 %0, %1, ror %2" : "=r" (rd) : "r" (rm), "I" (ror));
return rd;
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTH(uint32_t rm, uint32_t ror)
__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __SXTH(uint32_t rm, uint32_t ror)
{
uint32_t rd;
int32_t rd;
__ASM volatile ("sxth %0, %1, ror %2" : "=r" (rd) : "r" (rm), "I" (ror));
return rd;
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLATB(uint32_t rm, uint32_t rs, uint32_t rn) {
uint32_t rd;
__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __SMLATB(uint32_t rm, uint32_t rs, uint32_t rn) {
int32_t rd;
__ASM volatile ("smlatb %0, %1, %2, %3" : "=r" (rd) : "r" (rm), "r" (rs), "r" (rn));
return rd;
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLABB(uint32_t rm, uint32_t rs, uint32_t rn) {
uint32_t rd;
__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __SMLABB(uint32_t rm, uint32_t rs, uint32_t rn) {
int32_t rd;
__ASM volatile("smlabb %0, %1, %2, %3" : "=r" (rd) : "r" (rm), "r" (rs), "r" (rn));
return rd;
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAH(uint32_t rn, uint32_t rm, uint32_t ror) {
uint32_t rd;
__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __SXTAH(uint32_t rn, uint32_t rm, uint32_t ror) {
int32_t rd;
__ASM volatile("sxtah %0, %1, %2, ror %3" : "=r" (rd) : "r" (rn), "r" (rm), "I" (ror));
return rd;
}
@@ -172,37 +172,37 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __BFI(uint32_t rd, u
return rd;
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMULBB(uint32_t op1, uint32_t op2) {
uint32_t result;
__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __SMULBB(uint32_t op1, uint32_t op2) {
int32_t result;
__ASM volatile ("smulbb %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return result;
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMULBT(uint32_t op1, uint32_t op2) {
uint32_t result;
__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __SMULBT(uint32_t op1, uint32_t op2) {
int32_t result;
__ASM volatile ("smulbt %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return result;
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMULTB(uint32_t op1, uint32_t op2) {
uint32_t result;
__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __SMULTB(uint32_t op1, uint32_t op2) {
int32_t result;
__ASM volatile ("smultb %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return result;
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMULTT(uint32_t op1, uint32_t op2) {
uint32_t result;
__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __SMULTT(uint32_t op1, uint32_t op2) {
int32_t result;
__ASM volatile ("smultt %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return result;
}
#undef __SMLALD
__attribute__( ( always_inline ) ) static inline uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
__attribute__( ( always_inline ) ) static inline int64_t __SMLALD (uint32_t op1, uint32_t op2, int64_t acc)
{
union llreg_u{
uint32_t w32[2];
uint64_t w64;
int64_t w64;
} llr;
llr.w64 = acc;
@@ -213,11 +213,11 @@ __attribute__( ( always_inline ) ) static inline uint64_t __SMLALD (uint32_t op1
#undef __SMLALDX
__attribute__( ( always_inline ) ) static inline uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
__attribute__( ( always_inline ) ) static inline int64_t __SMLALDX (uint32_t op1, uint32_t op2, int64_t acc)
{
union llreg_u{
uint32_t w32[2];
uint64_t w64;
int64_t w64;
} llr;
llr.w64 = acc;
@@ -228,11 +228,11 @@ __attribute__( ( always_inline ) ) static inline uint64_t __SMLALDX (uint32_t op
#undef __SMLSLD
__attribute__( ( always_inline ) ) static inline uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
__attribute__( ( always_inline ) ) static inline int64_t __SMLSLD (uint32_t op1, uint32_t op2, int64_t acc)
{
union llreg_u{
uint32_t w32[2];
uint64_t w64;
int64_t w64;
} llr;
llr.w64 = acc;
@@ -241,6 +241,14 @@ __attribute__( ( always_inline ) ) static inline uint64_t __SMLSLD (uint32_t op1
return(llr.w64);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __SMMULR (int32_t op1, int32_t op2)
{
uint32_t result;
__ASM volatile ("smmulr %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
#endif /* __cplusplus */
#endif /* __LPC43XX_M4_H */