diff --git a/firmware/application/audio.cpp b/firmware/application/audio.cpp
index 67dfee76b..19022434e 100644
--- a/firmware/application/audio.cpp
+++ b/firmware/application/audio.cpp
@@ -55,6 +55,7 @@ constexpr i2s::ConfigTX i2s0_config_tx {
 		.four_pin = 0,
 		.mclk_out_en = 1,
 	},
+	.sck_in_sel = 1,
 };
 
 constexpr i2s::ConfigRX i2s0_config_rx {
@@ -78,6 +79,7 @@ constexpr i2s::ConfigRX i2s0_config_rx {
 		.four_pin = 1,
 		.mclk_out_en = 0,
 	},
+	.sck_in_sel = 0,
 };
 
 constexpr i2s::ConfigDMA i2s0_config_dma {
diff --git a/firmware/chibios-portapack/os/hal/platforms/LPC43xx/lpc43xx.inc b/firmware/chibios-portapack/os/hal/platforms/LPC43xx/lpc43xx.inc
index fb09b7826..94ea0812a 100644
--- a/firmware/chibios-portapack/os/hal/platforms/LPC43xx/lpc43xx.inc
+++ b/firmware/chibios-portapack/os/hal/platforms/LPC43xx/lpc43xx.inc
@@ -41,6 +41,19 @@ extern "C" {
   * @brief Product name title=UM10503 Chapter title=LPC43xx Configuration Registers (CREG) Modification date=1/28/2014 Major revision=1 Minor revision=8
   */
 
+typedef struct {
+  __IO uint32_t ETHMODE            : 3;
+       uint32_t RESERVED0          : 1;
+  __IO uint32_t CTOUTCTRL          : 1;
+       uint32_t RESERVED1          : 7;
+  __IO uint32_t I2S0_TX_SCK_IN_SEL : 1;
+  __IO uint32_t I2S0_RX_SCK_IN_SEL : 1;
+  __IO uint32_t I2S1_TX_SCK_IN_SEL : 1;
+  __IO uint32_t I2S1_RX_SCK_IN_SEL : 1;
+  __IO uint32_t EMC_CLK_SEL        : 1;
+       uint32_t RESERVED2          : 15;
+} LPC_CREG_CREG6_Type;
+
 typedef struct {
        uint32_t RESERVED0;
   __IO uint32_t CREG0;
@@ -52,7 +65,7 @@ typedef struct {
   __IO uint32_t FLASHCFGA;
   __IO uint32_t FLASHCFGB;
   __IO uint32_t ETBCFG;
-  __IO uint32_t CREG6;
+  LPC_CREG_CREG6_Type CREG6;
   __IO uint32_t M4TXEVENT;
        uint32_t RESERVED3[51];
   __I  uint32_t CHIPID;
diff --git a/firmware/common/i2s.hpp b/firmware/common/i2s.hpp
index 0ddaa9664..d715146d9 100644
--- a/firmware/common/i2s.hpp
+++ b/firmware/common/i2s.hpp
@@ -138,6 +138,7 @@ struct ConfigTX {
 	uint32_t txrate;
 	uint32_t txbitrate;
 	uint32_t txmode;
+	uint32_t sck_in_sel;
 };
 
 struct ConfigRX {
@@ -145,6 +146,7 @@ struct ConfigRX {
 	uint32_t rxrate;
 	uint32_t rxbitrate;
 	uint32_t rxmode;
+	uint32_t sck_in_sel;
 };
 
 struct ConfigDMA {
@@ -161,21 +163,13 @@ public:
 	) {
 		reset();
 
-		/* I2S operates in master mode, use PLL0AUDIO as MCLK source for TX. */
-		/* NOTE: Documentation of CREG6 is quite confusing. Refer to "I2S clocking and
-		 * pin connections" and other I2S diagrams for more clarity.
-		 */
 		if( &p() == LPC_I2S0 ) {
-			LPC_CREG->CREG6 |=
-				  (1U << 12)
-				| (1U << 13)
-				;
+			LPC_CREG->CREG6.I2S0_TX_SCK_IN_SEL = config_tx.sck_in_sel;
+			LPC_CREG->CREG6.I2S0_RX_SCK_IN_SEL = config_rx.sck_in_sel;
 		}
 		if( &p() == LPC_I2S1 ) {
-			LPC_CREG->CREG6 |=
-				  (1U << 14)
-				| (1U << 15)
-				;
+			LPC_CREG->CREG6.I2S1_TX_SCK_IN_SEL = config_tx.sck_in_sel;
+			LPC_CREG->CREG6.I2S1_RX_SCK_IN_SEL = config_rx.sck_in_sel;
 		}
 
 		p().DAO = config_tx.dao;