diff --git a/firmware/common/cpld_xilinx.cpp b/firmware/common/cpld_xilinx.cpp new file mode 100644 index 00000000..7cc6b79d --- /dev/null +++ b/firmware/common/cpld_xilinx.cpp @@ -0,0 +1,145 @@ +/* + * Copyright (C) 2016 Jared Boone, ShareBrained Technology, Inc. + * + * This file is part of PortaPack. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; see the file COPYING. If not, write to + * the Free Software Foundation, Inc., 51 Franklin Street, + * Boston, MA 02110-1301, USA. + */ + +#include "cpld_xilinx.hpp" + +namespace cpld { +namespace xilinx { + +void XC2C64A::write_sram(const verify_blocks_t& blocks) { + tap.set_repeat(0); + tap.set_end_ir(state_t::run_test_idle); + tap.set_end_dr(state_t::run_test_idle); + + reset(); + enable(); + + shift_ir(instruction_t::ISC_WRITE); + for(const auto& block : blocks) { + tap.state(state_t::shift_dr); + tap.shift({ block.data.data(), block_length }, false); + tap.shift({ &block.id, block_id_length }, true); + tap.state(state_t::run_test_idle); + } + + disable(); + bypass(); + + tap.state(state_t::test_logic_reset); +} + +bool XC2C64A::verify_sram(const verify_blocks_t& blocks) { + tap.set_repeat(0); + tap.set_end_ir(state_t::run_test_idle); + tap.set_end_dr(state_t::run_test_idle); + + reset(); + enable(); + + shift_ir(instruction_t::ISC_SRAM_READ); + + // Prime the operation with a read of an empty row. + const jtag::tap::bits_t empty_row { block_length }; + + tap.state(state_t::shift_dr); + tap.shift(empty_row, false); + + auto error = false; + for(const auto& block : blocks) { + tap.shift({ &block.id, block_id_length }, true); + tap.state(state_t::run_test_idle); + + tap.state(state_t::shift_dr); + error |= tap.shift(empty_row, { block.data.data(), block_length }, { block.mask.data(), block_length }, false); + } + // Redundant operation to finish the row. + tap.shift({ &blocks[0].id, block_id_length }, true); + tap.state(state_t::run_test_idle); + tap.set_end_dr(state_t::run_test_idle); + + disable(); + bypass(); + + tap.state(state_t::test_logic_reset); + + return !error; +} + +bool XC2C64A::verify_eeprom(const verify_blocks_t& blocks) { + tap.set_repeat(0); + tap.set_end_ir(state_t::run_test_idle); + tap.set_end_dr(state_t::run_test_idle); + + reset(); + bypass(); + enable(); + + shift_ir(instruction_t::ISC_READ); + + const jtag::tap::bits_t empty_row { block_length }; + + auto error = false; + for(const auto& block : blocks) { + tap.set_end_dr(state_t::pause_dr); + tap.shift_dr({ &block.id, block_id_length }); + tap.set_end_ir(state_t::run_test_idle); + tap.wait(state_t::pause_dr, state_t::pause_dr, 20); + tap.set_end_ir(state_t::run_test_idle); + tap.wait(state_t::run_test_idle, state_t::run_test_idle, 100); + error |= tap.shift_dr(empty_row, { block.data.data(), block_length }, { block.mask.data(), block_length }); + tap.wait(state_t::run_test_idle, state_t::run_test_idle, 100); + } + + disable(); + bypass(); + + tap.state(state_t::test_logic_reset); + + return !error; +} + +bool XC2C64A::shift_ir(const instruction_t instruction) { + const ir_t ir_buffer = toUType(instruction); + const jtag::tap::bits_t bits { &ir_buffer, ir_length }; + return tap.shift_ir(bits); +} + +void XC2C64A::reset() { + tap.state(state_t::test_logic_reset); + tap.state(state_t::run_test_idle); +} + +void XC2C64A::enable() { + shift_ir(instruction_t::ISC_ENABLE); + tap.wait(state_t::run_test_idle, state_t::run_test_idle, 800); +} + +void XC2C64A::disable() { + shift_ir(instruction_t::ISC_DISABLE); + tap.wait(state_t::run_test_idle, state_t::run_test_idle, 100); +} + +bool XC2C64A::bypass() { + return shift_ir(instruction_t::BYPASS); +} + +} /* namespace xilinx */ +} /* namespace cpld */ diff --git a/firmware/common/cpld_xilinx.hpp b/firmware/common/cpld_xilinx.hpp new file mode 100644 index 00000000..36f7476a --- /dev/null +++ b/firmware/common/cpld_xilinx.hpp @@ -0,0 +1,122 @@ +/* + * Copyright (C) 2016 Jared Boone, ShareBrained Technology, Inc. + * + * This file is part of PortaPack. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; see the file COPYING. If not, write to + * the Free Software Foundation, Inc., 51 Franklin Street, + * Boston, MA 02110-1301, USA. + */ + +#ifndef __CPLD_XILINX_H__ +#define __CPLD_XILINX_H__ + +#include "jtag_tap.hpp" + +#include "utility.hpp" + +#include +#include +#include + +namespace cpld { +namespace xilinx { + +using jtag::tap::state_t; + +class XC2C64A { +public: + using block_id_t = uint8_t; + + static constexpr size_t block_length = 274; + static constexpr size_t blocks_count = 98; + + static constexpr size_t block_bytes = (block_length + 7) >> 3; + + struct verify_block_t { + block_id_t id; + std::array data; + std::array mask; + }; + + struct program_block_t { + block_id_t id; + std::array data; + }; + + using verify_blocks_t = std::array; + + constexpr XC2C64A( + jtag::Target& jtag_interface + ) : tap { jtag_interface } + { + } + + void write_sram(const verify_blocks_t& blocks); + bool verify_sram(const verify_blocks_t& blocks); + + bool verify_eeprom(const verify_blocks_t& blocks); + +private: + static constexpr size_t idcode_length = 32; + using idcode_t = uint32_t; + + static constexpr size_t ir_length = 8; + static constexpr size_t block_id_length = 7; + + static constexpr idcode_t idcode = 0x06e58093; + static constexpr idcode_t idcode_mask = 0x0fff8fff; + + using ir_t = uint8_t; + + jtag::tap::TAPMachine tap; + + enum class instruction_t : ir_t { + INTEST = 0b00000010, // -> boundary-scan + BYPASS = 0b11111111, // -> bypass + SAMPLE = 0b00000011, // -> boundary-scan + EXTEST = 0b00000000, // -> boundary-scan + IDCODE = 0b00000001, // -> device ID + USERCODE = 0b11111101, // -> device ID + HIGHZ = 0b11111100, // -> bypass + ISC_ENABLE_CLAMP = 0b11101001, // -> ISC shift + ISC_ENABLE_OTF = 0b11100100, // -> ISC shift + ISC_ENABLE = 0b11101000, // -> ISC shift + ISC_SRAM_READ = 0b11100111, // -> ISC shift + ISC_WRITE = 0b11100110, // -> ISC shift, alias ISC_SRAM_WRITE + ISC_ERASE = 0b11101101, // -> ISC shift + ISC_PROGRAM = 0b11101010, // -> ISC shift + ISC_READ = 0b11101110, // -> ISC shift, alias ISC_VERIFY + ISC_INIT = 0b11110000, // -> ISC shift + ISC_DISABLE = 0b11000000, // -> ISC shift + TEST_ENABLE = 0b00010001, // alias Private1 + BULKPROG = 0b00010010, // alias Private2 + ERASE_ALL = 0b00010100, // alias Private4 + MVERIFY = 0b00010011, // alias Private3 + TEST_DISABLE = 0b00010101, // alias Private5 + ISC_NOOP = 0b11100000, // -> bypass + }; + + bool shift_ir(const instruction_t instruction); + + void reset(); + void enable(); + void disable(); + bool bypass(); +}; + +} /* namespace xilinx */ +} /* namespace cpld */ + +#endif/*__CPLD_XILINX_H__*/