diff --git a/firmware/baseband/mcuconf.h b/firmware/baseband/mcuconf.h
index 76f84576..eae37545 100755
--- a/firmware/baseband/mcuconf.h
+++ b/firmware/baseband/mcuconf.h
@@ -41,3 +41,7 @@
 //#define LPC_ADC1_IRQ_PRIORITY               4
 
 #define LPC43XX_M0APPTXEVENT_IRQ_PRIORITY   4
+
+/* M4 is initialized by M0, which has already started PLL1 */
+#define LPC43XX_M4_CLK                      200000000
+#define LPC43XX_M4_CLK_SRC                  0x09
\ No newline at end of file
diff --git a/firmware/chibios-portapack/os/hal/platforms/LPC43xx_M4/hal_lld.c b/firmware/chibios-portapack/os/hal/platforms/LPC43xx_M4/hal_lld.c
index 4ef29412..b610f250 100755
--- a/firmware/chibios-portapack/os/hal/platforms/LPC43xx_M4/hal_lld.c
+++ b/firmware/chibios-portapack/os/hal/platforms/LPC43xx_M4/hal_lld.c
@@ -41,7 +41,7 @@
 /* TODO: Somehow share this value between the M4 and M0 cores. The M0 always
  * runs at the same speed as the M4 core.
  */
-static halclock_t hal_clock_f = LPC43XX_M4_CLK_IRC;
+static halclock_t hal_clock_f = LPC43XX_M4_CLK;
 
 /*===========================================================================*/
 /* Driver local functions.                                                   */
@@ -74,7 +74,7 @@ void systick_adjust_period(const uint32_t counts_per_tick) {
  */
 void hal_lld_init(void) {
   LPC_CGU->BASE_M4_CLK.AUTOBLOCK = 1;
-  LPC_CGU->BASE_M4_CLK.CLK_SEL = 1;
+  LPC_CGU->BASE_M4_CLK.CLK_SEL = LPC43XX_M4_CLK_SRC;
 
   /* SysTick initialization using the system clock.*/
   systick_adjust_period(halLPCGetSystemClock() / CH_FREQUENCY - 1);