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Sync with Sharebrained's fw, only Xylos TX works for now

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This commit is contained in:
furrtek
2016-07-27 03:03:40 +02:00
parent fdfa7c9776
commit 739956b42b
150 changed files with 17236 additions and 7875 deletions
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24
firmware/baseband/baseband_dma.cpp
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@@ -115,16 +115,9 @@ static void dma_error() {
void init() {
gpdma_channel_sgpio.set_handlers(transfer_complete, dma_error);
#if defined(PORTAPACK_BASEBAND_DMA_NO_SYNC)
/* Disable synchronization logic to improve(?) DMA response time.
* SGPIO (peripheral) must be on same clock as GPDMA peripheral.
* SGPIO runs from BASE_PERIPH_CLK, which is set to PLL1 in normal
* operation, same as the M4 and M0 cores. Memory, of course, is
* running from the same clock as the cores.
*/
LPC_GPDMA->SYNC |= (1 << gpdma_src_peripheral);
LPC_GPDMA->SYNC |= (1 << gpdma_dest_peripheral);
#endif
// LPC_GPDMA->SYNC |= (1 << gpdma_src_peripheral);
// LPC_GPDMA->SYNC |= (1 << gpdma_dest_peripheral);
}
void configure(
@@ -167,5 +160,16 @@ baseband::buffer_t wait_for_rx_buffer() {
}
}
baseband::buffer_t wait_for_tx_buffer() {
const auto next_index = thread_wait.sleep();
if( next_index >= 0 ) {
const size_t free_index = (next_index + transfers_per_buffer - 2) & transfers_mask;
return { reinterpret_cast<sample_t*>(lli_loop[free_index].srcaddr), transfer_samples };
} else {
return { };
}
}
} /* namespace dma */
} /* namespace baseband */