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CPLD: Switch sense of LCD_RD/WR pins.

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Should keep CPLD settled when in HackRF mode.
This commit is contained in:
Jared Boone
2017-07-20 16:33:55 -07:00
parent 8bc878c5e5
commit 751ae92509
13 changed files with 3283 additions and 3221 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
firmware/application/portapack.cpp
View File

@@ -49,8 +49,8 @@ namespace portapack {
portapack::IO io {
portapack::gpio_dir,
portapack::gpio_lcd_rd,
portapack::gpio_lcd_wr,
portapack::gpio_lcd_rdx,
portapack::gpio_lcd_wrx,
portapack::gpio_io_stbx,
portapack::gpio_addr,
portapack::gpio_lcd_te,

10
firmware/common/pins.hpp
View File

@@ -64,20 +64,20 @@ constexpr Pin pins[] = {
[P1_18] = { 1, 18, PinConfig::gpio_out_with_pulldown(0) }, /* SGPIO12/BANK2F3M12: CPLD.70/HOST_INVERT(I) */
[P1_19] = { 1, 19, { .mode=1, .pd=1, .pu=0, .fast=0, .input=0, .ifilt=1 } }, /* SSP1_SCK/P39: MAX2837.SCLK(I), MAX5864.SCLK(I) */
[P1_20] = { 1, 20, { .mode=0, .pd=0, .pu=1, .fast=0, .input=0, .ifilt=1 } }, /* CS_XCVR/P53: MAX2837.CS(I) */
[P2_0] = { 2, 0, { .mode=4, .pd=0, .pu=1, .fast=0, .input=1, .ifilt=1 } }, /* U0_TXD: PortaPack P2_0/IO_STBX */
[P2_1] = { 2, 1, { .mode=4, .pd=1, .pu=0, .fast=0, .input=1, .ifilt=1 } }, /* U0_RXD: PortaPack P2_1/ADDR */
[P2_0] = { 2, 0, { .mode=4, .pd=0, .pu=0, .fast=0, .input=1, .ifilt=1 } }, /* U0_TXD: PortaPack P2_0/IO_STBX */
[P2_1] = { 2, 1, { .mode=4, .pd=0, .pu=0, .fast=0, .input=1, .ifilt=1 } }, /* U0_RXD: PortaPack P2_1/ADDR */
[P2_2] = { 2, 2, PinConfig::sgpio_inout_fast(0) }, /* SGPIO6/BANK2F3M16: CPLD.61/HOST_DATA6(IO) */
[P2_3] = { 2, 3, { .mode=4, .pd=0, .pu=0, .fast=0, .input=1, .ifilt=1 } }, /* I2C1_SDA: PortaPack P2_3/LCD_TE */
[P2_4] = { 2, 4, { .mode=4, .pd=0, .pu=0, .fast=0, .input=1, .ifilt=1 } }, /* I2C1_SCL: PortaPack P2_4/LCD_RD */
[P2_4] = { 2, 4, { .mode=4, .pd=0, .pu=0, .fast=0, .input=1, .ifilt=1 } }, /* I2C1_SCL: PortaPack P2_4/LCD_RDX */
[P2_5] = { 2, 5, { .mode=4, .pd=0, .pu=1, .fast=0, .input=0, .ifilt=1 } }, /* RX/P43: U7.VCTL1(I), U10.VCTL1(I), U2.VCTL1(I) */
[P2_6] = { 2, 6, { .mode=4, .pd=0, .pu=0, .fast=0, .input=0, .ifilt=1 } }, /* MIXER_SCLK/P31: 33pF, RFFC5072.SCLK(I) */
[P2_7] = { 2, 7, { .mode=0, .pd=0, .pu=0, .fast=0, .input=1, .ifilt=1 } }, /* ISP: 10K PU, Unused */
[P2_8] = { 2, 8, { .mode=4, .pd=0, .pu=0, .fast=0, .input=0, .ifilt=1 } }, /* P2_8: 10K PD, BOOT2, DFU switch, PortaPack P2_8/<unused> */
[P2_9] = { 2, 9, { .mode=0, .pd=0, .pu=0, .fast=0, .input=0, .ifilt=1 } }, /* P2_9: 10K PD, BOOT3, PortaPack P2_9/LCD_WR */
[P2_9] = { 2, 9, { .mode=0, .pd=0, .pu=0, .fast=0, .input=0, .ifilt=1 } }, /* P2_9: 10K PD, BOOT3, PortaPack P2_9/LCD_WRX */
[P2_10] = { 2, 10, { .mode=0, .pd=0, .pu=1, .fast=0, .input=0, .ifilt=1 } }, /* AMP_BYPASS/P50: U14.V2(I), U12.V2(I) */
[P2_11] = { 2, 11, { .mode=0, .pd=1, .pu=0, .fast=0, .input=0, .ifilt=1 } }, /* RX_AMP/P49: U12.V1(I), U14.V3(I) */
[P2_12] = { 2, 12, { .mode=0, .pd=0, .pu=0, .fast=0, .input=0, .ifilt=1 } }, /* !RX_AMP_PWR/P52: 10K PU, Q1.G(I), power to U13 (RX amp) */
[P2_13] = { 2, 13, { .mode=0, .pd=0, .pu=1, .fast=0, .input=1, .ifilt=1 } }, /* P2_13: PortaPack P2_13/DIR */
[P2_13] = { 2, 13, { .mode=0, .pd=0, .pu=0, .fast=0, .input=1, .ifilt=1 } }, /* P2_13: PortaPack P2_13/DIR */
[P3_0] = { 3, 0, { .mode=2, .pd=0, .pu=1, .fast=0, .input=0, .ifilt=1 } }, /* I2S0_TX_SCK: PortaPack I2S0_TX_SCK(I) */
[P3_1] = { 3, 1, { .mode=0, .pd=0, .pu=1, .fast=0, .input=1, .ifilt=1 } }, /* I2S0_RX_WS: PortaPack I2S0_TX_WS(I). Input enabled to fold back into RX. */
[P3_2] = { 3, 2, { .mode=0, .pd=0, .pu=1, .fast=0, .input=0, .ifilt=1 } }, /* I2S0_RX_SDA: PortaPack I2S0_TX_SDA(I) */

4
firmware/common/portapack_hal.hpp
View File

@@ -37,8 +37,8 @@ constexpr GPIO gpio_io_stbx = gpio[GPIO5_0]; /* P2_0 */
constexpr GPIO gpio_addr = gpio[GPIO5_1]; /* P2_1 */
constexpr GPIO gpio_lcd_te = gpio[GPIO5_3]; /* P2_3 */
constexpr GPIO gpio_unused = gpio[GPIO5_7]; /* P2_8 */
constexpr GPIO gpio_lcd_rd = gpio[GPIO5_4]; /* P2_4 */
constexpr GPIO gpio_lcd_wr = gpio[GPIO1_10]; /* P2_9 */
constexpr GPIO gpio_lcd_rdx = gpio[GPIO5_4]; /* P2_4 */
constexpr GPIO gpio_lcd_wrx = gpio[GPIO1_10]; /* P2_9 */
constexpr GPIO gpio_dir = gpio[GPIO1_13]; /* P2_13 */
constexpr std::array<GPIO, 8> gpios_data {
gpio[GPIO3_8],

4
firmware/common/portapack_io.cpp
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@@ -43,8 +43,8 @@ void IO::init() {
addr(0);
gpio_dir.output();
gpio_lcd_rd.output();
gpio_lcd_wr.output();
gpio_lcd_rdx.output();
gpio_lcd_wrx.output();
gpio_io_stbx.output();
gpio_addr.output();
gpio_rot_a.input();

20
firmware/common/portapack_io.hpp
View File

@@ -80,15 +80,15 @@ public:
constexpr IO(
GPIO gpio_dir,
GPIO gpio_lcd_rd,
GPIO gpio_lcd_wr,
GPIO gpio_lcd_rdx,
GPIO gpio_lcd_wrx,
GPIO gpio_io_stbx,
GPIO gpio_addr,
GPIO gpio_rot_a,
GPIO gpio_rot_b
) : gpio_dir { gpio_dir },
gpio_lcd_rd { gpio_lcd_rd },
gpio_lcd_wr { gpio_lcd_wr },
gpio_lcd_rdx { gpio_lcd_rdx },
gpio_lcd_wrx { gpio_lcd_wrx },
gpio_io_stbx { gpio_io_stbx },
gpio_addr { gpio_addr },
gpio_rot_a { gpio_rot_a },
@@ -199,8 +199,8 @@ public:
private:
const GPIO gpio_dir;
const GPIO gpio_lcd_rd;
const GPIO gpio_lcd_wr;
const GPIO gpio_lcd_rdx;
const GPIO gpio_lcd_wrx;
const GPIO gpio_io_stbx;
const GPIO gpio_addr;
const GPIO gpio_rot_a;
@@ -213,19 +213,19 @@ private:
uint8_t io_reg { 0x03 };
void lcd_rd_assert() {
gpio_lcd_rd.set();
gpio_lcd_rdx.clear();
}
void lcd_rd_deassert() {
gpio_lcd_rd.clear();
gpio_lcd_rdx.set();
}
void lcd_wr_assert() {
gpio_lcd_wr.set();
gpio_lcd_wrx.clear();
}
void lcd_wr_deassert() {
gpio_lcd_wr.clear();
gpio_lcd_wrx.set();
}
void io_stb_assert() {