mirror of
https://github.com/portapack-mayhem/mayhem-firmware.git
synced 2024-12-13 19:54:39 +00:00
removed need for cpld mode setup for QFP100
This commit is contained in:
parent
9b263def37
commit
75718c79b9
@ -489,12 +489,20 @@ bool init() {
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chThdSleepMilliseconds(10);
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chThdSleepMilliseconds(10);
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if( !portapack::cpld::update_if_necessary(portapack_cpld_config()) ) {
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auto pp_config = portapack_cpld_config();
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chThdSleepMilliseconds(10);
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auto cpld_update_possible = portapack::cpld::update_possible(); //QFP100 CPLD fails this check. skip CPLD update
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// If using a "2021/12 QFP100", press and hold the left button while booting. Should only need to do once.
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auto cpld_update_necessary = cpld_update_possible && portapack::cpld::update_necessary(pp_config);
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if (load_config() != 3 && load_config() != 4){
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if ( cpld_update_necessary ) {
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shutdown_base();
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auto ok = portapack::cpld::update(pp_config);
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return false;
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if( !ok ) {
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chThdSleepMilliseconds(10);
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// Mode left (R1) and right (R2,H2,H2+) bypass going into hackrf mode after failing CPLD update
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// Mode center (autodetect), up (R1) and down (R2,H2,H2) will go into hackrf mode after failing CPLD update
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if (load_config() != 3 /* left */ && load_config() != 4 /* right */){
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shutdown_base();
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return false;
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}
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}
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}
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}
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}
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@ -33,9 +33,7 @@
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namespace portapack {
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namespace portapack {
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namespace cpld {
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namespace cpld {
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bool update_if_necessary(
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bool update_possible() {
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const Config config
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) {
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jtag::GPIOTarget target {
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jtag::GPIOTarget target {
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portapack::gpio_cpld_tck,
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portapack::gpio_cpld_tck,
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portapack::gpio_cpld_tms,
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portapack::gpio_cpld_tms,
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@ -65,13 +63,40 @@ bool update_if_necessary(
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return false;
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return false;
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}
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}
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return true;
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}
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bool update_necessary(
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const Config config
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) {
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jtag::GPIOTarget target {
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portapack::gpio_cpld_tck,
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portapack::gpio_cpld_tms,
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portapack::gpio_cpld_tdi,
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portapack::gpio_cpld_tdo
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};
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jtag::JTAG jtag { target };
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CPLD cpld { jtag };
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/* Verify CPLD contents against current bitstream. */
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/* Verify CPLD contents against current bitstream. */
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auto ok = cpld.verify(config.block_0, config.block_1);
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auto ok = cpld.verify(config.block_0, config.block_1);
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return !ok;
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}
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bool update(
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const Config config
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) {
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jtag::GPIOTarget target {
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portapack::gpio_cpld_tck,
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portapack::gpio_cpld_tms,
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portapack::gpio_cpld_tdi,
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portapack::gpio_cpld_tdo
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};
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jtag::JTAG jtag { target };
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CPLD cpld { jtag };
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/* CPLD verifies incorrectly. Erase and program with current bitstream. */
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/* CPLD verifies incorrectly. Erase and program with current bitstream. */
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if( !ok ) {
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auto ok = cpld.program(config.block_0, config.block_1);
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ok = cpld.program(config.block_0, config.block_1);
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}
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/* If programming OK, reset CPLD to user mode. Otherwise leave it in
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/* If programming OK, reset CPLD to user mode. Otherwise leave it in
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* passive (ISP) state.
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* passive (ISP) state.
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@ -27,7 +27,13 @@
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namespace portapack {
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namespace portapack {
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namespace cpld {
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namespace cpld {
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bool update_if_necessary(
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bool update_possible();
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bool update_necessary(
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const Config config
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);
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bool update(
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const Config config
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const Config config
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);
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);
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