TheArchive/mayhem-firmware
1
0
Fork 0
mirror of https://github.com/portapack-mayhem/mayhem-firmware.git synced 2025-08-13 21:29:56 +00:00
Code Issues Packages Projects Releases Wiki Activity

Adding Rx IQ error phase CAL to SPEC Audio_App (#1963)

Browse Source
This commit is contained in:
Brumi-2021
2024-03-09 23:46:38 +01:00
committed by GitHub
parent 73c29f666f
commit 9d8132978f
9 changed files with 125 additions and 17 deletions
Download Patch File Download Diff File Expand all files Collapse all files

33
firmware/application/hw/max2837.cpp
View File

@@ -150,7 +150,7 @@ void MAX2837::init() {
}
void MAX2837::set_tx_LO_iq_phase_calibration(const size_t v) {
/* IQ phase deg CAL adj (+4 ...-4) in 32 steps (5 bits), 00000 = +4deg (Q lags I by 94degs, default), 01111 = +0deg, 11111 = -4deg (Q lags I by 86degs) */
/* TX IQ phase deg CAL adj (+4 ...-4) in 32 steps (5 bits), 00000 = +4deg (Q lags I by 94degs, default), 01111 = +0deg, 11111 = -4deg (Q lags I by 86degs) */
// TX calibration , Logic pins , ENABLE, RXENABLE, TXENABLE = 1,0,1 (5dec), and Reg address 16, D1 (CAL mode 1):DO (CHIP ENABLE 1)
set_mode(Mode::Tx_Calibration); // write to ram 3 LOGIC Pins .
@@ -324,14 +324,41 @@ bool MAX2837::set_frequency(const rf::Frequency lo_frequency) {
return true;
}
void MAX2837::set_rx_lo_iq_calibration(const size_t v) {
/*
void MAX2837::set_rx_lo_iq_calibration(const size_t v) { // Original code , rewritten below
_map.r.rx_top_rx_bias.RX_IQERR_SPI_EN = 1;
_dirty[Register::RX_TOP_RX_BIAS] = 1;
_map.r.rxrf_2.iqerr_trim = v;
_dirty[Register::RXRF_2] = 1;
flush();
}
*/
void MAX2837::set_rx_LO_iq_phase_calibration(const size_t v) {
/* RX IQ phase deg CAL adj (+4 ...-4) in 32 steps (5 bits), 00000 = +4deg (Q lags I by 94degs, default), 01111 = +0deg, 11111 = -4deg (Q lags I by 86degs) */
// RX calibration , Logic pins , ENABLE, RXENABLE, TXENABLE = 1,1,0 (3dec), and Reg address 16, D1 (CAL mode 1):DO (CHIP ENABLE 1)
set_mode(Mode::Rx_Calibration); // write to ram 3 LOGIC Pins .
gpio_max283x_enable.output();
gpio_max2837_rxenable.output();
gpio_max2837_txenable.output();
_map.r.spi_en.CAL_SPI = 1; // Register Settings reg address 16, D1 (CAL mode 1)
_map.r.spi_en.EN_SPI = 1; // Register Settings reg address 16, DO (CHIP ENABLE 1)
flush_one(Register::SPI_EN);
_map.r.rx_top_rx_bias.RX_IQERR_SPI_EN = 1; // reg 8 D9, RX LO IQ Phase calibration SPI control. Active when Address 8 D<9> = 1.
flush_one(Register::RX_TOP_RX_BIAS);
_map.r.rxrf_2.iqerr_trim = v; // reg 1 D9:D5, RX LO I/Q Phase SPI 5 bits Adjust
flush_one(Register::RXRF_2);
// Exit Calibration mode, Go back to reg 16, D1:D0 , Out of CALIBRATION , back to default conditions, but keep CS activated.
_map.r.spi_en.CAL_SPI = 0; // Register Settings reg address 16, D1 (0 = Normal operation (default)
_map.r.spi_en.EN_SPI = 1; // Register Settings reg address 16, DO (1 = Chip select enable )
flush_one(Register::SPI_EN);
}
void MAX2837::set_rx_bias_trim(const size_t v) {
_map.r.rx_top_rx_bias.EN_Bias_Trim = 1;

2
firmware/application/hw/max2837.hpp
View File

@@ -828,7 +828,7 @@ class MAX2837 : public MAX283x {
bool set_frequency(const rf::Frequency lo_frequency) override;
void set_rx_lo_iq_calibration(const size_t v) override;
void set_rx_LO_iq_phase_calibration(const size_t v) override;
void set_tx_LO_iq_phase_calibration(const size_t v) override;
void set_rx_bias_trim(const size_t v);
void set_vco_bias(const size_t v);

29
firmware/application/hw/max2839.cpp
View File

@@ -367,13 +367,38 @@ bool MAX2839::set_frequency(const rf::Frequency lo_frequency) {
return true;
}
void MAX2839::set_rx_lo_iq_calibration(const size_t v) {
/*
void MAX2839::set_rx_LO_iq_phase_calibration(const size_t v) { // Original code , rewritten below
_map.r.rxrf_2.RX_IQERR_SPI_EN = 1;
_dirty[Register::RXRF_2] = 1;
_map.r.rxrf_1.iqerr_trim = v;
_dirty[Register::RXRF_1] = 1;
flush();
}*/
void MAX2839::set_rx_LO_iq_phase_calibration(const size_t v) {
/* RX IQ phase deg CAL adj (+4 ...-4) in 64 steps (6 bits), 000000 = +4deg (Q lags I by 94degs, default), 011111 = +0deg, 111111 = -4deg (Q lags I by 86degs) */
// RX calibration , Logic pins , ENABLE, RXENABLE, TXENABLE = 1,1,0 (3dec), and Reg address 16, D1 (CAL mode 1):DO (CHIP ENABLE 1)
set_mode(Mode::Rx_Calibration); // write to ram 3 LOGIC Pins .
gpio_max283x_enable.output(); // max2839 has only 2 x pins + regs to decide mode.
gpio_max2839_rxtx.output(); // Here is combined rx & tx pin in one port.
_map.r.spi_en.CAL_SPI = 1; // Register Settings reg address 16, D1 (CAL mode 1)
_map.r.spi_en.EN_SPI = 1; // Register Settings reg address 16, DO (CHIP ENABLE 1)
flush_one(Register::SPI_EN);
_map.r.rxrf_2.RX_IQERR_SPI_EN = 1; // reg 2 D<2> = 1, RX LO IQ calibration SPI control. Active when Address 2 D<2> = 1.
_dirty[Register::RXRF_2] = 1;
_map.r.rxrf_1.iqerr_trim = v;
_dirty[Register::RXRF_1] = 1;
flush();
_map.r.spi_en.CAL_SPI = 0; // Register Settings reg address 16, D1 (CAL mode 1)
_map.r.spi_en.EN_SPI = 1; // Register Settings reg address 16, DO (CHIP ENABLE 1)
flush_one(Register::SPI_EN);
}
void MAX2839::set_rx_buff_vcm(const size_t v) {

8
firmware/application/hw/max2839.hpp
View File

@@ -82,11 +82,11 @@ struct RXENABLE_Type {
static_assert(sizeof(RXENABLE_Type) == sizeof(reg_t), "RXENABLE_Type wrong size");
struct RXRF_1_Type {
reg_t LNAband : 1;
reg_t LNAband : 2; // Datasheet says D1:D0 , 2 bits, maybe D1 Rx_B, D0 Rx_A , (original code said wrongly ,reg_t LNAband : 1; that was of for max2837, not max2839 )
reg_t RESERVED0 : 1;
reg_t MIMOmode : 1;
reg_t iqerr_trim : 5;
reg_t RESERVED1 : 6;
reg_t iqerr_trim : 6; // Datasheet says D9_D4 , that means 6 bits, (original code said wrongly ,reg_t iqerr_trim : 5; )
reg_t RESERVED1 : 6; // we are using 16 bits , even top part mapping is not used
};
static_assert(sizeof(RXRF_1_Type) == sizeof(reg_t), "RXRF_1_Type wrong size");
@@ -689,7 +689,7 @@ class MAX2839 : public MAX283x {
void set_lpf_rf_bandwidth_rx(const uint32_t bandwidth_minimum) override;
void set_lpf_rf_bandwidth_tx(const uint32_t bandwidth_minimum) override;
bool set_frequency(const rf::Frequency lo_frequency) override;
void set_rx_lo_iq_calibration(const size_t v) override;
void set_rx_LO_iq_phase_calibration(const size_t v) override;
void set_tx_LO_iq_phase_calibration(const size_t v) override;
void set_rx_buff_vcm(const size_t v) override;

2
firmware/application/hw/max283x.hpp
View File

@@ -125,7 +125,7 @@ class MAX283x {
virtual bool set_frequency(const rf::Frequency lo_frequency);
virtual void set_rx_lo_iq_calibration(const size_t v);
virtual void set_rx_LO_iq_phase_calibration(const size_t v);
virtual void set_tx_LO_iq_phase_calibration(const size_t v);
virtual void set_rx_buff_vcm(const size_t v);