diff --git a/hardware/portapack_h4m/CPLD/.gitignore b/hardware/portapack_h4m/CPLD/.gitignore
new file mode 100644
index 00000000..8399f17b
--- /dev/null
+++ b/hardware/portapack_h4m/CPLD/.gitignore
@@ -0,0 +1,14 @@
+**/*.qws
+**/*.chg
+**/smart.log
+**/db/
+**/incremental_db/
+**/output_files/*.done
+**/output_files/*.smsg
+**/output_files/*.summary
+**/output_files/*.jdi
+**/output_files/*.pin
+**/output_files/*.pof
+**/output_files/*.rpt
+**/output_files/*.sld
+**/simulation/
diff --git a/hardware/portapack_h4m/CPLD/AG256SL100/Makefile b/hardware/portapack_h4m/CPLD/AG256SL100/Makefile
new file mode 100644
index 00000000..749e23b3
--- /dev/null
+++ b/hardware/portapack_h4m/CPLD/AG256SL100/Makefile
@@ -0,0 +1,109 @@
+#
+# Copyright (C) 2017 Jared Boone, ShareBrained Technology, Inc.
+# Copyright (C) 2024 jLynx.net https://github.com/jLynx
+#
+# This file is part of PortaPack.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2, or (at your option)
+# any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; see the file COPYING.  If not, write to
+# the Free Software Foundation, Inc., 51 Franklin Street,
+# Boston, MA 02110-1301, USA.
+
+# Makefile based on Altera Quartus documentation example, topic
+# "About Using Quartus II from the Command Line"
+
+###################################################################
+# Project Configuration: 
+# 
+# Specify the name of the design (project) and Quartus II Settings 
+# File (.qsf) and the list of source files used.
+###################################################################
+
+PROJECT=portapack_h4m_cpld
+SOURCE_FILES=top.vhd
+ASSIGNMENT_FILES=$(PROJECT).qpf $(PROJECT).qsf $(PROJECT).sdc
+OUTPUT_DIR=output_files
+
+###################################################################
+# Main Targets
+#
+# all: build everything
+# clean: remove output files and database
+###################################################################
+
+all: smart.log $(OUTPUT_DIR)/$(PROJECT).asm.rpt $(OUTPUT_DIR)/$(PROJECT).sta.rpt
+
+clean:
+	rm -rf *.chg *.qws smart.log db/ incremental_db/ $(OUTPUT_DIR)/
+
+map: smart.log $(OUTPUT_DIR)/$(PROJECT).map.rpt
+
+fit: smart.log $(OUTPUT_DIR)/$(PROJECT).fit.rpt
+
+asm: smart.log $(OUTPUT_DIR)/$(PROJECT).asm.rpt
+
+sta: smart.log $(OUTPUT_DIR)/$(PROJECT).sta.rpt
+
+smart: smart.log
+
+###################################################################
+# Executable Configuration
+###################################################################
+
+MAP_ARGS=
+FIT_ARGS=
+ASM_ARGS=
+STA_ARGS=
+
+###################################################################
+# Target implementations
+###################################################################
+
+STAMP = echo done >
+
+$(OUTPUT_DIR)/$(PROJECT).map.rpt: $(SOURCE_FILES)
+	quartus_map $(MAP_ARGS) $(PROJECT)
+	$(STAMP) fit.chg
+
+$(OUTPUT_DIR)/$(PROJECT).fit.rpt: fit.chg $(OUTPUT_DIR)/$(PROJECT).map.rpt
+	quartus_fit $(FIT_ARGS) $(PROJECT)
+	$(STAMP) asm.chg
+	$(STAMP) sta.chg
+
+$(OUTPUT_DIR)/$(PROJECT).asm.rpt: asm.chg $(OUTPUT_DIR)/$(PROJECT).fit.rpt
+	quartus_asm $(ASM_ARGS) $(PROJECT)
+
+$(OUTPUT_DIR)/$(PROJECT).sta.rpt: sta.chg $(OUTPUT_DIR)/$(PROJECT).fit.rpt
+	quartus_sta $(STA_ARGS) $(PROJECT)
+
+smart.log: $(ASSIGNMENT_FILES) $(OUTPUT_DIR)
+	quartus_sh --determine_smart_action $(PROJECT) > smart.log
+
+###################################################################
+# Project initialization
+###################################################################
+
+$(OUTPUT_DIR):
+	mkdir $(OUTPUT_DIR)
+
+$(ASSIGNMENT_FILES): $(OUTPUT_DIR)
+	quartus_sh --prepare $(PROJECT)
+
+fit.chg:
+	$(STAMP) fit.chg
+
+sta.chg:
+	$(STAMP) sta.chg
+
+asm.chg:
+	$(STAMP) asm.chg
diff --git a/hardware/portapack_h4m/CPLD/AG256SL100/output_files/portapack_h4m_cpld.svf b/hardware/portapack_h4m/CPLD/AG256SL100/output_files/portapack_h4m_cpld.svf
new file mode 100644
index 00000000..f61e6a6e
--- /dev/null
+++ b/hardware/portapack_h4m/CPLD/AG256SL100/output_files/portapack_h4m_cpld.svf
@@ -0,0 +1,11651 @@
+!Copyright (C) 2023  Intel Corporation. All rights reserved.
+!Your use of Intel Corporation's design tools, logic functions 
+!and other software and tools, and any partner logic 
+!functions, and any output files from any of the foregoing 
+!(including device programming or simulation files), and any 
+!associated documentation or information are expressly subject 
+!to the terms and conditions of the Intel Program License 
+!Subscription Agreement, the Intel Quartus Prime License Agreement,
+!the Intel FPGA IP License Agreement, or other applicable license
+!agreement, including, without limitation, that your use is for
+!the sole purpose of programming logic devices manufactured by
+!Intel and sold by Intel or its authorized distributors.  Please
+!refer to the applicable agreement for further details, at
+!https://fpgasoftware.intel.com/eula.
+!
+!Quartus Prime SVF converter 22.1
+!
+!Device #1: EPM240 - A:/Users/jLynx/Documents/Code/C/portapack-mayhem/hardware/portapack_h4m/CPLD/AG256SL100/output_files/portapack_h4m_cpld.pof Sun Nov  3 11:15:25 2024
+!
+!NOTE "USERCODE" "0018A481";
+!
+!NOTE "CHECKSUM" "0018A981";
+!
+!
+!
+FREQUENCY 1.80E+07 HZ;
+!
+!
+!
+TRST ABSENT;
+ENDDR IDLE;
+ENDIR IRPAUSE;
+STATE IDLE;
+SIR 10 TDI (005);
+RUNTEST IDLE 93 TCK ENDSTATE IDLE;
+SDR 240 TDI (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF);
+SIR 10 TDI (3FF);
+RUNTEST 18003 TCK;
+SIR 10 TDI (2CC);
+RUNTEST 18003 TCK;
+!
+!
+!
+!CHECKING SILICON ID
+!
+!
+!
+SIR 10 TDI (203);
+RUNTEST 93 TCK;
+SDR 13 TDI (0089);
+SIR 10 TDI (205);
+RUNTEST 93 TCK;
+SDR 16 TDI (FFFF) TDO (8232) MASK (FFFF);
+SDR 16 TDI (FFFF) TDO (2AA2);
+SDR 16 TDI (FFFF) TDO (4A82);
+SDR 16 TDI (FFFF) TDO (0C2C);
+SDR 16 TDI (FFFF) TDO (0000);
+!
+!
+!
+!BULK ERASE
+!
+!
+!
+SIR 10 TDI (203);
+RUNTEST 93 TCK;
+SDR 13 TDI (0011);
+SIR 10 TDI (2F2);
+RUNTEST 9000003 TCK;
+SIR 10 TDI (203);
+RUNTEST 93 TCK;
+SDR 13 TDI (0001);
+SIR 10 TDI (2F2);
+RUNTEST 9000003 TCK;
+SIR 10 TDI (203);
+RUNTEST 93 TCK;
+SDR 13 TDI (0000);
+SIR 10 TDI (2F2);
+RUNTEST 9000003 TCK;
+!
+!
+!
+!PROGRAM
+!
+!
+!
+SIR 10 TDI (203);
+RUNTEST 93 TCK;
+SDR 13 TDI (0000);
+SIR 10 TDI (2F4);
+RUNTEST 93 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFC);
+RUNTEST 1800 TCK;
+SDR 16 TDI (F9FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (79FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFE);
+RUNTEST 1800 TCK;
+SDR 16 TDI (AF9E);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7EFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FBF7);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BBF7);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7F3E);
+RUNTEST 1800 TCK;
+SDR 16 TDI (79F3);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFF7);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFE);
+RUNTEST 1800 TCK;
+SDR 16 TDI (67FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (F7FE);
+RUNTEST 1800 TCK;
+SDR 16 TDI (6FEF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FF7F);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFDD);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FBF9);
+RUNTEST 1800 TCK;
+SDR 16 TDI (733F);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FF19);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B33F);
+RUNTEST 1800 TCK;
+SDR 16 TDI (CCCF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (999F);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BCCC);
+RUNTEST 1800 TCK;
+SDR 16 TDI (CFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FEEF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFD);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFF7);
+RUNTEST 1800 TCK;
+SDR 16 TDI (6FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (6EBF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (EFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (77FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FEFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FF3);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (F6FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FBF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FEFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFF7);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (6FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFDB);
+RUNTEST 1800 TCK;
+SDR 16 TDI (EFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (6FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (EFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFEF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFE);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7EFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (EFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (6FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FE6F);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FF7);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFF7);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FF6);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FB7);
+RUNTEST 1800 TCK;
+SDR 16 TDI (EFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFD);
+RUNTEST 1800 TCK;
+SDR 16 TDI (F7FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (EFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFE);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FDBF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FEF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFB);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FCF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (EFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFEF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFD);
+RUNTEST 1800 TCK;
+SDR 16 TDI (67FA);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (6FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFE);
+RUNTEST 1800 TCK;
+SDR 16 TDI (EFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BF7F);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FEFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFB);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFEF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (77FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFEF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (6FFE);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (EFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (EEFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BDFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B7FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (6FEF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BCFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FF7F);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFDF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (EFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FDFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BBFD);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFB);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (DFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (EFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFDF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (77FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (EFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFDF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFF7);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (EFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (A65F);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFE);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (AFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFEB);
+RUNTEST 1800 TCK;
+SDR 16 TDI (77FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (A65F);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFE);
+RUNTEST 1800 TCK;
+SDR 16 TDI (77FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (AFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (F7FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFF5);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BBFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7EFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7F7F);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BDFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFF5);
+RUNTEST 1800 TCK;
+SDR 16 TDI (6FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FBFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BBAF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (CFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FDF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFEF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B7FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7BFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BAFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (CFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7EFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFDF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFE);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (AFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFEB);
+RUNTEST 1800 TCK;
+SDR 16 TDI (67FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFAF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (CFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFEF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (CFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFB7);
+RUNTEST 1800 TCK;
+SDR 16 TDI (77FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BAF7);
+RUNTEST 1800 TCK;
+SDR 16 TDI (3B33);
+RUNTEST 1800 TCK;
+SDR 16 TDI (63E6);
+RUNTEST 1800 TCK;
+SDR 16 TDI (6667);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B333);
+RUNTEST 1800 TCK;
+SDR 16 TDI (31F3);
+RUNTEST 1800 TCK;
+SDR 16 TDI (6666);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7CCC);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B98F);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9999);
+RUNTEST 1800 TCK;
+SDR 16 TDI (73CC);
+RUNTEST 1800 TCK;
+SDR 16 TDI (CCC7);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B999);
+RUNTEST 1800 TCK;
+SDR 16 TDI (99E8);
+RUNTEST 1800 TCK;
+SDR 16 TDI (77FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7377);
+RUNTEST 1800 TCK;
+SDR 16 TDI (6957);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7777);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B777);
+RUNTEST 1800 TCK;
+SDR 16 TDI (74AB);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7777);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7DDD);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BBA5);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5DDD);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7BDD);
+RUNTEST 1800 TCK;
+SDR 16 TDI (DDD2);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B5DD);
+RUNTEST 1800 TCK;
+SDR 16 TDI (DDBF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (77FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFE7);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FDF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFEF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B7FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFED);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (77FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (AFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFB);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFE);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFB);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFEF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (EFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7BFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7DFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7BFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (AFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BBFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (6FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFD);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFA);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (DFF7);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (F7FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (77FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (EFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFD);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFD);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (EFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BBFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FEF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BDFD);
+RUNTEST 1800 TCK;
+SDR 16 TDI (DEF7);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFB);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B7FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFF5);
+RUNTEST 1800 TCK;
+SDR 16 TDI (6BFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFD);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (F7FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BDFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7BDF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (F7FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFEF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FB7F);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BF7F);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FF7);
+RUNTEST 1800 TCK;
+SDR 16 TDI (DBFD);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B3FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7DFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFCF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (6FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFBF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFB);
+RUNTEST 1800 TCK;
+SDR 16 TDI (77FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (AFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FBFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BCBF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7BFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFDF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FEF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FD7E);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFB);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FF7);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFDE);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7EFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BF7F);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFF7);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFBF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BBFD);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B5FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FCFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7BFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFD7);
+RUNTEST 1800 TCK;
+SDR 16 TDI (6FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FF7F);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFF7);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (F7FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFB);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BDFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FEFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7DFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFEA);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B6AF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (6FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFF7);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFD);
+RUNTEST 1800 TCK;
+SDR 16 TDI (AFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FDFD);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7BFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (77FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFAF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7F7F);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFBF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (AFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFE);
+RUNTEST 1800 TCK;
+SDR 16 TDI (77FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B5FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FEFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFEB);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (77F7);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FD7B);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7EFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFF5);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFF5);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (6FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FF7F);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BBFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (77FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7EFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFF7);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFF7);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FF7F);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FBFC);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BDFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FE3F);
+RUNTEST 1800 TCK;
+SDR 16 TDI (6FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFB);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (6FEF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFF6);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BBFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FF7F);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7CFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFEC);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFEF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (F7FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFF9);
+RUNTEST 1800 TCK;
+SDR 16 TDI (A5FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FCFB);
+RUNTEST 1800 TCK;
+SDR 16 TDI (73FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B7AF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFBC);
+RUNTEST 1800 TCK;
+SDR 16 TDI (67DF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFEF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFC3);
+RUNTEST 1800 TCK;
+SDR 16 TDI (C3EF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (67E6);
+RUNTEST 1800 TCK;
+SDR 16 TDI (1FFA);
+RUNTEST 1800 TCK;
+SDR 16 TDI (ABFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (79FB);
+RUNTEST 1800 TCK;
+SDR 16 TDI (73FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B7FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFF7);
+RUNTEST 1800 TCK;
+SDR 16 TDI (67FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFAF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFBC);
+RUNTEST 1800 TCK;
+SDR 16 TDI (67FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFEF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFC3);
+RUNTEST 1800 TCK;
+SDR 16 TDI (C3FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (67E6);
+RUNTEST 1800 TCK;
+SDR 16 TDI (1FFA);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B9FE);
+RUNTEST 1800 TCK;
+SDR 16 TDI (F9FB);
+RUNTEST 1800 TCK;
+SDR 16 TDI (73FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (AFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7DFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BAFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FD3C);
+RUNTEST 1800 TCK;
+SDR 16 TDI (67FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFE5);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFC3);
+RUNTEST 1800 TCK;
+SDR 16 TDI (C3FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (67E6);
+RUNTEST 1800 TCK;
+SDR 16 TDI (1FF9);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B9FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (F9F9);
+RUNTEST 1800 TCK;
+SDR 16 TDI (63FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFF3);
+RUNTEST 1800 TCK;
+SDR 16 TDI (6BFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B7F7);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FD3C);
+RUNTEST 1800 TCK;
+SDR 16 TDI (67FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFE5);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFC3);
+RUNTEST 1800 TCK;
+SDR 16 TDI (C3FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (67E6);
+RUNTEST 1800 TCK;
+SDR 16 TDI (1FF3);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B9FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FB79);
+RUNTEST 1800 TCK;
+SDR 16 TDI (66FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BA8F);
+RUNTEST 1800 TCK;
+SDR 16 TDI (3133);
+RUNTEST 1800 TCK;
+SDR 16 TDI (73E6);
+RUNTEST 1800 TCK;
+SDR 16 TDI (6665);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B33B);
+RUNTEST 1800 TCK;
+SDR 16 TDI (3973);
+RUNTEST 1800 TCK;
+SDR 16 TDI (6E66);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FCCC);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B98F);
+RUNTEST 1800 TCK;
+SDR 16 TDI (989B);
+RUNTEST 1800 TCK;
+SDR 16 TDI (63CC);
+RUNTEST 1800 TCK;
+SDR 16 TDI (CCC7);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B999);
+RUNTEST 1800 TCK;
+SDR 16 TDI (99CA);
+RUNTEST 1800 TCK;
+SDR 16 TDI (77FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BBFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7637);
+RUNTEST 1800 TCK;
+SDR 16 TDI (6557);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7763);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B773);
+RUNTEST 1800 TCK;
+SDR 16 TDI (72AB);
+RUNTEST 1800 TCK;
+SDR 16 TDI (6766);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7DD9);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B3B5);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5DD8);
+RUNTEST 1800 TCK;
+SDR 16 TDI (79DD);
+RUNTEST 1800 TCK;
+SDR 16 TDI (DDD2);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B5DD);
+RUNTEST 1800 TCK;
+SDR 16 TDI (DDDF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFEB);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FDFD);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FDF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFD);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFDF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (DFEF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (DFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (6FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B7FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFA);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFF7);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFE);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FBF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BF7F);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B7FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFDD);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFBF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FBFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BEEF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (6BFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFB);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B7FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFED);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFBF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFE);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BBFB);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFE);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFEF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FBF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFAF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (EFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (DFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFE);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FBB);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFE);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (EFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (EFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BDFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (DEFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (DFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFD);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FEF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7F77);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFF7);
+RUNTEST 1800 TCK;
+SDR 16 TDI (6FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (EFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BEFA);
+RUNTEST 1800 TCK;
+SDR 16 TDI (F9FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFDF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FBFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (AAFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FEF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFDF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (F6FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BBEF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFD);
+RUNTEST 1800 TCK;
+SDR 16 TDI (F7FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FF7);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (DFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (F7FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FD7F);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BEF7);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FEFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFEF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FDFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BDFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFF7);
+RUNTEST 1800 TCK;
+SDR 16 TDI (D7FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFBF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FDBF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFF7);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFBF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7BFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (E7FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BF5D);
+RUNTEST 1800 TCK;
+SDR 16 TDI (DBFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7BFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B7FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFB);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FEDF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BBFE);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFB);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFBF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FF7F);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7BFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B7FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFB7);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFD);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (DB7F);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BEFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B5FD);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFDF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFEF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (77FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FDFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BDCD);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BBFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FF3F);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (D8DF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BBB2);
+RUNTEST 1800 TCK;
+SDR 16 TDI (DEFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FDFB);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (F7FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BE4D);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7DEA);
+RUNTEST 1800 TCK;
+SDR 16 TDI (77FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFF7);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFBB);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFB);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7BFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (AFAF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BDFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (ABFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B6AF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFF3);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FDF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFE1);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFEF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BE1F);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FF9);
+RUNTEST 1800 TCK;
+SDR 16 TDI (70FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (E0EF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B027);
+RUNTEST 1800 TCK;
+SDR 16 TDI (3BF5);
+RUNTEST 1800 TCK;
+SDR 16 TDI (6BFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FF33);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FBF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFE1);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFDF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BE1F);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFF9);
+RUNTEST 1800 TCK;
+SDR 16 TDI (70FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (E4EF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (A8B9);
+RUNTEST 1800 TCK;
+SDR 16 TDI (3BFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7DFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B5AF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FCF3);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFE1);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BE1F);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFF9);
+RUNTEST 1800 TCK;
+SDR 16 TDI (70FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (1F4F);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFCF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9475);
+RUNTEST 1800 TCK;
+SDR 16 TDI (6BFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BBFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FC33);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFE1);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BE1F);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFF9);
+RUNTEST 1800 TCK;
+SDR 16 TDI (70FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (174F);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BEC8);
+RUNTEST 1800 TCK;
+SDR 16 TDI (1477);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BABF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (31B3);
+RUNTEST 1800 TCK;
+SDR 16 TDI (62E6);
+RUNTEST 1800 TCK;
+SDR 16 TDI (6667);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B333);
+RUNTEST 1800 TCK;
+SDR 16 TDI (31F3);
+RUNTEST 1800 TCK;
+SDR 16 TDI (6666);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7CCC);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B9CB);
+RUNTEST 1800 TCK;
+SDR 16 TDI (999B);
+RUNTEST 1800 TCK;
+SDR 16 TDI (73CC);
+RUNTEST 1800 TCK;
+SDR 16 TDI (6C67);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B998);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B37A);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B7FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7633);
+RUNTEST 1800 TCK;
+SDR 16 TDI (6D57);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7767);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B777);
+RUNTEST 1800 TCK;
+SDR 16 TDI (74AB);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7777);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7DDD);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BB95);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5DD9);
+RUNTEST 1800 TCK;
+SDR 16 TDI (73DD);
+RUNTEST 1800 TCK;
+SDR 16 TDI (C9CA);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B4CD);
+RUNTEST 1800 TCK;
+SDR 16 TDI (99FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FDFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FDF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFD);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFEF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BEFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7EFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (6F6F);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B7FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B36F);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFD);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFB);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFE);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FBFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (DFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7DBF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (AFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (F7FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FEF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFEF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BBFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFF7);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFD);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFB);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BEBF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FDFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFDD);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FDFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (6FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFE);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFA);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (EFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7BFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BF7F);
+RUNTEST 1800 TCK;
+SDR 16 TDI (F7FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FEF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FDFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BDFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FDFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BBFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFE);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FBFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FBF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B7DF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFDF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFDB);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BBFB);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (EFDF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FDF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (F7FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (6FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFAF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (77FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FEFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (EFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFCF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BF5F);
+RUNTEST 1800 TCK;
+SDR 16 TDI (F7EB);
+RUNTEST 1800 TCK;
+SDR 16 TDI (77FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFD);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FDFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (F7FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FBF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (6FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFD7);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFE);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFEF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (EFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FF7);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (EF7F);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFDF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FF6F);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (77FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFF7);
+RUNTEST 1800 TCK;
+SDR 16 TDI (DFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFDF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7BFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFDF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FF6F);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FEEF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B9FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFF7);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFBF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFF5);
+RUNTEST 1800 TCK;
+SDR 16 TDI (6BFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFAF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FF7F);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFF7);
+RUNTEST 1800 TCK;
+SDR 16 TDI (DFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7BFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B9AF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FDDF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFF5);
+RUNTEST 1800 TCK;
+SDR 16 TDI (6DFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFD);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFB);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFEE);
+RUNTEST 1800 TCK;
+SDR 16 TDI (79FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BEFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFD);
+RUNTEST 1800 TCK;
+SDR 16 TDI (DFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7BFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFF7);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFD);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFB);
+RUNTEST 1800 TCK;
+SDR 16 TDI (77FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B5FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFEF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (DDDF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7BFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFEA);
+RUNTEST 1800 TCK;
+SDR 16 TDI (77FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FF7F);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFE);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFBF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFAC);
+RUNTEST 1800 TCK;
+SDR 16 TDI (3C3F);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7DDF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFE1);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFEF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFC);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BE1F);
+RUNTEST 1800 TCK;
+SDR 16 TDI (0781);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7CFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B7FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFF5);
+RUNTEST 1800 TCK;
+SDR 16 TDI (6BFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BDAC);
+RUNTEST 1800 TCK;
+SDR 16 TDI (3C3F);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FBF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFE1);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFDF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFC);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BE1B);
+RUNTEST 1800 TCK;
+SDR 16 TDI (8781);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7CFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (AFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BBFC);
+RUNTEST 1800 TCK;
+SDR 16 TDI (3C3F);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFE1);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFC);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BE0F);
+RUNTEST 1800 TCK;
+SDR 16 TDI (E001);
+RUNTEST 1800 TCK;
+SDR 16 TDI (70FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFF5);
+RUNTEST 1800 TCK;
+SDR 16 TDI (6BFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BBFC);
+RUNTEST 1800 TCK;
+SDR 16 TDI (3C3F);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFE1);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFC);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BE1F);
+RUNTEST 1800 TCK;
+SDR 16 TDI (E001);
+RUNTEST 1800 TCK;
+SDR 16 TDI (70FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BAA7);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B3B3);
+RUNTEST 1800 TCK;
+SDR 16 TDI (63E6);
+RUNTEST 1800 TCK;
+SDR 16 TDI (666F);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B333);
+RUNTEST 1800 TCK;
+SDR 16 TDI (31F3);
+RUNTEST 1800 TCK;
+SDR 16 TDI (6666);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7CCC);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B99F);
+RUNTEST 1800 TCK;
+SDR 16 TDI (8B9B);
+RUNTEST 1800 TCK;
+SDR 16 TDI (71CC);
+RUNTEST 1800 TCK;
+SDR 16 TDI (CCC7);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B999);
+RUNTEST 1800 TCK;
+SDR 16 TDI (99EE);
+RUNTEST 1800 TCK;
+SDR 16 TDI (77FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B7FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (3737);
+RUNTEST 1800 TCK;
+SDR 16 TDI (6D57);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7767);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B777);
+RUNTEST 1800 TCK;
+SDR 16 TDI (74AB);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7777);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7DDC);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BB95);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5999);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7BDD);
+RUNTEST 1800 TCK;
+SDR 16 TDI (DDD2);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B5DD);
+RUNTEST 1800 TCK;
+SDR 16 TDI (DDFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFF9);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FDFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FDF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFD);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFEF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BEFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (3FF7);
+RUNTEST 1800 TCK;
+SDR 16 TDI (77FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B7FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (AFEF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFBF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFD);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (F5FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FBF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FBFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BEFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (F7FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BDF6);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFBF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (EFEF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFBF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFBF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (EFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FBFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BF7F);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFB);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FDFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FBF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (F7EF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BBBB);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFB);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7BFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (EFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFBF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFD);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFEF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7DFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (EFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FBFB);
+RUNTEST 1800 TCK;
+SDR 16 TDI (77FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BEDB);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFBF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FF7);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (EFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFF7);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BD9F);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B9AF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFF5);
+RUNTEST 1800 TCK;
+SDR 16 TDI (6BFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BEAF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFF5);
+RUNTEST 1800 TCK;
+SDR 16 TDI (6BFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B7FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFEA);
+RUNTEST 1800 TCK;
+SDR 16 TDI (77FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BBBF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFB);
+RUNTEST 1800 TCK;
+SDR 16 TDI (77FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B56C);
+RUNTEST 1800 TCK;
+SDR 16 TDI (3FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7DDF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFEF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B7FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFF4);
+RUNTEST 1800 TCK;
+SDR 16 TDI (79FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFC);
+RUNTEST 1800 TCK;
+SDR 16 TDI (3FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FBF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFDF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFE);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (AFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (6DFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B66C);
+RUNTEST 1800 TCK;
+SDR 16 TDI (3FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFF5);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5BFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFC);
+RUNTEST 1800 TCK;
+SDR 16 TDI (3FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (6FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BEAF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B333);
+RUNTEST 1800 TCK;
+SDR 16 TDI (63E6);
+RUNTEST 1800 TCK;
+SDR 16 TDI (6667);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B333);
+RUNTEST 1800 TCK;
+SDR 16 TDI (31F3);
+RUNTEST 1800 TCK;
+SDR 16 TDI (4666);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7CCC);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B98F);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9999);
+RUNTEST 1800 TCK;
+SDR 16 TDI (73CC);
+RUNTEST 1800 TCK;
+SDR 16 TDI (CCC7);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B999);
+RUNTEST 1800 TCK;
+SDR 16 TDI (99FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (3777);
+RUNTEST 1800 TCK;
+SDR 16 TDI (6D57);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7777);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B777);
+RUNTEST 1800 TCK;
+SDR 16 TDI (74AB);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7777);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7DDD);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BBA5);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5DDD);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7BDD);
+RUNTEST 1800 TCK;
+SDR 16 TDI (DDD2);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B5DD);
+RUNTEST 1800 TCK;
+SDR 16 TDI (DDFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9FFD);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FDF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFEF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (97FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (4FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFB);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FBF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (8FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FFB);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5DFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (AFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5F7F);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7DFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (EFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (AFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (EFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (8FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (EFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (EFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (A55F);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFD);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7BFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (AFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (A55F);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFD);
+RUNTEST 1800 TCK;
+SDR 16 TDI (79FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (AAAF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFB);
+RUNTEST 1800 TCK;
+SDR 16 TDI (75FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9BBF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFEA);
+RUNTEST 1800 TCK;
+SDR 16 TDI (57FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (A65F);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FDF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFEF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B7FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFF5);
+RUNTEST 1800 TCK;
+SDR 16 TDI (69FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (AEFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FBF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFDF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFE);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (AFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7DFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (975F);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFF5);
+RUNTEST 1800 TCK;
+SDR 16 TDI (6BFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFB);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (3333);
+RUNTEST 1800 TCK;
+SDR 16 TDI (63E6);
+RUNTEST 1800 TCK;
+SDR 16 TDI (6667);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9333);
+RUNTEST 1800 TCK;
+SDR 16 TDI (31F3);
+RUNTEST 1800 TCK;
+SDR 16 TDI (6666);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7CCC);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B98F);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9999);
+RUNTEST 1800 TCK;
+SDR 16 TDI (73CC);
+RUNTEST 1800 TCK;
+SDR 16 TDI (CCC7);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B999);
+RUNTEST 1800 TCK;
+SDR 16 TDI (99FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7777);
+RUNTEST 1800 TCK;
+SDR 16 TDI (6957);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7777);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9777);
+RUNTEST 1800 TCK;
+SDR 16 TDI (74AB);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5777);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7DDD);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BBA5);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5DDD);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7BDD);
+RUNTEST 1800 TCK;
+SDR 16 TDI (DDD2);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B5DD);
+RUNTEST 1800 TCK;
+SDR 16 TDI (DDFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9FF7);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FDF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFEF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B7FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFEF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7DFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7DFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FF7);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (EFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FF7F);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (EFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FF7F);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FF7);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (EFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (EFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (B7FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (DFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (EFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BF7F);
+RUNTEST 1800 TCK;
+SDR 16 TDI (EFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FBFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9F7F);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FE7E);
+RUNTEST 1800 TCK;
+SDR 16 TDI (6FF3);
+RUNTEST 1800 TCK;
+SDR 16 TDI (3FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9FE6);
+RUNTEST 1800 TCK;
+SDR 16 TDI (67F9);
+RUNTEST 1800 TCK;
+SDR 16 TDI (53FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFF9);
+RUNTEST 1800 TCK;
+SDR 16 TDI (93FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (F7FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (999F);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BCCF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (F9FF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FF3);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFE);
+RUNTEST 1800 TCK;
+SDR 16 TDI (AF9E);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7CF9);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (F3E7);
+RUNTEST 1800 TCK;
+SDR 16 TDI (93E7);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5F3E);
+RUNTEST 1800 TCK;
+SDR 16 TDI (79F3);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9CFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (5FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (9FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (7FFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SIR 10 TDI (203);
+RUNTEST 93 TCK;
+SDR 13 TDI (0001);
+SIR 10 TDI (2F4);
+RUNTEST 93 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+!
+!
+!
+!VERIFY
+!
+!
+!
+SIR 10 TDI (203);
+RUNTEST 93 TCK;
+SDR 13 TDI (0000);
+SIR 10 TDI (205);
+RUNTEST 93 TCK;
+SDR 16 TDI (FFFF) TDO (7FFF) MASK (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFC);
+SDR 16 TDI (FFFF) TDO (F9FF);
+SDR 16 TDI (FFFF) TDO (79FF);
+SDR 16 TDI (FFFF) TDO (FFFE);
+SDR 16 TDI (FFFF) TDO (AF9E);
+SDR 16 TDI (FFFF) TDO (7EFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FBF7);
+SDR 16 TDI (FFFF) TDO (BBF7);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7F3E);
+SDR 16 TDI (FFFF) TDO (79F3);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFF7);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFE);
+SDR 16 TDI (FFFF) TDO (67FF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (F7FE);
+SDR 16 TDI (FFFF) TDO (6FEF);
+SDR 16 TDI (FFFF) TDO (FF7F);
+SDR 16 TDI (FFFF) TDO (BFDD);
+SDR 16 TDI (FFFF) TDO (FBF9);
+SDR 16 TDI (FFFF) TDO (733F);
+SDR 16 TDI (FFFF) TDO (FF19);
+SDR 16 TDI (FFFF) TDO (B33F);
+SDR 16 TDI (FFFF) TDO (CCCF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (999F);
+SDR 16 TDI (FFFF) TDO (BCCC);
+SDR 16 TDI (FFFF) TDO (CFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FEEF);
+SDR 16 TDI (FFFF) TDO (7FFD);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFF7);
+SDR 16 TDI (FFFF) TDO (6FFF);
+SDR 16 TDI (FFFF) TDO (6EBF);
+SDR 16 TDI (FFFF) TDO (EFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (77FF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FEFF);
+SDR 16 TDI (FFFF) TDO (7FF3);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (F6FF);
+SDR 16 TDI (FFFF) TDO (7FBF);
+SDR 16 TDI (FFFF) TDO (FEFF);
+SDR 16 TDI (FFFF) TDO (BFF7);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (6FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFDB);
+SDR 16 TDI (FFFF) TDO (EFFF);
+SDR 16 TDI (FFFF) TDO (6FFF);
+SDR 16 TDI (FFFF) TDO (EFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFEF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFE);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (7EFF);
+SDR 16 TDI (FFFF) TDO (EFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (6FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FE6F);
+SDR 16 TDI (FFFF) TDO (7FF7);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFF7);
+SDR 16 TDI (FFFF) TDO (5FF6);
+SDR 16 TDI (FFFF) TDO (7FB7);
+SDR 16 TDI (FFFF) TDO (EFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFD);
+SDR 16 TDI (FFFF) TDO (F7FF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (EFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFE);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FDBF);
+SDR 16 TDI (FFFF) TDO (7FEF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFB);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FCF);
+SDR 16 TDI (FFFF) TDO (EFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFEF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFD);
+SDR 16 TDI (FFFF) TDO (67FA);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (6FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFE);
+SDR 16 TDI (FFFF) TDO (EFFF);
+SDR 16 TDI (FFFF) TDO (BF7F);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FEFF);
+SDR 16 TDI (FFFF) TDO (BFFB);
+SDR 16 TDI (FFFF) TDO (FFEF);
+SDR 16 TDI (FFFF) TDO (77FF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFEF);
+SDR 16 TDI (FFFF) TDO (6FFE);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (EFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (EEFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BDFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (B7FF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (6FEF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (BCFF);
+SDR 16 TDI (FFFF) TDO (FF7F);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFDF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (EFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FDFF);
+SDR 16 TDI (FFFF) TDO (BBFD);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFB);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (DFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (EFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFDF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (77FF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (EFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFDF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFF7);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (EFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (A65F);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFE);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (AFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFEB);
+SDR 16 TDI (FFFF) TDO (77FF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (A65F);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFE);
+SDR 16 TDI (FFFF) TDO (77FF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (AFFF);
+SDR 16 TDI (FFFF) TDO (F7FF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFF5);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BBFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7EFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7F7F);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BDFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFF5);
+SDR 16 TDI (FFFF) TDO (6FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FBFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BBAF);
+SDR 16 TDI (FFFF) TDO (CFFF);
+SDR 16 TDI (FFFF) TDO (7FDF);
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+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (9FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (EFFF);
+SDR 16 TDI (FFFF) TDO (9FFF);
+SDR 16 TDI (FFFF) TDO (FF7F);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (9FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (EFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FF7F);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (5FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FF7);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (5FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (5FFF);
+SDR 16 TDI (FFFF) TDO (EFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (9FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (5FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (EFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (B7FF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (9FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (5FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (9FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (5FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (DFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (9FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (5FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (EFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (5FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BF7F);
+SDR 16 TDI (FFFF) TDO (EFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (9FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (5FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (9FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (5FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (9FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (9FFF);
+SDR 16 TDI (FFFF) TDO (FBFF);
+SDR 16 TDI (FFFF) TDO (5FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (9FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (9FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (5FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (9F7F);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (5FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (9FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FE7E);
+SDR 16 TDI (FFFF) TDO (6FF3);
+SDR 16 TDI (FFFF) TDO (3FFF);
+SDR 16 TDI (FFFF) TDO (9FE6);
+SDR 16 TDI (FFFF) TDO (67F9);
+SDR 16 TDI (FFFF) TDO (53FF);
+SDR 16 TDI (FFFF) TDO (FFF9);
+SDR 16 TDI (FFFF) TDO (93FF);
+SDR 16 TDI (FFFF) TDO (F7FF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (999F);
+SDR 16 TDI (FFFF) TDO (BCCF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (9FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (5FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (9FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (9FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (5FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (9FFF);
+SDR 16 TDI (FFFF) TDO (F9FF);
+SDR 16 TDI (FFFF) TDO (7FF3);
+SDR 16 TDI (FFFF) TDO (FFFE);
+SDR 16 TDI (FFFF) TDO (AF9E);
+SDR 16 TDI (FFFF) TDO (7CF9);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (F3E7);
+SDR 16 TDI (FFFF) TDO (93E7);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (5F3E);
+SDR 16 TDI (FFFF) TDO (79F3);
+SDR 16 TDI (FFFF) TDO (9CFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (9FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (5FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (9FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (7FFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (BFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SIR 10 TDI (203);
+RUNTEST 93 TCK;
+SDR 13 TDI (0001);
+SIR 10 TDI (205);
+RUNTEST 93 TCK;
+SDR 16 TDI (FFFF) TDO (FFFF) MASK (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
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+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
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+SDR 16 TDI (FFFF) TDO (FFFF);
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+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
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+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
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+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
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+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
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+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
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+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SDR 16 TDI (FFFF) TDO (FFFF);
+SIR 10 TDI (203);
+RUNTEST 93 TCK;
+SDR 13 TDI (0000);
+SIR 10 TDI (2F4);
+RUNTEST 93 TCK;
+SDR 16 TDI (7BFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (FFFF);
+RUNTEST 1800 TCK;
+SDR 16 TDI (BFFC);
+RUNTEST 1800 TCK;
+SDR 16 TDI (F9FF);
+RUNTEST 1800 TCK;
+SIR 10 TDI (201);
+RUNTEST 18003 TCK;
+SIR 10 TDI (3FF);
+RUNTEST 18000 TCK;
+STATE IDLE;
diff --git a/hardware/portapack_h4m/CPLD/AG256SL100/portapack_h4m_cpld.qpf b/hardware/portapack_h4m/CPLD/AG256SL100/portapack_h4m_cpld.qpf
new file mode 100644
index 00000000..2378c009
--- /dev/null
+++ b/hardware/portapack_h4m/CPLD/AG256SL100/portapack_h4m_cpld.qpf
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 32-bit
+# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
+# Date created = 21:24:55  April 29, 2014
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.1"
+DATE = "21:24:55  April 29, 2014"
+
+# Revisions
+
+PROJECT_REVISION = "portapack_h4m_cpld"
diff --git a/hardware/portapack_h4m/CPLD/AG256SL100/portapack_h4m_cpld.qsf b/hardware/portapack_h4m/CPLD/AG256SL100/portapack_h4m_cpld.qsf
new file mode 100644
index 00000000..697b7004
--- /dev/null
+++ b/hardware/portapack_h4m/CPLD/AG256SL100/portapack_h4m_cpld.qsf
@@ -0,0 +1,352 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 32-bit
+# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
+# Date created = 21:24:55  April 29, 2014
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		portapack_h4m_cpld_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "MAX II"
+set_global_assignment -name DEVICE EPM240T100C5
+set_global_assignment -name TOP_LEVEL_ENTITY top
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:24:55  APRIL 29, 2014"
+set_global_assignment -name LAST_QUARTUS_VERSION "22.1std.1 Lite Edition"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 100
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
+set_global_assignment -name EDA_SIMULATION_TOOL "Questa Intel FPGA (VHDL)"
+set_global_assignment -name EDA_NETLIST_WRITER_OUTPUT_DIR simulation/modelsim -section_id eda_simulation
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
+set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVCMOS"
+set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to SW_D
+set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to SW_L
+set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to SW_R
+set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to SW_ROT_A
+set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to SW_ROT_B
+set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to SW_SEL
+set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to SW_U
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TP_D
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TP_L
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TP_R
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TP_U
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_DB[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_DB[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_DB[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_DB[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_DB[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_DB[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_DB[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_DB[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_DB[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_DB[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_DB[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_DB[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_DB[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_DB[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_DB[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_DB[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_RDX
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_RS
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_TE
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_WRX
+set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
+set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH top_tb -section_id eda_simulation
+set_global_assignment -name EDA_TEST_BENCH_NAME top_tb -section_id eda_simulation
+set_global_assignment -name EDA_DESIGN_INSTANCE_NAME uut -section_id top_tb
+set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME top_tb -section_id top_tb
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
+set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "500 ns" -section_id top_tb
+set_global_assignment -name EDA_TEST_BENCH_FILE top_tb.vhd -section_id top_tb
+set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "BSDL (Boundary Scan)"
+set_global_assignment -name EDA_NETLIST_WRITER_OUTPUT_DIR /home/jboone/src/portapack/portapack_hackrf/hardware/portapack_h2/cpld -section_id eda_board_design_boundary_scan
+set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION POST_CONFIG -section_id eda_board_design_boundary_scan
+set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
+set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
+set_global_assignment -name ENABLE_NCE_PIN OFF
+set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name GENERATE_RBF_FILE OFF
+set_global_assignment -name GENERATE_SVF_FILE ON
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH BUS-HOLD"
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_RESETX
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_ADDR
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_D[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_DIR
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SW_D
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SW_L
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SW_R
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SW_U
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SW_ROT_B
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SW_SEL
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SW_ROT_A
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[15]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[14]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[13]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[12]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[11]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[10]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[9]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[8]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[7]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[6]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[5]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[4]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[3]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[2]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[1]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[0]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_RDX
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_RESETX
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_RS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_TE
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_WRX
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_ADDR
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_D[7]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_D[6]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_D[5]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_D[4]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_D[3]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_D[2]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_D[1]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_D[0]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_DIR
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SW_D
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SW_L
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SW_R
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SW_ROT_A
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SW_ROT_B
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SW_SEL
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SW_U
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to TP_D
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to TP_L
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to TP_R
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to TP_U
+set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[15]
+set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[14]
+set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[13]
+set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[12]
+set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[11]
+set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[10]
+set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[9]
+set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[8]
+set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[7]
+set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[6]
+set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[5]
+set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[4]
+set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[3]
+set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[2]
+set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[1]
+set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[0]
+set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_RDX
+set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_RESETX
+set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_RS
+set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_TE
+set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_WRX
+set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_ADDR
+set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_D[7]
+set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_D[6]
+set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_D[5]
+set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_D[4]
+set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_D[3]
+set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_D[2]
+set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_D[1]
+set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_D[0]
+set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_DIR
+set_instance_assignment -name SLOW_SLEW_RATE ON -to SW_D
+set_instance_assignment -name SLOW_SLEW_RATE ON -to SW_L
+set_instance_assignment -name SLOW_SLEW_RATE ON -to SW_R
+set_instance_assignment -name SLOW_SLEW_RATE ON -to SW_ROT_A
+set_instance_assignment -name SLOW_SLEW_RATE ON -to SW_ROT_B
+set_instance_assignment -name SLOW_SLEW_RATE ON -to SW_SEL
+set_instance_assignment -name SLOW_SLEW_RATE ON -to SW_U
+set_instance_assignment -name SLOW_SLEW_RATE ON -to TP_D
+set_instance_assignment -name SLOW_SLEW_RATE ON -to TP_L
+set_instance_assignment -name SLOW_SLEW_RATE ON -to TP_R
+set_instance_assignment -name SLOW_SLEW_RATE ON -to TP_U
+set_global_assignment -name ENABLE_DEVICE_WIDE_RESET OFF
+set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 2
+set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 1
+set_instance_assignment -name PCI_IO OFF -to MCU_DIR
+set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER ON
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_BACKLIGHT
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_BACKLIGHT
+set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_BACKLIGHT
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AUDIO_RESETX
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to AUDIO_RESETX
+set_instance_assignment -name SLOW_SLEW_RATE ON -to AUDIO_RESETX
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_LCD_RDX
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_LCD_RDX
+set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_LCD_RDX
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_LCD_WRX
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_LCD_WRX
+set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_LCD_WRX
+set_instance_assignment -name PCI_IO OFF -to MCU_LCD_WRX
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_IO_STBX
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_IO_STBX
+set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_IO_STBX
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TP_R
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TP_D
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TP_L
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TP_U
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_LCD_TE
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_LCD_TE
+set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_LCD_TE
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_P2_8
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_P2_8
+set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_P2_8
+set_instance_assignment -name PCI_IO OFF -to MCU_P2_8
+set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
+
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to LCD_DB[15]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to LCD_DB[14]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to LCD_DB[13]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to LCD_DB[12]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to LCD_DB[11]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to LCD_DB[10]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to LCD_DB[9]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to LCD_DB[8]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to LCD_DB[7]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to LCD_DB[6]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to LCD_DB[5]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to LCD_DB[4]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to LCD_DB[3]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to LCD_DB[2]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to LCD_DB[1]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to LCD_DB[0]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MCU_D[7]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MCU_D[6]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MCU_D[5]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MCU_D[4]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MCU_D[3]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MCU_D[2]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MCU_D[1]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MCU_D[0]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MCU_ADDR
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MCU_DIR
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MCU_IO_STBX
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MCU_LCD_RDX
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to MCU_LCD_WRX
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to MCU_P2_8
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to GPS_TIMEPULSE
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to GPS_TIMEPULSE
+set_instance_assignment -name SLOW_SLEW_RATE ON -to GPS_TIMEPULSE
+set_instance_assignment -name PCI_IO OFF -to GPS_TIMEPULSE
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to GPS_TIMEPULSE
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to GPS_TX_READY
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to GPS_TX_READY
+set_instance_assignment -name SLOW_SLEW_RATE ON -to GPS_TX_READY
+set_instance_assignment -name PCI_IO OFF -to GPS_TX_READY
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to GPS_TX_READY
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to REF_EN
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to REF_EN
+set_instance_assignment -name SLOW_SLEW_RATE ON -to REF_EN
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to GPS_RESETX
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to GPS_RESETX
+set_instance_assignment -name SLOW_SLEW_RATE ON -to GPS_RESETX
+
+set_location_assignment PIN_58 -to REF_EN
+set_location_assignment PIN_72 -to MCU_DIR
+set_location_assignment PIN_41 -to MCU_IO_STBX
+set_location_assignment PIN_40 -to MCU_LCD_TE
+set_location_assignment PIN_43 -to MCU_P2_8
+set_location_assignment PIN_71 -to MCU_LCD_WRX
+set_location_assignment PIN_42 -to MCU_ADDR
+set_location_assignment PIN_39 -to MCU_LCD_RDX
+set_location_assignment PIN_35 -to MCU_D[0]
+set_location_assignment PIN_33 -to MCU_D[2]
+set_location_assignment PIN_28 -to MCU_D[4]
+set_location_assignment PIN_27 -to MCU_D[6]
+set_location_assignment PIN_8 -to TP_U
+set_location_assignment PIN_7 -to TP_L
+set_location_assignment PIN_6 -to TP_D
+set_location_assignment PIN_5 -to TP_R
+set_location_assignment PIN_26 -to MCU_D[7]
+set_location_assignment PIN_29 -to MCU_D[5]
+set_location_assignment PIN_30 -to MCU_D[3]
+set_location_assignment PIN_36 -to MCU_D[1]
+set_location_assignment PIN_73 -to GPS_RESETX
+set_location_assignment PIN_75 -to GPS_TX_READY
+set_location_assignment PIN_74 -to GPS_TIMEPULSE
+set_location_assignment PIN_34 -to SW_U
+set_location_assignment PIN_37 -to SW_L
+set_location_assignment PIN_17 -to SW_SEL
+set_location_assignment PIN_12 -to SW_R
+set_location_assignment PIN_14 -to SW_D
+set_location_assignment PIN_15 -to SW_ROT_A
+set_location_assignment PIN_16 -to SW_ROT_B
+set_location_assignment PIN_99 -to LCD_DB[0]
+set_location_assignment PIN_98 -to LCD_DB[1]
+set_location_assignment PIN_97 -to LCD_DB[2]
+set_location_assignment PIN_96 -to LCD_DB[3]
+set_location_assignment PIN_95 -to LCD_DB[4]
+set_location_assignment PIN_92 -to LCD_DB[5]
+set_location_assignment PIN_91 -to LCD_DB[6]
+set_location_assignment PIN_90 -to LCD_DB[7]
+set_location_assignment PIN_89 -to LCD_DB[8]
+set_location_assignment PIN_88 -to LCD_DB[9]
+set_location_assignment PIN_87 -to LCD_DB[10]
+set_location_assignment PIN_86 -to LCD_DB[11]
+set_location_assignment PIN_85 -to LCD_DB[12]
+set_location_assignment PIN_84 -to LCD_DB[13]
+set_location_assignment PIN_83 -to LCD_DB[14]
+set_location_assignment PIN_82 -to LCD_DB[15]
+set_location_assignment PIN_100 -to LCD_RESETX
+set_location_assignment PIN_1 -to LCD_RDX
+set_location_assignment PIN_3 -to LCD_RS
+set_location_assignment PIN_2 -to LCD_WRX
+set_location_assignment PIN_76 -to LCD_BACKLIGHT
+set_location_assignment PIN_4 -to LCD_TE
+set_global_assignment -name ENABLE_OCT_DONE OFF
+set_location_assignment PIN_38 -to DEVICE_RESET_V
+set_location_assignment PIN_44 -to DEVICE_RESET
+set_global_assignment -name SDC_FILE portapack_h4m_cpld.sdc
+set_global_assignment -name VHDL_FILE top.vhd
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SYSOFF
+set_location_assignment PIN_47 -to SYSOFF
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SYSOFF
\ No newline at end of file
diff --git a/hardware/portapack_h4m/CPLD/AG256SL100/portapack_h4m_cpld.sdc b/hardware/portapack_h4m/CPLD/AG256SL100/portapack_h4m_cpld.sdc
new file mode 100644
index 00000000..5546679a
--- /dev/null
+++ b/hardware/portapack_h4m/CPLD/AG256SL100/portapack_h4m_cpld.sdc
@@ -0,0 +1,116 @@
+## Generated SDC file "portapack_hackrf_one_cpld.sdc"
+
+## Copyright (C) 1991-2014 Altera Corporation
+## Your use of Altera Corporation's design tools, logic functions 
+## and other software and tools, and its AMPP partner logic 
+## functions, and any output files from any of the foregoing 
+## (including device programming or simulation files), and any 
+## associated documentation or information are expressly subject 
+## to the terms and conditions of the Altera Program License 
+## Subscription Agreement, Altera MegaCore Function License 
+## Agreement, or other applicable license agreement, including, 
+## without limitation, that your use is for the sole purpose of 
+## programming logic devices manufactured by Altera and sold by 
+## Altera or its authorized distributors.  Please refer to the 
+## applicable agreement for further details.
+
+
+## VENDOR  "Altera"
+## PROGRAM "Quartus II"
+## VERSION "Version 13.1.4 Build 182 03/12/2014 SJ Web Edition"
+
+## DATE    "Sat May  3 10:22:18 2014"
+
+##
+## DEVICE  "5M40ZE64C5"
+##
+
+# RS = 0, D = DB[15:8]
+#		wait max(tast = 0 ns, CPLD setup = ?)
+# WR = 0, D = DB[7:0]
+#		wait max(CPLD )
+
+#**************************************************************
+# Time Information
+#**************************************************************
+
+set_time_format -unit ns -decimal_places 3
+
+set mcu_clk_period 4.9
+
+set lcd_data_wr_setup 10.0
+set lcd_data_wr_hold 10.0
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+create_clock -name {MCU_LCD_WRX} -period 66.000 -waveform { 0.000 33.000 } [get_ports {MCU_LCD_WRX}]
+#create_clock -name strobe_virt -period 66.000
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+#set_input_delay -clock strobe_virt [get_ports {D[*]}]
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+#set_false_path -from [get_clocks {MCU_IO_STBX}] -to [get_ports {TP_D TP_L TP_R TP_U}]
+#set_false_path -from [get_ports {SW_D SW_L SW_R SW_ROT_A SW_ROT_B SW_SEL SW_U}] -to [get_ports {MCU_D[*]}]
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
diff --git a/hardware/portapack_h4m/CPLD/AG256SL100/quartus.ini_ignore b/hardware/portapack_h4m/CPLD/AG256SL100/quartus.ini_ignore
new file mode 100644
index 00000000..edc6cbd0
--- /dev/null
+++ b/hardware/portapack_h4m/CPLD/AG256SL100/quartus.ini_ignore
@@ -0,0 +1 @@
+dft_skip_oct_vccn_check = on
\ No newline at end of file
diff --git a/hardware/portapack_h4m/CPLD/AG256SL100/top.vhd b/hardware/portapack_h4m/CPLD/AG256SL100/top.vhd
new file mode 100644
index 00000000..88661184
--- /dev/null
+++ b/hardware/portapack_h4m/CPLD/AG256SL100/top.vhd
@@ -0,0 +1,207 @@
+--
+-- Copyright (C) 2012 Jared Boone, ShareBrained Technology, Inc.
+-- Copyright (C) 2024 jLynx.net https://github.com/jLynx
+--
+-- This file is part of PortaPack.
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2, or (at your option)
+-- any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; see the file COPYING.  If not, write to
+-- the Free Software Foundation, Inc., 51 Franklin Street,
+-- Boston, MA 02110-1301, USA.
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity top is
+	port (
+		MCU_D				:	inout	std_logic_vector(7 downto 0);
+		MCU_DIR			:	in		std_logic;
+		MCU_IO_STBX		:	in		std_logic;
+		MCU_LCD_WRX		:	in		std_logic;
+		MCU_ADDR			:	in		std_logic;
+		MCU_LCD_TE		:	out	std_logic;
+		MCU_P2_8			:	in		std_logic;
+		MCU_LCD_RDX		:	in		std_logic;
+		
+		TP_U				:	out	std_logic;
+		TP_D				:	out	std_logic;
+		TP_L				:	out	std_logic;
+		TP_R				:	out	std_logic;
+		
+		SW_SEL			:	in		std_logic;
+		SW_ROT_A			:	in		std_logic;
+		SW_ROT_B			:	in		std_logic;
+		SW_U				:	in		std_logic;
+		SW_D				:	in		std_logic;
+		SW_L				:	in		std_logic;
+		SW_R				:	in		std_logic;
+		
+		LCD_RESETX		:	out	std_logic;
+		LCD_RS			:	out	std_logic;
+		LCD_WRX			:	out	std_logic;
+		LCD_RDX			:	out	std_logic;
+		LCD_DB			:	inout	std_logic_vector(15 downto 0);
+		LCD_TE			:	in		std_logic;
+		LCD_BACKLIGHT	:	out	std_logic;
+		
+		SYSOFF         :  out   std_logic;
+
+		AUDIO_RESETX	:	out	std_logic;
+
+		REF_EN			:	out	std_logic;
+
+		GPS_RESETX		:	out	std_logic;
+		GPS_TX_READY	:	in		std_logic;
+		GPS_TIMEPULSE	:	in		std_logic;
+		
+		DEVICE_RESET	:	in		std_logic;
+		DEVICE_RESET_V	:	in		std_logic
+	);
+end top;
+
+architecture rtl of top is
+
+	signal	switches : std_logic_vector(7 downto 0);
+	
+	type data_direction_t is (from_mcu, to_mcu);
+	signal	data_dir	: data_direction_t;
+	
+	signal	mcu_data_out_lcd : std_logic_vector(7 downto 0);
+	signal	mcu_data_out_io : std_logic_vector(7 downto 0);
+	signal	mcu_data_out : std_logic_vector(7 downto 0);
+	signal	mcu_data_in	: std_logic_vector(7 downto 0);
+	
+	signal	lcd_data_in : std_logic_vector(15 downto 0);
+	signal  lcd_data_in_mux : std_logic_vector(7 downto 0);
+	signal	lcd_data_out : std_logic_vector(15 downto 0);
+	
+	signal  lcd_data_in_q : std_logic_vector(7 downto 0) := (others => '0');
+	signal  lcd_data_out_q : std_logic_vector(7 downto 0) := (others => '0');
+	
+	signal	tp_q : std_logic_vector(7 downto 0) := (others => '0');
+	
+	signal	lcd_reset_q : std_logic := '1';
+	signal	lcd_backlight_q : std_logic := '0';
+	
+	signal sysoff_q : std_logic := '0';
+
+	signal	audio_reset_q : std_logic := '1';
+
+	signal	ref_en_q : std_logic := '0';
+	
+	signal	device_reset_q : std_logic := '1';
+
+	signal	dir_read : boolean;
+	signal	dir_write : boolean;
+	
+	signal	lcd_read_strobe : boolean;
+	signal	lcd_write_strobe : boolean;
+	signal	lcd_write : boolean;
+
+	signal	io_strobe : boolean;
+	signal	io_read_strobe : boolean;
+	signal	io_write_strobe : boolean;
+	
+	signal reset_flag: boolean := false;
+	signal reset_sync: std_logic := '1';
+	signal counter: integer range 0 to 25000000 := 0;  -- Adjust the count value for desired delay (e.g., 1 second with a 25 MHz clock)
+
+	constant COUNTER_MAX: integer := 25000000;  -- Adjust this value to match the counter range
+	
+begin
+
+	-- I/O data
+	switches <= LCD_TE & not SW_ROT_B & not SW_ROT_A & not SW_SEL & not SW_U & not SW_D & not SW_L & not SW_R;
+
+	TP_U <= tp_q(3) when tp_q(7) = '1' else 'Z';
+	TP_D <= tp_q(2) when tp_q(6) = '1' else 'Z';
+	TP_L <= tp_q(1) when tp_q(5) = '1' else 'Z';
+	TP_R <= tp_q(0) when tp_q(4) = '1' else 'Z';
+	
+	LCD_BACKLIGHT <= lcd_backlight_q;
+	
+	SYSOFF <= sysoff_q;
+	
+	MCU_LCD_TE <= LCD_TE;
+	
+	
+	-- State management
+	data_dir <= to_mcu when MCU_DIR = '1' else from_mcu;
+	dir_read <= (data_dir = to_mcu);
+	dir_write <= (data_dir = from_mcu);
+
+	io_strobe <= (MCU_IO_STBX = '0');
+	io_read_strobe <= io_strobe and dir_read;
+
+	lcd_read_strobe <= (MCU_LCD_RDX = '0');
+	lcd_write <= not lcd_read_strobe;
+
+	-- LCD interface
+	LCD_RS <= MCU_ADDR;
+	LCD_RDX <= MCU_LCD_RDX;
+	LCD_WRX <= MCU_LCD_WRX;
+
+	lcd_data_out <= lcd_data_out_q & mcu_data_in;
+	lcd_data_in <= LCD_DB;
+	LCD_DB <= lcd_data_out when lcd_write else (others => 'Z');
+
+	-- Reference clock
+	REF_EN <= ref_en_q;
+
+	-- Peripheral reset control
+	LCD_RESETX <= not lcd_reset_q;
+	AUDIO_RESETX <= not audio_reset_q;
+	GPS_RESETX <= '1';
+
+	-- MCU interface
+	mcu_data_out_lcd <= lcd_data_in(15 downto 8) when lcd_read_strobe else lcd_data_in_q;
+	mcu_data_out_io <= switches;
+	mcu_data_out <= mcu_data_out_io when io_read_strobe else mcu_data_out_lcd;
+
+	mcu_data_in <= MCU_D;
+	MCU_D <= mcu_data_out when dir_read else (others => 'Z');
+	
+	-- Synchronous behaviors:
+	-- LCD write: Capture LCD high byte on LCD_WRX falling edge.
+	process(MCU_LCD_WRX, mcu_data_in)
+	begin
+		if falling_edge(MCU_LCD_WRX) then
+			lcd_data_out_q <= mcu_data_in;
+		end if;
+	end process;
+	
+	-- LCD read: Capture LCD low byte on LCD_RD falling edge.
+	process(MCU_LCD_RDX, lcd_data_in)
+	begin
+		if rising_edge(MCU_LCD_RDX) then
+			lcd_data_in_q <= lcd_data_in(7 downto 0);
+		end if;
+	end process;
+	
+	-- I/O write (to resistive touch panel): Capture data from
+	-- MCU and hold on TP pins until further notice.
+	process(MCU_IO_STBX, dir_write, mcu_data_in, MCU_ADDR)
+	begin
+		if rising_edge(MCU_IO_STBX) and dir_write then
+			if MCU_ADDR = '0' then
+				tp_q <= mcu_data_in;
+			else
+				lcd_reset_q <= mcu_data_in(0);
+				audio_reset_q <= mcu_data_in(1);
+				ref_en_q <= mcu_data_in(6);
+				lcd_backlight_q <= mcu_data_in(7);
+				sysoff_q <= mcu_data_in(2); 
+			end if;
+		end if;
+	end process;
+end rtl;
\ No newline at end of file
diff --git a/hardware/portapack_h4m/CPLD/README.md b/hardware/portapack_h4m/CPLD/README.md
new file mode 100644
index 00000000..ee1b5fb5
--- /dev/null
+++ b/hardware/portapack_h4m/CPLD/README.md
@@ -0,0 +1,58 @@
+# Project Setup Guide
+
+## Prerequisites
+
+- Intel Quartus Prime
+- Supra-2023.02.b0-7773ca8a-win64-all
+
+## Installation Steps
+
+1. **Project Setup**
+
+- Create a new AG256SL100 project in Quartus Prime
+- (Alternatively, copy an existing project)
+
+2. **Code Implementation**
+
+- Implement your code in the project
+- Compile the project to verify there are no errors
+- Ensure successful compilation before proceeding
+
+3. **Supra Configuration**
+
+- Launch Supra.exe
+- Navigate to: File → Project → Open Project
+- Select the H4M project when prompted
+- Select Tools → Migrate → Next
+
+4. **Additional Setup**
+
+- Follow the on-screen prompts
+- You will need to:
+    - Open a second Quartus project
+    - Execute a provided script
+
+5. **Programming**
+
+- In Supra, go to: Tools → Program
+- Click "Query device ID"
+- Verify the returned ID is: 0x00025610
+
+6. **File Selection**
+
+- Select the programming file (if not automatically loaded)
+- Use the .prg file from the Supra src folder (non-SRAM version)
+
+7. **Programming Process**
+
+- Click "Program" to begin
+- Note: The counter shows elapsed seconds, not progress percentage
+- Programming is complete when "USB driver disconnected" message appears
+
+## Troubleshooting
+
+If you encounter any issues, ensure:
+
+- All prerequisites are properly installed
+- Project configurations are correct
+- Device connections are secure
\ No newline at end of file
diff --git a/hardware/portapack_h4m/CPLD/Supra/H4M.proj b/hardware/portapack_h4m/CPLD/Supra/H4M.proj
new file mode 100644
index 00000000..21d3c746
--- /dev/null
+++ b/hardware/portapack_h4m/CPLD/Supra/H4M.proj
@@ -0,0 +1,62 @@
+[GuiMigrateSetupPage]
+fromDir=../AG256SL100
+design=portapack_h4m_cpld
+device=AG256SL100
+veFile=
+ipFiles=
+backwardCompatible=false
+modeGroup=false
+modeQuartus=true
+modeSynplicity=false
+modeNative=false
+
+[GuiMigrateRunPage]
+isMC=false
+count=
+jobs=
+seed=
+retry=0
+fitting=0
+fitter=0
+effort=0
+holdx=0
+skew=0
+skope=0
+preset=0
+adjust=0
+target=0
+tuning=0
+corner=0
+flow=0
+orgPlace=false
+quartusSdc=false
+probeForce=false
+probeState=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\x2\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x2m\0\0\0\x2\0\x1\x1\x1\0\0\0\0\0\0\0\0\0\0\0\0\x64\0\0\0K\0\0\0\x4\0\0\0\0\0\0\0\x2\0\0\x1\xc2\0\0\0\x1\0\0\0\0\0\0\0\xab\0\0\0\x1\0\0\0\0)
+probeCount=5
+probe0From=
+probe0Pad=
+probe1From=
+probe1Pad=
+probe2From=
+probe2Pad=
+probe3From=
+probe3Pad=
+probe4From=
+probe4Pad=
+
+[GuiProgramScreen]
+hardwareId=0
+blasterSpeed=70
+prgFile=portapack_h4m_cpld.prg
+eraseBox=false
+cable=0
+runAction=program
+eraseChip=true
+eraseFrom=
+eraseTo=
+binFile=
+readFrom=
+readTo=
+
+[MainWindow]
+recentFile.0=
diff --git a/hardware/portapack_h4m/CPLD/Supra/af_batch.tcl b/hardware/portapack_h4m/CPLD/Supra/af_batch.tcl
new file mode 100644
index 00000000..51b040ae
--- /dev/null
+++ b/hardware/portapack_h4m/CPLD/Supra/af_batch.tcl
@@ -0,0 +1,114 @@
+if {![info exist MODE ]} {set MODE QUARTUS}
+if {![info exists QUARTUS_SDC]} {set QUARTUS_SDC true}
+if {![info exists CORNER]} {set CORNER ""}
+if {![info exist COUNT]} {set COUNT 6}
+if {![info exist JOBS ]} {set JOBS  1}
+
+if {![info exist SEEDS   ]} {set SEEDS    {0        0        0        0          666        888    }}
+if {![info exist EFFORTS ]} {set EFFORTS  {highest  highest  highest  highest    high       high   }}
+if {![info exist FITTERS ]} {set FITTERS  {hybrid   hybrid   hybrid   hybrid     hybrid     hybrid }}
+if {![info exist FITTINGS]} {set FITTINGS {timing_more timing_more timing_more timing timing basic }}
+if {![info exist SKEWS   ]} {set SKEWS    {advanced advanced advanced advanced   aggressive basic  }}
+if {![info exist HOLDXS  ]} {set HOLDXS   {default  default  default  default    default    default}}
+
+set bc_config "./bc_config.txt"
+if { [file exists $bc_config] } {
+  alta::tcl_highlight "Using MC config $bc_config.\n"
+  source "$bc_config"
+}
+
+#######################################################################
+
+proc get_rand_value { values } {
+  if {[llength $values] == 0} { return {} }
+  return [lindex $values [expr {int(rand()*10000)%[llength $values]}]]
+}
+
+set results "bc_results"
+set summary "bc_summary.txt"
+file delete -force $results; file mkdir $results
+file delete $summary; print -nonewline "" >! $summary
+
+set is_parallel [expr $JOBS > 1]
+set is_color ""; set is_gui ""; set is_quiet ""
+if { $is_parallel } {
+  set is_gui "--quiet"
+} else {
+  if { [alta::tcl_is_color] } { set is_color "--color" }
+  if { [alta::tcl_is_gui  ] } { set is_gui   "--gui"   }
+}
+
+#######################################################################
+
+set progs {}
+set titles {}
+for {set id 1} {$id <= $COUNT} {incr id} {
+set result_dir "$results/$id"
+file mkdir $result_dir
+
+set seed    [get_rand_value $SEEDS   ]
+set effort  [get_rand_value $EFFORTS ]
+set skew    [get_rand_value $SKEWS   ]
+set fitter  [get_rand_value $FITTERS ]
+set fitting [get_rand_value $FITTINGS]
+set holdx   [get_rand_value $HOLDXS  ]
+
+set prog [list [info nameofexec] $is_quiet $is_color $is_gui -B --batch --mode $MODE]
+alta::lconcat prog [list -X "set QUARTUS_SDC $QUARTUS_SDC"]
+if { $CORNER != "" } {
+  alta::lconcat prog [list -X "set CORNER $CORNER"]
+}
+alta::lconcat prog [list -X "set RESULT_DIR $result_dir"]
+if { $seed != "" } {
+  alta::lconcat prog [list -X "set SEED $seed"]
+}
+if { $effort != "" } {
+  alta::lconcat prog [list -X "set EFFORT $effort"]
+}
+if { $fitter != "" } {
+  alta::lconcat prog [list -X "set FITTER $fitter"]
+}
+if { $fitting != "" } {
+  alta::lconcat prog [list -X "set FITTING $fitting"]
+}
+if { $skew != "" } {
+  alta::lconcat prog [list -X "set SKEW $skew"]
+}
+if { $holdx != "" } {
+  alta::lconcat prog [list -X "set HOLDX $holdx"]
+}
+#alta::lconcat prog [list -F af_run.tcl]
+lappend progs $prog
+lappend titles "#$id $result_dir"
+}
+
+#######################################################################
+
+if { $is_parallel } {
+  set bg_progs {}
+  foreach bg_prog $progs {
+    lappend bg_progs [lappend bg_prog $is_quiet]
+  }
+  bg_exec_queue $titles $bg_progs $JOBS
+}
+
+#######################################################################
+
+for {set id 1} {$id <= $COUNT} {incr id} {
+set result_dir "$results/$id"
+set prog  [lindex $progs  [expr $id-1]]
+set title [lindex $titles [expr $id-1]]
+if { ! $is_parallel } {
+  puts $title
+  puts $prog
+  eval exec -ignorestderr $prog >&@ stdout
+}
+
+print "***************************************************************************\n" >> $summary
+print "$title\n" >> $summary
+cat "$result_dir/alta_db/fmax.rpt" >> $summary
+cat "$result_dir/alta_db/xfer.rpt" >> $summary
+print "" >> $summary
+}
+
+alta::tcl_highlight "Check $summary for result.\n"
diff --git a/hardware/portapack_h4m/CPLD/Supra/af_ip.tcl b/hardware/portapack_h4m/CPLD/Supra/af_ip.tcl
new file mode 100644
index 00000000..3e3c5cb0
--- /dev/null
+++ b/hardware/portapack_h4m/CPLD/Supra/af_ip.tcl
@@ -0,0 +1,50 @@
+set AGM_SUPRA true
+set DESIGN "portapack_h4m_cpld"
+set IPLIST {alta_bram alta_bram9k alta_sram alta_wram alta_pll alta_pllx alta_pllv alta_pllve alta_boot alta_osc alta_mult alta_multm alta_ufm alta_ufms alta_ufml alta_i2c alta_spi alta_irda alta_mcu alta_mcu_m3 alta_saradc alta_adc alta_dac alta_cmp }
+lappend IPLIST alta_rv32
+
+proc set_alta_partition {inst tag} {
+  set full_name [get_name_info -observable_type pre_synthesis -info full_path $inst]
+  set inst_name [get_name_info -observable_type pre_synthesis -info short_full_path $inst]
+  set base_name [get_name_info -observable_type pre_synthesis -info instance_name $inst]
+  set section_id [string map { [ _ ] _ . _ | _} $inst_name]
+  eval "set_global_assignment -name PARTITION_COLOR 52377 -section_id $section_id -tag $tag"
+  eval "set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id $section_id -tag $tag"
+  eval "set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id $section_id -tag $tag"
+  eval "set_instance_assignment -name PARTITION_HIERARCHY $section_id -to $full_name -section_id $section_id -tag $tag"
+}
+
+load_package flow
+if { $DESIGN == "" } {
+  set DESIGN $::quartus(args)
+}
+project_open $DESIGN
+
+set tag alta_auto
+if { [llength $IPLIST] > 0 } {
+  # A Quartus bug saves PARTITION_HIERARCHY assignments without tag. Use section_id to remove them.
+  set asgn_col [get_all_global_assignments -name PARTITION_NETLIST_TYPE -tag $tag]
+  foreach_in_collection part $asgn_col {
+    set section_id [lindex $part 0]
+    eval "remove_all_instance_assignments -name PARTITION_HIERARCHY -section_id $section_id"
+  }
+  eval "remove_all_global_assignments -name PARTITION_COLOR -tag $tag"
+  eval "remove_all_global_assignments -name PARTITION_NETLIST_TYPE -tag $tag"
+  eval "remove_all_global_assignments -name PARTITION_FITTER_PRESERVATION_LEVEL -tag $tag"
+  catch { execute_module -tool map }
+
+  foreach ip $IPLIST {
+    foreach_in_collection inst [get_names -node_type hierarchy -observable_type pre_synthesis -filter "$ip:*"] {
+      set_alta_partition $inst $tag
+    }
+    foreach_in_collection inst [get_names -node_type hierarchy -observable_type pre_synthesis -filter "*|$ip:*"] {
+      set_alta_partition $inst $tag
+    }
+  }
+}
+eval "set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY PARTITION_ONLY -section_id eda_simulation"
+
+project_close
+
+exit
+
diff --git a/hardware/portapack_h4m/CPLD/Supra/af_map.tcl b/hardware/portapack_h4m/CPLD/Supra/af_map.tcl
new file mode 100644
index 00000000..ebdf2911
--- /dev/null
+++ b/hardware/portapack_h4m/CPLD/Supra/af_map.tcl
@@ -0,0 +1,79 @@
+map -import
+
+if { [info exists DESIGN] && ! [info exists TOP_MODULE] } {
+  set TOP_MODULE "$DESIGN"
+}
+if { ! [info exists DESIGN] } {
+  set DESIGN "portapack_h4m_cpld"
+}
+if { ! [info exists TOP_MODULE] } {
+  set TOP_MODULE "top"
+}
+
+set verilogs { }
+if { [ llength $verilogs ] == 0 } {
+  set verilogs "A:/Users/jLynx/Documents/Code/C/portapack-mayhem/hardware/portapack_h4m/CPLD/AG256SL100/${DESIGN}.v"
+}
+foreach verilog $verilogs {
+  read_verilog "$verilog"
+}
+
+  read_verilog -sv -lib +/agm/rodina/cells_sim.v
+  read_verilog -sv -lib +/agm/common/m9k_bb.v
+  read_verilog -sv -lib +/agm/common/altpll_bb.v
+  hierarchy -check -top ${TOP_MODULE}
+
+  synth -run coarse -top ${DESIGN}
+
+  map proc
+  opt_expr
+  opt_clean
+  check
+  opt
+
+  wreduce
+  alumacc
+  share
+  opt
+  fsm
+  opt -fast
+  memory -nomap
+  opt_clean
+
+  memory_bram -rules +/agm/common/brams.txt
+  techmap -map +/agm/common/brams_map.v
+
+  opt -fast -mux_undef -undriven -fine -full
+  memory_map
+  opt -undriven -fine
+
+  techmap -autoproc -map +/techmap.v -map +/agm/rodina/arith_map.v
+  dffsr2dff
+  dff2dffe -direct-match \$_DFF_*
+  opt -full
+
+  techmap -map +/agm/rodina/cells_map.v
+  agm_dffeas
+  opt -full
+
+  clean -purge
+  setundef -undriven -zero
+  abc -markgroups -dff
+  opt_expr -mux_undef -undriven -full
+  opt_merge
+  opt_rmdff
+  opt_clean
+
+  abc -lut 4
+  clean
+
+  techmap -map +/agm/rodina/cells_map.v
+  dffinit -ff dffeas Q INIT
+  clean -purge
+
+  hierarchy -check
+  check -noinit
+
+  write_verilog -bitblasted -attr2comment -defparam -decimal -renameprefix syn_ ${DESIGN}.vqm
+# exec sed -i "/\\\\\\\$paramod/s/\[$=\\]/_/g" ${DESIGN}.vqm
+
diff --git a/hardware/portapack_h4m/CPLD/Supra/af_quartus.tcl b/hardware/portapack_h4m/CPLD/Supra/af_quartus.tcl
new file mode 100644
index 00000000..54463c74
--- /dev/null
+++ b/hardware/portapack_h4m/CPLD/Supra/af_quartus.tcl
@@ -0,0 +1,50 @@
+set AGM_SUPRA true
+set RETRY 0
+set DESIGN "portapack_h4m_cpld"
+
+if { [is_project_open] } {
+  export_assignments
+}
+
+set is_compatible false
+if { $is_compatible } {
+  cd A:/Users/jLynx/Documents/Code/C/portapack-mayhem/hardware/portapack_h4m/CPLD/AG256SL100
+  qexec "[file join $::quartus(binpath) quartus_eda] $DESIGN --simulation --tool=modelsim --format=verilog"
+} else {
+  set FITTER_EFFORTS    {"STANDARD FIT" "STANDARD FIT" "FAST FIT" "FAST FIT" "FAST FIT"}
+  set SEEDS             [list [expr int(rand()*100)] \
+                              [expr int(rand()*100)] \
+                              [expr int(rand()*100)] \
+                              [expr int(rand()*100)] \
+                              [expr int(rand()*100)]]
+  set PLACEMENT_EFFORTS [list [expr rand()*5+0.1] \
+                              [expr rand()*5+0.1] \
+                              [expr rand()*5+0.1] \
+                              [expr rand()*5+0.1] \
+                              [expr rand()*5+0.1]]
+  set    ROUTER_EFFORTS [list [expr rand()*5+0.25] \
+                              [expr rand()*5+0.25] \
+                              [expr rand()*5+0.25] \
+                              [expr rand()*5+0.25] \
+                              [expr rand()*5+0.25]]
+
+  qexec "[file join $::quartus(binpath) quartus_sh] -t af_ip.tcl"
+
+  load_package flow
+  project_open $DESIGN
+
+  set RETRY [expr $RETRY<[llength $FITTER_EFFORTS]?$RETRY:[llength $FITTER_EFFORTS]]
+  for {set nn -1} {$nn < $RETRY} {incr nn} {
+    if {$nn >= 0}  {
+      set_global_assignment -name FITTER_EFFORT \"[lindex $FITTER_EFFORTS $nn]\"
+      set_global_assignment -name SEED [lindex $SEEDS $nn]
+      set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER [lindex $PLACEMENT_EFFORTS $nn]
+      set_global_assignment -name    ROUTER_EFFORT_MULTIPLIER [lindex    $ROUTER_EFFORTS $nn]
+    }
+
+    set code [catch {execute_flow -compile} msg]
+    if { $code == 0 } { break }
+  }
+}
+
+
diff --git a/hardware/portapack_h4m/CPLD/Supra/af_run.tcl b/hardware/portapack_h4m/CPLD/Supra/af_run.tcl
new file mode 100644
index 00000000..7988dddd
--- /dev/null
+++ b/hardware/portapack_h4m/CPLD/Supra/af_run.tcl
@@ -0,0 +1,340 @@
+set ALTA_SUPRA true
+set sh_continue_on_error false
+set sh_echo_on_source  true
+set sh_quiet_on_source true
+set cc_critical_as_fatal true
+set rt_incremental_route true
+set ta_report_auto 1
+set ta_report_auto_constraints $ta_report_auto
+
+if { ! [info exists RESULT_DIR] } {
+  set RESULT_DIR "."
+} elseif { ! [info exists alta_work] } {
+  set alta_work "${RESULT_DIR}/alta_db"
+}
+if { ! [info exists DEVICE] } {
+  set DEVICE "AG256SL100"
+}
+if { [info exists DESIGN] && ! [info exists TOP_MODULE] } {
+  set TOP_MODULE "$DESIGN"
+}
+if { ! [info exists DESIGN] } {
+  set DESIGN "portapack_h4m_cpld"
+}
+if { ! [info exists TOP_MODULE] } {
+  set TOP_MODULE "top"
+}
+if { ! [info exists IP_FILES] } {
+  set IP_FILES {}
+}
+if { ! [info exists VE_FILE] } {
+  set VE_FILE ""
+}
+if { ! [info exists TIMING_DERATE] } {
+  set TIMING_DERATE {1.000000 1.000000}
+}
+if { [info exists NO_ROUTE] && $NO_ROUTE } {
+  set no_route "-no_route"
+} else {
+  set no_route ""
+}
+if { ! [info exists RETRY] } { set RETRY 0 }
+if { ! [info exists SEED ] } { set SEED 666 }
+set seed_rand ""
+if { $SEED == 0 } { set seed_rand "-seed_rand" }
+if { [info exists QUARTUS_SDC] } {
+  set sdc_remove_quartus_column_name $QUARTUS_SDC
+}
+if { ! [info exists ORG_PLACE] } { set ORG_PLACE false }
+if { ! [info exists MODE] } { set MODE "QUARTUS" }
+if { ! [info exists FLOW] } { set FLOW "ALL"    }
+if { $FLOW == "PROBE" } {
+  if { ! [info exists PROBE_FORCE] } { set PROBE_FORCE false }
+  if { ! [info exists PREFIX] } { set PREFIX "probe_" }
+}
+if { ! [info exists PREFIX] } {
+  set RESULT $DESIGN
+} else {
+  set RESULT $PREFIX$DESIGN
+}
+if { $FLOW == "GEN" || $FLOW == "PACK" || $FLOW == "LOAD" } { set no_route "-no_route" }
+set RUN "run"
+if { $FLOW == "CHECK" } {
+  set RUN "check"
+} elseif { $FLOW == "PROBE" } {
+  set RUN "probe"
+} elseif { $FLOW == "GEN" } {
+  set RUN "gen"
+}
+
+if { ! [info exists alta_logs] } {
+  set alta_logs "${RESULT_DIR}/alta_logs"
+}
+file mkdir $alta_logs
+alta::begin_log_cmd "$alta_logs/${RUN}.log" "$alta_logs/${RUN}.err"
+alta::tcl_whisper "Cmd : [alta::prog_path] [alta::prog_version]([alta::prog_subversion])\n"
+alta::tcl_whisper "Args : [string map {\{ \" \} \"} $tcl_cmd_args]\n"
+
+set_seed_rand $SEED
+set ar_timing_derate ${TIMING_DERATE}
+
+date_time
+if { [file exists "./${DESIGN}.pre.asf"] } {
+  alta::tcl_highlight "Using pre-ASF file ${DESIGN}.pre.asf.\n"
+  source "./${DESIGN}.pre.asf"
+}
+
+set LOAD_DB    false
+set LOAD_PLACE false
+set LOAD_ROUTE false
+if { $FLOW == "LOAD" || $FLOW == "CHECK" || $FLOW == "PROBE" } {
+  set LOAD_DB    true
+  set LOAD_PLACE true
+  set LOAD_ROUTE true
+} elseif { $FLOW == "R" || $FLOW == "ROUTE" } {
+  set LOAD_DB    true
+  set LOAD_PLACE true
+}
+
+set ORIGINAL_QSF "A:/Users/jLynx/Documents/Code/C/portapack-mayhem/hardware/portapack_h4m/CPLD/AG256SL100/./portapack_h4m_cpld.qsf"
+set ORIGINAL_PIN "A:/Users/jLynx/Documents/Code/C/portapack-mayhem/hardware/portapack_h4m/CPLD/AG256SL100/output_files/portapack_h4m_cpld.pin"
+
+#################################################################################
+
+while (1) {
+if { [info exists CORNER] } { set_mode -corner $CORNER; }
+
+eval "load_architect ${no_route} -type ${DEVICE} 1 1 1000 1000"
+foreach ip_file $IP_FILES { read_ip $ip_file; }
+
+
+if { $FLOW == "GEN" } {
+  if { ! [info exists CONFIG_BITS] } {
+    set CONFIG_BITS "${RESULT_DIR}/${DESIGN}.bin"
+  }
+  if { [llength $CONFIG_BITS] > 1 } {
+    if { ! [info exists BOOT_BINARY] } {
+      set BOOT_BINARY "${RESULT_DIR}/${DESIGN}_boot.bin"
+    }
+    if { ! [info exists CONFIG_ADDRESSES] } {
+      set CONFIG_ADDRESSES ""
+    }
+    generate_binary -master $BOOT_BINARY -inputs $CONFIG_BITS -address $CONFIG_ADDRESSES
+  } else {
+    set CONFIG_ROOT   [file rootname [lindex $CONFIG_BITS 0]]
+    set SLAVE_RBF     "${CONFIG_ROOT}_slave.rbf"
+    set MASTER_BINARY "${CONFIG_ROOT}_master.bin"
+    if { [file exists [lindex $CONFIG_BITS 0]] } {
+      generate_binary -slave  $SLAVE_RBF     -inputs [lindex $CONFIG_BITS 0] -reverse
+      generate_binary -master $MASTER_BINARY -inputs [lindex $CONFIG_BITS 0]
+    }
+    if { ! [info exists BOOT_BINARY] } {
+      set BOOT_BINARY $MASTER_BINARY
+    }
+  }
+  set PRG_FILE [file rootname $BOOT_BINARY].prg
+  set AS_FILE  [file rootname $BOOT_BINARY]_as.prg
+  generate_programming_file $BOOT_BINARY -erase $ERASE \
+                            -program $PROGRAM -verify $VERIFY -offset $OFFSET \
+                            -prg $PRG_FILE -as $AS_FILE
+  break
+}
+
+if { $LOAD_DB } {
+  load_db -top ${TOP_MODULE}
+  set sdc "./${DESIGN}.adc"
+  if { ! [file exists $sdc] } { set sdc "./${DESIGN}.sdc"; }
+  if { [file exists $sdc] } { read_sdc $sdc; }
+
+} elseif { $MODE == "QUARTUS" } {
+  set verilog ${DESIGN}.vo
+  set is_migrated false
+  if { ! [file exists $verilog] } {
+    set verilog "./simulation/modelsim/${DESIGN}.vo"
+    set is_migrated true
+  }
+  if { ! [file exists $verilog] } {
+    error "Can not find design verilog file $verilog"
+  }
+  alta::tcl_highlight "Using design verilog file $verilog.\n"
+  set ret [read_design -top ${TOP_MODULE} -ve $VE_FILE -qsf $ORIGINAL_QSF $verilog -hierachy 1]
+  if { !$ret } { exit -1; }
+
+  set sdc "./${DESIGN}.adc"
+  if { ! [file exists $sdc] } { set sdc "./${DESIGN}.sdc"; }
+  if { ! [file exists $sdc] } {
+    alta::tcl_warn "Can not find design SDC file $sdc"
+  } else {
+    alta::tcl_highlight "Using design SDC file $sdc.\n"
+    read_sdc $sdc
+  }
+
+} elseif { $MODE == "SYNPLICITY" || $MODE == "NATIVE" } {
+  set db_gclk_assignment_level 2
+  set verilog ${DESIGN}.vqm
+  set is_migrated false
+  if { ! [file exists $verilog] } {
+    error "Can not find design verilog file $verilog"
+  }
+
+  set sdc "./${DESIGN}.adc"
+  if { ! [file exists $sdc] } { set sdc "./${DESIGN}.sdc"; }
+  alta::tcl_highlight "Using design verilog file $verilog.\n"
+  if { ! [file exists $sdc] } {
+    alta::tcl_warn "Can not find design SDC file $sdc"
+    set ret [read_design_and_pack -sdc $sdc  -top ${TOP_MODULE} $verilog]
+  } else {
+    alta::tcl_highlight "Using design SDC file $sdc.\n"
+    set ret [read_design_and_pack -top ${TOP_MODULE} $verilog]
+  }
+  if { !$ret } { exit -1; }
+
+} else {
+  error "Unsupported mode $MODE"
+}
+
+if { $FLOW == "PACK" } { break }
+
+if { [info exists FITTING] } {
+  if { $FITTING == "Auto" } { set FITTING auto; }
+  set_mode -fitting $FITTING
+}
+if { [info exists FITTER] } {
+  if { $FITTER == "Auto" } {
+    if { $MODE == "QUARTUS" } { set FITTER hybrid; } else { set FITTER full; }
+  }
+  if { $MODE == "SYNPLICITY" || $MODE == "NATIVE" } { set FITTER full; }
+  set_mode -fitter $FITTER
+}
+if { [info exists EFFORT] } { set_mode -effort $EFFORT; }
+if { [info exists SKEW  ] } { set_mode -skew   $SKEW  ; }
+if { [info exists SKOPE ] } { set_mode -skope  $SKOPE ; }
+if { [info exists HOLDX ] } { set_mode -holdx  $HOLDX; }
+if { [info exists TUNING] } { set_mode -tuning $TUNING; }
+if { [info exists TARGET] } { set_mode -target $TARGET; }
+if { [info exists PRESET] } { set_mode -preset $PRESET; }
+if { [info exists ADJUST] } { set pl_criticality_wadjust $ADJUST; }
+
+set alta_aqf $::alta_work/alta.aqf
+if { $LOAD_DB } {
+  # Empty
+} elseif { true } {
+  if { [file exists $VE_FILE] } {
+    set ORIGINAL_PIN ""
+  } elseif { ! [file exists $ORIGINAL_PIN] } {
+    if { $is_migrated } {
+      error "Can not find design PIN file $ORIGINAL_PIN, please compile design first"
+    }
+    set ORIGINAL_PIN ""
+  }
+  if { [file exists $ORIGINAL_QSF] } {
+    alta::convert_quartus_settings_cmd $ORIGINAL_QSF $ORIGINAL_PIN $alta_aqf
+  } elseif { $is_migrated } {
+    error "Can not find design exported QSF file $ORIGINAL_QSF, please export assigments first"
+  }
+}
+if { [file exists "$alta_aqf"] } {
+  alta::tcl_highlight "Using AQF file $alta_aqf.\n"
+  source "$alta_aqf"
+}
+if { [file exists "./${DESIGN}.asf"] } {
+  alta::tcl_highlight "Using ASF file ${DESIGN}.asf.\n"
+  source "./${DESIGN}.asf"
+}
+
+if { $FLOW == "PROBE" } {
+  set ret [place_pseudo -user_io -place_io -place_pll -place_gclk]
+  if { !$ret } { exit -1 }
+
+  set force ""
+  if { [info exists PROBE_FORCE] && $PROBE_FORCE } { set force "-force" }
+  eval "probe_design -froms {${PROBE_FROMS}} -tos {${PROBE_TOS}} ${force}"
+
+} elseif { $FLOW == "CHECK" } {
+  set ret [place_pseudo -user_io -place_io -place_pll -place_gclk]
+  if { !$ret } { exit -1 }
+
+  if { [file exists "./${DESIGN}.chk"] } {
+    alta::tcl_highlight "Using CHK file ${DESIGN}.chk.\n"
+    source "./${DESIGN}.chk"
+    place_design -dry
+    check_design -rule led_guide
+  } else {
+    error "Can not find design CHECK file ${DESIGN}.chk"
+  }
+
+} else {
+  set ret [place_pseudo -user_io -place_io -place_pll -place_gclk -warn_io]
+  if { !$ret } { exit -1 }
+
+  set org_place ""
+  set load_place ""
+  set load_route ""
+  set quiet ""
+  if {  $ORG_PLACE } { set  org_place "-org_place" ; }
+  if { $LOAD_PLACE } { set load_place "-load_place"; }
+  if { $LOAD_ROUTE } { set load_route "-load_route"; }
+  eval "place_and_route_design $org_place $load_place $load_route \
+                               -retry $RETRY $seed_rand $quiet"
+}
+
+date_time
+if { $FLOW != "CHECK" } {
+if { $FLOW != "PROBE" } {
+#report_timing -verbose 1 -file $::alta_work/timing.rpt.gz
+report_timing -verbose 2 -setup -file $::alta_work/setup.rpt.gz
+report_timing -verbose 2 -setup -brief -file $::alta_work/setup_summary.rpt.gz
+report_timing -verbose 2 -hold -file $::alta_work/hold.rpt.gz
+report_timing -verbose 2 -hold -brief -file $::alta_work/hold_summary.rpt.gz
+
+set ta_report_auto_constraints 0
+report_timing -fmax -file $::alta_work/fmax.rpt
+report_timing -xfer -file $::alta_work/xfer.rpt
+set ta_report_auto_constraints $ta_report_auto
+
+#set ta_coverage_limit "0.95 0.90"
+set ta_dump_uncovered 1
+report_timing -verbose 1 -coverage >! $::alta_work/coverage.rpt.gz
+#unset ta_coverage_limit
+unset ta_dump_uncovered
+
+
+if { ! [info exists rt_report_timing_fast] } {
+  set rt_report_timing_fast false
+}
+if { $rt_report_timing_fast } {
+  set_timing_corner fast
+  route_delay -quiet
+  report_timing -verbose 2 -setup -file $::alta_work/setup_fast.rpt.gz
+  report_timing -verbose 2 -setup -brief -file $::alta_work/setup_fast_summary.rpt.gz
+  report_timing -verbose 2 -hold -file $::alta_work/hold_fast.rpt.gz
+  report_timing -verbose 2 -hold -brief -file $::alta_work/hold_fast_summary.rpt.gz
+  set ta_report_auto_constraints 0
+  report_timing -fmax -file $::alta_work/fmax_fast.rpt
+  report_timing -xfer -file $::alta_work/xfer_fast.rpt
+  set ta_report_auto_constraints $ta_report_auto
+}
+
+write_routed_design "${RESULT_DIR}/${RESULT}_routed.v"
+}
+
+bitgen normal -prg "${RESULT_DIR}/${RESULT}.prg" -bin "${RESULT_DIR}/${RESULT}.bin"
+bitgen sram -prg "${RESULT_DIR}/${RESULT}_sram.prg"
+bitgen download -bin "${RESULT_DIR}/${RESULT}.bin" -svf "${RESULT_DIR}/${RESULT}_download.svf"
+generate_binary -slave "${RESULT_DIR}/${RESULT}_slave.rbf" \
+                -inputs "${RESULT_DIR}/${RESULT}.bin" -reverse
+generate_binary -master "${RESULT_DIR}/${RESULT}_master.bin" \
+                -inputs "${RESULT_DIR}/${RESULT}.bin"
+generate_programming_file "${RESULT_DIR}/${RESULT}_master.bin" -prg "${RESULT_DIR}/${RESULT}_master.prg" \
+  -as "${RESULT_DIR}/${RESULT}_master_as.prg" -hybrid "${RESULT_DIR}/${RESULT}_hybrid.prg"
+}
+break
+}
+
+if { [file exists "./${DESIGN}.post.asf"] } {
+  alta::tcl_highlight "Using post-ASF file ${DESIGN}.post.asf.\n"
+  source "./${DESIGN}.post.asf"
+}
+date_time
+exit
+
diff --git a/hardware/portapack_h4m/CPLD/Supra/alta_db/alta.aqf b/hardware/portapack_h4m/CPLD/Supra/alta_db/alta.aqf
new file mode 100644
index 00000000..694cd105
--- /dev/null
+++ b/hardware/portapack_h4m/CPLD/Supra/alta_db/alta.aqf
@@ -0,0 +1,266 @@
+set_global_assignment -name DEVICE_IO_STANDARD "3.3-V LVCMOS"
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH BUS-HOLD"
+set_global_assignment -name ENABLE_DEVICE_WIDE_RESET "OFF"
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to SW_D
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to SW_L
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to SW_R
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to SW_U
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to SW_ROT_B
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to SW_SEL
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to SW_ROT_A
+set_instance_assignment -name SLOW_SLEW_RATE "ON" -to LCD_DB[15]
+set_instance_assignment -name SLOW_SLEW_RATE "ON" -to LCD_DB[14]
+set_instance_assignment -name SLOW_SLEW_RATE "ON" -to LCD_DB[13]
+set_instance_assignment -name SLOW_SLEW_RATE "ON" -to LCD_DB[12]
+set_instance_assignment -name SLOW_SLEW_RATE "ON" -to LCD_DB[11]
+set_instance_assignment -name SLOW_SLEW_RATE "ON" -to LCD_DB[10]
+set_instance_assignment -name SLOW_SLEW_RATE "ON" -to LCD_DB[9]
+set_instance_assignment -name SLOW_SLEW_RATE "ON" -to LCD_DB[8]
+set_instance_assignment -name SLOW_SLEW_RATE "ON" -to LCD_DB[7]
+set_instance_assignment -name SLOW_SLEW_RATE "ON" -to LCD_DB[6]
+set_instance_assignment -name SLOW_SLEW_RATE "ON" -to LCD_DB[5]
+set_instance_assignment -name SLOW_SLEW_RATE "ON" -to LCD_DB[4]
+set_instance_assignment -name SLOW_SLEW_RATE "ON" -to LCD_DB[3]
+set_instance_assignment -name SLOW_SLEW_RATE "ON" -to LCD_DB[2]
+set_instance_assignment -name SLOW_SLEW_RATE "ON" -to LCD_DB[1]
+set_instance_assignment -name SLOW_SLEW_RATE "ON" -to LCD_DB[0]
+set_instance_assignment -name SLOW_SLEW_RATE "ON" -to LCD_RDX
+set_instance_assignment -name SLOW_SLEW_RATE "ON" -to LCD_RESETX
+set_instance_assignment -name SLOW_SLEW_RATE "ON" -to LCD_RS
+set_instance_assignment -name SLOW_SLEW_RATE "ON" -to LCD_TE
+set_instance_assignment -name SLOW_SLEW_RATE "ON" -to LCD_WRX
+set_instance_assignment -name SLOW_SLEW_RATE "ON" -to MCU_ADDR
+set_instance_assignment -name SLOW_SLEW_RATE "ON" -to MCU_D[7]
+set_instance_assignment -name SLOW_SLEW_RATE "ON" -to MCU_D[6]
+set_instance_assignment -name SLOW_SLEW_RATE "ON" -to MCU_D[5]
+set_instance_assignment -name SLOW_SLEW_RATE "ON" -to MCU_D[4]
+set_instance_assignment -name SLOW_SLEW_RATE "ON" -to MCU_D[3]
+set_instance_assignment -name SLOW_SLEW_RATE "ON" -to MCU_D[2]
+set_instance_assignment -name SLOW_SLEW_RATE "ON" -to MCU_D[1]
+set_instance_assignment -name SLOW_SLEW_RATE "ON" -to MCU_D[0]
+set_instance_assignment -name SLOW_SLEW_RATE "ON" -to MCU_DIR
+set_instance_assignment -name SLOW_SLEW_RATE "ON" -to SW_D
+set_instance_assignment -name SLOW_SLEW_RATE "ON" -to SW_L
+set_instance_assignment -name SLOW_SLEW_RATE "ON" -to SW_R
+set_instance_assignment -name SLOW_SLEW_RATE "ON" -to SW_ROT_A
+set_instance_assignment -name SLOW_SLEW_RATE "ON" -to SW_ROT_B
+set_instance_assignment -name SLOW_SLEW_RATE "ON" -to SW_SEL
+set_instance_assignment -name SLOW_SLEW_RATE "ON" -to SW_U
+set_instance_assignment -name SLOW_SLEW_RATE "ON" -to TP_D
+set_instance_assignment -name SLOW_SLEW_RATE "ON" -to TP_L
+set_instance_assignment -name SLOW_SLEW_RATE "ON" -to TP_R
+set_instance_assignment -name SLOW_SLEW_RATE "ON" -to TP_U
+set_instance_assignment -name SLOW_SLEW_RATE "ON" -to LCD_BACKLIGHT
+set_instance_assignment -name SLOW_SLEW_RATE "ON" -to AUDIO_RESETX
+set_instance_assignment -name SLOW_SLEW_RATE "ON" -to MCU_LCD_RDX
+set_instance_assignment -name SLOW_SLEW_RATE "ON" -to MCU_LCD_WRX
+set_instance_assignment -name SLOW_SLEW_RATE "ON" -to MCU_IO_STBX
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to TP_R
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to TP_D
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to TP_L
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to TP_U
+set_instance_assignment -name SLOW_SLEW_RATE "ON" -to MCU_LCD_TE
+set_instance_assignment -name SLOW_SLEW_RATE "ON" -to MCU_P2_8
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to LCD_DB[15]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to LCD_DB[14]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to LCD_DB[13]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to LCD_DB[12]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to LCD_DB[11]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to LCD_DB[10]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to LCD_DB[9]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to LCD_DB[8]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to LCD_DB[7]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to LCD_DB[6]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to LCD_DB[5]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to LCD_DB[4]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to LCD_DB[3]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to LCD_DB[2]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to LCD_DB[1]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to LCD_DB[0]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to MCU_D[7]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to MCU_D[6]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to MCU_D[5]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to MCU_D[4]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to MCU_D[3]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to MCU_D[2]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to MCU_D[1]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to MCU_D[0]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to MCU_ADDR
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to MCU_DIR
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to MCU_IO_STBX
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to MCU_LCD_RDX
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR "OFF" -to MCU_LCD_WRX
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR "OFF" -to MCU_P2_8
+set_instance_assignment -name SLOW_SLEW_RATE "ON" -to GPS_TIMEPULSE
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to GPS_TIMEPULSE
+set_instance_assignment -name SLOW_SLEW_RATE "ON" -to GPS_TX_READY
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR "ON" -to GPS_TX_READY
+set_instance_assignment -name SLOW_SLEW_RATE "ON" -to REF_EN
+set_instance_assignment -name SLOW_SLEW_RATE "ON" -to GPS_RESETX
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR "OFF" -to SYSOFF
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AUDIO_RESETX
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DEVICE_RESET
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DEVICE_RESET_V
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to GPS_RESETX
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to GPS_TIMEPULSE
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to GPS_TX_READY
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_BACKLIGHT
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_DB[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_DB[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_DB[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_DB[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_DB[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_DB[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_DB[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_DB[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_DB[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_DB[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_DB[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_DB[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_DB[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_DB[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_DB[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_DB[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_RDX
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_RESETX
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_RS
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_TE
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_WRX
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_ADDR
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_DIR
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_D[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_IO_STBX
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_LCD_RDX
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_LCD_TE
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_LCD_WRX
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_P2_8
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to REF_EN
+set_instance_assignment -name IO_STANDARD "3.3V Schmitt Trigger Input" -to SW_D
+set_instance_assignment -name IO_STANDARD "3.3V Schmitt Trigger Input" -to SW_L
+set_instance_assignment -name IO_STANDARD "3.3V Schmitt Trigger Input" -to SW_R
+set_instance_assignment -name IO_STANDARD "3.3V Schmitt Trigger Input" -to SW_ROT_A
+set_instance_assignment -name IO_STANDARD "3.3V Schmitt Trigger Input" -to SW_ROT_B
+set_instance_assignment -name IO_STANDARD "3.3V Schmitt Trigger Input" -to SW_SEL
+set_instance_assignment -name IO_STANDARD "3.3V Schmitt Trigger Input" -to SW_U
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SYSOFF
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TP_D
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TP_L
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TP_R
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TP_U
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to AUDIO_RESETX
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to GPS_RESETX
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to GPS_TIMEPULSE
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to GPS_TX_READY
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_BACKLIGHT
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[0]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[10]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[11]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[12]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[13]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[14]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[15]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[1]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[2]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[3]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[4]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[5]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[6]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[7]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[8]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[9]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_RDX
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_RESETX
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_RS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_TE
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_WRX
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_ADDR
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_DIR
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_D[0]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_D[1]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_D[2]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_D[3]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_D[4]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_D[5]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_D[6]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_D[7]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_IO_STBX
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_LCD_RDX
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_LCD_TE
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_LCD_WRX
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_P2_8
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to REF_EN
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SW_D
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SW_L
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SW_R
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SW_ROT_A
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SW_ROT_B
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SW_SEL
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SW_U
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SYSOFF
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to TP_D
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to TP_L
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to TP_R
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to TP_U
+set_location_assignment PIN_57 -to AUDIO_RESETX
+set_location_assignment PIN_44 -to DEVICE_RESET
+set_location_assignment PIN_38 -to DEVICE_RESET_V
+set_location_assignment PIN_73 -to GPS_RESETX
+set_location_assignment PIN_74 -to GPS_TIMEPULSE
+set_location_assignment PIN_75 -to GPS_TX_READY
+set_location_assignment PIN_76 -to LCD_BACKLIGHT
+set_location_assignment PIN_99 -to LCD_DB[0]
+set_location_assignment PIN_87 -to LCD_DB[10]
+set_location_assignment PIN_86 -to LCD_DB[11]
+set_location_assignment PIN_85 -to LCD_DB[12]
+set_location_assignment PIN_84 -to LCD_DB[13]
+set_location_assignment PIN_83 -to LCD_DB[14]
+set_location_assignment PIN_82 -to LCD_DB[15]
+set_location_assignment PIN_98 -to LCD_DB[1]
+set_location_assignment PIN_97 -to LCD_DB[2]
+set_location_assignment PIN_96 -to LCD_DB[3]
+set_location_assignment PIN_95 -to LCD_DB[4]
+set_location_assignment PIN_92 -to LCD_DB[5]
+set_location_assignment PIN_91 -to LCD_DB[6]
+set_location_assignment PIN_90 -to LCD_DB[7]
+set_location_assignment PIN_89 -to LCD_DB[8]
+set_location_assignment PIN_88 -to LCD_DB[9]
+set_location_assignment PIN_1 -to LCD_RDX
+set_location_assignment PIN_100 -to LCD_RESETX
+set_location_assignment PIN_3 -to LCD_RS
+set_location_assignment PIN_4 -to LCD_TE
+set_location_assignment PIN_2 -to LCD_WRX
+set_location_assignment PIN_42 -to MCU_ADDR
+set_location_assignment PIN_72 -to MCU_DIR
+set_location_assignment PIN_35 -to MCU_D[0]
+set_location_assignment PIN_36 -to MCU_D[1]
+set_location_assignment PIN_33 -to MCU_D[2]
+set_location_assignment PIN_30 -to MCU_D[3]
+set_location_assignment PIN_28 -to MCU_D[4]
+set_location_assignment PIN_29 -to MCU_D[5]
+set_location_assignment PIN_27 -to MCU_D[6]
+set_location_assignment PIN_26 -to MCU_D[7]
+set_location_assignment PIN_41 -to MCU_IO_STBX
+set_location_assignment PIN_39 -to MCU_LCD_RDX
+set_location_assignment PIN_40 -to MCU_LCD_TE
+set_location_assignment PIN_71 -to MCU_LCD_WRX
+set_location_assignment PIN_43 -to MCU_P2_8
+set_location_assignment PIN_58 -to REF_EN
+set_location_assignment PIN_14 -to SW_D
+set_location_assignment PIN_37 -to SW_L
+set_location_assignment PIN_12 -to SW_R
+set_location_assignment PIN_15 -to SW_ROT_A
+set_location_assignment PIN_16 -to SW_ROT_B
+set_location_assignment PIN_17 -to SW_SEL
+set_location_assignment PIN_34 -to SW_U
+set_location_assignment PIN_47 -to SYSOFF
+set_location_assignment PIN_6 -to TP_D
+set_location_assignment PIN_7 -to TP_L
+set_location_assignment PIN_5 -to TP_R
+set_location_assignment PIN_8 -to TP_U
diff --git a/hardware/portapack_h4m/CPLD/Supra/alta_db/alta.asf b/hardware/portapack_h4m/CPLD/Supra/alta_db/alta.asf
new file mode 100644
index 00000000..36e9d5b1
--- /dev/null
+++ b/hardware/portapack_h4m/CPLD/Supra/alta_db/alta.asf
@@ -0,0 +1,38 @@
+set_instance_assignment -name ENABLE_OPEN_DRAIN -to TP_U~output false
+set_instance_assignment -name ENABLE_OPEN_DRAIN -to TP_L~output false
+set_instance_assignment -name ENABLE_OPEN_DRAIN -to TP_R~output false
+set_instance_assignment -name ENABLE_OPEN_DRAIN -to TP_D~output false
+set_instance_assignment -name ENABLE_OPEN_DRAIN -to MCU_D[1]~output false
+set_instance_assignment -name ENABLE_OPEN_DRAIN -to MCU_D[2]~output false
+set_instance_assignment -name ENABLE_OPEN_DRAIN -to MCU_D[0]~output false
+set_instance_assignment -name ENABLE_OPEN_DRAIN -to MCU_D[6]~output false
+set_instance_assignment -name ENABLE_OPEN_DRAIN -to MCU_D[7]~output false
+set_instance_assignment -name ENABLE_OPEN_DRAIN -to LCD_DB[8]~output false
+set_instance_assignment -name ENABLE_OPEN_DRAIN -to LCD_DB[0]~output false
+set_instance_assignment -name ENABLE_OPEN_DRAIN -to LCD_DB[6]~output false
+set_instance_assignment -name ENABLE_OPEN_DRAIN -to LCD_DB[14]~output false
+set_instance_assignment -name ENABLE_OPEN_DRAIN -to LCD_DB[15]~output false
+set_instance_assignment -name ENABLE_OPEN_DRAIN -to LCD_DB[7]~output false
+set_instance_assignment -name ENABLE_OPEN_DRAIN -to LCD_DB[1]~output false
+set_instance_assignment -name ENABLE_OPEN_DRAIN -to MCU_D[5]~output false
+set_instance_assignment -name ENABLE_OPEN_DRAIN -to MCU_D[3]~output false
+set_instance_assignment -name ENABLE_OPEN_DRAIN -to MCU_D[4]~output false
+set_instance_assignment -name ENABLE_OPEN_DRAIN -to LCD_DB[2]~output false
+set_instance_assignment -name ENABLE_OPEN_DRAIN -to LCD_DB[9]~output false
+set_instance_assignment -name ENABLE_OPEN_DRAIN -to LCD_DB[10]~output false
+set_instance_assignment -name ENABLE_OPEN_DRAIN -to LCD_DB[13]~output false
+set_instance_assignment -name ENABLE_OPEN_DRAIN -to LCD_DB[5]~output false
+set_instance_assignment -name ENABLE_OPEN_DRAIN -to LCD_DB[3]~output false
+set_instance_assignment -name ENABLE_OPEN_DRAIN -to LCD_DB[4]~output false
+set_instance_assignment -name ENABLE_OPEN_DRAIN -to LCD_DB[11]~output false
+set_instance_assignment -name ENABLE_OPEN_DRAIN -to LCD_DB[12]~output false
+set_instance_assignment -name ENABLE_OPEN_DRAIN -to LCD_RDX~output false
+set_instance_assignment -name ENABLE_OPEN_DRAIN -to LCD_WRX~output false
+set_instance_assignment -name ENABLE_OPEN_DRAIN -to LCD_RS~output false
+set_instance_assignment -name ENABLE_OPEN_DRAIN -to MCU_LCD_TE~output false
+set_instance_assignment -name ENABLE_OPEN_DRAIN -to LCD_RESETX~output false
+set_instance_assignment -name ENABLE_OPEN_DRAIN -to REF_EN~output false
+set_instance_assignment -name ENABLE_OPEN_DRAIN -to LCD_BACKLIGHT~output false
+set_instance_assignment -name ENABLE_OPEN_DRAIN -to SYSOFF~output false
+set_instance_assignment -name ENABLE_OPEN_DRAIN -to AUDIO_RESETX~output false
+set_instance_assignment -name ENABLE_OPEN_DRAIN -to GPS_RESETX~output false
diff --git a/hardware/portapack_h4m/CPLD/Supra/alta_db/alta.cellmap b/hardware/portapack_h4m/CPLD/Supra/alta_db/alta.cellmap
new file mode 100644
index 00000000..c5b6f4af
--- /dev/null
+++ b/hardware/portapack_h4m/CPLD/Supra/alta_db/alta.cellmap
@@ -0,0 +1,29 @@
+tp_q[3] clken_ctrl_X1_Y15_N0
+tp_q[4] clken_ctrl_X1_Y15_N0
+lcd_backlight_q clken_ctrl_X1_Y15_N1
+tp_q[0] clken_ctrl_X1_Y15_N0
+lcd_reset_q clken_ctrl_X1_Y15_N1
+tp_q[1] clken_ctrl_X1_Y15_N0
+audio_reset_q clken_ctrl_X1_Y15_N1
+tp_q[7] clken_ctrl_X1_Y15_N0
+tp_q[2] clken_ctrl_X1_Y15_N0
+tp_q[5] clken_ctrl_X1_Y15_N0
+ref_en_q clken_ctrl_X1_Y15_N1
+sysoff_q clken_ctrl_X1_Y15_N1
+tp_q[6] clken_ctrl_X1_Y15_N0
+lcd_data_in_q[0] clken_ctrl_X1_Y19_N0
+lcd_data_in_q[6] clken_ctrl_X1_Y19_N0
+lcd_data_out_q[1] clken_ctrl_X1_Y20_N0
+lcd_data_out_q[2] clken_ctrl_X1_Y20_N0
+lcd_data_out_q[6] clken_ctrl_X1_Y20_N0
+lcd_data_out_q[7] clken_ctrl_X1_Y20_N0
+lcd_data_out_q[0] clken_ctrl_X1_Y20_N0
+lcd_data_in_q[7] clken_ctrl_X1_Y21_N0
+lcd_data_in_q[1] clken_ctrl_X1_Y21_N0
+lcd_data_in_q[2] clken_ctrl_X1_Y24_N0
+lcd_data_in_q[4] clken_ctrl_X1_Y26_N0
+lcd_data_out_q[4] clken_ctrl_X1_Y26_N1
+lcd_data_out_q[3] clken_ctrl_X1_Y26_N1
+lcd_data_out_q[5] clken_ctrl_X1_Y26_N1
+lcd_data_in_q[3] clken_ctrl_X1_Y26_N0
+lcd_data_in_q[5] clken_ctrl_X1_Y26_N0
diff --git a/hardware/portapack_h4m/CPLD/Supra/alta_db/alta.pinmap b/hardware/portapack_h4m/CPLD/Supra/alta_db/alta.pinmap
new file mode 100644
index 00000000..9a3d413a
--- /dev/null
+++ b/hardware/portapack_h4m/CPLD/Supra/alta_db/alta.pinmap
@@ -0,0 +1,859 @@
+SW_L~input|datain SW_L~input|datain
+SW_L~input|oe SW_L~input|oe
+SW_L~input|outclk SW_L~input|outclk
+SW_L~input|outclkena SW_L~input|outclkena
+SW_L~input|inclk SW_L~input|inclk
+SW_L~input|inclkena SW_L~input|inclkena
+SW_L~input|areset SW_L~input|areset
+SW_L~input|sreset SW_L~input|sreset
+SW_L~input|combout SW_L~input|combout
+SW_L~input|padio SW_L~input|padio
+SW_R~input|datain SW_R~input|datain
+SW_R~input|oe SW_R~input|oe
+SW_R~input|outclk SW_R~input|outclk
+SW_R~input|outclkena SW_R~input|outclkena
+SW_R~input|inclk SW_R~input|inclk
+SW_R~input|inclkena SW_R~input|inclkena
+SW_R~input|areset SW_R~input|areset
+SW_R~input|sreset SW_R~input|sreset
+SW_R~input|combout SW_R~input|combout
+SW_R~input|padio SW_R~input|padio
+TP_U~output|datain TP_U~output|datain
+TP_U~output|oe TP_U~output|oe
+TP_U~output|outclk TP_U~output|outclk
+TP_U~output|outclkena TP_U~output|outclkena
+TP_U~output|inclk TP_U~output|inclk
+TP_U~output|inclkena TP_U~output|inclkena
+TP_U~output|areset TP_U~output|areset
+TP_U~output|sreset TP_U~output|sreset
+TP_U~output|padio TP_U~output|padio
+TP_L~output|datain TP_L~output|datain
+TP_L~output|oe TP_L~output|oe
+TP_L~output|outclk TP_L~output|outclk
+TP_L~output|outclkena TP_L~output|outclkena
+TP_L~output|inclk TP_L~output|inclk
+TP_L~output|inclkena TP_L~output|inclkena
+TP_L~output|areset TP_L~output|areset
+TP_L~output|sreset TP_L~output|sreset
+TP_L~output|padio TP_L~output|padio
+SW_ROT_B~input|datain SW_ROT_B~input|datain
+SW_ROT_B~input|oe SW_ROT_B~input|oe
+SW_ROT_B~input|outclk SW_ROT_B~input|outclk
+SW_ROT_B~input|outclkena SW_ROT_B~input|outclkena
+SW_ROT_B~input|inclk SW_ROT_B~input|inclk
+SW_ROT_B~input|inclkena SW_ROT_B~input|inclkena
+SW_ROT_B~input|areset SW_ROT_B~input|areset
+SW_ROT_B~input|sreset SW_ROT_B~input|sreset
+SW_ROT_B~input|combout SW_ROT_B~input|combout
+SW_ROT_B~input|padio SW_ROT_B~input|padio
+TP_R~output|datain TP_R~output|datain
+TP_R~output|oe TP_R~output|oe
+TP_R~output|outclk TP_R~output|outclk
+TP_R~output|outclkena TP_R~output|outclkena
+TP_R~output|inclk TP_R~output|inclk
+TP_R~output|inclkena TP_R~output|inclkena
+TP_R~output|areset TP_R~output|areset
+TP_R~output|sreset TP_R~output|sreset
+TP_R~output|padio TP_R~output|padio
+TP_D~output|datain TP_D~output|datain
+TP_D~output|oe TP_D~output|oe
+TP_D~output|outclk TP_D~output|outclk
+TP_D~output|outclkena TP_D~output|outclkena
+TP_D~output|inclk TP_D~output|inclk
+TP_D~output|inclkena TP_D~output|inclkena
+TP_D~output|areset TP_D~output|areset
+TP_D~output|sreset TP_D~output|sreset
+TP_D~output|padio TP_D~output|padio
+MCU_D[1]~output|datain MCU_D[1]~output|datain
+MCU_D[1]~output|oe MCU_D[1]~output|oe
+MCU_D[1]~output|outclk MCU_D[1]~output|outclk
+MCU_D[1]~output|outclkena MCU_D[1]~output|outclkena
+MCU_D[1]~output|inclk MCU_D[1]~output|inclk
+MCU_D[1]~output|inclkena MCU_D[1]~output|inclkena
+MCU_D[1]~output|areset MCU_D[1]~output|areset
+MCU_D[1]~output|sreset MCU_D[1]~output|sreset
+MCU_D[1]~output|combout MCU_D[1]~output|combout
+MCU_D[1]~output|padio MCU_D[1]~output|padio
+MCU_D[2]~output|datain MCU_D[2]~output|datain
+MCU_D[2]~output|oe MCU_D[2]~output|oe
+MCU_D[2]~output|outclk MCU_D[2]~output|outclk
+MCU_D[2]~output|outclkena MCU_D[2]~output|outclkena
+MCU_D[2]~output|inclk MCU_D[2]~output|inclk
+MCU_D[2]~output|inclkena MCU_D[2]~output|inclkena
+MCU_D[2]~output|areset MCU_D[2]~output|areset
+MCU_D[2]~output|sreset MCU_D[2]~output|sreset
+MCU_D[2]~output|combout MCU_D[2]~output|combout
+MCU_D[2]~output|padio MCU_D[2]~output|padio
+MCU_DIR~input|datain MCU_DIR~input|datain
+MCU_DIR~input|oe MCU_DIR~input|oe
+MCU_DIR~input|outclk MCU_DIR~input|outclk
+MCU_DIR~input|outclkena MCU_DIR~input|outclkena
+MCU_DIR~input|inclk MCU_DIR~input|inclk
+MCU_DIR~input|inclkena MCU_DIR~input|inclkena
+MCU_DIR~input|areset MCU_DIR~input|areset
+MCU_DIR~input|sreset MCU_DIR~input|sreset
+MCU_DIR~input|combout MCU_DIR~input|combout
+MCU_DIR~input|padio MCU_DIR~input|padio
+MCU_D[0]~output|datain MCU_D[0]~output|datain
+MCU_D[0]~output|oe MCU_D[0]~output|oe
+MCU_D[0]~output|outclk MCU_D[0]~output|outclk
+MCU_D[0]~output|outclkena MCU_D[0]~output|outclkena
+MCU_D[0]~output|inclk MCU_D[0]~output|inclk
+MCU_D[0]~output|inclkena MCU_D[0]~output|inclkena
+MCU_D[0]~output|areset MCU_D[0]~output|areset
+MCU_D[0]~output|sreset MCU_D[0]~output|sreset
+MCU_D[0]~output|combout MCU_D[0]~output|combout
+MCU_D[0]~output|padio MCU_D[0]~output|padio
+MCU_D[6]~output|datain MCU_D[6]~output|datain
+MCU_D[6]~output|oe MCU_D[6]~output|oe
+MCU_D[6]~output|outclk MCU_D[6]~output|outclk
+MCU_D[6]~output|outclkena MCU_D[6]~output|outclkena
+MCU_D[6]~output|inclk MCU_D[6]~output|inclk
+MCU_D[6]~output|inclkena MCU_D[6]~output|inclkena
+MCU_D[6]~output|areset MCU_D[6]~output|areset
+MCU_D[6]~output|sreset MCU_D[6]~output|sreset
+MCU_D[6]~output|combout MCU_D[6]~output|combout
+MCU_D[6]~output|padio MCU_D[6]~output|padio
+MCU_D[7]~output|datain MCU_D[7]~output|datain
+MCU_D[7]~output|oe MCU_D[7]~output|oe
+MCU_D[7]~output|outclk MCU_D[7]~output|outclk
+MCU_D[7]~output|outclkena MCU_D[7]~output|outclkena
+MCU_D[7]~output|inclk MCU_D[7]~output|inclk
+MCU_D[7]~output|inclkena MCU_D[7]~output|inclkena
+MCU_D[7]~output|areset MCU_D[7]~output|areset
+MCU_D[7]~output|sreset MCU_D[7]~output|sreset
+MCU_D[7]~output|combout MCU_D[7]~output|combout
+MCU_D[7]~output|padio MCU_D[7]~output|padio
+LCD_DB[8]~output|datain LCD_DB[8]~output|datain
+LCD_DB[8]~output|oe LCD_DB[8]~output|oe
+LCD_DB[8]~output|outclk LCD_DB[8]~output|outclk
+LCD_DB[8]~output|outclkena LCD_DB[8]~output|outclkena
+LCD_DB[8]~output|inclk LCD_DB[8]~output|inclk
+LCD_DB[8]~output|inclkena LCD_DB[8]~output|inclkena
+LCD_DB[8]~output|areset LCD_DB[8]~output|areset
+LCD_DB[8]~output|sreset LCD_DB[8]~output|sreset
+LCD_DB[8]~output|combout LCD_DB[8]~output|combout
+LCD_DB[8]~output|padio LCD_DB[8]~output|padio
+LCD_DB[0]~output|datain LCD_DB[0]~output|datain
+LCD_DB[0]~output|oe LCD_DB[0]~output|oe
+LCD_DB[0]~output|outclk LCD_DB[0]~output|outclk
+LCD_DB[0]~output|outclkena LCD_DB[0]~output|outclkena
+LCD_DB[0]~output|inclk LCD_DB[0]~output|inclk
+LCD_DB[0]~output|inclkena LCD_DB[0]~output|inclkena
+LCD_DB[0]~output|areset LCD_DB[0]~output|areset
+LCD_DB[0]~output|sreset LCD_DB[0]~output|sreset
+LCD_DB[0]~output|combout LCD_DB[0]~output|combout
+LCD_DB[0]~output|padio LCD_DB[0]~output|padio
+LCD_DB[6]~output|datain LCD_DB[6]~output|datain
+LCD_DB[6]~output|oe LCD_DB[6]~output|oe
+LCD_DB[6]~output|outclk LCD_DB[6]~output|outclk
+LCD_DB[6]~output|outclkena LCD_DB[6]~output|outclkena
+LCD_DB[6]~output|inclk LCD_DB[6]~output|inclk
+LCD_DB[6]~output|inclkena LCD_DB[6]~output|inclkena
+LCD_DB[6]~output|areset LCD_DB[6]~output|areset
+LCD_DB[6]~output|sreset LCD_DB[6]~output|sreset
+LCD_DB[6]~output|combout LCD_DB[6]~output|combout
+LCD_DB[6]~output|padio LCD_DB[6]~output|padio
+LCD_DB[14]~output|datain LCD_DB[14]~output|datain
+LCD_DB[14]~output|oe LCD_DB[14]~output|oe
+LCD_DB[14]~output|outclk LCD_DB[14]~output|outclk
+LCD_DB[14]~output|outclkena LCD_DB[14]~output|outclkena
+LCD_DB[14]~output|inclk LCD_DB[14]~output|inclk
+LCD_DB[14]~output|inclkena LCD_DB[14]~output|inclkena
+LCD_DB[14]~output|areset LCD_DB[14]~output|areset
+LCD_DB[14]~output|sreset LCD_DB[14]~output|sreset
+LCD_DB[14]~output|combout LCD_DB[14]~output|combout
+LCD_DB[14]~output|padio LCD_DB[14]~output|padio
+LCD_DB[15]~output|datain LCD_DB[15]~output|datain
+LCD_DB[15]~output|oe LCD_DB[15]~output|oe
+LCD_DB[15]~output|outclk LCD_DB[15]~output|outclk
+LCD_DB[15]~output|outclkena LCD_DB[15]~output|outclkena
+LCD_DB[15]~output|inclk LCD_DB[15]~output|inclk
+LCD_DB[15]~output|inclkena LCD_DB[15]~output|inclkena
+LCD_DB[15]~output|areset LCD_DB[15]~output|areset
+LCD_DB[15]~output|sreset LCD_DB[15]~output|sreset
+LCD_DB[15]~output|combout LCD_DB[15]~output|combout
+LCD_DB[15]~output|padio LCD_DB[15]~output|padio
+LCD_DB[7]~output|datain LCD_DB[7]~output|datain
+LCD_DB[7]~output|oe LCD_DB[7]~output|oe
+LCD_DB[7]~output|outclk LCD_DB[7]~output|outclk
+LCD_DB[7]~output|outclkena LCD_DB[7]~output|outclkena
+LCD_DB[7]~output|inclk LCD_DB[7]~output|inclk
+LCD_DB[7]~output|inclkena LCD_DB[7]~output|inclkena
+LCD_DB[7]~output|areset LCD_DB[7]~output|areset
+LCD_DB[7]~output|sreset LCD_DB[7]~output|sreset
+LCD_DB[7]~output|combout LCD_DB[7]~output|combout
+LCD_DB[7]~output|padio LCD_DB[7]~output|padio
+LCD_DB[1]~output|datain LCD_DB[1]~output|datain
+LCD_DB[1]~output|oe LCD_DB[1]~output|oe
+LCD_DB[1]~output|outclk LCD_DB[1]~output|outclk
+LCD_DB[1]~output|outclkena LCD_DB[1]~output|outclkena
+LCD_DB[1]~output|inclk LCD_DB[1]~output|inclk
+LCD_DB[1]~output|inclkena LCD_DB[1]~output|inclkena
+LCD_DB[1]~output|areset LCD_DB[1]~output|areset
+LCD_DB[1]~output|sreset LCD_DB[1]~output|sreset
+LCD_DB[1]~output|combout LCD_DB[1]~output|combout
+LCD_DB[1]~output|padio LCD_DB[1]~output|padio
+MCU_D[5]~output|datain MCU_D[5]~output|datain
+MCU_D[5]~output|oe MCU_D[5]~output|oe
+MCU_D[5]~output|outclk MCU_D[5]~output|outclk
+MCU_D[5]~output|outclkena MCU_D[5]~output|outclkena
+MCU_D[5]~output|inclk MCU_D[5]~output|inclk
+MCU_D[5]~output|inclkena MCU_D[5]~output|inclkena
+MCU_D[5]~output|areset MCU_D[5]~output|areset
+MCU_D[5]~output|sreset MCU_D[5]~output|sreset
+MCU_D[5]~output|combout MCU_D[5]~output|combout
+MCU_D[5]~output|padio MCU_D[5]~output|padio
+MCU_D[3]~output|datain MCU_D[3]~output|datain
+MCU_D[3]~output|oe MCU_D[3]~output|oe
+MCU_D[3]~output|outclk MCU_D[3]~output|outclk
+MCU_D[3]~output|outclkena MCU_D[3]~output|outclkena
+MCU_D[3]~output|inclk MCU_D[3]~output|inclk
+MCU_D[3]~output|inclkena MCU_D[3]~output|inclkena
+MCU_D[3]~output|areset MCU_D[3]~output|areset
+MCU_D[3]~output|sreset MCU_D[3]~output|sreset
+MCU_D[3]~output|combout MCU_D[3]~output|combout
+MCU_D[3]~output|padio MCU_D[3]~output|padio
+MCU_D[4]~output|datain MCU_D[4]~output|datain
+MCU_D[4]~output|oe MCU_D[4]~output|oe
+MCU_D[4]~output|outclk MCU_D[4]~output|outclk
+MCU_D[4]~output|outclkena MCU_D[4]~output|outclkena
+MCU_D[4]~output|inclk MCU_D[4]~output|inclk
+MCU_D[4]~output|inclkena MCU_D[4]~output|inclkena
+MCU_D[4]~output|areset MCU_D[4]~output|areset
+MCU_D[4]~output|sreset MCU_D[4]~output|sreset
+MCU_D[4]~output|combout MCU_D[4]~output|combout
+MCU_D[4]~output|padio MCU_D[4]~output|padio
+LCD_DB[2]~output|datain LCD_DB[2]~output|datain
+LCD_DB[2]~output|oe LCD_DB[2]~output|oe
+LCD_DB[2]~output|outclk LCD_DB[2]~output|outclk
+LCD_DB[2]~output|outclkena LCD_DB[2]~output|outclkena
+LCD_DB[2]~output|inclk LCD_DB[2]~output|inclk
+LCD_DB[2]~output|inclkena LCD_DB[2]~output|inclkena
+LCD_DB[2]~output|areset LCD_DB[2]~output|areset
+LCD_DB[2]~output|sreset LCD_DB[2]~output|sreset
+LCD_DB[2]~output|combout LCD_DB[2]~output|combout
+LCD_DB[2]~output|padio LCD_DB[2]~output|padio
+LCD_DB[9]~output|datain LCD_DB[9]~output|datain
+LCD_DB[9]~output|oe LCD_DB[9]~output|oe
+LCD_DB[9]~output|outclk LCD_DB[9]~output|outclk
+LCD_DB[9]~output|outclkena LCD_DB[9]~output|outclkena
+LCD_DB[9]~output|inclk LCD_DB[9]~output|inclk
+LCD_DB[9]~output|inclkena LCD_DB[9]~output|inclkena
+LCD_DB[9]~output|areset LCD_DB[9]~output|areset
+LCD_DB[9]~output|sreset LCD_DB[9]~output|sreset
+LCD_DB[9]~output|combout LCD_DB[9]~output|combout
+LCD_DB[9]~output|padio LCD_DB[9]~output|padio
+LCD_DB[10]~output|datain LCD_DB[10]~output|datain
+LCD_DB[10]~output|oe LCD_DB[10]~output|oe
+LCD_DB[10]~output|outclk LCD_DB[10]~output|outclk
+LCD_DB[10]~output|outclkena LCD_DB[10]~output|outclkena
+LCD_DB[10]~output|inclk LCD_DB[10]~output|inclk
+LCD_DB[10]~output|inclkena LCD_DB[10]~output|inclkena
+LCD_DB[10]~output|areset LCD_DB[10]~output|areset
+LCD_DB[10]~output|sreset LCD_DB[10]~output|sreset
+LCD_DB[10]~output|combout LCD_DB[10]~output|combout
+LCD_DB[10]~output|padio LCD_DB[10]~output|padio
+SW_D~input|datain SW_D~input|datain
+SW_D~input|oe SW_D~input|oe
+SW_D~input|outclk SW_D~input|outclk
+SW_D~input|outclkena SW_D~input|outclkena
+SW_D~input|inclk SW_D~input|inclk
+SW_D~input|inclkena SW_D~input|inclkena
+SW_D~input|areset SW_D~input|areset
+SW_D~input|sreset SW_D~input|sreset
+SW_D~input|combout SW_D~input|combout
+SW_D~input|padio SW_D~input|padio
+LCD_DB[13]~output|datain LCD_DB[13]~output|datain
+LCD_DB[13]~output|oe LCD_DB[13]~output|oe
+LCD_DB[13]~output|outclk LCD_DB[13]~output|outclk
+LCD_DB[13]~output|outclkena LCD_DB[13]~output|outclkena
+LCD_DB[13]~output|inclk LCD_DB[13]~output|inclk
+LCD_DB[13]~output|inclkena LCD_DB[13]~output|inclkena
+LCD_DB[13]~output|areset LCD_DB[13]~output|areset
+LCD_DB[13]~output|sreset LCD_DB[13]~output|sreset
+LCD_DB[13]~output|combout LCD_DB[13]~output|combout
+LCD_DB[13]~output|padio LCD_DB[13]~output|padio
+LCD_DB[5]~output|datain LCD_DB[5]~output|datain
+LCD_DB[5]~output|oe LCD_DB[5]~output|oe
+LCD_DB[5]~output|outclk LCD_DB[5]~output|outclk
+LCD_DB[5]~output|outclkena LCD_DB[5]~output|outclkena
+LCD_DB[5]~output|inclk LCD_DB[5]~output|inclk
+LCD_DB[5]~output|inclkena LCD_DB[5]~output|inclkena
+LCD_DB[5]~output|areset LCD_DB[5]~output|areset
+LCD_DB[5]~output|sreset LCD_DB[5]~output|sreset
+LCD_DB[5]~output|combout LCD_DB[5]~output|combout
+LCD_DB[5]~output|padio LCD_DB[5]~output|padio
+LCD_DB[3]~output|datain LCD_DB[3]~output|datain
+LCD_DB[3]~output|oe LCD_DB[3]~output|oe
+LCD_DB[3]~output|outclk LCD_DB[3]~output|outclk
+LCD_DB[3]~output|outclkena LCD_DB[3]~output|outclkena
+LCD_DB[3]~output|inclk LCD_DB[3]~output|inclk
+LCD_DB[3]~output|inclkena LCD_DB[3]~output|inclkena
+LCD_DB[3]~output|areset LCD_DB[3]~output|areset
+LCD_DB[3]~output|sreset LCD_DB[3]~output|sreset
+LCD_DB[3]~output|combout LCD_DB[3]~output|combout
+LCD_DB[3]~output|padio LCD_DB[3]~output|padio
+LCD_DB[4]~output|datain LCD_DB[4]~output|datain
+LCD_DB[4]~output|oe LCD_DB[4]~output|oe
+LCD_DB[4]~output|outclk LCD_DB[4]~output|outclk
+LCD_DB[4]~output|outclkena LCD_DB[4]~output|outclkena
+LCD_DB[4]~output|inclk LCD_DB[4]~output|inclk
+LCD_DB[4]~output|inclkena LCD_DB[4]~output|inclkena
+LCD_DB[4]~output|areset LCD_DB[4]~output|areset
+LCD_DB[4]~output|sreset LCD_DB[4]~output|sreset
+LCD_DB[4]~output|combout LCD_DB[4]~output|combout
+LCD_DB[4]~output|padio LCD_DB[4]~output|padio
+SW_ROT_A~input|datain SW_ROT_A~input|datain
+SW_ROT_A~input|oe SW_ROT_A~input|oe
+SW_ROT_A~input|outclk SW_ROT_A~input|outclk
+SW_ROT_A~input|outclkena SW_ROT_A~input|outclkena
+SW_ROT_A~input|inclk SW_ROT_A~input|inclk
+SW_ROT_A~input|inclkena SW_ROT_A~input|inclkena
+SW_ROT_A~input|areset SW_ROT_A~input|areset
+SW_ROT_A~input|sreset SW_ROT_A~input|sreset
+SW_ROT_A~input|combout SW_ROT_A~input|combout
+SW_ROT_A~input|padio SW_ROT_A~input|padio
+SW_U~input|datain SW_U~input|datain
+SW_U~input|oe SW_U~input|oe
+SW_U~input|outclk SW_U~input|outclk
+SW_U~input|outclkena SW_U~input|outclkena
+SW_U~input|inclk SW_U~input|inclk
+SW_U~input|inclkena SW_U~input|inclkena
+SW_U~input|areset SW_U~input|areset
+SW_U~input|sreset SW_U~input|sreset
+SW_U~input|combout SW_U~input|combout
+SW_U~input|padio SW_U~input|padio
+LCD_DB[11]~output|datain LCD_DB[11]~output|datain
+LCD_DB[11]~output|oe LCD_DB[11]~output|oe
+LCD_DB[11]~output|outclk LCD_DB[11]~output|outclk
+LCD_DB[11]~output|outclkena LCD_DB[11]~output|outclkena
+LCD_DB[11]~output|inclk LCD_DB[11]~output|inclk
+LCD_DB[11]~output|inclkena LCD_DB[11]~output|inclkena
+LCD_DB[11]~output|areset LCD_DB[11]~output|areset
+LCD_DB[11]~output|sreset LCD_DB[11]~output|sreset
+LCD_DB[11]~output|combout LCD_DB[11]~output|combout
+LCD_DB[11]~output|padio LCD_DB[11]~output|padio
+LCD_DB[12]~output|datain LCD_DB[12]~output|datain
+LCD_DB[12]~output|oe LCD_DB[12]~output|oe
+LCD_DB[12]~output|outclk LCD_DB[12]~output|outclk
+LCD_DB[12]~output|outclkena LCD_DB[12]~output|outclkena
+LCD_DB[12]~output|inclk LCD_DB[12]~output|inclk
+LCD_DB[12]~output|inclkena LCD_DB[12]~output|inclkena
+LCD_DB[12]~output|areset LCD_DB[12]~output|areset
+LCD_DB[12]~output|sreset LCD_DB[12]~output|sreset
+LCD_DB[12]~output|combout LCD_DB[12]~output|combout
+LCD_DB[12]~output|padio LCD_DB[12]~output|padio
+LCD_RDX~output|datain LCD_RDX~output|datain
+LCD_RDX~output|oe LCD_RDX~output|oe
+LCD_RDX~output|outclk LCD_RDX~output|outclk
+LCD_RDX~output|outclkena LCD_RDX~output|outclkena
+LCD_RDX~output|inclk LCD_RDX~output|inclk
+LCD_RDX~output|inclkena LCD_RDX~output|inclkena
+LCD_RDX~output|areset LCD_RDX~output|areset
+LCD_RDX~output|sreset LCD_RDX~output|sreset
+LCD_RDX~output|padio LCD_RDX~output|padio
+SW_SEL~input|datain SW_SEL~input|datain
+SW_SEL~input|oe SW_SEL~input|oe
+SW_SEL~input|outclk SW_SEL~input|outclk
+SW_SEL~input|outclkena SW_SEL~input|outclkena
+SW_SEL~input|inclk SW_SEL~input|inclk
+SW_SEL~input|inclkena SW_SEL~input|inclkena
+SW_SEL~input|areset SW_SEL~input|areset
+SW_SEL~input|sreset SW_SEL~input|sreset
+SW_SEL~input|combout SW_SEL~input|combout
+SW_SEL~input|padio SW_SEL~input|padio
+MCU_IO_STBX~input|datain MCU_IO_STBX~input|datain
+MCU_IO_STBX~input|oe MCU_IO_STBX~input|oe
+MCU_IO_STBX~input|outclk MCU_IO_STBX~input|outclk
+MCU_IO_STBX~input|outclkena MCU_IO_STBX~input|outclkena
+MCU_IO_STBX~input|inclk MCU_IO_STBX~input|inclk
+MCU_IO_STBX~input|inclkena MCU_IO_STBX~input|inclkena
+MCU_IO_STBX~input|areset MCU_IO_STBX~input|areset
+MCU_IO_STBX~input|sreset MCU_IO_STBX~input|sreset
+MCU_IO_STBX~input|combout MCU_IO_STBX~input|combout
+MCU_IO_STBX~input|padio MCU_IO_STBX~input|padio
+MCU_LCD_RDX~input|datain MCU_LCD_RDX~input|datain
+MCU_LCD_RDX~input|oe MCU_LCD_RDX~input|oe
+MCU_LCD_RDX~input|outclk MCU_LCD_RDX~input|outclk
+MCU_LCD_RDX~input|outclkena MCU_LCD_RDX~input|outclkena
+MCU_LCD_RDX~input|inclk MCU_LCD_RDX~input|inclk
+MCU_LCD_RDX~input|inclkena MCU_LCD_RDX~input|inclkena
+MCU_LCD_RDX~input|areset MCU_LCD_RDX~input|areset
+MCU_LCD_RDX~input|sreset MCU_LCD_RDX~input|sreset
+MCU_LCD_RDX~input|combout MCU_LCD_RDX~input|combout
+MCU_LCD_RDX~input|padio MCU_LCD_RDX~input|padio
+MCU_LCD_WRX~input|datain MCU_LCD_WRX~input|datain
+MCU_LCD_WRX~input|oe MCU_LCD_WRX~input|oe
+MCU_LCD_WRX~input|outclk MCU_LCD_WRX~input|outclk
+MCU_LCD_WRX~input|outclkena MCU_LCD_WRX~input|outclkena
+MCU_LCD_WRX~input|inclk MCU_LCD_WRX~input|inclk
+MCU_LCD_WRX~input|inclkena MCU_LCD_WRX~input|inclkena
+MCU_LCD_WRX~input|areset MCU_LCD_WRX~input|areset
+MCU_LCD_WRX~input|sreset MCU_LCD_WRX~input|sreset
+MCU_LCD_WRX~input|combout MCU_LCD_WRX~input|combout
+MCU_LCD_WRX~input|padio MCU_LCD_WRX~input|padio
+LCD_WRX~output|datain LCD_WRX~output|datain
+LCD_WRX~output|oe LCD_WRX~output|oe
+LCD_WRX~output|outclk LCD_WRX~output|outclk
+LCD_WRX~output|outclkena LCD_WRX~output|outclkena
+LCD_WRX~output|inclk LCD_WRX~output|inclk
+LCD_WRX~output|inclkena LCD_WRX~output|inclkena
+LCD_WRX~output|areset LCD_WRX~output|areset
+LCD_WRX~output|sreset LCD_WRX~output|sreset
+LCD_WRX~output|padio LCD_WRX~output|padio
+LCD_RS~output|datain LCD_RS~output|datain
+LCD_RS~output|oe LCD_RS~output|oe
+LCD_RS~output|outclk LCD_RS~output|outclk
+LCD_RS~output|outclkena LCD_RS~output|outclkena
+LCD_RS~output|inclk LCD_RS~output|inclk
+LCD_RS~output|inclkena LCD_RS~output|inclkena
+LCD_RS~output|areset LCD_RS~output|areset
+LCD_RS~output|sreset LCD_RS~output|sreset
+LCD_RS~output|padio LCD_RS~output|padio
+MCU_ADDR~input|datain MCU_ADDR~input|datain
+MCU_ADDR~input|oe MCU_ADDR~input|oe
+MCU_ADDR~input|outclk MCU_ADDR~input|outclk
+MCU_ADDR~input|outclkena MCU_ADDR~input|outclkena
+MCU_ADDR~input|inclk MCU_ADDR~input|inclk
+MCU_ADDR~input|inclkena MCU_ADDR~input|inclkena
+MCU_ADDR~input|areset MCU_ADDR~input|areset
+MCU_ADDR~input|sreset MCU_ADDR~input|sreset
+MCU_ADDR~input|combout MCU_ADDR~input|combout
+MCU_ADDR~input|padio MCU_ADDR~input|padio
+MCU_LCD_TE~output|datain MCU_LCD_TE~output|datain
+MCU_LCD_TE~output|oe MCU_LCD_TE~output|oe
+MCU_LCD_TE~output|outclk MCU_LCD_TE~output|outclk
+MCU_LCD_TE~output|outclkena MCU_LCD_TE~output|outclkena
+MCU_LCD_TE~output|inclk MCU_LCD_TE~output|inclk
+MCU_LCD_TE~output|inclkena MCU_LCD_TE~output|inclkena
+MCU_LCD_TE~output|areset MCU_LCD_TE~output|areset
+MCU_LCD_TE~output|sreset MCU_LCD_TE~output|sreset
+MCU_LCD_TE~output|padio MCU_LCD_TE~output|padio
+LCD_TE~input|datain LCD_TE~input|datain
+LCD_TE~input|oe LCD_TE~input|oe
+LCD_TE~input|outclk LCD_TE~input|outclk
+LCD_TE~input|outclkena LCD_TE~input|outclkena
+LCD_TE~input|inclk LCD_TE~input|inclk
+LCD_TE~input|inclkena LCD_TE~input|inclkena
+LCD_TE~input|areset LCD_TE~input|areset
+LCD_TE~input|sreset LCD_TE~input|sreset
+LCD_TE~input|combout LCD_TE~input|combout
+LCD_TE~input|padio LCD_TE~input|padio
+LCD_RESETX~output|datain LCD_RESETX~output|datain
+LCD_RESETX~output|oe LCD_RESETX~output|oe
+LCD_RESETX~output|outclk LCD_RESETX~output|outclk
+LCD_RESETX~output|outclkena LCD_RESETX~output|outclkena
+LCD_RESETX~output|inclk LCD_RESETX~output|inclk
+LCD_RESETX~output|inclkena LCD_RESETX~output|inclkena
+LCD_RESETX~output|areset LCD_RESETX~output|areset
+LCD_RESETX~output|sreset LCD_RESETX~output|sreset
+LCD_RESETX~output|padio LCD_RESETX~output|padio
+REF_EN~output|datain REF_EN~output|datain
+REF_EN~output|oe REF_EN~output|oe
+REF_EN~output|outclk REF_EN~output|outclk
+REF_EN~output|outclkena REF_EN~output|outclkena
+REF_EN~output|inclk REF_EN~output|inclk
+REF_EN~output|inclkena REF_EN~output|inclkena
+REF_EN~output|areset REF_EN~output|areset
+REF_EN~output|sreset REF_EN~output|sreset
+REF_EN~output|padio REF_EN~output|padio
+LCD_BACKLIGHT~output|datain LCD_BACKLIGHT~output|datain
+LCD_BACKLIGHT~output|oe LCD_BACKLIGHT~output|oe
+LCD_BACKLIGHT~output|outclk LCD_BACKLIGHT~output|outclk
+LCD_BACKLIGHT~output|outclkena LCD_BACKLIGHT~output|outclkena
+LCD_BACKLIGHT~output|inclk LCD_BACKLIGHT~output|inclk
+LCD_BACKLIGHT~output|inclkena LCD_BACKLIGHT~output|inclkena
+LCD_BACKLIGHT~output|areset LCD_BACKLIGHT~output|areset
+LCD_BACKLIGHT~output|sreset LCD_BACKLIGHT~output|sreset
+LCD_BACKLIGHT~output|padio LCD_BACKLIGHT~output|padio
+SYSOFF~output|datain SYSOFF~output|datain
+SYSOFF~output|oe SYSOFF~output|oe
+SYSOFF~output|outclk SYSOFF~output|outclk
+SYSOFF~output|outclkena SYSOFF~output|outclkena
+SYSOFF~output|inclk SYSOFF~output|inclk
+SYSOFF~output|inclkena SYSOFF~output|inclkena
+SYSOFF~output|areset SYSOFF~output|areset
+SYSOFF~output|sreset SYSOFF~output|sreset
+SYSOFF~output|padio SYSOFF~output|padio
+AUDIO_RESETX~output|datain AUDIO_RESETX~output|datain
+AUDIO_RESETX~output|oe AUDIO_RESETX~output|oe
+AUDIO_RESETX~output|outclk AUDIO_RESETX~output|outclk
+AUDIO_RESETX~output|outclkena AUDIO_RESETX~output|outclkena
+AUDIO_RESETX~output|inclk AUDIO_RESETX~output|inclk
+AUDIO_RESETX~output|inclkena AUDIO_RESETX~output|inclkena
+AUDIO_RESETX~output|areset AUDIO_RESETX~output|areset
+AUDIO_RESETX~output|sreset AUDIO_RESETX~output|sreset
+AUDIO_RESETX~output|padio AUDIO_RESETX~output|padio
+MCU_P2_8~input|datain MCU_P2_8~input|datain
+MCU_P2_8~input|oe MCU_P2_8~input|oe
+MCU_P2_8~input|outclk MCU_P2_8~input|outclk
+MCU_P2_8~input|outclkena MCU_P2_8~input|outclkena
+MCU_P2_8~input|inclk MCU_P2_8~input|inclk
+MCU_P2_8~input|inclkena MCU_P2_8~input|inclkena
+MCU_P2_8~input|areset MCU_P2_8~input|areset
+MCU_P2_8~input|sreset MCU_P2_8~input|sreset
+MCU_P2_8~input|combout MCU_P2_8~input|combout
+MCU_P2_8~input|padio MCU_P2_8~input|padio
+GPS_TX_READY~input|datain GPS_TX_READY~input|datain
+GPS_TX_READY~input|oe GPS_TX_READY~input|oe
+GPS_TX_READY~input|outclk GPS_TX_READY~input|outclk
+GPS_TX_READY~input|outclkena GPS_TX_READY~input|outclkena
+GPS_TX_READY~input|inclk GPS_TX_READY~input|inclk
+GPS_TX_READY~input|inclkena GPS_TX_READY~input|inclkena
+GPS_TX_READY~input|areset GPS_TX_READY~input|areset
+GPS_TX_READY~input|sreset GPS_TX_READY~input|sreset
+GPS_TX_READY~input|combout GPS_TX_READY~input|combout
+GPS_TX_READY~input|padio GPS_TX_READY~input|padio
+DEVICE_RESET~input|datain DEVICE_RESET~input|datain
+DEVICE_RESET~input|oe DEVICE_RESET~input|oe
+DEVICE_RESET~input|outclk DEVICE_RESET~input|outclk
+DEVICE_RESET~input|outclkena DEVICE_RESET~input|outclkena
+DEVICE_RESET~input|inclk DEVICE_RESET~input|inclk
+DEVICE_RESET~input|inclkena DEVICE_RESET~input|inclkena
+DEVICE_RESET~input|areset DEVICE_RESET~input|areset
+DEVICE_RESET~input|sreset DEVICE_RESET~input|sreset
+DEVICE_RESET~input|combout DEVICE_RESET~input|combout
+DEVICE_RESET~input|padio DEVICE_RESET~input|padio
+GPS_TIMEPULSE~input|datain GPS_TIMEPULSE~input|datain
+GPS_TIMEPULSE~input|oe GPS_TIMEPULSE~input|oe
+GPS_TIMEPULSE~input|outclk GPS_TIMEPULSE~input|outclk
+GPS_TIMEPULSE~input|outclkena GPS_TIMEPULSE~input|outclkena
+GPS_TIMEPULSE~input|inclk GPS_TIMEPULSE~input|inclk
+GPS_TIMEPULSE~input|inclkena GPS_TIMEPULSE~input|inclkena
+GPS_TIMEPULSE~input|areset GPS_TIMEPULSE~input|areset
+GPS_TIMEPULSE~input|sreset GPS_TIMEPULSE~input|sreset
+GPS_TIMEPULSE~input|combout GPS_TIMEPULSE~input|combout
+GPS_TIMEPULSE~input|padio GPS_TIMEPULSE~input|padio
+DEVICE_RESET_V~input|datain DEVICE_RESET_V~input|datain
+DEVICE_RESET_V~input|oe DEVICE_RESET_V~input|oe
+DEVICE_RESET_V~input|outclk DEVICE_RESET_V~input|outclk
+DEVICE_RESET_V~input|outclkena DEVICE_RESET_V~input|outclkena
+DEVICE_RESET_V~input|inclk DEVICE_RESET_V~input|inclk
+DEVICE_RESET_V~input|inclkena DEVICE_RESET_V~input|inclkena
+DEVICE_RESET_V~input|areset DEVICE_RESET_V~input|areset
+DEVICE_RESET_V~input|sreset DEVICE_RESET_V~input|sreset
+DEVICE_RESET_V~input|combout DEVICE_RESET_V~input|combout
+DEVICE_RESET_V~input|padio DEVICE_RESET_V~input|padio
+GPS_RESETX~output|datain GPS_RESETX~output|datain
+GPS_RESETX~output|oe GPS_RESETX~output|oe
+GPS_RESETX~output|outclk GPS_RESETX~output|outclk
+GPS_RESETX~output|outclkena GPS_RESETX~output|outclkena
+GPS_RESETX~output|inclk GPS_RESETX~output|inclk
+GPS_RESETX~output|inclkena GPS_RESETX~output|inclkena
+GPS_RESETX~output|areset GPS_RESETX~output|areset
+GPS_RESETX~output|sreset GPS_RESETX~output|sreset
+GPS_RESETX~output|padio GPS_RESETX~output|padio
+lcd_reset_q~0|dataa lcd_reset_q~0|A
+lcd_reset_q~0|datab lcd_reset_q~0|B
+lcd_reset_q~0|datac lcd_reset_q~0|C
+lcd_reset_q~0|datad lcd_reset_q~0|D
+lcd_reset_q~0|combout lcd_reset_q~0|LutOut
+|datac tp_q[3]|C
+tp_q[3]|clk tp_q[3]|Clk
+tp_q[3]|clrn tp_q[3]|AsyncReset
+tp_q[3]|sclr tp_q[3]|SyncReset
+tp_q[3]|sload tp_q[3]|SyncLoad
+tp_q[3]|q tp_q[3]|Q
+tp_q[4]~feeder|dataa tp_q[4]|A
+tp_q[4]~feeder|datab tp_q[4]|B
+tp_q[4]~feeder|datac tp_q[4]|C
+tp_q[4]~feeder|datad tp_q[4]|D
+tp_q[4]|clk tp_q[4]|Clk
+tp_q[4]|clrn tp_q[4]|AsyncReset
+tp_q[4]~feeder|combout tp_q[4]|LutOut
+tp_q[4]|q tp_q[4]|Q
+lcd_backlight_q~feeder|dataa lcd_backlight_q|A
+lcd_backlight_q~feeder|datab lcd_backlight_q|B
+lcd_backlight_q~feeder|datac lcd_backlight_q|C
+lcd_backlight_q~feeder|datad lcd_backlight_q|D
+lcd_backlight_q|clk lcd_backlight_q|Clk
+lcd_backlight_q|clrn lcd_backlight_q|AsyncReset
+lcd_backlight_q~feeder|combout lcd_backlight_q|LutOut
+lcd_backlight_q|q lcd_backlight_q|Q
+|datac tp_q[0]|C
+tp_q[0]|clk tp_q[0]|Clk
+tp_q[0]|clrn tp_q[0]|AsyncReset
+tp_q[0]|sclr tp_q[0]|SyncReset
+tp_q[0]|sload tp_q[0]|SyncLoad
+tp_q[0]|q tp_q[0]|Q
+lcd_reset_q~1|dataa lcd_reset_q|A
+lcd_reset_q~1|datab lcd_reset_q|B
+lcd_reset_q~1|datac lcd_reset_q|C
+lcd_reset_q~1|datad lcd_reset_q|D
+lcd_reset_q|clk lcd_reset_q|Clk
+lcd_reset_q|clrn lcd_reset_q|AsyncReset
+lcd_reset_q~1|combout lcd_reset_q|LutOut
+lcd_reset_q|q lcd_reset_q|Q
+|datac tp_q[1]|C
+tp_q[1]|clk tp_q[1]|Clk
+tp_q[1]|clrn tp_q[1]|AsyncReset
+tp_q[1]|sclr tp_q[1]|SyncReset
+tp_q[1]|sload tp_q[1]|SyncLoad
+tp_q[1]|q tp_q[1]|Q
+audio_reset_q~0|dataa audio_reset_q|A
+audio_reset_q~0|datab audio_reset_q|B
+audio_reset_q~0|datac audio_reset_q|C
+audio_reset_q~0|datad audio_reset_q|D
+audio_reset_q|clk audio_reset_q|Clk
+audio_reset_q|clrn audio_reset_q|AsyncReset
+audio_reset_q~0|combout audio_reset_q|LutOut
+audio_reset_q|q audio_reset_q|Q
+tp_q[7]~feeder|dataa tp_q[7]|A
+tp_q[7]~feeder|datab tp_q[7]|B
+tp_q[7]~feeder|datac tp_q[7]|C
+tp_q[7]~feeder|datad tp_q[7]|D
+tp_q[7]|clk tp_q[7]|Clk
+tp_q[7]|clrn tp_q[7]|AsyncReset
+tp_q[7]~feeder|combout tp_q[7]|LutOut
+tp_q[7]|q tp_q[7]|Q
+tp_q[2]~feeder|dataa tp_q[2]|A
+tp_q[2]~feeder|datab tp_q[2]|B
+tp_q[2]~feeder|datac tp_q[2]|C
+tp_q[2]~feeder|datad tp_q[2]|D
+tp_q[2]|clk tp_q[2]|Clk
+tp_q[2]|clrn tp_q[2]|AsyncReset
+tp_q[2]~feeder|combout tp_q[2]|LutOut
+tp_q[2]|q tp_q[2]|Q
+|datac tp_q[5]|C
+tp_q[5]|clk tp_q[5]|Clk
+tp_q[5]|clrn tp_q[5]|AsyncReset
+tp_q[5]|sclr tp_q[5]|SyncReset
+tp_q[5]|sload tp_q[5]|SyncLoad
+tp_q[5]|q tp_q[5]|Q
+ref_en_q~feeder|dataa ref_en_q|A
+ref_en_q~feeder|datab ref_en_q|B
+ref_en_q~feeder|datac ref_en_q|C
+ref_en_q~feeder|datad ref_en_q|D
+ref_en_q|clk ref_en_q|Clk
+ref_en_q|clrn ref_en_q|AsyncReset
+ref_en_q~feeder|combout ref_en_q|LutOut
+ref_en_q|q ref_en_q|Q
+tp_q[3]~0|dataa tp_q[3]~0|A
+tp_q[3]~0|datab tp_q[3]~0|B
+tp_q[3]~0|datac tp_q[3]~0|C
+tp_q[3]~0|datad tp_q[3]~0|D
+tp_q[3]~0|combout tp_q[3]~0|LutOut
+sysoff_q~feeder|dataa sysoff_q|A
+sysoff_q~feeder|datab sysoff_q|B
+sysoff_q~feeder|datac sysoff_q|C
+sysoff_q~feeder|datad sysoff_q|D
+sysoff_q|clk sysoff_q|Clk
+sysoff_q|clrn sysoff_q|AsyncReset
+sysoff_q~feeder|combout sysoff_q|LutOut
+sysoff_q|q sysoff_q|Q
+tp_q[6]~feeder|dataa tp_q[6]|A
+tp_q[6]~feeder|datab tp_q[6]|B
+tp_q[6]~feeder|datac tp_q[6]|C
+tp_q[6]~feeder|datad tp_q[6]|D
+tp_q[6]|clk tp_q[6]|Clk
+tp_q[6]|clrn tp_q[6]|AsyncReset
+tp_q[6]~feeder|combout tp_q[6]|LutOut
+tp_q[6]|q tp_q[6]|Q
+tp_q[3]|ena clken_ctrl_X1_Y15_N0|ClkEn
+tp_q[4]|ena clken_ctrl_X1_Y15_N0|ClkEn
+lcd_backlight_q|ena clken_ctrl_X1_Y15_N1|ClkEn
+tp_q[0]|ena clken_ctrl_X1_Y15_N0|ClkEn
+lcd_reset_q|ena clken_ctrl_X1_Y15_N1|ClkEn
+tp_q[1]|ena clken_ctrl_X1_Y15_N0|ClkEn
+audio_reset_q|ena clken_ctrl_X1_Y15_N1|ClkEn
+tp_q[7]|ena clken_ctrl_X1_Y15_N0|ClkEn
+tp_q[2]|ena clken_ctrl_X1_Y15_N0|ClkEn
+tp_q[5]|ena clken_ctrl_X1_Y15_N0|ClkEn
+ref_en_q|ena clken_ctrl_X1_Y15_N1|ClkEn
+sysoff_q|ena clken_ctrl_X1_Y15_N1|ClkEn
+tp_q[6]|ena clken_ctrl_X1_Y15_N0|ClkEn
+mcu_data_out[7]~15|dataa mcu_data_out[7]~15|A
+mcu_data_out[7]~15|datab mcu_data_out[7]~15|B
+mcu_data_out[7]~15|datac mcu_data_out[7]~15|C
+mcu_data_out[7]~15|datad mcu_data_out[7]~15|D
+mcu_data_out[7]~15|combout mcu_data_out[7]~15|LutOut
+mcu_data_out[6]~13|dataa mcu_data_out[6]~13|A
+mcu_data_out[6]~13|datab mcu_data_out[6]~13|B
+mcu_data_out[6]~13|datac mcu_data_out[6]~13|C
+mcu_data_out[6]~13|datad mcu_data_out[6]~13|D
+mcu_data_out[6]~13|combout mcu_data_out[6]~13|LutOut
+mcu_data_out[1]~3|dataa mcu_data_out[1]~3|A
+mcu_data_out[1]~3|datab mcu_data_out[1]~3|B
+mcu_data_out[1]~3|datac mcu_data_out[1]~3|C
+mcu_data_out[1]~3|datad mcu_data_out[1]~3|D
+mcu_data_out[1]~3|combout mcu_data_out[1]~3|LutOut
+mcu_data_out[0]~1|dataa mcu_data_out[0]~1|A
+mcu_data_out[0]~1|datab mcu_data_out[0]~1|B
+mcu_data_out[0]~1|datac mcu_data_out[0]~1|C
+mcu_data_out[0]~1|datad mcu_data_out[0]~1|D
+mcu_data_out[0]~1|combout mcu_data_out[0]~1|LutOut
+mcu_data_out[0]~0|dataa lcd_data_in_q[0]|A
+mcu_data_out[0]~0|datab lcd_data_in_q[0]|B
+mcu_data_out[0]~0|datac lcd_data_in_q[0]|C
+mcu_data_out[0]~0|datad lcd_data_in_q[0]|D
+lcd_data_in_q[0]|clk lcd_data_in_q[0]|Clk
+lcd_data_in_q[0]|clrn lcd_data_in_q[0]|AsyncReset
+lcd_data_in_q[0]|sclr lcd_data_in_q[0]|SyncReset
+lcd_data_in_q[0]|sload lcd_data_in_q[0]|SyncLoad
+mcu_data_out[0]~0|combout lcd_data_in_q[0]|LutOut
+lcd_data_in_q[0]|q lcd_data_in_q[0]|Q
+mcu_data_out[6]~12|dataa lcd_data_in_q[6]|A
+mcu_data_out[6]~12|datab lcd_data_in_q[6]|B
+mcu_data_out[6]~12|datac lcd_data_in_q[6]|C
+mcu_data_out[6]~12|datad lcd_data_in_q[6]|D
+lcd_data_in_q[6]|clk lcd_data_in_q[6]|Clk
+lcd_data_in_q[6]|clrn lcd_data_in_q[6]|AsyncReset
+lcd_data_in_q[6]|sclr lcd_data_in_q[6]|SyncReset
+lcd_data_in_q[6]|sload lcd_data_in_q[6]|SyncLoad
+mcu_data_out[6]~12|combout lcd_data_in_q[6]|LutOut
+lcd_data_in_q[6]|q lcd_data_in_q[6]|Q
+lcd_data_in_q[0]|ena clken_ctrl_X1_Y19_N0|ClkEn
+lcd_data_in_q[6]|ena clken_ctrl_X1_Y19_N0|ClkEn
+lcd_data_out_q[1]~feeder|dataa lcd_data_out_q[1]|A
+lcd_data_out_q[1]~feeder|datab lcd_data_out_q[1]|B
+lcd_data_out_q[1]~feeder|datac lcd_data_out_q[1]|C
+lcd_data_out_q[1]~feeder|datad lcd_data_out_q[1]|D
+lcd_data_out_q[1]|clk lcd_data_out_q[1]|Clk
+lcd_data_out_q[1]|clrn lcd_data_out_q[1]|AsyncReset
+lcd_data_out_q[1]~feeder|combout lcd_data_out_q[1]|LutOut
+lcd_data_out_q[1]|q lcd_data_out_q[1]|Q
+lcd_data_out_q[2]~feeder|dataa lcd_data_out_q[2]|A
+lcd_data_out_q[2]~feeder|datab lcd_data_out_q[2]|B
+lcd_data_out_q[2]~feeder|datac lcd_data_out_q[2]|C
+lcd_data_out_q[2]~feeder|datad lcd_data_out_q[2]|D
+lcd_data_out_q[2]|clk lcd_data_out_q[2]|Clk
+lcd_data_out_q[2]|clrn lcd_data_out_q[2]|AsyncReset
+lcd_data_out_q[2]~feeder|combout lcd_data_out_q[2]|LutOut
+lcd_data_out_q[2]|q lcd_data_out_q[2]|Q
+|datac lcd_data_out_q[6]|C
+lcd_data_out_q[6]|clk lcd_data_out_q[6]|Clk
+lcd_data_out_q[6]|clrn lcd_data_out_q[6]|AsyncReset
+lcd_data_out_q[6]|sclr lcd_data_out_q[6]|SyncReset
+lcd_data_out_q[6]|sload lcd_data_out_q[6]|SyncLoad
+lcd_data_out_q[6]|q lcd_data_out_q[6]|Q
+lcd_data_out_q[7]~feeder|dataa lcd_data_out_q[7]|A
+lcd_data_out_q[7]~feeder|datab lcd_data_out_q[7]|B
+lcd_data_out_q[7]~feeder|datac lcd_data_out_q[7]|C
+lcd_data_out_q[7]~feeder|datad lcd_data_out_q[7]|D
+lcd_data_out_q[7]|clk lcd_data_out_q[7]|Clk
+lcd_data_out_q[7]|clrn lcd_data_out_q[7]|AsyncReset
+lcd_data_out_q[7]~feeder|combout lcd_data_out_q[7]|LutOut
+lcd_data_out_q[7]|q lcd_data_out_q[7]|Q
+lcd_data_out_q[0]~feeder|dataa lcd_data_out_q[0]|A
+lcd_data_out_q[0]~feeder|datab lcd_data_out_q[0]|B
+lcd_data_out_q[0]~feeder|datac lcd_data_out_q[0]|C
+lcd_data_out_q[0]~feeder|datad lcd_data_out_q[0]|D
+lcd_data_out_q[0]|clk lcd_data_out_q[0]|Clk
+lcd_data_out_q[0]|clrn lcd_data_out_q[0]|AsyncReset
+lcd_data_out_q[0]~feeder|combout lcd_data_out_q[0]|LutOut
+lcd_data_out_q[0]|q lcd_data_out_q[0]|Q
+lcd_data_out_q[1]|ena clken_ctrl_X1_Y20_N0|ClkEn
+lcd_data_out_q[2]|ena clken_ctrl_X1_Y20_N0|ClkEn
+lcd_data_out_q[6]|ena clken_ctrl_X1_Y20_N0|ClkEn
+lcd_data_out_q[7]|ena clken_ctrl_X1_Y20_N0|ClkEn
+lcd_data_out_q[0]|ena clken_ctrl_X1_Y20_N0|ClkEn
+mcu_data_out[7]~14|dataa lcd_data_in_q[7]|A
+mcu_data_out[7]~14|datab lcd_data_in_q[7]|B
+mcu_data_out[7]~14|datac lcd_data_in_q[7]|C
+mcu_data_out[7]~14|datad lcd_data_in_q[7]|D
+lcd_data_in_q[7]|clk lcd_data_in_q[7]|Clk
+lcd_data_in_q[7]|clrn lcd_data_in_q[7]|AsyncReset
+lcd_data_in_q[7]|sclr lcd_data_in_q[7]|SyncReset
+lcd_data_in_q[7]|sload lcd_data_in_q[7]|SyncLoad
+mcu_data_out[7]~14|combout lcd_data_in_q[7]|LutOut
+lcd_data_in_q[7]|q lcd_data_in_q[7]|Q
+mcu_data_out[1]~2|dataa lcd_data_in_q[1]|A
+mcu_data_out[1]~2|datab lcd_data_in_q[1]|B
+mcu_data_out[1]~2|datac lcd_data_in_q[1]|C
+mcu_data_out[1]~2|datad lcd_data_in_q[1]|D
+lcd_data_in_q[1]|clk lcd_data_in_q[1]|Clk
+lcd_data_in_q[1]|clrn lcd_data_in_q[1]|AsyncReset
+lcd_data_in_q[1]|sclr lcd_data_in_q[1]|SyncReset
+lcd_data_in_q[1]|sload lcd_data_in_q[1]|SyncLoad
+mcu_data_out[1]~2|combout lcd_data_in_q[1]|LutOut
+lcd_data_in_q[1]|q lcd_data_in_q[1]|Q
+lcd_data_in_q[7]|ena clken_ctrl_X1_Y21_N0|ClkEn
+lcd_data_in_q[1]|ena clken_ctrl_X1_Y21_N0|ClkEn
+mcu_data_out[3]~7|dataa mcu_data_out[3]~7|A
+mcu_data_out[3]~7|datab mcu_data_out[3]~7|B
+mcu_data_out[3]~7|datac mcu_data_out[3]~7|C
+mcu_data_out[3]~7|datad mcu_data_out[3]~7|D
+mcu_data_out[3]~7|combout mcu_data_out[3]~7|LutOut
+mcu_data_out[4]~9|dataa mcu_data_out[4]~9|A
+mcu_data_out[4]~9|datab mcu_data_out[4]~9|B
+mcu_data_out[4]~9|datac mcu_data_out[4]~9|C
+mcu_data_out[4]~9|datad mcu_data_out[4]~9|D
+mcu_data_out[4]~9|combout mcu_data_out[4]~9|LutOut
+mcu_data_out[2]~5|dataa mcu_data_out[2]~5|A
+mcu_data_out[2]~5|datab mcu_data_out[2]~5|B
+mcu_data_out[2]~5|datac mcu_data_out[2]~5|C
+mcu_data_out[2]~5|datad mcu_data_out[2]~5|D
+mcu_data_out[2]~5|combout mcu_data_out[2]~5|LutOut
+mcu_data_out[5]~11|dataa mcu_data_out[5]~11|A
+mcu_data_out[5]~11|datab mcu_data_out[5]~11|B
+mcu_data_out[5]~11|datac mcu_data_out[5]~11|C
+mcu_data_out[5]~11|datad mcu_data_out[5]~11|D
+mcu_data_out[5]~11|combout mcu_data_out[5]~11|LutOut
+mcu_data_out[2]~4|dataa lcd_data_in_q[2]|A
+mcu_data_out[2]~4|datab lcd_data_in_q[2]|B
+mcu_data_out[2]~4|datac lcd_data_in_q[2]|C
+mcu_data_out[2]~4|datad lcd_data_in_q[2]|D
+lcd_data_in_q[2]|clk lcd_data_in_q[2]|Clk
+lcd_data_in_q[2]|clrn lcd_data_in_q[2]|AsyncReset
+lcd_data_in_q[2]|sclr lcd_data_in_q[2]|SyncReset
+lcd_data_in_q[2]|sload lcd_data_in_q[2]|SyncLoad
+mcu_data_out[2]~4|combout lcd_data_in_q[2]|LutOut
+lcd_data_in_q[2]|q lcd_data_in_q[2]|Q
+lcd_data_in_q[2]|ena clken_ctrl_X1_Y24_N0|ClkEn
+mcu_data_out[4]~8|dataa lcd_data_in_q[4]|A
+mcu_data_out[4]~8|datab lcd_data_in_q[4]|B
+mcu_data_out[4]~8|datac lcd_data_in_q[4]|C
+mcu_data_out[4]~8|datad lcd_data_in_q[4]|D
+lcd_data_in_q[4]|clk lcd_data_in_q[4]|Clk
+lcd_data_in_q[4]|clrn lcd_data_in_q[4]|AsyncReset
+lcd_data_in_q[4]|sclr lcd_data_in_q[4]|SyncReset
+lcd_data_in_q[4]|sload lcd_data_in_q[4]|SyncLoad
+mcu_data_out[4]~8|combout lcd_data_in_q[4]|LutOut
+lcd_data_in_q[4]|q lcd_data_in_q[4]|Q
+lcd_data_out_q[4]~feeder|dataa lcd_data_out_q[4]|A
+lcd_data_out_q[4]~feeder|datab lcd_data_out_q[4]|B
+lcd_data_out_q[4]~feeder|datac lcd_data_out_q[4]|C
+lcd_data_out_q[4]~feeder|datad lcd_data_out_q[4]|D
+lcd_data_out_q[4]|clk lcd_data_out_q[4]|Clk
+lcd_data_out_q[4]|clrn lcd_data_out_q[4]|AsyncReset
+lcd_data_out_q[4]~feeder|combout lcd_data_out_q[4]|LutOut
+lcd_data_out_q[4]|q lcd_data_out_q[4]|Q
+|datac lcd_data_out_q[3]|C
+lcd_data_out_q[3]|clk lcd_data_out_q[3]|Clk
+lcd_data_out_q[3]|clrn lcd_data_out_q[3]|AsyncReset
+lcd_data_out_q[3]|sclr lcd_data_out_q[3]|SyncReset
+lcd_data_out_q[3]|sload lcd_data_out_q[3]|SyncLoad
+lcd_data_out_q[3]|q lcd_data_out_q[3]|Q
+|datac lcd_data_out_q[5]|C
+lcd_data_out_q[5]|clk lcd_data_out_q[5]|Clk
+lcd_data_out_q[5]|clrn lcd_data_out_q[5]|AsyncReset
+lcd_data_out_q[5]|sclr lcd_data_out_q[5]|SyncReset
+lcd_data_out_q[5]|sload lcd_data_out_q[5]|SyncLoad
+lcd_data_out_q[5]|q lcd_data_out_q[5]|Q
+mcu_data_out[3]~6|dataa lcd_data_in_q[3]|A
+mcu_data_out[3]~6|datab lcd_data_in_q[3]|B
+mcu_data_out[3]~6|datac lcd_data_in_q[3]|C
+mcu_data_out[3]~6|datad lcd_data_in_q[3]|D
+lcd_data_in_q[3]|clk lcd_data_in_q[3]|Clk
+lcd_data_in_q[3]|clrn lcd_data_in_q[3]|AsyncReset
+lcd_data_in_q[3]|sclr lcd_data_in_q[3]|SyncReset
+lcd_data_in_q[3]|sload lcd_data_in_q[3]|SyncLoad
+mcu_data_out[3]~6|combout lcd_data_in_q[3]|LutOut
+lcd_data_in_q[3]|q lcd_data_in_q[3]|Q
+mcu_data_out[5]~10|dataa lcd_data_in_q[5]|A
+mcu_data_out[5]~10|datab lcd_data_in_q[5]|B
+mcu_data_out[5]~10|datac lcd_data_in_q[5]|C
+mcu_data_out[5]~10|datad lcd_data_in_q[5]|D
+lcd_data_in_q[5]|clk lcd_data_in_q[5]|Clk
+lcd_data_in_q[5]|clrn lcd_data_in_q[5]|AsyncReset
+lcd_data_in_q[5]|sclr lcd_data_in_q[5]|SyncReset
+lcd_data_in_q[5]|sload lcd_data_in_q[5]|SyncLoad
+mcu_data_out[5]~10|combout lcd_data_in_q[5]|LutOut
+lcd_data_in_q[5]|q lcd_data_in_q[5]|Q
+lcd_data_in_q[4]|ena clken_ctrl_X1_Y26_N0|ClkEn
+lcd_data_out_q[4]|ena clken_ctrl_X1_Y26_N1|ClkEn
+lcd_data_out_q[3]|ena clken_ctrl_X1_Y26_N1|ClkEn
+lcd_data_out_q[5]|ena clken_ctrl_X1_Y26_N1|ClkEn
+lcd_data_in_q[3]|ena clken_ctrl_X1_Y26_N0|ClkEn
+lcd_data_in_q[5]|ena clken_ctrl_X1_Y26_N0|ClkEn
diff --git a/hardware/portapack_h4m/CPLD/Supra/alta_db/alta_lib.v b/hardware/portapack_h4m/CPLD/Supra/alta_db/alta_lib.v
new file mode 100644
index 00000000..35366174
--- /dev/null
+++ b/hardware/portapack_h4m/CPLD/Supra/alta_db/alta_lib.v
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diff --git a/hardware/portapack_h4m/CPLD/Supra/alta_db/coverage.rpt.gz b/hardware/portapack_h4m/CPLD/Supra/alta_db/coverage.rpt.gz
new file mode 100644
index 00000000..c1ae0075
Binary files /dev/null and b/hardware/portapack_h4m/CPLD/Supra/alta_db/coverage.rpt.gz differ
diff --git a/hardware/portapack_h4m/CPLD/Supra/alta_db/filtered.vx b/hardware/portapack_h4m/CPLD/Supra/alta_db/filtered.vx
new file mode 100644
index 00000000..457460e9
--- /dev/null
+++ b/hardware/portapack_h4m/CPLD/Supra/alta_db/filtered.vx
@@ -0,0 +1,2929 @@
+`timescale 1 ps/ 1 ps
+
+module top(
+	MCU_D,
+	MCU_DIR,
+	MCU_IO_STBX,
+	MCU_LCD_WRX,
+	MCU_ADDR,
+	MCU_LCD_TE,
+	MCU_P2_8,
+	MCU_LCD_RDX,
+	TP_U,
+	TP_D,
+	TP_L,
+	TP_R,
+	SW_SEL,
+	SW_ROT_A,
+	SW_ROT_B,
+	SW_U,
+	SW_D,
+	SW_L,
+	SW_R,
+	LCD_RESETX,
+	LCD_RS,
+	LCD_WRX,
+	LCD_RDX,
+	LCD_DB,
+	LCD_TE,
+	LCD_BACKLIGHT,
+	SYSOFF,
+	AUDIO_RESETX,
+	REF_EN,
+	GPS_RESETX,
+	GPS_TX_READY,
+	GPS_TIMEPULSE,
+	DEVICE_RESET,
+	DEVICE_RESET_V);
+output	[7:0] MCU_D;
+input	MCU_DIR;
+input	MCU_IO_STBX;
+input	MCU_LCD_WRX;
+input	MCU_ADDR;
+output	MCU_LCD_TE;
+input	MCU_P2_8;
+input	MCU_LCD_RDX;
+output	TP_U;
+output	TP_D;
+output	TP_L;
+output	TP_R;
+input	SW_SEL;
+input	SW_ROT_A;
+input	SW_ROT_B;
+input	SW_U;
+input	SW_D;
+input	SW_L;
+input	SW_R;
+output	LCD_RESETX;
+output	LCD_RS;
+output	LCD_WRX;
+output	LCD_RDX;
+output	[15:0] LCD_DB;
+input	LCD_TE;
+output	LCD_BACKLIGHT;
+output	SYSOFF;
+output	AUDIO_RESETX;
+output	REF_EN;
+output	GPS_RESETX;
+input	GPS_TX_READY;
+input	GPS_TIMEPULSE;
+input	DEVICE_RESET;
+input	DEVICE_RESET_V;
+
+// module hard_block
+// Design Ports Information
+// ~ALTERA_ASDO_DATA1~	=>  Location: PIN_F4,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// ~ALTERA_FLASH_nCE_nCSO~	=>  Location: PIN_E2,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// ~ALTERA_DCLK~	=>  Location: PIN_P3,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// ~ALTERA_DATA0~	=>  Location: PIN_N7,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// ~ALTERA_nCEO~	=>  Location: PIN_P28,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+
+// module top
+// Design Ports Information
+// MCU_LCD_TE	=>  Location: PIN_AC4,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// MCU_P2_8	=>  Location: PIN_D6,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// TP_U	=>  Location: PIN_AA4,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// TP_D	=>  Location: PIN_AB3,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// TP_L	=>  Location: PIN_AA3,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// TP_R	=>  Location: PIN_AD1,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LCD_RESETX	=>  Location: PIN_AB4,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LCD_RS	=>  Location: PIN_AF2,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LCD_WRX	=>  Location: PIN_M1,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LCD_RDX	=>  Location: PIN_R6,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LCD_BACKLIGHT	=>  Location: PIN_W3,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// SYSOFF	=>  Location: PIN_AE2,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// AUDIO_RESETX	=>  Location: PIN_AE1,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// REF_EN	=>  Location: PIN_AC5,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// GPS_RESETX	=>  Location: PIN_AC26,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// GPS_TX_READY	=>  Location: PIN_D9,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// GPS_TIMEPULSE	=>  Location: PIN_E25,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// DEVICE_RESET	=>  Location: PIN_AF15,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// DEVICE_RESET_V	=>  Location: PIN_AE25,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// MCU_D[0]	=>  Location: PIN_AC1,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// MCU_D[1]	=>  Location: PIN_AC3,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// MCU_D[2]	=>  Location: PIN_AD3,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// MCU_D[3]	=>  Location: PIN_V3,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// MCU_D[4]	=>  Location: PIN_V2,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// MCU_D[5]	=>  Location: PIN_V1,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// MCU_D[6]	=>  Location: PIN_Y3,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// MCU_D[7]	=>  Location: PIN_AC2,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LCD_DB[0]	=>  Location: PIN_U5,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LCD_DB[1]	=>  Location: PIN_AB1,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LCD_DB[2]	=>  Location: PIN_U2,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LCD_DB[3]	=>  Location: PIN_T3,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LCD_DB[4]	=>  Location: PIN_R5,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LCD_DB[5]	=>  Location: PIN_T4,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LCD_DB[6]	=>  Location: PIN_Y4,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LCD_DB[7]	=>  Location: PIN_AB2,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LCD_DB[8]	=>  Location: PIN_U6,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LCD_DB[9]	=>  Location: PIN_U1,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LCD_DB[10]	=>  Location: PIN_V4,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LCD_DB[11]	=>  Location: PIN_R2,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LCD_DB[12]	=>  Location: PIN_R1,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LCD_DB[13]	=>  Location: PIN_R4,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LCD_DB[14]	=>  Location: PIN_W2,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LCD_DB[15]	=>  Location: PIN_W1,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LCD_TE	=>  Location: PIN_AB6,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// MCU_ADDR	=>  Location: PIN_AB5,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// MCU_LCD_WRX	=>  Location: PIN_Y1,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// MCU_LCD_RDX	=>  Location: PIN_Y2,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// MCU_IO_STBX	=>  Location: PIN_J1,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// MCU_DIR	=>  Location: PIN_AD2,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW_R	=>  Location: PIN_U8,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW_L	=>  Location: PIN_U7,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW_D	=>  Location: PIN_T7,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW_U	=>  Location: PIN_R3,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW_SEL	=>  Location: PIN_U3,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW_ROT_A	=>  Location: PIN_U4,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW_ROT_B	=>  Location: PIN_T8,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+
+//wire	gnd;
+//wire	gnd;
+//wire	vcc;
+//wire	vcc;
+//wire	\AUDIO_RESETX~output_o ;
+wire	\DEVICE_RESET_V~input_o ;
+wire	\DEVICE_RESET~input_o ;
+//wire	\GPS_RESETX~output_o ;
+wire	\GPS_TIMEPULSE~input_o ;
+wire	\GPS_TX_READY~input_o ;
+//wire	\LCD_BACKLIGHT~output_o ;
+//wire	\LCD_DB[0]~output_o ;
+wire	\LCD_DB[0]~input_o ;
+//wire	\LCD_DB[10]~output_o ;
+wire	\LCD_DB[10]~input_o ;
+//wire	\LCD_DB[11]~output_o ;
+wire	\LCD_DB[11]~input_o ;
+//wire	\LCD_DB[12]~output_o ;
+wire	\LCD_DB[12]~input_o ;
+//wire	\LCD_DB[13]~output_o ;
+wire	\LCD_DB[13]~input_o ;
+//wire	\LCD_DB[14]~output_o ;
+wire	\LCD_DB[14]~input_o ;
+//wire	\LCD_DB[15]~output_o ;
+wire	\LCD_DB[15]~input_o ;
+//wire	\LCD_DB[1]~output_o ;
+wire	\LCD_DB[1]~input_o ;
+//wire	\LCD_DB[2]~output_o ;
+wire	\LCD_DB[2]~input_o ;
+//wire	\LCD_DB[3]~output_o ;
+wire	\LCD_DB[3]~input_o ;
+//wire	\LCD_DB[4]~output_o ;
+wire	\LCD_DB[4]~input_o ;
+//wire	\LCD_DB[5]~output_o ;
+wire	\LCD_DB[5]~input_o ;
+//wire	\LCD_DB[6]~output_o ;
+wire	\LCD_DB[6]~input_o ;
+//wire	\LCD_DB[7]~output_o ;
+wire	\LCD_DB[7]~input_o ;
+//wire	\LCD_DB[8]~output_o ;
+wire	\LCD_DB[8]~input_o ;
+//wire	\LCD_DB[9]~output_o ;
+wire	\LCD_DB[9]~input_o ;
+//wire	\LCD_RDX~output_o ;
+//wire	\LCD_RESETX~output_o ;
+//wire	\LCD_RS~output_o ;
+wire	\LCD_TE~input_o ;
+//wire	\LCD_WRX~output_o ;
+wire	\MCU_ADDR~input_o ;
+wire	\MCU_DIR~input_o ;
+//wire	\MCU_D[0]~output_o ;
+wire	\MCU_D[0]~input_o ;
+//wire	\MCU_D[1]~output_o ;
+wire	\MCU_D[1]~input_o ;
+//wire	\MCU_D[2]~output_o ;
+wire	\MCU_D[2]~input_o ;
+//wire	\MCU_D[3]~output_o ;
+wire	\MCU_D[3]~input_o ;
+//wire	\MCU_D[4]~output_o ;
+wire	\MCU_D[4]~input_o ;
+//wire	\MCU_D[5]~output_o ;
+wire	\MCU_D[5]~input_o ;
+//wire	\MCU_D[6]~output_o ;
+wire	\MCU_D[6]~input_o ;
+//wire	\MCU_D[7]~output_o ;
+wire	\MCU_D[7]~input_o ;
+wire	\MCU_IO_STBX~input_o ;
+wire	\MCU_IO_STBX~inputclkctrl_outclk ;
+wire	\MCU_LCD_RDX~input_o ;
+wire	\MCU_LCD_RDX~inputclkctrl_outclk ;
+//wire	\MCU_LCD_TE~output_o ;
+wire	\MCU_LCD_WRX~input_o ;
+wire	\MCU_LCD_WRX~inputclkctrl_outclk ;
+wire	\MCU_P2_8~input_o ;
+//wire	\REF_EN~output_o ;
+wire	\SW_D~input_o ;
+wire	\SW_L~input_o ;
+wire	\SW_ROT_A~input_o ;
+wire	\SW_ROT_B~input_o ;
+wire	\SW_R~input_o ;
+wire	\SW_SEL~input_o ;
+wire	\SW_U~input_o ;
+//wire	\SYSOFF~output_o ;
+//wire	\TP_D~output_o ;
+//wire	\TP_L~output_o ;
+//wire	\TP_R~output_o ;
+//wire	\TP_U~output_o ;
+wire	\audio_reset_q~0_combout ;
+wire	\audio_reset_q~q ;
+//wire	devclrn;
+tri1	devclrn;
+//wire	devoe;
+tri1	devoe;
+//wire	devpor;
+tri1	devpor;
+wire	\lcd_backlight_q~feeder_combout ;
+wire	\lcd_backlight_q~q ;
+wire	[7:0] lcd_data_in_q;
+//wire	lcd_data_in_q[0];
+//wire	lcd_data_in_q[1];
+//wire	lcd_data_in_q[2];
+//wire	lcd_data_in_q[3];
+//wire	lcd_data_in_q[4];
+//wire	lcd_data_in_q[5];
+//wire	lcd_data_in_q[6];
+//wire	lcd_data_in_q[7];
+wire	[7:0] lcd_data_out_q;
+//wire	lcd_data_out_q[0];
+wire	\lcd_data_out_q[0]~feeder_combout ;
+//wire	lcd_data_out_q[1];
+wire	\lcd_data_out_q[1]~feeder_combout ;
+//wire	lcd_data_out_q[2];
+wire	\lcd_data_out_q[2]~feeder_combout ;
+//wire	lcd_data_out_q[3];
+//wire	lcd_data_out_q[4];
+wire	\lcd_data_out_q[4]~feeder_combout ;
+//wire	lcd_data_out_q[5];
+//wire	lcd_data_out_q[6];
+//wire	lcd_data_out_q[7];
+wire	\lcd_data_out_q[7]~feeder_combout ;
+wire	\lcd_reset_q~0_combout ;
+wire	\lcd_reset_q~1_combout ;
+wire	\lcd_reset_q~q ;
+wire	\mcu_data_out[0]~0_combout ;
+wire	\mcu_data_out[0]~1_combout ;
+wire	\mcu_data_out[1]~2_combout ;
+wire	\mcu_data_out[1]~3_combout ;
+wire	\mcu_data_out[2]~4_combout ;
+wire	\mcu_data_out[2]~5_combout ;
+wire	\mcu_data_out[3]~6_combout ;
+wire	\mcu_data_out[3]~7_combout ;
+wire	\mcu_data_out[4]~8_combout ;
+wire	\mcu_data_out[4]~9_combout ;
+wire	\mcu_data_out[5]~10_combout ;
+wire	\mcu_data_out[5]~11_combout ;
+wire	\mcu_data_out[6]~12_combout ;
+wire	\mcu_data_out[6]~13_combout ;
+wire	\mcu_data_out[7]~14_combout ;
+wire	\mcu_data_out[7]~15_combout ;
+wire	\ref_en_q~feeder_combout ;
+wire	\ref_en_q~q ;
+wire	\sysoff_q~feeder_combout ;
+wire	\sysoff_q~q ;
+wire	[7:0] tp_q;
+//wire	tp_q[0];
+//wire	tp_q[1];
+//wire	tp_q[2];
+wire	\tp_q[2]~feeder_combout ;
+//wire	tp_q[3];
+wire	\tp_q[3]~0_combout ;
+//wire	tp_q[4];
+wire	\tp_q[4]~feeder_combout ;
+//wire	tp_q[5];
+//wire	tp_q[6];
+wire	\tp_q[6]~feeder_combout ;
+//wire	tp_q[7];
+wire	\tp_q[7]~feeder_combout ;
+wire	unknown;
+wire	unknown;
+wire	\~ALTERA_ASDO_DATA1~~ibuf_o ;
+wire	\~ALTERA_ASDO_DATA1~~padout ;
+wire	\~ALTERA_DATA0~~ibuf_o ;
+wire	\~ALTERA_DATA0~~padout ;
+wire	\~ALTERA_FLASH_nCE_nCSO~~ibuf_o ;
+wire	\~ALTERA_FLASH_nCE_nCSO~~padout ;
+
+wire vcc;
+wire gnd;
+assign vcc = 1'b1;
+assign gnd = 1'b0;
+
+// Location: IOIBUF_X0_Y10_N0
+// alta_io_ibuf \SW_L~input (
+alta_io \SW_L~input (
+	.datain(gnd),
+	.oe(gnd),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\SW_L~input_o ),
+	.regout(),
+	.padio(SW_L));
+defparam \SW_L~input .CFG_KEEP = 2'b00;
+// defparam \SW_L~input .simulate_z_as = "z";
+
+defparam \SW_L~input .coord_x = 0;
+defparam \SW_L~input .coord_y = 10;
+defparam \SW_L~input .coord_z = 0;
+// Location: IOIBUF_X0_Y10_N1
+// alta_io_ibuf \SW_R~input (
+alta_io \SW_R~input (
+	.datain(gnd),
+	.oe(gnd),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\SW_R~input_o ),
+	.regout(),
+	.padio(SW_R));
+defparam \SW_R~input .CFG_KEEP = 2'b00;
+// defparam \SW_R~input .simulate_z_as = "z";
+
+defparam \SW_R~input .coord_x = 0;
+defparam \SW_R~input .coord_y = 10;
+defparam \SW_R~input .coord_z = 1;
+// Location: IOOBUF_X0_Y11_N0
+// alta_io_obuf \TP_U~output (
+alta_io \TP_U~output (
+	.datain(tp_q[3]),
+	.oe(tp_q[7]),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(),
+	.regout(),
+	.padio(TP_U));
+defparam \TP_U~output .CFG_KEEP = 2'b00;
+// defparam \TP_U~output .open_drain_output = "false";
+
+defparam \TP_U~output .coord_x = 0;
+defparam \TP_U~output .coord_y = 11;
+defparam \TP_U~output .coord_z = 0;
+// Location: IOOBUF_X0_Y11_N1
+// alta_io_obuf \TP_L~output (
+alta_io \TP_L~output (
+	.datain(tp_q[1]),
+	.oe(tp_q[5]),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(),
+	.regout(),
+	.padio(TP_L));
+defparam \TP_L~output .CFG_KEEP = 2'b00;
+// defparam \TP_L~output .open_drain_output = "false";
+
+defparam \TP_L~output .coord_x = 0;
+defparam \TP_L~output .coord_y = 11;
+defparam \TP_L~output .coord_z = 1;
+// Location: IOIBUF_X0_Y14_N1
+// alta_io_ibuf \SW_ROT_B~input (
+alta_io \SW_ROT_B~input (
+	.datain(gnd),
+	.oe(gnd),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\SW_ROT_B~input_o ),
+	.regout(),
+	.padio(SW_ROT_B));
+defparam \SW_ROT_B~input .CFG_KEEP = 2'b00;
+// defparam \SW_ROT_B~input .simulate_z_as = "z";
+
+defparam \SW_ROT_B~input .coord_x = 0;
+defparam \SW_ROT_B~input .coord_y = 14;
+defparam \SW_ROT_B~input .coord_z = 1;
+// Location: IOOBUF_X0_Y15_N2
+// alta_io_obuf \TP_R~output (
+alta_io \TP_R~output (
+	.datain(tp_q[0]),
+	.oe(tp_q[4]),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(),
+	.regout(),
+	.padio(TP_R));
+defparam \TP_R~output .CFG_KEEP = 2'b00;
+// defparam \TP_R~output .open_drain_output = "false";
+
+defparam \TP_R~output .coord_x = 0;
+defparam \TP_R~output .coord_y = 15;
+defparam \TP_R~output .coord_z = 2;
+// Location: IOOBUF_X0_Y15_N3
+// alta_io_obuf \TP_D~output (
+alta_io \TP_D~output (
+	.datain(tp_q[2]),
+	.oe(tp_q[6]),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(),
+	.regout(),
+	.padio(TP_D));
+defparam \TP_D~output .CFG_KEEP = 2'b00;
+// defparam \TP_D~output .open_drain_output = "false";
+
+defparam \TP_D~output .coord_x = 0;
+defparam \TP_D~output .coord_y = 15;
+defparam \TP_D~output .coord_z = 3;
+// Location: IOIBUF_X0_Y16_N1
+// alta_io_ibuf \MCU_D[1]~input (
+// Location: IOOBUF_X0_Y16_N1
+// alta_io_obuf \MCU_D[1]~output (
+alta_io \MCU_D[1]~output (
+	.datain(\mcu_data_out[1]~3_combout ),
+	.oe(\MCU_DIR~input_o ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\MCU_D[1]~input_o ),
+	.regout(),
+	.padio(MCU_D[1]));
+defparam \MCU_D[1]~output .CFG_KEEP = 2'b00;
+// defparam \MCU_D[1]~input .simulate_z_as = "z";
+// defparam \MCU_D[1]~output .open_drain_output = "false";
+
+defparam \MCU_D[1]~output .coord_x = 0;
+defparam \MCU_D[1]~output .coord_y = 16;
+defparam \MCU_D[1]~output .coord_z = 1;
+// Location: IOIBUF_X0_Y16_N2
+// alta_io_ibuf \MCU_D[2]~input (
+// Location: IOOBUF_X0_Y16_N2
+// alta_io_obuf \MCU_D[2]~output (
+alta_io \MCU_D[2]~output (
+	.datain(\mcu_data_out[2]~5_combout ),
+	.oe(\MCU_DIR~input_o ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\MCU_D[2]~input_o ),
+	.regout(),
+	.padio(MCU_D[2]));
+defparam \MCU_D[2]~output .CFG_KEEP = 2'b00;
+// defparam \MCU_D[2]~input .simulate_z_as = "z";
+// defparam \MCU_D[2]~output .open_drain_output = "false";
+
+defparam \MCU_D[2]~output .coord_x = 0;
+defparam \MCU_D[2]~output .coord_y = 16;
+defparam \MCU_D[2]~output .coord_z = 2;
+// Location: IOIBUF_X0_Y16_N3
+// alta_io_ibuf \MCU_DIR~input (
+alta_io \MCU_DIR~input (
+	.datain(gnd),
+	.oe(gnd),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\MCU_DIR~input_o ),
+	.regout(),
+	.padio(MCU_DIR));
+defparam \MCU_DIR~input .CFG_KEEP = 2'b00;
+// defparam \MCU_DIR~input .simulate_z_as = "z";
+
+defparam \MCU_DIR~input .coord_x = 0;
+defparam \MCU_DIR~input .coord_y = 16;
+defparam \MCU_DIR~input .coord_z = 3;
+// Location: IOIBUF_X0_Y17_N1
+// alta_io_ibuf \MCU_D[0]~input (
+// Location: IOOBUF_X0_Y17_N1
+// alta_io_obuf \MCU_D[0]~output (
+alta_io \MCU_D[0]~output (
+	.datain(\mcu_data_out[0]~1_combout ),
+	.oe(\MCU_DIR~input_o ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\MCU_D[0]~input_o ),
+	.regout(),
+	.padio(MCU_D[0]));
+defparam \MCU_D[0]~output .CFG_KEEP = 2'b00;
+// defparam \MCU_D[0]~input .simulate_z_as = "z";
+// defparam \MCU_D[0]~output .open_drain_output = "false";
+
+defparam \MCU_D[0]~output .coord_x = 0;
+defparam \MCU_D[0]~output .coord_y = 17;
+defparam \MCU_D[0]~output .coord_z = 1;
+// Location: IOIBUF_X0_Y18_N2
+// alta_io_ibuf \MCU_D[6]~input (
+// Location: IOOBUF_X0_Y18_N2
+// alta_io_obuf \MCU_D[6]~output (
+alta_io \MCU_D[6]~output (
+	.datain(\mcu_data_out[6]~13_combout ),
+	.oe(\MCU_DIR~input_o ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\MCU_D[6]~input_o ),
+	.regout(),
+	.padio(MCU_D[6]));
+defparam \MCU_D[6]~output .CFG_KEEP = 2'b00;
+// defparam \MCU_D[6]~input .simulate_z_as = "z";
+// defparam \MCU_D[6]~output .open_drain_output = "false";
+
+defparam \MCU_D[6]~output .coord_x = 0;
+defparam \MCU_D[6]~output .coord_y = 18;
+defparam \MCU_D[6]~output .coord_z = 2;
+// Location: IOIBUF_X0_Y18_N3
+// alta_io_ibuf \MCU_D[7]~input (
+// Location: IOOBUF_X0_Y18_N3
+// alta_io_obuf \MCU_D[7]~output (
+alta_io \MCU_D[7]~output (
+	.datain(\mcu_data_out[7]~15_combout ),
+	.oe(\MCU_DIR~input_o ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\MCU_D[7]~input_o ),
+	.regout(),
+	.padio(MCU_D[7]));
+defparam \MCU_D[7]~output .CFG_KEEP = 2'b00;
+// defparam \MCU_D[7]~input .simulate_z_as = "z";
+// defparam \MCU_D[7]~output .open_drain_output = "false";
+
+defparam \MCU_D[7]~output .coord_x = 0;
+defparam \MCU_D[7]~output .coord_y = 18;
+defparam \MCU_D[7]~output .coord_z = 3;
+// Location: IOIBUF_X0_Y19_N0
+// alta_io_ibuf \LCD_DB[8]~input (
+// Location: IOOBUF_X0_Y19_N0
+// alta_io_obuf \LCD_DB[8]~output (
+alta_io \LCD_DB[8]~output (
+	.datain(lcd_data_out_q[0]),
+	.oe(\MCU_LCD_RDX~input_o ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\LCD_DB[8]~input_o ),
+	.regout(),
+	.padio(LCD_DB[8]));
+defparam \LCD_DB[8]~output .CFG_KEEP = 2'b00;
+// defparam \LCD_DB[8]~input .simulate_z_as = "z";
+// defparam \LCD_DB[8]~output .open_drain_output = "false";
+
+defparam \LCD_DB[8]~output .coord_x = 0;
+defparam \LCD_DB[8]~output .coord_y = 19;
+defparam \LCD_DB[8]~output .coord_z = 0;
+// Location: IOIBUF_X0_Y19_N2
+// alta_io_ibuf \LCD_DB[0]~input (
+// Location: IOOBUF_X0_Y19_N2
+// alta_io_obuf \LCD_DB[0]~output (
+alta_io \LCD_DB[0]~output (
+	.datain(\MCU_D[0]~input_o ),
+	.oe(\MCU_LCD_RDX~input_o ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\LCD_DB[0]~input_o ),
+	.regout(),
+	.padio(LCD_DB[0]));
+defparam \LCD_DB[0]~output .CFG_KEEP = 2'b00;
+// defparam \LCD_DB[0]~input .simulate_z_as = "z";
+// defparam \LCD_DB[0]~output .open_drain_output = "false";
+
+defparam \LCD_DB[0]~output .coord_x = 0;
+defparam \LCD_DB[0]~output .coord_y = 19;
+defparam \LCD_DB[0]~output .coord_z = 2;
+// Location: IOIBUF_X0_Y19_N3
+// alta_io_ibuf \LCD_DB[6]~input (
+// Location: IOOBUF_X0_Y19_N3
+// alta_io_obuf \LCD_DB[6]~output (
+alta_io \LCD_DB[6]~output (
+	.datain(\MCU_D[6]~input_o ),
+	.oe(\MCU_LCD_RDX~input_o ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\LCD_DB[6]~input_o ),
+	.regout(),
+	.padio(LCD_DB[6]));
+defparam \LCD_DB[6]~output .CFG_KEEP = 2'b00;
+// defparam \LCD_DB[6]~input .simulate_z_as = "z";
+// defparam \LCD_DB[6]~output .open_drain_output = "false";
+
+defparam \LCD_DB[6]~output .coord_x = 0;
+defparam \LCD_DB[6]~output .coord_y = 19;
+defparam \LCD_DB[6]~output .coord_z = 3;
+// Location: IOIBUF_X0_Y20_N0
+// alta_io_ibuf \LCD_DB[14]~input (
+// Location: IOOBUF_X0_Y20_N0
+// alta_io_obuf \LCD_DB[14]~output (
+alta_io \LCD_DB[14]~output (
+	.datain(lcd_data_out_q[6]),
+	.oe(\MCU_LCD_RDX~input_o ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\LCD_DB[14]~input_o ),
+	.regout(),
+	.padio(LCD_DB[14]));
+defparam \LCD_DB[14]~output .CFG_KEEP = 2'b00;
+// defparam \LCD_DB[14]~input .simulate_z_as = "z";
+// defparam \LCD_DB[14]~output .open_drain_output = "false";
+
+defparam \LCD_DB[14]~output .coord_x = 0;
+defparam \LCD_DB[14]~output .coord_y = 20;
+defparam \LCD_DB[14]~output .coord_z = 0;
+// Location: IOIBUF_X0_Y20_N1
+// alta_io_ibuf \LCD_DB[15]~input (
+// Location: IOOBUF_X0_Y20_N1
+// alta_io_obuf \LCD_DB[15]~output (
+alta_io \LCD_DB[15]~output (
+	.datain(lcd_data_out_q[7]),
+	.oe(\MCU_LCD_RDX~input_o ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\LCD_DB[15]~input_o ),
+	.regout(),
+	.padio(LCD_DB[15]));
+defparam \LCD_DB[15]~output .CFG_KEEP = 2'b00;
+// defparam \LCD_DB[15]~input .simulate_z_as = "z";
+// defparam \LCD_DB[15]~output .open_drain_output = "false";
+
+defparam \LCD_DB[15]~output .coord_x = 0;
+defparam \LCD_DB[15]~output .coord_y = 20;
+defparam \LCD_DB[15]~output .coord_z = 1;
+// Location: IOIBUF_X0_Y21_N0
+// alta_io_ibuf \LCD_DB[7]~input (
+// Location: IOOBUF_X0_Y21_N0
+// alta_io_obuf \LCD_DB[7]~output (
+alta_io \LCD_DB[7]~output (
+	.datain(\MCU_D[7]~input_o ),
+	.oe(\MCU_LCD_RDX~input_o ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\LCD_DB[7]~input_o ),
+	.regout(),
+	.padio(LCD_DB[7]));
+defparam \LCD_DB[7]~output .CFG_KEEP = 2'b00;
+// defparam \LCD_DB[7]~input .simulate_z_as = "z";
+// defparam \LCD_DB[7]~output .open_drain_output = "false";
+
+defparam \LCD_DB[7]~output .coord_x = 0;
+defparam \LCD_DB[7]~output .coord_y = 21;
+defparam \LCD_DB[7]~output .coord_z = 0;
+// Location: IOIBUF_X0_Y21_N1
+// alta_io_ibuf \LCD_DB[1]~input (
+// Location: IOOBUF_X0_Y21_N1
+// alta_io_obuf \LCD_DB[1]~output (
+alta_io \LCD_DB[1]~output (
+	.datain(\MCU_D[1]~input_o ),
+	.oe(\MCU_LCD_RDX~input_o ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\LCD_DB[1]~input_o ),
+	.regout(),
+	.padio(LCD_DB[1]));
+defparam \LCD_DB[1]~output .CFG_KEEP = 2'b00;
+// defparam \LCD_DB[1]~input .simulate_z_as = "z";
+// defparam \LCD_DB[1]~output .open_drain_output = "false";
+
+defparam \LCD_DB[1]~output .coord_x = 0;
+defparam \LCD_DB[1]~output .coord_y = 21;
+defparam \LCD_DB[1]~output .coord_z = 1;
+// Location: IOIBUF_X0_Y22_N1
+// alta_io_ibuf \MCU_D[5]~input (
+// Location: IOOBUF_X0_Y22_N1
+// alta_io_obuf \MCU_D[5]~output (
+alta_io \MCU_D[5]~output (
+	.datain(\mcu_data_out[5]~11_combout ),
+	.oe(\MCU_DIR~input_o ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\MCU_D[5]~input_o ),
+	.regout(),
+	.padio(MCU_D[5]));
+defparam \MCU_D[5]~output .CFG_KEEP = 2'b00;
+// defparam \MCU_D[5]~input .simulate_z_as = "z";
+// defparam \MCU_D[5]~output .open_drain_output = "false";
+
+defparam \MCU_D[5]~output .coord_x = 0;
+defparam \MCU_D[5]~output .coord_y = 22;
+defparam \MCU_D[5]~output .coord_z = 1;
+// Location: IOIBUF_X0_Y23_N0
+// alta_io_ibuf \MCU_D[3]~input (
+// Location: IOOBUF_X0_Y23_N0
+// alta_io_obuf \MCU_D[3]~output (
+alta_io \MCU_D[3]~output (
+	.datain(\mcu_data_out[3]~7_combout ),
+	.oe(\MCU_DIR~input_o ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\MCU_D[3]~input_o ),
+	.regout(),
+	.padio(MCU_D[3]));
+defparam \MCU_D[3]~output .CFG_KEEP = 2'b00;
+// defparam \MCU_D[3]~input .simulate_z_as = "z";
+// defparam \MCU_D[3]~output .open_drain_output = "false";
+
+defparam \MCU_D[3]~output .coord_x = 0;
+defparam \MCU_D[3]~output .coord_y = 23;
+defparam \MCU_D[3]~output .coord_z = 0;
+// Location: IOIBUF_X0_Y23_N1
+// alta_io_ibuf \MCU_D[4]~input (
+// Location: IOOBUF_X0_Y23_N1
+// alta_io_obuf \MCU_D[4]~output (
+alta_io \MCU_D[4]~output (
+	.datain(\mcu_data_out[4]~9_combout ),
+	.oe(\MCU_DIR~input_o ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\MCU_D[4]~input_o ),
+	.regout(),
+	.padio(MCU_D[4]));
+defparam \MCU_D[4]~output .CFG_KEEP = 2'b00;
+// defparam \MCU_D[4]~input .simulate_z_as = "z";
+// defparam \MCU_D[4]~output .open_drain_output = "false";
+
+defparam \MCU_D[4]~output .coord_x = 0;
+defparam \MCU_D[4]~output .coord_y = 23;
+defparam \MCU_D[4]~output .coord_z = 1;
+// Location: IOIBUF_X0_Y24_N0
+// alta_io_ibuf \LCD_DB[2]~input (
+// Location: IOOBUF_X0_Y24_N0
+// alta_io_obuf \LCD_DB[2]~output (
+alta_io \LCD_DB[2]~output (
+	.datain(\MCU_D[2]~input_o ),
+	.oe(\MCU_LCD_RDX~input_o ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\LCD_DB[2]~input_o ),
+	.regout(),
+	.padio(LCD_DB[2]));
+defparam \LCD_DB[2]~output .CFG_KEEP = 2'b00;
+// defparam \LCD_DB[2]~input .simulate_z_as = "z";
+// defparam \LCD_DB[2]~output .open_drain_output = "false";
+
+defparam \LCD_DB[2]~output .coord_x = 0;
+defparam \LCD_DB[2]~output .coord_y = 24;
+defparam \LCD_DB[2]~output .coord_z = 0;
+// Location: IOIBUF_X0_Y24_N1
+// alta_io_ibuf \LCD_DB[9]~input (
+// Location: IOOBUF_X0_Y24_N1
+// alta_io_obuf \LCD_DB[9]~output (
+alta_io \LCD_DB[9]~output (
+	.datain(lcd_data_out_q[1]),
+	.oe(\MCU_LCD_RDX~input_o ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\LCD_DB[9]~input_o ),
+	.regout(),
+	.padio(LCD_DB[9]));
+defparam \LCD_DB[9]~output .CFG_KEEP = 2'b00;
+// defparam \LCD_DB[9]~input .simulate_z_as = "z";
+// defparam \LCD_DB[9]~output .open_drain_output = "false";
+
+defparam \LCD_DB[9]~output .coord_x = 0;
+defparam \LCD_DB[9]~output .coord_y = 24;
+defparam \LCD_DB[9]~output .coord_z = 1;
+// Location: IOIBUF_X0_Y24_N3
+// alta_io_ibuf \LCD_DB[10]~input (
+// Location: IOOBUF_X0_Y24_N3
+// alta_io_obuf \LCD_DB[10]~output (
+alta_io \LCD_DB[10]~output (
+	.datain(lcd_data_out_q[2]),
+	.oe(\MCU_LCD_RDX~input_o ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\LCD_DB[10]~input_o ),
+	.regout(),
+	.padio(LCD_DB[10]));
+defparam \LCD_DB[10]~output .CFG_KEEP = 2'b00;
+// defparam \LCD_DB[10]~input .simulate_z_as = "z";
+// defparam \LCD_DB[10]~output .open_drain_output = "false";
+
+defparam \LCD_DB[10]~output .coord_x = 0;
+defparam \LCD_DB[10]~output .coord_y = 24;
+defparam \LCD_DB[10]~output .coord_z = 3;
+// Location: IOIBUF_X0_Y25_N2
+// alta_io_ibuf \SW_D~input (
+alta_io \SW_D~input (
+	.datain(gnd),
+	.oe(gnd),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\SW_D~input_o ),
+	.regout(),
+	.padio(SW_D));
+defparam \SW_D~input .CFG_KEEP = 2'b00;
+// defparam \SW_D~input .simulate_z_as = "z";
+
+defparam \SW_D~input .coord_x = 0;
+defparam \SW_D~input .coord_y = 25;
+defparam \SW_D~input .coord_z = 2;
+// Location: IOIBUF_X0_Y26_N0
+// alta_io_ibuf \LCD_DB[13]~input (
+// Location: IOOBUF_X0_Y26_N0
+// alta_io_obuf \LCD_DB[13]~output (
+alta_io \LCD_DB[13]~output (
+	.datain(lcd_data_out_q[5]),
+	.oe(\MCU_LCD_RDX~input_o ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\LCD_DB[13]~input_o ),
+	.regout(),
+	.padio(LCD_DB[13]));
+defparam \LCD_DB[13]~output .CFG_KEEP = 2'b00;
+// defparam \LCD_DB[13]~input .simulate_z_as = "z";
+// defparam \LCD_DB[13]~output .open_drain_output = "false";
+
+defparam \LCD_DB[13]~output .coord_x = 0;
+defparam \LCD_DB[13]~output .coord_y = 26;
+defparam \LCD_DB[13]~output .coord_z = 0;
+// Location: IOIBUF_X0_Y26_N1
+// alta_io_ibuf \LCD_DB[5]~input (
+// Location: IOOBUF_X0_Y26_N1
+// alta_io_obuf \LCD_DB[5]~output (
+alta_io \LCD_DB[5]~output (
+	.datain(\MCU_D[5]~input_o ),
+	.oe(\MCU_LCD_RDX~input_o ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\LCD_DB[5]~input_o ),
+	.regout(),
+	.padio(LCD_DB[5]));
+defparam \LCD_DB[5]~output .CFG_KEEP = 2'b00;
+// defparam \LCD_DB[5]~input .simulate_z_as = "z";
+// defparam \LCD_DB[5]~output .open_drain_output = "false";
+
+defparam \LCD_DB[5]~output .coord_x = 0;
+defparam \LCD_DB[5]~output .coord_y = 26;
+defparam \LCD_DB[5]~output .coord_z = 1;
+// Location: IOIBUF_X0_Y26_N2
+// alta_io_ibuf \LCD_DB[3]~input (
+// Location: IOOBUF_X0_Y26_N2
+// alta_io_obuf \LCD_DB[3]~output (
+alta_io \LCD_DB[3]~output (
+	.datain(\MCU_D[3]~input_o ),
+	.oe(\MCU_LCD_RDX~input_o ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\LCD_DB[3]~input_o ),
+	.regout(),
+	.padio(LCD_DB[3]));
+defparam \LCD_DB[3]~output .CFG_KEEP = 2'b00;
+// defparam \LCD_DB[3]~input .simulate_z_as = "z";
+// defparam \LCD_DB[3]~output .open_drain_output = "false";
+
+defparam \LCD_DB[3]~output .coord_x = 0;
+defparam \LCD_DB[3]~output .coord_y = 26;
+defparam \LCD_DB[3]~output .coord_z = 2;
+// Location: IOIBUF_X0_Y26_N3
+// alta_io_ibuf \LCD_DB[4]~input (
+// Location: IOOBUF_X0_Y26_N3
+// alta_io_obuf \LCD_DB[4]~output (
+alta_io \LCD_DB[4]~output (
+	.datain(\MCU_D[4]~input_o ),
+	.oe(\MCU_LCD_RDX~input_o ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\LCD_DB[4]~input_o ),
+	.regout(),
+	.padio(LCD_DB[4]));
+defparam \LCD_DB[4]~output .CFG_KEEP = 2'b00;
+// defparam \LCD_DB[4]~input .simulate_z_as = "z";
+// defparam \LCD_DB[4]~output .open_drain_output = "false";
+
+defparam \LCD_DB[4]~output .coord_x = 0;
+defparam \LCD_DB[4]~output .coord_y = 26;
+defparam \LCD_DB[4]~output .coord_z = 3;
+// Location: IOIBUF_X0_Y28_N1
+// alta_io_ibuf \SW_ROT_A~input (
+alta_io \SW_ROT_A~input (
+	.datain(gnd),
+	.oe(gnd),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\SW_ROT_A~input_o ),
+	.regout(),
+	.padio(SW_ROT_A));
+defparam \SW_ROT_A~input .CFG_KEEP = 2'b00;
+// defparam \SW_ROT_A~input .simulate_z_as = "z";
+
+defparam \SW_ROT_A~input .coord_x = 0;
+defparam \SW_ROT_A~input .coord_y = 28;
+defparam \SW_ROT_A~input .coord_z = 1;
+// Location: IOIBUF_X0_Y28_N2
+// alta_io_ibuf \SW_U~input (
+alta_io \SW_U~input (
+	.datain(gnd),
+	.oe(gnd),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\SW_U~input_o ),
+	.regout(),
+	.padio(SW_U));
+defparam \SW_U~input .CFG_KEEP = 2'b00;
+// defparam \SW_U~input .simulate_z_as = "z";
+
+defparam \SW_U~input .coord_x = 0;
+defparam \SW_U~input .coord_y = 28;
+defparam \SW_U~input .coord_z = 2;
+// Location: IOIBUF_X0_Y29_N0
+// alta_io_ibuf \LCD_DB[11]~input (
+// Location: IOOBUF_X0_Y29_N0
+// alta_io_obuf \LCD_DB[11]~output (
+alta_io \LCD_DB[11]~output (
+	.datain(lcd_data_out_q[3]),
+	.oe(\MCU_LCD_RDX~input_o ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\LCD_DB[11]~input_o ),
+	.regout(),
+	.padio(LCD_DB[11]));
+defparam \LCD_DB[11]~output .CFG_KEEP = 2'b00;
+// defparam \LCD_DB[11]~input .simulate_z_as = "z";
+// defparam \LCD_DB[11]~output .open_drain_output = "false";
+
+defparam \LCD_DB[11]~output .coord_x = 0;
+defparam \LCD_DB[11]~output .coord_y = 29;
+defparam \LCD_DB[11]~output .coord_z = 0;
+// Location: IOIBUF_X0_Y29_N1
+// alta_io_ibuf \LCD_DB[12]~input (
+// Location: IOOBUF_X0_Y29_N1
+// alta_io_obuf \LCD_DB[12]~output (
+alta_io \LCD_DB[12]~output (
+	.datain(lcd_data_out_q[4]),
+	.oe(\MCU_LCD_RDX~input_o ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\LCD_DB[12]~input_o ),
+	.regout(),
+	.padio(LCD_DB[12]));
+defparam \LCD_DB[12]~output .CFG_KEEP = 2'b00;
+// defparam \LCD_DB[12]~input .simulate_z_as = "z";
+// defparam \LCD_DB[12]~output .open_drain_output = "false";
+
+defparam \LCD_DB[12]~output .coord_x = 0;
+defparam \LCD_DB[12]~output .coord_y = 29;
+defparam \LCD_DB[12]~output .coord_z = 1;
+// Location: IOOBUF_X0_Y29_N2
+// alta_io_obuf \LCD_RDX~output (
+alta_io \LCD_RDX~output (
+	.datain(\MCU_LCD_RDX~input_o ),
+	.oe(vcc),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(),
+	.regout(),
+	.padio(LCD_RDX));
+defparam \LCD_RDX~output .CFG_KEEP = 2'b00;
+// defparam \LCD_RDX~output .open_drain_output = "false";
+
+defparam \LCD_RDX~output .coord_x = 0;
+defparam \LCD_RDX~output .coord_y = 29;
+defparam \LCD_RDX~output .coord_z = 2;
+// Location: IOIBUF_X0_Y29_N3
+// alta_io_ibuf \SW_SEL~input (
+alta_io \SW_SEL~input (
+	.datain(gnd),
+	.oe(gnd),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\SW_SEL~input_o ),
+	.regout(),
+	.padio(SW_SEL));
+defparam \SW_SEL~input .CFG_KEEP = 2'b00;
+// defparam \SW_SEL~input .simulate_z_as = "z";
+
+defparam \SW_SEL~input .coord_x = 0;
+defparam \SW_SEL~input .coord_y = 29;
+defparam \SW_SEL~input .coord_z = 3;
+// Location: IOIBUF_X0_Y30_N1
+// alta_io_ibuf \MCU_IO_STBX~input (
+alta_io \MCU_IO_STBX~input (
+	.datain(gnd),
+	.oe(gnd),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\MCU_IO_STBX~input_o ),
+	.regout(),
+	.padio(MCU_IO_STBX));
+defparam \MCU_IO_STBX~input .CFG_KEEP = 2'b00;
+// defparam \MCU_IO_STBX~input .simulate_z_as = "z";
+
+defparam \MCU_IO_STBX~input .coord_x = 0;
+defparam \MCU_IO_STBX~input .coord_y = 30;
+defparam \MCU_IO_STBX~input .coord_z = 1;
+// Location: IOIBUF_X0_Y30_N2
+// alta_io_ibuf \MCU_LCD_RDX~input (
+alta_io \MCU_LCD_RDX~input (
+	.datain(gnd),
+	.oe(gnd),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\MCU_LCD_RDX~input_o ),
+	.regout(),
+	.padio(MCU_LCD_RDX));
+defparam \MCU_LCD_RDX~input .CFG_KEEP = 2'b00;
+// defparam \MCU_LCD_RDX~input .simulate_z_as = "z";
+
+defparam \MCU_LCD_RDX~input .coord_x = 0;
+defparam \MCU_LCD_RDX~input .coord_y = 30;
+defparam \MCU_LCD_RDX~input .coord_z = 2;
+// Location: IOIBUF_X0_Y30_N3
+// alta_io_ibuf \MCU_LCD_WRX~input (
+alta_io \MCU_LCD_WRX~input (
+	.datain(gnd),
+	.oe(gnd),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\MCU_LCD_WRX~input_o ),
+	.regout(),
+	.padio(MCU_LCD_WRX));
+defparam \MCU_LCD_WRX~input .CFG_KEEP = 2'b00;
+// defparam \MCU_LCD_WRX~input .simulate_z_as = "z";
+
+defparam \MCU_LCD_WRX~input .coord_x = 0;
+defparam \MCU_LCD_WRX~input .coord_y = 30;
+defparam \MCU_LCD_WRX~input .coord_z = 3;
+// Location: IOOBUF_X0_Y37_N0
+// alta_io_obuf \LCD_WRX~output (
+alta_io \LCD_WRX~output (
+	.datain(\MCU_LCD_WRX~input_o ),
+	.oe(vcc),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(),
+	.regout(),
+	.padio(LCD_WRX));
+defparam \LCD_WRX~output .CFG_KEEP = 2'b00;
+// defparam \LCD_WRX~output .open_drain_output = "false";
+
+defparam \LCD_WRX~output .coord_x = 0;
+defparam \LCD_WRX~output .coord_y = 37;
+defparam \LCD_WRX~output .coord_z = 0;
+// Location: IOOBUF_X0_Y4_N2
+// alta_io_obuf \LCD_RS~output (
+alta_io \LCD_RS~output (
+	.datain(\MCU_ADDR~input_o ),
+	.oe(vcc),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(),
+	.regout(),
+	.padio(LCD_RS));
+defparam \LCD_RS~output .CFG_KEEP = 2'b00;
+// defparam \LCD_RS~output .open_drain_output = "false";
+
+defparam \LCD_RS~output .coord_x = 0;
+defparam \LCD_RS~output .coord_y = 4;
+defparam \LCD_RS~output .coord_z = 2;
+// Location: IOIBUF_X0_Y4_N3
+// alta_io_ibuf \MCU_ADDR~input (
+alta_io \MCU_ADDR~input (
+	.datain(gnd),
+	.oe(gnd),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\MCU_ADDR~input_o ),
+	.regout(),
+	.padio(MCU_ADDR));
+defparam \MCU_ADDR~input .CFG_KEEP = 2'b00;
+// defparam \MCU_ADDR~input .simulate_z_as = "z";
+
+defparam \MCU_ADDR~input .coord_x = 0;
+defparam \MCU_ADDR~input .coord_y = 4;
+defparam \MCU_ADDR~input .coord_z = 3;
+// Location: IOOBUF_X0_Y6_N2
+// alta_io_obuf \MCU_LCD_TE~output (
+alta_io \MCU_LCD_TE~output (
+	.datain(\LCD_TE~input_o ),
+	.oe(vcc),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(),
+	.regout(),
+	.padio(MCU_LCD_TE));
+defparam \MCU_LCD_TE~output .CFG_KEEP = 2'b00;
+// defparam \MCU_LCD_TE~output .open_drain_output = "false";
+
+defparam \MCU_LCD_TE~output .coord_x = 0;
+defparam \MCU_LCD_TE~output .coord_y = 6;
+defparam \MCU_LCD_TE~output .coord_z = 2;
+// Location: IOIBUF_X0_Y6_N3
+// alta_io_ibuf \LCD_TE~input (
+alta_io \LCD_TE~input (
+	.datain(gnd),
+	.oe(gnd),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\LCD_TE~input_o ),
+	.regout(),
+	.padio(LCD_TE));
+defparam \LCD_TE~input .CFG_KEEP = 2'b00;
+// defparam \LCD_TE~input .simulate_z_as = "z";
+
+defparam \LCD_TE~input .coord_x = 0;
+defparam \LCD_TE~input .coord_y = 6;
+defparam \LCD_TE~input .coord_z = 3;
+// Location: IOOBUF_X0_Y7_N0
+// alta_io_obuf \LCD_RESETX~output (
+alta_io \LCD_RESETX~output (
+	.datain(\lcd_reset_q~q ),
+	.oe(vcc),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(),
+	.regout(),
+	.padio(LCD_RESETX));
+defparam \LCD_RESETX~output .CFG_KEEP = 2'b00;
+// defparam \LCD_RESETX~output .open_drain_output = "false";
+
+defparam \LCD_RESETX~output .coord_x = 0;
+defparam \LCD_RESETX~output .coord_y = 7;
+defparam \LCD_RESETX~output .coord_z = 0;
+// Location: IOOBUF_X0_Y7_N1
+// alta_io_obuf \REF_EN~output (
+alta_io \REF_EN~output (
+	.datain(\ref_en_q~q ),
+	.oe(vcc),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(),
+	.regout(),
+	.padio(REF_EN));
+defparam \REF_EN~output .CFG_KEEP = 2'b00;
+// defparam \REF_EN~output .open_drain_output = "false";
+
+defparam \REF_EN~output .coord_x = 0;
+defparam \REF_EN~output .coord_y = 7;
+defparam \REF_EN~output .coord_z = 1;
+// Location: IOOBUF_X0_Y8_N3
+// alta_io_obuf \LCD_BACKLIGHT~output (
+alta_io \LCD_BACKLIGHT~output (
+	.datain(\lcd_backlight_q~q ),
+	.oe(vcc),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(),
+	.regout(),
+	.padio(LCD_BACKLIGHT));
+defparam \LCD_BACKLIGHT~output .CFG_KEEP = 2'b00;
+// defparam \LCD_BACKLIGHT~output .open_drain_output = "false";
+
+defparam \LCD_BACKLIGHT~output .coord_x = 0;
+defparam \LCD_BACKLIGHT~output .coord_y = 8;
+defparam \LCD_BACKLIGHT~output .coord_z = 3;
+// Location: IOOBUF_X0_Y9_N1
+// alta_io_obuf \SYSOFF~output (
+alta_io \SYSOFF~output (
+	.datain(\sysoff_q~q ),
+	.oe(vcc),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(),
+	.regout(),
+	.padio(SYSOFF));
+defparam \SYSOFF~output .CFG_KEEP = 2'b00;
+// defparam \SYSOFF~output .open_drain_output = "false";
+
+defparam \SYSOFF~output .coord_x = 0;
+defparam \SYSOFF~output .coord_y = 9;
+defparam \SYSOFF~output .coord_z = 1;
+// Location: IOOBUF_X0_Y9_N2
+// alta_io_obuf \AUDIO_RESETX~output (
+alta_io \AUDIO_RESETX~output (
+	.datain(\audio_reset_q~q ),
+	.oe(vcc),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(),
+	.regout(),
+	.padio(AUDIO_RESETX));
+defparam \AUDIO_RESETX~output .CFG_KEEP = 2'b00;
+// defparam \AUDIO_RESETX~output .open_drain_output = "false";
+
+defparam \AUDIO_RESETX~output .coord_x = 0;
+defparam \AUDIO_RESETX~output .coord_y = 9;
+defparam \AUDIO_RESETX~output .coord_z = 2;
+// Location: IOIBUF_X18_Y62_N2
+// alta_io_ibuf \MCU_P2_8~input (
+alta_io \MCU_P2_8~input (
+	.datain(gnd),
+	.oe(gnd),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\MCU_P2_8~input_o ),
+	.regout(),
+	.padio(MCU_P2_8));
+defparam \MCU_P2_8~input .CFG_KEEP = 2'b00;
+// defparam \MCU_P2_8~input .simulate_z_as = "z";
+
+defparam \MCU_P2_8~input .coord_x = 18;
+defparam \MCU_P2_8~input .coord_y = 62;
+defparam \MCU_P2_8~input .coord_z = 2;
+// Location: IOIBUF_X23_Y62_N3
+// alta_io_ibuf \GPS_TX_READY~input (
+alta_io \GPS_TX_READY~input (
+	.datain(gnd),
+	.oe(gnd),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\GPS_TX_READY~input_o ),
+	.regout(),
+	.padio(GPS_TX_READY));
+defparam \GPS_TX_READY~input .CFG_KEEP = 2'b00;
+// defparam \GPS_TX_READY~input .simulate_z_as = "z";
+
+defparam \GPS_TX_READY~input .coord_x = 23;
+defparam \GPS_TX_READY~input .coord_y = 62;
+defparam \GPS_TX_READY~input .coord_z = 3;
+// Location: IOIBUF_X51_Y0_N0
+// alta_io_ibuf \DEVICE_RESET~input (
+alta_io \DEVICE_RESET~input (
+	.datain(gnd),
+	.oe(gnd),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\DEVICE_RESET~input_o ),
+	.regout(),
+	.padio(DEVICE_RESET));
+defparam \DEVICE_RESET~input .CFG_KEEP = 2'b00;
+// defparam \DEVICE_RESET~input .simulate_z_as = "z";
+
+defparam \DEVICE_RESET~input .coord_x = 51;
+defparam \DEVICE_RESET~input .coord_y = 0;
+defparam \DEVICE_RESET~input .coord_z = 0;
+// Location: IOIBUF_X56_Y62_N0
+// alta_io_ibuf \GPS_TIMEPULSE~input (
+alta_io \GPS_TIMEPULSE~input (
+	.datain(gnd),
+	.oe(gnd),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\GPS_TIMEPULSE~input_o ),
+	.regout(),
+	.padio(GPS_TIMEPULSE));
+defparam \GPS_TIMEPULSE~input .CFG_KEEP = 2'b00;
+// defparam \GPS_TIMEPULSE~input .simulate_z_as = "z";
+
+defparam \GPS_TIMEPULSE~input .coord_x = 56;
+defparam \GPS_TIMEPULSE~input .coord_y = 62;
+defparam \GPS_TIMEPULSE~input .coord_z = 0;
+// Location: IOIBUF_X78_Y0_N1
+// alta_io_ibuf \DEVICE_RESET_V~input (
+alta_io \DEVICE_RESET_V~input (
+	.datain(gnd),
+	.oe(gnd),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\DEVICE_RESET_V~input_o ),
+	.regout(),
+	.padio(DEVICE_RESET_V));
+defparam \DEVICE_RESET_V~input .CFG_KEEP = 2'b00;
+// defparam \DEVICE_RESET_V~input .simulate_z_as = "z";
+
+defparam \DEVICE_RESET_V~input .coord_x = 78;
+defparam \DEVICE_RESET_V~input .coord_y = 0;
+defparam \DEVICE_RESET_V~input .coord_z = 1;
+// Location: IOOBUF_X94_Y9_N2
+// alta_io_obuf \GPS_RESETX~output (
+alta_io \GPS_RESETX~output (
+	.datain(vcc),
+	.oe(vcc),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(),
+	.regout(),
+	.padio(GPS_RESETX));
+defparam \GPS_RESETX~output .CFG_KEEP = 2'b00;
+// defparam \GPS_RESETX~output .open_drain_output = "false";
+
+defparam \GPS_RESETX~output .coord_x = 94;
+defparam \GPS_RESETX~output .coord_y = 9;
+defparam \GPS_RESETX~output .coord_z = 2;
+// Location: CLKCTRL_G2
+alta_io_gclk \MCU_IO_STBX~inputclkctrl (
+	.inclk (\MCU_IO_STBX~input_o ),
+	.outclk(\MCU_IO_STBX~inputclkctrl_outclk ));
+//defparam \MCU_IO_STBX~inputclkctrl .clock_type = "global clock";
+//defparam \MCU_IO_STBX~inputclkctrl .ena_register_mode = "none";
+
+// Location: CLKCTRL_G3
+alta_io_gclk \MCU_LCD_WRX~inputclkctrl (
+	.inclk (\MCU_LCD_WRX~input_o ),
+	.outclk(\MCU_LCD_WRX~inputclkctrl_outclk ));
+//defparam \MCU_LCD_WRX~inputclkctrl .clock_type = "global clock";
+//defparam \MCU_LCD_WRX~inputclkctrl .ena_register_mode = "none";
+
+// Location: CLKCTRL_G4
+alta_io_gclk \MCU_LCD_RDX~inputclkctrl (
+	.inclk (\MCU_LCD_RDX~input_o ),
+	.outclk(\MCU_LCD_RDX~inputclkctrl_outclk ));
+//defparam \MCU_LCD_RDX~inputclkctrl .clock_type = "global clock";
+//defparam \MCU_LCD_RDX~inputclkctrl .ena_register_mode = "none";
+
+// Location: LCCOMB_X1_Y15_N10
+// alta_lcell_comb \lcd_reset_q~0 (
+alta_slice \lcd_reset_q~0 (
+	.A(vcc),
+	.B(vcc),
+	.C(\MCU_ADDR~input_o ),
+	.D(\MCU_DIR~input_o ),
+	.Cin(),
+	.Qin(),
+	.Clk(),
+	.AsyncReset(),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\lcd_reset_q~0_combout ),
+	.Cout(),
+	.Q());
+defparam \lcd_reset_q~0 .mask = 16'h00F0;
+defparam \lcd_reset_q~0 .mode = "logic";
+defparam \lcd_reset_q~0 .modeMux = 1'b0;
+defparam \lcd_reset_q~0 .FeedbackMux = 1'b0;
+defparam \lcd_reset_q~0 .ShiftMux = 1'b0;
+defparam \lcd_reset_q~0 .BypassEn = 1'b0;
+defparam \lcd_reset_q~0 .CarryEnb = 1'b1;
+defparam \lcd_reset_q~0 .AsyncResetMux = 2'bxx;
+defparam \lcd_reset_q~0 .SyncResetMux = 2'bxx;
+defparam \lcd_reset_q~0 .SyncLoadMux = 2'bxx;
+defparam \lcd_reset_q~0 .coord_x = 1;
+defparam \lcd_reset_q~0 .coord_y = 15;
+defparam \lcd_reset_q~0 .coord_z = 5;
+// Location: FF_X1_Y15_N12
+// alta_lcell_ff \tp_q[3] (
+alta_slice \tp_q[3] (
+	.A(),
+	.B(),
+	.C(\MCU_D[3]~input_o ),
+	.D(),
+	.Cin(),
+	.Qin(tp_q[3]),
+	.Clk(\MCU_IO_STBX~inputclkctrl_outclk__tp_q[3]~0_combout_X1_Y15_SIG_SIG ),
+	.AsyncReset(AsyncReset_X1_Y15_GND),
+	.SyncReset(SyncReset_X1_Y15_GND),
+	.ShiftData(),
+	.SyncLoad(SyncLoad_X1_Y15_VCC),
+	.LutOut(),
+	.Cout(),
+	.Q(tp_q[3]));
+defparam \tp_q[3] .mask = 16'hFFFF;
+defparam \tp_q[3] .mode = "ripple";
+defparam \tp_q[3] .modeMux = 1'b1;
+defparam \tp_q[3] .FeedbackMux = 1'b0;
+defparam \tp_q[3] .ShiftMux = 1'b0;
+defparam \tp_q[3] .BypassEn = 1'b1;
+defparam \tp_q[3] .CarryEnb = 1'b1;
+defparam \tp_q[3] .AsyncResetMux = 2'b00;
+defparam \tp_q[3] .SyncResetMux = 2'b00;
+defparam \tp_q[3] .SyncLoadMux = 2'b01;
+defparam \tp_q[3] .coord_x = 1;
+defparam \tp_q[3] .coord_y = 15;
+defparam \tp_q[3] .coord_z = 6;
+// Location: FF_X1_Y15_N14
+// alta_lcell_ff \tp_q[4] (
+// Location: LCCOMB_X1_Y15_N14
+// alta_lcell_comb \tp_q[4]~feeder (
+alta_slice \tp_q[4] (
+	.A(vcc),
+	.B(vcc),
+	.C(vcc),
+	.D(\MCU_D[4]~input_o ),
+	.Cin(),
+	.Qin(tp_q[4]),
+	.Clk(\MCU_IO_STBX~inputclkctrl_outclk__tp_q[3]~0_combout_X1_Y15_SIG_SIG ),
+	.AsyncReset(AsyncReset_X1_Y15_GND),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\tp_q[4]~feeder_combout ),
+	.Cout(),
+	.Q(tp_q[4]));
+defparam \tp_q[4] .mask = 16'hFF00;
+defparam \tp_q[4] .mode = "logic";
+defparam \tp_q[4] .modeMux = 1'b0;
+defparam \tp_q[4] .FeedbackMux = 1'b0;
+defparam \tp_q[4] .ShiftMux = 1'b0;
+defparam \tp_q[4] .BypassEn = 1'b0;
+defparam \tp_q[4] .CarryEnb = 1'b1;
+defparam \tp_q[4] .AsyncResetMux = 2'b00;
+defparam \tp_q[4] .SyncResetMux = 2'bxx;
+defparam \tp_q[4] .SyncLoadMux = 2'bxx;
+defparam \tp_q[4] .coord_x = 1;
+defparam \tp_q[4] .coord_y = 15;
+defparam \tp_q[4] .coord_z = 7;
+// Location: FF_X1_Y15_N16
+// alta_lcell_ff lcd_backlight_q(
+// Location: LCCOMB_X1_Y15_N16
+// alta_lcell_comb \lcd_backlight_q~feeder (
+alta_slice lcd_backlight_q(
+	.A(vcc),
+	.B(vcc),
+	.C(vcc),
+	.D(\MCU_D[7]~input_o ),
+	.Cin(),
+	.Qin(\lcd_backlight_q~q ),
+	.Clk(\MCU_IO_STBX~inputclkctrl_outclk__lcd_reset_q~0_combout_X1_Y15_SIG_SIG ),
+	.AsyncReset(AsyncReset_X1_Y15_GND),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\lcd_backlight_q~feeder_combout ),
+	.Cout(),
+	.Q(\lcd_backlight_q~q ));
+defparam lcd_backlight_q.mask = 16'hFF00;
+defparam lcd_backlight_q.mode = "logic";
+defparam lcd_backlight_q.modeMux = 1'b0;
+defparam lcd_backlight_q.FeedbackMux = 1'b0;
+defparam lcd_backlight_q.ShiftMux = 1'b0;
+defparam lcd_backlight_q.BypassEn = 1'b0;
+defparam lcd_backlight_q.CarryEnb = 1'b1;
+defparam lcd_backlight_q.AsyncResetMux = 2'b00;
+defparam lcd_backlight_q.SyncResetMux = 2'bxx;
+defparam lcd_backlight_q.SyncLoadMux = 2'bxx;
+defparam lcd_backlight_q.coord_x = 1;
+defparam lcd_backlight_q.coord_y = 15;
+defparam lcd_backlight_q.coord_z = 8;
+// Location: FF_X1_Y15_N18
+// alta_lcell_ff \tp_q[0] (
+alta_slice \tp_q[0] (
+	.A(),
+	.B(),
+	.C(\MCU_D[0]~input_o ),
+	.D(),
+	.Cin(),
+	.Qin(tp_q[0]),
+	.Clk(\MCU_IO_STBX~inputclkctrl_outclk__tp_q[3]~0_combout_X1_Y15_SIG_SIG ),
+	.AsyncReset(AsyncReset_X1_Y15_GND),
+	.SyncReset(SyncReset_X1_Y15_GND),
+	.ShiftData(),
+	.SyncLoad(SyncLoad_X1_Y15_VCC),
+	.LutOut(),
+	.Cout(),
+	.Q(tp_q[0]));
+defparam \tp_q[0] .mask = 16'hFFFF;
+defparam \tp_q[0] .mode = "ripple";
+defparam \tp_q[0] .modeMux = 1'b1;
+defparam \tp_q[0] .FeedbackMux = 1'b0;
+defparam \tp_q[0] .ShiftMux = 1'b0;
+defparam \tp_q[0] .BypassEn = 1'b1;
+defparam \tp_q[0] .CarryEnb = 1'b1;
+defparam \tp_q[0] .AsyncResetMux = 2'b00;
+defparam \tp_q[0] .SyncResetMux = 2'b00;
+defparam \tp_q[0] .SyncLoadMux = 2'b01;
+defparam \tp_q[0] .coord_x = 1;
+defparam \tp_q[0] .coord_y = 15;
+defparam \tp_q[0] .coord_z = 9;
+// Location: FF_X1_Y15_N2
+// alta_lcell_ff lcd_reset_q(
+// Location: LCCOMB_X1_Y15_N2
+// alta_lcell_comb \lcd_reset_q~1 (
+alta_slice lcd_reset_q(
+	.A(vcc),
+	.B(vcc),
+	.C(\MCU_D[0]~input_o ),
+	.D(vcc),
+	.Cin(),
+	.Qin(\lcd_reset_q~q ),
+	.Clk(\MCU_IO_STBX~inputclkctrl_outclk__lcd_reset_q~0_combout_X1_Y15_SIG_SIG ),
+	.AsyncReset(AsyncReset_X1_Y15_GND),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\lcd_reset_q~1_combout ),
+	.Cout(),
+	.Q(\lcd_reset_q~q ));
+defparam lcd_reset_q.mask = 16'h0F0F;
+defparam lcd_reset_q.mode = "logic";
+defparam lcd_reset_q.modeMux = 1'b0;
+defparam lcd_reset_q.FeedbackMux = 1'b0;
+defparam lcd_reset_q.ShiftMux = 1'b0;
+defparam lcd_reset_q.BypassEn = 1'b0;
+defparam lcd_reset_q.CarryEnb = 1'b1;
+defparam lcd_reset_q.AsyncResetMux = 2'b00;
+defparam lcd_reset_q.SyncResetMux = 2'bxx;
+defparam lcd_reset_q.SyncLoadMux = 2'bxx;
+defparam lcd_reset_q.coord_x = 1;
+defparam lcd_reset_q.coord_y = 15;
+defparam lcd_reset_q.coord_z = 1;
+// Location: FF_X1_Y15_N20
+// alta_lcell_ff \tp_q[1] (
+alta_slice \tp_q[1] (
+	.A(),
+	.B(),
+	.C(\MCU_D[1]~input_o ),
+	.D(),
+	.Cin(),
+	.Qin(tp_q[1]),
+	.Clk(\MCU_IO_STBX~inputclkctrl_outclk__tp_q[3]~0_combout_X1_Y15_SIG_SIG ),
+	.AsyncReset(AsyncReset_X1_Y15_GND),
+	.SyncReset(SyncReset_X1_Y15_GND),
+	.ShiftData(),
+	.SyncLoad(SyncLoad_X1_Y15_VCC),
+	.LutOut(),
+	.Cout(),
+	.Q(tp_q[1]));
+defparam \tp_q[1] .mask = 16'hFFFF;
+defparam \tp_q[1] .mode = "ripple";
+defparam \tp_q[1] .modeMux = 1'b1;
+defparam \tp_q[1] .FeedbackMux = 1'b0;
+defparam \tp_q[1] .ShiftMux = 1'b0;
+defparam \tp_q[1] .BypassEn = 1'b1;
+defparam \tp_q[1] .CarryEnb = 1'b1;
+defparam \tp_q[1] .AsyncResetMux = 2'b00;
+defparam \tp_q[1] .SyncResetMux = 2'b00;
+defparam \tp_q[1] .SyncLoadMux = 2'b01;
+defparam \tp_q[1] .coord_x = 1;
+defparam \tp_q[1] .coord_y = 15;
+defparam \tp_q[1] .coord_z = 10;
+// Location: FF_X1_Y15_N22
+// alta_lcell_ff audio_reset_q(
+// Location: LCCOMB_X1_Y15_N22
+// alta_lcell_comb \audio_reset_q~0 (
+alta_slice audio_reset_q(
+	.A(vcc),
+	.B(vcc),
+	.C(\MCU_D[1]~input_o ),
+	.D(vcc),
+	.Cin(),
+	.Qin(\audio_reset_q~q ),
+	.Clk(\MCU_IO_STBX~inputclkctrl_outclk__lcd_reset_q~0_combout_X1_Y15_SIG_SIG ),
+	.AsyncReset(AsyncReset_X1_Y15_GND),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\audio_reset_q~0_combout ),
+	.Cout(),
+	.Q(\audio_reset_q~q ));
+defparam audio_reset_q.mask = 16'h0F0F;
+defparam audio_reset_q.mode = "logic";
+defparam audio_reset_q.modeMux = 1'b0;
+defparam audio_reset_q.FeedbackMux = 1'b0;
+defparam audio_reset_q.ShiftMux = 1'b0;
+defparam audio_reset_q.BypassEn = 1'b0;
+defparam audio_reset_q.CarryEnb = 1'b1;
+defparam audio_reset_q.AsyncResetMux = 2'b00;
+defparam audio_reset_q.SyncResetMux = 2'bxx;
+defparam audio_reset_q.SyncLoadMux = 2'bxx;
+defparam audio_reset_q.coord_x = 1;
+defparam audio_reset_q.coord_y = 15;
+defparam audio_reset_q.coord_z = 11;
+// Location: FF_X1_Y15_N24
+// alta_lcell_ff \tp_q[7] (
+// Location: LCCOMB_X1_Y15_N24
+// alta_lcell_comb \tp_q[7]~feeder (
+alta_slice \tp_q[7] (
+	.A(vcc),
+	.B(vcc),
+	.C(vcc),
+	.D(\MCU_D[7]~input_o ),
+	.Cin(),
+	.Qin(tp_q[7]),
+	.Clk(\MCU_IO_STBX~inputclkctrl_outclk__tp_q[3]~0_combout_X1_Y15_SIG_SIG ),
+	.AsyncReset(AsyncReset_X1_Y15_GND),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\tp_q[7]~feeder_combout ),
+	.Cout(),
+	.Q(tp_q[7]));
+defparam \tp_q[7] .mask = 16'hFF00;
+defparam \tp_q[7] .mode = "logic";
+defparam \tp_q[7] .modeMux = 1'b0;
+defparam \tp_q[7] .FeedbackMux = 1'b0;
+defparam \tp_q[7] .ShiftMux = 1'b0;
+defparam \tp_q[7] .BypassEn = 1'b0;
+defparam \tp_q[7] .CarryEnb = 1'b1;
+defparam \tp_q[7] .AsyncResetMux = 2'b00;
+defparam \tp_q[7] .SyncResetMux = 2'bxx;
+defparam \tp_q[7] .SyncLoadMux = 2'bxx;
+defparam \tp_q[7] .coord_x = 1;
+defparam \tp_q[7] .coord_y = 15;
+defparam \tp_q[7] .coord_z = 12;
+// Location: FF_X1_Y15_N26
+// alta_lcell_ff \tp_q[2] (
+// Location: LCCOMB_X1_Y15_N26
+// alta_lcell_comb \tp_q[2]~feeder (
+alta_slice \tp_q[2] (
+	.A(vcc),
+	.B(vcc),
+	.C(vcc),
+	.D(\MCU_D[2]~input_o ),
+	.Cin(),
+	.Qin(tp_q[2]),
+	.Clk(\MCU_IO_STBX~inputclkctrl_outclk__tp_q[3]~0_combout_X1_Y15_SIG_SIG ),
+	.AsyncReset(AsyncReset_X1_Y15_GND),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\tp_q[2]~feeder_combout ),
+	.Cout(),
+	.Q(tp_q[2]));
+defparam \tp_q[2] .mask = 16'hFF00;
+defparam \tp_q[2] .mode = "logic";
+defparam \tp_q[2] .modeMux = 1'b0;
+defparam \tp_q[2] .FeedbackMux = 1'b0;
+defparam \tp_q[2] .ShiftMux = 1'b0;
+defparam \tp_q[2] .BypassEn = 1'b0;
+defparam \tp_q[2] .CarryEnb = 1'b1;
+defparam \tp_q[2] .AsyncResetMux = 2'b00;
+defparam \tp_q[2] .SyncResetMux = 2'bxx;
+defparam \tp_q[2] .SyncLoadMux = 2'bxx;
+defparam \tp_q[2] .coord_x = 1;
+defparam \tp_q[2] .coord_y = 15;
+defparam \tp_q[2] .coord_z = 13;
+// Location: FF_X1_Y15_N28
+// alta_lcell_ff \tp_q[5] (
+alta_slice \tp_q[5] (
+	.A(),
+	.B(),
+	.C(\MCU_D[5]~input_o ),
+	.D(),
+	.Cin(),
+	.Qin(tp_q[5]),
+	.Clk(\MCU_IO_STBX~inputclkctrl_outclk__tp_q[3]~0_combout_X1_Y15_SIG_SIG ),
+	.AsyncReset(AsyncReset_X1_Y15_GND),
+	.SyncReset(SyncReset_X1_Y15_GND),
+	.ShiftData(),
+	.SyncLoad(SyncLoad_X1_Y15_VCC),
+	.LutOut(),
+	.Cout(),
+	.Q(tp_q[5]));
+defparam \tp_q[5] .mask = 16'hFFFF;
+defparam \tp_q[5] .mode = "ripple";
+defparam \tp_q[5] .modeMux = 1'b1;
+defparam \tp_q[5] .FeedbackMux = 1'b0;
+defparam \tp_q[5] .ShiftMux = 1'b0;
+defparam \tp_q[5] .BypassEn = 1'b1;
+defparam \tp_q[5] .CarryEnb = 1'b1;
+defparam \tp_q[5] .AsyncResetMux = 2'b00;
+defparam \tp_q[5] .SyncResetMux = 2'b00;
+defparam \tp_q[5] .SyncLoadMux = 2'b01;
+defparam \tp_q[5] .coord_x = 1;
+defparam \tp_q[5] .coord_y = 15;
+defparam \tp_q[5] .coord_z = 14;
+// Location: FF_X1_Y15_N30
+// alta_lcell_ff ref_en_q(
+// Location: LCCOMB_X1_Y15_N30
+// alta_lcell_comb \ref_en_q~feeder (
+alta_slice ref_en_q(
+	.A(vcc),
+	.B(vcc),
+	.C(vcc),
+	.D(\MCU_D[6]~input_o ),
+	.Cin(),
+	.Qin(\ref_en_q~q ),
+	.Clk(\MCU_IO_STBX~inputclkctrl_outclk__lcd_reset_q~0_combout_X1_Y15_SIG_SIG ),
+	.AsyncReset(AsyncReset_X1_Y15_GND),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\ref_en_q~feeder_combout ),
+	.Cout(),
+	.Q(\ref_en_q~q ));
+defparam ref_en_q.mask = 16'hFF00;
+defparam ref_en_q.mode = "logic";
+defparam ref_en_q.modeMux = 1'b0;
+defparam ref_en_q.FeedbackMux = 1'b0;
+defparam ref_en_q.ShiftMux = 1'b0;
+defparam ref_en_q.BypassEn = 1'b0;
+defparam ref_en_q.CarryEnb = 1'b1;
+defparam ref_en_q.AsyncResetMux = 2'b00;
+defparam ref_en_q.SyncResetMux = 2'bxx;
+defparam ref_en_q.SyncLoadMux = 2'bxx;
+defparam ref_en_q.coord_x = 1;
+defparam ref_en_q.coord_y = 15;
+defparam ref_en_q.coord_z = 15;
+// Location: LCCOMB_X1_Y15_N4
+// alta_lcell_comb \tp_q[3]~0 (
+alta_slice \tp_q[3]~0 (
+	.A(vcc),
+	.B(vcc),
+	.C(\MCU_ADDR~input_o ),
+	.D(\MCU_DIR~input_o ),
+	.Cin(),
+	.Qin(),
+	.Clk(),
+	.AsyncReset(),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\tp_q[3]~0_combout ),
+	.Cout(),
+	.Q());
+defparam \tp_q[3]~0 .mask = 16'h000F;
+defparam \tp_q[3]~0 .mode = "logic";
+defparam \tp_q[3]~0 .modeMux = 1'b0;
+defparam \tp_q[3]~0 .FeedbackMux = 1'b0;
+defparam \tp_q[3]~0 .ShiftMux = 1'b0;
+defparam \tp_q[3]~0 .BypassEn = 1'b0;
+defparam \tp_q[3]~0 .CarryEnb = 1'b1;
+defparam \tp_q[3]~0 .AsyncResetMux = 2'bxx;
+defparam \tp_q[3]~0 .SyncResetMux = 2'bxx;
+defparam \tp_q[3]~0 .SyncLoadMux = 2'bxx;
+defparam \tp_q[3]~0 .coord_x = 1;
+defparam \tp_q[3]~0 .coord_y = 15;
+defparam \tp_q[3]~0 .coord_z = 2;
+// Location: FF_X1_Y15_N6
+// alta_lcell_ff sysoff_q(
+// Location: LCCOMB_X1_Y15_N6
+// alta_lcell_comb \sysoff_q~feeder (
+alta_slice sysoff_q(
+	.A(vcc),
+	.B(vcc),
+	.C(vcc),
+	.D(\MCU_D[2]~input_o ),
+	.Cin(),
+	.Qin(\sysoff_q~q ),
+	.Clk(\MCU_IO_STBX~inputclkctrl_outclk__lcd_reset_q~0_combout_X1_Y15_SIG_SIG ),
+	.AsyncReset(AsyncReset_X1_Y15_GND),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\sysoff_q~feeder_combout ),
+	.Cout(),
+	.Q(\sysoff_q~q ));
+defparam sysoff_q.mask = 16'hFF00;
+defparam sysoff_q.mode = "logic";
+defparam sysoff_q.modeMux = 1'b0;
+defparam sysoff_q.FeedbackMux = 1'b0;
+defparam sysoff_q.ShiftMux = 1'b0;
+defparam sysoff_q.BypassEn = 1'b0;
+defparam sysoff_q.CarryEnb = 1'b1;
+defparam sysoff_q.AsyncResetMux = 2'b00;
+defparam sysoff_q.SyncResetMux = 2'bxx;
+defparam sysoff_q.SyncLoadMux = 2'bxx;
+defparam sysoff_q.coord_x = 1;
+defparam sysoff_q.coord_y = 15;
+defparam sysoff_q.coord_z = 3;
+// Location: FF_X1_Y15_N8
+// alta_lcell_ff \tp_q[6] (
+// Location: LCCOMB_X1_Y15_N8
+// alta_lcell_comb \tp_q[6]~feeder (
+alta_slice \tp_q[6] (
+	.A(vcc),
+	.B(vcc),
+	.C(vcc),
+	.D(\MCU_D[6]~input_o ),
+	.Cin(),
+	.Qin(tp_q[6]),
+	.Clk(\MCU_IO_STBX~inputclkctrl_outclk__tp_q[3]~0_combout_X1_Y15_SIG_SIG ),
+	.AsyncReset(AsyncReset_X1_Y15_GND),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\tp_q[6]~feeder_combout ),
+	.Cout(),
+	.Q(tp_q[6]));
+defparam \tp_q[6] .mask = 16'hFF00;
+defparam \tp_q[6] .mode = "logic";
+defparam \tp_q[6] .modeMux = 1'b0;
+defparam \tp_q[6] .FeedbackMux = 1'b0;
+defparam \tp_q[6] .ShiftMux = 1'b0;
+defparam \tp_q[6] .BypassEn = 1'b0;
+defparam \tp_q[6] .CarryEnb = 1'b1;
+defparam \tp_q[6] .AsyncResetMux = 2'b00;
+defparam \tp_q[6] .SyncResetMux = 2'bxx;
+defparam \tp_q[6] .SyncLoadMux = 2'bxx;
+
+defparam \tp_q[6] .coord_x = 1;
+defparam \tp_q[6] .coord_y = 15;
+defparam \tp_q[6] .coord_z = 4;
+// Location: CLKENCTRL_X1_Y15_N0
+alta_clkenctrl clken_ctrl_X1_Y15_N0(.ClkIn(\MCU_IO_STBX~inputclkctrl_outclk ), .ClkEn(\tp_q[3]~0_combout ), .ClkOut(\MCU_IO_STBX~inputclkctrl_outclk__tp_q[3]~0_combout_X1_Y15_SIG_SIG ));
+defparam clken_ctrl_X1_Y15_N0.ClkMux = 2'b10;
+defparam clken_ctrl_X1_Y15_N0.ClkEnMux = 2'b10;
+
+defparam clken_ctrl_X1_Y15_N0.coord_x = 1;
+defparam clken_ctrl_X1_Y15_N0.coord_y = 15;
+defparam clken_ctrl_X1_Y15_N0.coord_z = 0;
+// Location: ASYNCCTRL_X1_Y15_N0
+alta_asyncctrl asyncreset_ctrl_X1_Y15_N0(.Din(), .Dout(AsyncReset_X1_Y15_GND));
+defparam asyncreset_ctrl_X1_Y15_N0.AsyncCtrlMux = 2'b00;
+
+defparam asyncreset_ctrl_X1_Y15_N0.coord_x = 1;
+defparam asyncreset_ctrl_X1_Y15_N0.coord_y = 15;
+defparam asyncreset_ctrl_X1_Y15_N0.coord_z = 0;
+// Location: CLKENCTRL_X1_Y15_N1
+alta_clkenctrl clken_ctrl_X1_Y15_N1(.ClkIn(\MCU_IO_STBX~inputclkctrl_outclk ), .ClkEn(\lcd_reset_q~0_combout ), .ClkOut(\MCU_IO_STBX~inputclkctrl_outclk__lcd_reset_q~0_combout_X1_Y15_SIG_SIG ));
+defparam clken_ctrl_X1_Y15_N1.ClkMux = 2'b10;
+defparam clken_ctrl_X1_Y15_N1.ClkEnMux = 2'b10;
+
+defparam clken_ctrl_X1_Y15_N1.coord_x = 1;
+defparam clken_ctrl_X1_Y15_N1.coord_y = 15;
+defparam clken_ctrl_X1_Y15_N1.coord_z = 1;
+// Location: SYNCCTRL_X1_Y15_N0
+alta_syncctrl syncreset_ctrl_X1_Y15(.Din(), .Dout(SyncReset_X1_Y15_GND));
+defparam syncreset_ctrl_X1_Y15.SyncCtrlMux = 2'b00;
+
+defparam syncreset_ctrl_X1_Y15.coord_x = 1;
+defparam syncreset_ctrl_X1_Y15.coord_y = 15;
+defparam syncreset_ctrl_X1_Y15.coord_z = 0;
+// Location: SYNCCTRL_X1_Y15_N1
+alta_syncctrl syncload_ctrl_X1_Y15(.Din(), .Dout(SyncLoad_X1_Y15_VCC));
+defparam syncload_ctrl_X1_Y15.SyncCtrlMux = 2'b01;
+defparam syncload_ctrl_X1_Y15.coord_x = 1;
+defparam syncload_ctrl_X1_Y15.coord_y = 15;
+defparam syncload_ctrl_X1_Y15.coord_z = 1;
+// Location: LCCOMB_X1_Y18_N14
+// alta_lcell_comb \mcu_data_out[7]~15 (
+alta_slice \mcu_data_out[7]~15 (
+	.A(\LCD_TE~input_o ),
+	.B(\MCU_DIR~input_o ),
+	.C(\MCU_IO_STBX~input_o ),
+	.D(\mcu_data_out[7]~14_combout ),
+	.Cin(),
+	.Qin(),
+	.Clk(),
+	.AsyncReset(),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\mcu_data_out[7]~15_combout ),
+	.Cout(),
+	.Q());
+defparam \mcu_data_out[7]~15 .mask = 16'hFB08;
+defparam \mcu_data_out[7]~15 .mode = "logic";
+defparam \mcu_data_out[7]~15 .modeMux = 1'b0;
+defparam \mcu_data_out[7]~15 .FeedbackMux = 1'b0;
+defparam \mcu_data_out[7]~15 .ShiftMux = 1'b0;
+defparam \mcu_data_out[7]~15 .BypassEn = 1'b0;
+defparam \mcu_data_out[7]~15 .CarryEnb = 1'b1;
+defparam \mcu_data_out[7]~15 .AsyncResetMux = 2'bxx;
+defparam \mcu_data_out[7]~15 .SyncResetMux = 2'bxx;
+defparam \mcu_data_out[7]~15 .SyncLoadMux = 2'bxx;
+defparam \mcu_data_out[7]~15 .coord_x = 1;
+defparam \mcu_data_out[7]~15 .coord_y = 18;
+defparam \mcu_data_out[7]~15 .coord_z = 7;
+// Location: LCCOMB_X1_Y18_N16
+// alta_lcell_comb \mcu_data_out[6]~13 (
+alta_slice \mcu_data_out[6]~13 (
+	.A(\SW_ROT_B~input_o ),
+	.B(\MCU_IO_STBX~input_o ),
+	.C(\mcu_data_out[6]~12_combout ),
+	.D(\MCU_DIR~input_o ),
+	.Cin(),
+	.Qin(),
+	.Clk(),
+	.AsyncReset(),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\mcu_data_out[6]~13_combout ),
+	.Cout(),
+	.Q());
+defparam \mcu_data_out[6]~13 .mask = 16'hD1F0;
+defparam \mcu_data_out[6]~13 .mode = "logic";
+defparam \mcu_data_out[6]~13 .modeMux = 1'b0;
+defparam \mcu_data_out[6]~13 .FeedbackMux = 1'b0;
+defparam \mcu_data_out[6]~13 .ShiftMux = 1'b0;
+defparam \mcu_data_out[6]~13 .BypassEn = 1'b0;
+defparam \mcu_data_out[6]~13 .CarryEnb = 1'b1;
+defparam \mcu_data_out[6]~13 .AsyncResetMux = 2'bxx;
+defparam \mcu_data_out[6]~13 .SyncResetMux = 2'bxx;
+defparam \mcu_data_out[6]~13 .SyncLoadMux = 2'bxx;
+defparam \mcu_data_out[6]~13 .coord_x = 1;
+defparam \mcu_data_out[6]~13 .coord_y = 18;
+defparam \mcu_data_out[6]~13 .coord_z = 8;
+// Location: LCCOMB_X1_Y18_N28
+// alta_lcell_comb \mcu_data_out[1]~3 (
+alta_slice \mcu_data_out[1]~3 (
+	.A(\SW_L~input_o ),
+	.B(\MCU_DIR~input_o ),
+	.C(\MCU_IO_STBX~input_o ),
+	.D(\mcu_data_out[1]~2_combout ),
+	.Cin(),
+	.Qin(),
+	.Clk(),
+	.AsyncReset(),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\mcu_data_out[1]~3_combout ),
+	.Cout(),
+	.Q());
+defparam \mcu_data_out[1]~3 .mask = 16'hF704;
+defparam \mcu_data_out[1]~3 .mode = "logic";
+defparam \mcu_data_out[1]~3 .modeMux = 1'b0;
+defparam \mcu_data_out[1]~3 .FeedbackMux = 1'b0;
+defparam \mcu_data_out[1]~3 .ShiftMux = 1'b0;
+defparam \mcu_data_out[1]~3 .BypassEn = 1'b0;
+defparam \mcu_data_out[1]~3 .CarryEnb = 1'b1;
+defparam \mcu_data_out[1]~3 .AsyncResetMux = 2'bxx;
+defparam \mcu_data_out[1]~3 .SyncResetMux = 2'bxx;
+defparam \mcu_data_out[1]~3 .SyncLoadMux = 2'bxx;
+defparam \mcu_data_out[1]~3 .coord_x = 1;
+defparam \mcu_data_out[1]~3 .coord_y = 18;
+defparam \mcu_data_out[1]~3 .coord_z = 14;
+// Location: LCCOMB_X1_Y18_N30
+// alta_lcell_comb \mcu_data_out[0]~1 (
+alta_slice \mcu_data_out[0]~1 (
+	.A(\SW_R~input_o ),
+	.B(\MCU_IO_STBX~input_o ),
+	.C(\mcu_data_out[0]~0_combout ),
+	.D(\MCU_DIR~input_o ),
+	.Cin(),
+	.Qin(),
+	.Clk(),
+	.AsyncReset(),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\mcu_data_out[0]~1_combout ),
+	.Cout(),
+	.Q());
+defparam \mcu_data_out[0]~1 .mask = 16'hD1F0;
+defparam \mcu_data_out[0]~1 .mode = "logic";
+defparam \mcu_data_out[0]~1 .modeMux = 1'b0;
+defparam \mcu_data_out[0]~1 .FeedbackMux = 1'b0;
+defparam \mcu_data_out[0]~1 .ShiftMux = 1'b0;
+defparam \mcu_data_out[0]~1 .BypassEn = 1'b0;
+defparam \mcu_data_out[0]~1 .CarryEnb = 1'b1;
+defparam \mcu_data_out[0]~1 .AsyncResetMux = 2'bxx;
+defparam \mcu_data_out[0]~1 .SyncResetMux = 2'bxx;
+defparam \mcu_data_out[0]~1 .SyncLoadMux = 2'bxx;
+defparam \mcu_data_out[0]~1 .coord_x = 1;
+defparam \mcu_data_out[0]~1 .coord_y = 18;
+defparam \mcu_data_out[0]~1 .coord_z = 15;
+// Location: FF_X1_Y19_N30
+// alta_lcell_ff \lcd_data_in_q[0] (
+// Location: LCCOMB_X1_Y19_N30
+// alta_lcell_comb \mcu_data_out[0]~0 (
+alta_slice \lcd_data_in_q[0] (
+	.A(\LCD_DB[8]~input_o ),
+	.B(vcc),
+	.C(\LCD_DB[0]~input_o ),
+	.D(\MCU_LCD_RDX~input_o ),
+	.Cin(),
+	.Qin(lcd_data_in_q[0]),
+	.Clk(\MCU_LCD_RDX~inputclkctrl_outclk_X1_Y19_SIG_VCC ),
+	.AsyncReset(AsyncReset_X1_Y19_GND),
+	.SyncReset(SyncReset_X1_Y19_GND),
+	.ShiftData(),
+	.SyncLoad(SyncLoad_X1_Y19_VCC),
+	.LutOut(\mcu_data_out[0]~0_combout ),
+	.Cout(),
+	.Q(lcd_data_in_q[0]));
+defparam \lcd_data_in_q[0] .mask = 16'hF0AA;
+defparam \lcd_data_in_q[0] .mode = "logic";
+defparam \lcd_data_in_q[0] .modeMux = 1'b0;
+defparam \lcd_data_in_q[0] .FeedbackMux = 1'b1;
+defparam \lcd_data_in_q[0] .ShiftMux = 1'b0;
+defparam \lcd_data_in_q[0] .BypassEn = 1'b1;
+defparam \lcd_data_in_q[0] .CarryEnb = 1'b1;
+defparam \lcd_data_in_q[0] .AsyncResetMux = 2'b00;
+defparam \lcd_data_in_q[0] .SyncResetMux = 2'b00;
+defparam \lcd_data_in_q[0] .SyncLoadMux = 2'b01;
+defparam \lcd_data_in_q[0] .coord_x = 1;
+defparam \lcd_data_in_q[0] .coord_y = 19;
+defparam \lcd_data_in_q[0] .coord_z = 15;
+// Location: FF_X1_Y19_N4
+// alta_lcell_ff \lcd_data_in_q[6] (
+// Location: LCCOMB_X1_Y19_N4
+// alta_lcell_comb \mcu_data_out[6]~12 (
+alta_slice \lcd_data_in_q[6] (
+	.A(\LCD_DB[14]~input_o ),
+	.B(vcc),
+	.C(\LCD_DB[6]~input_o ),
+	.D(\MCU_LCD_RDX~input_o ),
+	.Cin(),
+	.Qin(lcd_data_in_q[6]),
+	.Clk(\MCU_LCD_RDX~inputclkctrl_outclk_X1_Y19_SIG_VCC ),
+	.AsyncReset(AsyncReset_X1_Y19_GND),
+	.SyncReset(SyncReset_X1_Y19_GND),
+	.ShiftData(),
+	.SyncLoad(SyncLoad_X1_Y19_VCC),
+	.LutOut(\mcu_data_out[6]~12_combout ),
+	.Cout(),
+	.Q(lcd_data_in_q[6]));
+defparam \lcd_data_in_q[6] .mask = 16'hF0AA;
+defparam \lcd_data_in_q[6] .mode = "logic";
+defparam \lcd_data_in_q[6] .modeMux = 1'b0;
+defparam \lcd_data_in_q[6] .FeedbackMux = 1'b1;
+defparam \lcd_data_in_q[6] .ShiftMux = 1'b0;
+defparam \lcd_data_in_q[6] .BypassEn = 1'b1;
+defparam \lcd_data_in_q[6] .CarryEnb = 1'b1;
+defparam \lcd_data_in_q[6] .AsyncResetMux = 2'b00;
+defparam \lcd_data_in_q[6] .SyncResetMux = 2'b00;
+defparam \lcd_data_in_q[6] .SyncLoadMux = 2'b01;
+
+defparam \lcd_data_in_q[6] .coord_x = 1;
+defparam \lcd_data_in_q[6] .coord_y = 19;
+defparam \lcd_data_in_q[6] .coord_z = 2;
+// Location: CLKENCTRL_X1_Y19_N0
+alta_clkenctrl clken_ctrl_X1_Y19_N0(.ClkIn(\MCU_LCD_RDX~inputclkctrl_outclk ), .ClkEn(), .ClkOut(\MCU_LCD_RDX~inputclkctrl_outclk_X1_Y19_SIG_VCC ));
+defparam clken_ctrl_X1_Y19_N0.ClkMux = 2'b10;
+defparam clken_ctrl_X1_Y19_N0.ClkEnMux = 2'b01;
+
+defparam clken_ctrl_X1_Y19_N0.coord_x = 1;
+defparam clken_ctrl_X1_Y19_N0.coord_y = 19;
+defparam clken_ctrl_X1_Y19_N0.coord_z = 0;
+// Location: ASYNCCTRL_X1_Y19_N0
+alta_asyncctrl asyncreset_ctrl_X1_Y19_N0(.Din(), .Dout(AsyncReset_X1_Y19_GND));
+defparam asyncreset_ctrl_X1_Y19_N0.AsyncCtrlMux = 2'b00;
+
+defparam asyncreset_ctrl_X1_Y19_N0.coord_x = 1;
+defparam asyncreset_ctrl_X1_Y19_N0.coord_y = 19;
+defparam asyncreset_ctrl_X1_Y19_N0.coord_z = 0;
+// Location: SYNCCTRL_X1_Y19_N0
+alta_syncctrl syncreset_ctrl_X1_Y19(.Din(), .Dout(SyncReset_X1_Y19_GND));
+defparam syncreset_ctrl_X1_Y19.SyncCtrlMux = 2'b00;
+
+defparam syncreset_ctrl_X1_Y19.coord_x = 1;
+defparam syncreset_ctrl_X1_Y19.coord_y = 19;
+defparam syncreset_ctrl_X1_Y19.coord_z = 0;
+// Location: SYNCCTRL_X1_Y19_N1
+alta_syncctrl syncload_ctrl_X1_Y19(.Din(), .Dout(SyncLoad_X1_Y19_VCC));
+defparam syncload_ctrl_X1_Y19.SyncCtrlMux = 2'b01;
+defparam syncload_ctrl_X1_Y19.coord_x = 1;
+defparam syncload_ctrl_X1_Y19.coord_y = 19;
+defparam syncload_ctrl_X1_Y19.coord_z = 1;
+// Location: FF_X1_Y20_N0
+// alta_lcell_ff \lcd_data_out_q[1] (
+// Location: LCCOMB_X1_Y20_N0
+// alta_lcell_comb \lcd_data_out_q[1]~feeder (
+alta_slice \lcd_data_out_q[1] (
+	.A(vcc),
+	.B(vcc),
+	.C(vcc),
+	.D(\MCU_D[1]~input_o ),
+	.Cin(),
+	.Qin(lcd_data_out_q[1]),
+	.Clk(\MCU_LCD_WRX~inputclkctrl_outclk_X1_Y20_INV_VCC ),
+	.AsyncReset(AsyncReset_X1_Y20_GND),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\lcd_data_out_q[1]~feeder_combout ),
+	.Cout(),
+	.Q(lcd_data_out_q[1]));
+defparam \lcd_data_out_q[1] .mask = 16'hFF00;
+defparam \lcd_data_out_q[1] .mode = "logic";
+defparam \lcd_data_out_q[1] .modeMux = 1'b0;
+defparam \lcd_data_out_q[1] .FeedbackMux = 1'b0;
+defparam \lcd_data_out_q[1] .ShiftMux = 1'b0;
+defparam \lcd_data_out_q[1] .BypassEn = 1'b0;
+defparam \lcd_data_out_q[1] .CarryEnb = 1'b1;
+defparam \lcd_data_out_q[1] .AsyncResetMux = 2'b00;
+defparam \lcd_data_out_q[1] .SyncResetMux = 2'bxx;
+defparam \lcd_data_out_q[1] .SyncLoadMux = 2'bxx;
+defparam \lcd_data_out_q[1] .coord_x = 1;
+defparam \lcd_data_out_q[1] .coord_y = 20;
+defparam \lcd_data_out_q[1] .coord_z = 0;
+// Location: FF_X1_Y20_N10
+// alta_lcell_ff \lcd_data_out_q[2] (
+// Location: LCCOMB_X1_Y20_N10
+// alta_lcell_comb \lcd_data_out_q[2]~feeder (
+alta_slice \lcd_data_out_q[2] (
+	.A(vcc),
+	.B(vcc),
+	.C(vcc),
+	.D(\MCU_D[2]~input_o ),
+	.Cin(),
+	.Qin(lcd_data_out_q[2]),
+	.Clk(\MCU_LCD_WRX~inputclkctrl_outclk_X1_Y20_INV_VCC ),
+	.AsyncReset(AsyncReset_X1_Y20_GND),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\lcd_data_out_q[2]~feeder_combout ),
+	.Cout(),
+	.Q(lcd_data_out_q[2]));
+defparam \lcd_data_out_q[2] .mask = 16'hFF00;
+defparam \lcd_data_out_q[2] .mode = "logic";
+defparam \lcd_data_out_q[2] .modeMux = 1'b0;
+defparam \lcd_data_out_q[2] .FeedbackMux = 1'b0;
+defparam \lcd_data_out_q[2] .ShiftMux = 1'b0;
+defparam \lcd_data_out_q[2] .BypassEn = 1'b0;
+defparam \lcd_data_out_q[2] .CarryEnb = 1'b1;
+defparam \lcd_data_out_q[2] .AsyncResetMux = 2'b00;
+defparam \lcd_data_out_q[2] .SyncResetMux = 2'bxx;
+defparam \lcd_data_out_q[2] .SyncLoadMux = 2'bxx;
+defparam \lcd_data_out_q[2] .coord_x = 1;
+defparam \lcd_data_out_q[2] .coord_y = 20;
+defparam \lcd_data_out_q[2] .coord_z = 5;
+// Location: FF_X1_Y20_N12
+// alta_lcell_ff \lcd_data_out_q[6] (
+alta_slice \lcd_data_out_q[6] (
+	.A(),
+	.B(),
+	.C(\MCU_D[6]~input_o ),
+	.D(),
+	.Cin(),
+	.Qin(lcd_data_out_q[6]),
+	.Clk(\MCU_LCD_WRX~inputclkctrl_outclk_X1_Y20_INV_VCC ),
+	.AsyncReset(AsyncReset_X1_Y20_GND),
+	.SyncReset(SyncReset_X1_Y20_GND),
+	.ShiftData(),
+	.SyncLoad(SyncLoad_X1_Y20_VCC),
+	.LutOut(),
+	.Cout(),
+	.Q(lcd_data_out_q[6]));
+defparam \lcd_data_out_q[6] .mask = 16'hFFFF;
+defparam \lcd_data_out_q[6] .mode = "ripple";
+defparam \lcd_data_out_q[6] .modeMux = 1'b1;
+defparam \lcd_data_out_q[6] .FeedbackMux = 1'b0;
+defparam \lcd_data_out_q[6] .ShiftMux = 1'b0;
+defparam \lcd_data_out_q[6] .BypassEn = 1'b1;
+defparam \lcd_data_out_q[6] .CarryEnb = 1'b1;
+defparam \lcd_data_out_q[6] .AsyncResetMux = 2'b00;
+defparam \lcd_data_out_q[6] .SyncResetMux = 2'b00;
+defparam \lcd_data_out_q[6] .SyncLoadMux = 2'b01;
+defparam \lcd_data_out_q[6] .coord_x = 1;
+defparam \lcd_data_out_q[6] .coord_y = 20;
+defparam \lcd_data_out_q[6] .coord_z = 6;
+// Location: FF_X1_Y20_N14
+// alta_lcell_ff \lcd_data_out_q[7] (
+// Location: LCCOMB_X1_Y20_N14
+// alta_lcell_comb \lcd_data_out_q[7]~feeder (
+alta_slice \lcd_data_out_q[7] (
+	.A(vcc),
+	.B(vcc),
+	.C(vcc),
+	.D(\MCU_D[7]~input_o ),
+	.Cin(),
+	.Qin(lcd_data_out_q[7]),
+	.Clk(\MCU_LCD_WRX~inputclkctrl_outclk_X1_Y20_INV_VCC ),
+	.AsyncReset(AsyncReset_X1_Y20_GND),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\lcd_data_out_q[7]~feeder_combout ),
+	.Cout(),
+	.Q(lcd_data_out_q[7]));
+defparam \lcd_data_out_q[7] .mask = 16'hFF00;
+defparam \lcd_data_out_q[7] .mode = "logic";
+defparam \lcd_data_out_q[7] .modeMux = 1'b0;
+defparam \lcd_data_out_q[7] .FeedbackMux = 1'b0;
+defparam \lcd_data_out_q[7] .ShiftMux = 1'b0;
+defparam \lcd_data_out_q[7] .BypassEn = 1'b0;
+defparam \lcd_data_out_q[7] .CarryEnb = 1'b1;
+defparam \lcd_data_out_q[7] .AsyncResetMux = 2'b00;
+defparam \lcd_data_out_q[7] .SyncResetMux = 2'bxx;
+defparam \lcd_data_out_q[7] .SyncLoadMux = 2'bxx;
+defparam \lcd_data_out_q[7] .coord_x = 1;
+defparam \lcd_data_out_q[7] .coord_y = 20;
+defparam \lcd_data_out_q[7] .coord_z = 7;
+// Location: FF_X1_Y20_N30
+// alta_lcell_ff \lcd_data_out_q[0] (
+// Location: LCCOMB_X1_Y20_N30
+// alta_lcell_comb \lcd_data_out_q[0]~feeder (
+alta_slice \lcd_data_out_q[0] (
+	.A(vcc),
+	.B(vcc),
+	.C(vcc),
+	.D(\MCU_D[0]~input_o ),
+	.Cin(),
+	.Qin(lcd_data_out_q[0]),
+	.Clk(\MCU_LCD_WRX~inputclkctrl_outclk_X1_Y20_INV_VCC ),
+	.AsyncReset(AsyncReset_X1_Y20_GND),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\lcd_data_out_q[0]~feeder_combout ),
+	.Cout(),
+	.Q(lcd_data_out_q[0]));
+defparam \lcd_data_out_q[0] .mask = 16'hFF00;
+defparam \lcd_data_out_q[0] .mode = "logic";
+defparam \lcd_data_out_q[0] .modeMux = 1'b0;
+defparam \lcd_data_out_q[0] .FeedbackMux = 1'b0;
+defparam \lcd_data_out_q[0] .ShiftMux = 1'b0;
+defparam \lcd_data_out_q[0] .BypassEn = 1'b0;
+defparam \lcd_data_out_q[0] .CarryEnb = 1'b1;
+defparam \lcd_data_out_q[0] .AsyncResetMux = 2'b00;
+defparam \lcd_data_out_q[0] .SyncResetMux = 2'bxx;
+defparam \lcd_data_out_q[0] .SyncLoadMux = 2'bxx;
+
+defparam \lcd_data_out_q[0] .coord_x = 1;
+defparam \lcd_data_out_q[0] .coord_y = 20;
+defparam \lcd_data_out_q[0] .coord_z = 15;
+// Location: CLKENCTRL_X1_Y20_N0
+alta_clkenctrl clken_ctrl_X1_Y20_N0(.ClkIn(\MCU_LCD_WRX~inputclkctrl_outclk ), .ClkEn(), .ClkOut(\MCU_LCD_WRX~inputclkctrl_outclk_X1_Y20_INV_VCC ));
+defparam clken_ctrl_X1_Y20_N0.ClkMux = 2'b11;
+defparam clken_ctrl_X1_Y20_N0.ClkEnMux = 2'b01;
+
+defparam clken_ctrl_X1_Y20_N0.coord_x = 1;
+defparam clken_ctrl_X1_Y20_N0.coord_y = 20;
+defparam clken_ctrl_X1_Y20_N0.coord_z = 0;
+// Location: ASYNCCTRL_X1_Y20_N0
+alta_asyncctrl asyncreset_ctrl_X1_Y20_N0(.Din(), .Dout(AsyncReset_X1_Y20_GND));
+defparam asyncreset_ctrl_X1_Y20_N0.AsyncCtrlMux = 2'b00;
+
+defparam asyncreset_ctrl_X1_Y20_N0.coord_x = 1;
+defparam asyncreset_ctrl_X1_Y20_N0.coord_y = 20;
+defparam asyncreset_ctrl_X1_Y20_N0.coord_z = 0;
+// Location: SYNCCTRL_X1_Y20_N0
+alta_syncctrl syncreset_ctrl_X1_Y20(.Din(), .Dout(SyncReset_X1_Y20_GND));
+defparam syncreset_ctrl_X1_Y20.SyncCtrlMux = 2'b00;
+
+defparam syncreset_ctrl_X1_Y20.coord_x = 1;
+defparam syncreset_ctrl_X1_Y20.coord_y = 20;
+defparam syncreset_ctrl_X1_Y20.coord_z = 0;
+// Location: SYNCCTRL_X1_Y20_N1
+alta_syncctrl syncload_ctrl_X1_Y20(.Din(), .Dout(SyncLoad_X1_Y20_VCC));
+defparam syncload_ctrl_X1_Y20.SyncCtrlMux = 2'b01;
+defparam syncload_ctrl_X1_Y20.coord_x = 1;
+defparam syncload_ctrl_X1_Y20.coord_y = 20;
+defparam syncload_ctrl_X1_Y20.coord_z = 1;
+// Location: FF_X1_Y21_N28
+// alta_lcell_ff \lcd_data_in_q[7] (
+// Location: LCCOMB_X1_Y21_N28
+// alta_lcell_comb \mcu_data_out[7]~14 (
+alta_slice \lcd_data_in_q[7] (
+	.A(\LCD_DB[15]~input_o ),
+	.B(\MCU_LCD_RDX~input_o ),
+	.C(\LCD_DB[7]~input_o ),
+	.D(vcc),
+	.Cin(),
+	.Qin(lcd_data_in_q[7]),
+	.Clk(\MCU_LCD_RDX~inputclkctrl_outclk_X1_Y21_SIG_VCC ),
+	.AsyncReset(AsyncReset_X1_Y21_GND),
+	.SyncReset(SyncReset_X1_Y21_GND),
+	.ShiftData(),
+	.SyncLoad(SyncLoad_X1_Y21_VCC),
+	.LutOut(\mcu_data_out[7]~14_combout ),
+	.Cout(),
+	.Q(lcd_data_in_q[7]));
+defparam \lcd_data_in_q[7] .mask = 16'hE2E2;
+defparam \lcd_data_in_q[7] .mode = "logic";
+defparam \lcd_data_in_q[7] .modeMux = 1'b0;
+defparam \lcd_data_in_q[7] .FeedbackMux = 1'b1;
+defparam \lcd_data_in_q[7] .ShiftMux = 1'b0;
+defparam \lcd_data_in_q[7] .BypassEn = 1'b1;
+defparam \lcd_data_in_q[7] .CarryEnb = 1'b1;
+defparam \lcd_data_in_q[7] .AsyncResetMux = 2'b00;
+defparam \lcd_data_in_q[7] .SyncResetMux = 2'b00;
+defparam \lcd_data_in_q[7] .SyncLoadMux = 2'b01;
+defparam \lcd_data_in_q[7] .coord_x = 1;
+defparam \lcd_data_in_q[7] .coord_y = 21;
+defparam \lcd_data_in_q[7] .coord_z = 14;
+// Location: FF_X1_Y21_N4
+// alta_lcell_ff \lcd_data_in_q[1] (
+// Location: LCCOMB_X1_Y21_N4
+// alta_lcell_comb \mcu_data_out[1]~2 (
+alta_slice \lcd_data_in_q[1] (
+	.A(\LCD_DB[9]~input_o ),
+	.B(\MCU_LCD_RDX~input_o ),
+	.C(\LCD_DB[1]~input_o ),
+	.D(vcc),
+	.Cin(),
+	.Qin(lcd_data_in_q[1]),
+	.Clk(\MCU_LCD_RDX~inputclkctrl_outclk_X1_Y21_SIG_VCC ),
+	.AsyncReset(AsyncReset_X1_Y21_GND),
+	.SyncReset(SyncReset_X1_Y21_GND),
+	.ShiftData(),
+	.SyncLoad(SyncLoad_X1_Y21_VCC),
+	.LutOut(\mcu_data_out[1]~2_combout ),
+	.Cout(),
+	.Q(lcd_data_in_q[1]));
+defparam \lcd_data_in_q[1] .mask = 16'hE2E2;
+defparam \lcd_data_in_q[1] .mode = "logic";
+defparam \lcd_data_in_q[1] .modeMux = 1'b0;
+defparam \lcd_data_in_q[1] .FeedbackMux = 1'b1;
+defparam \lcd_data_in_q[1] .ShiftMux = 1'b0;
+defparam \lcd_data_in_q[1] .BypassEn = 1'b1;
+defparam \lcd_data_in_q[1] .CarryEnb = 1'b1;
+defparam \lcd_data_in_q[1] .AsyncResetMux = 2'b00;
+defparam \lcd_data_in_q[1] .SyncResetMux = 2'b00;
+defparam \lcd_data_in_q[1] .SyncLoadMux = 2'b01;
+
+defparam \lcd_data_in_q[1] .coord_x = 1;
+defparam \lcd_data_in_q[1] .coord_y = 21;
+defparam \lcd_data_in_q[1] .coord_z = 2;
+// Location: CLKENCTRL_X1_Y21_N0
+alta_clkenctrl clken_ctrl_X1_Y21_N0(.ClkIn(\MCU_LCD_RDX~inputclkctrl_outclk ), .ClkEn(), .ClkOut(\MCU_LCD_RDX~inputclkctrl_outclk_X1_Y21_SIG_VCC ));
+defparam clken_ctrl_X1_Y21_N0.ClkMux = 2'b10;
+defparam clken_ctrl_X1_Y21_N0.ClkEnMux = 2'b01;
+
+defparam clken_ctrl_X1_Y21_N0.coord_x = 1;
+defparam clken_ctrl_X1_Y21_N0.coord_y = 21;
+defparam clken_ctrl_X1_Y21_N0.coord_z = 0;
+// Location: ASYNCCTRL_X1_Y21_N0
+alta_asyncctrl asyncreset_ctrl_X1_Y21_N0(.Din(), .Dout(AsyncReset_X1_Y21_GND));
+defparam asyncreset_ctrl_X1_Y21_N0.AsyncCtrlMux = 2'b00;
+
+defparam asyncreset_ctrl_X1_Y21_N0.coord_x = 1;
+defparam asyncreset_ctrl_X1_Y21_N0.coord_y = 21;
+defparam asyncreset_ctrl_X1_Y21_N0.coord_z = 0;
+// Location: SYNCCTRL_X1_Y21_N0
+alta_syncctrl syncreset_ctrl_X1_Y21(.Din(), .Dout(SyncReset_X1_Y21_GND));
+defparam syncreset_ctrl_X1_Y21.SyncCtrlMux = 2'b00;
+
+defparam syncreset_ctrl_X1_Y21.coord_x = 1;
+defparam syncreset_ctrl_X1_Y21.coord_y = 21;
+defparam syncreset_ctrl_X1_Y21.coord_z = 0;
+// Location: SYNCCTRL_X1_Y21_N1
+alta_syncctrl syncload_ctrl_X1_Y21(.Din(), .Dout(SyncLoad_X1_Y21_VCC));
+defparam syncload_ctrl_X1_Y21.SyncCtrlMux = 2'b01;
+defparam syncload_ctrl_X1_Y21.coord_x = 1;
+defparam syncload_ctrl_X1_Y21.coord_y = 21;
+defparam syncload_ctrl_X1_Y21.coord_z = 1;
+// Location: LCCOMB_X1_Y23_N12
+// alta_lcell_comb \mcu_data_out[3]~7 (
+alta_slice \mcu_data_out[3]~7 (
+	.A(\SW_U~input_o ),
+	.B(\MCU_IO_STBX~input_o ),
+	.C(\MCU_DIR~input_o ),
+	.D(\mcu_data_out[3]~6_combout ),
+	.Cin(),
+	.Qin(),
+	.Clk(),
+	.AsyncReset(),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\mcu_data_out[3]~7_combout ),
+	.Cout(),
+	.Q());
+defparam \mcu_data_out[3]~7 .mask = 16'hDF10;
+defparam \mcu_data_out[3]~7 .mode = "logic";
+defparam \mcu_data_out[3]~7 .modeMux = 1'b0;
+defparam \mcu_data_out[3]~7 .FeedbackMux = 1'b0;
+defparam \mcu_data_out[3]~7 .ShiftMux = 1'b0;
+defparam \mcu_data_out[3]~7 .BypassEn = 1'b0;
+defparam \mcu_data_out[3]~7 .CarryEnb = 1'b1;
+defparam \mcu_data_out[3]~7 .AsyncResetMux = 2'bxx;
+defparam \mcu_data_out[3]~7 .SyncResetMux = 2'bxx;
+defparam \mcu_data_out[3]~7 .SyncLoadMux = 2'bxx;
+defparam \mcu_data_out[3]~7 .coord_x = 1;
+defparam \mcu_data_out[3]~7 .coord_y = 23;
+defparam \mcu_data_out[3]~7 .coord_z = 6;
+// Location: LCCOMB_X1_Y23_N14
+// alta_lcell_comb \mcu_data_out[4]~9 (
+alta_slice \mcu_data_out[4]~9 (
+	.A(\MCU_DIR~input_o ),
+	.B(\SW_SEL~input_o ),
+	.C(\MCU_IO_STBX~input_o ),
+	.D(\mcu_data_out[4]~8_combout ),
+	.Cin(),
+	.Qin(),
+	.Clk(),
+	.AsyncReset(),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\mcu_data_out[4]~9_combout ),
+	.Cout(),
+	.Q());
+defparam \mcu_data_out[4]~9 .mask = 16'hF702;
+defparam \mcu_data_out[4]~9 .mode = "logic";
+defparam \mcu_data_out[4]~9 .modeMux = 1'b0;
+defparam \mcu_data_out[4]~9 .FeedbackMux = 1'b0;
+defparam \mcu_data_out[4]~9 .ShiftMux = 1'b0;
+defparam \mcu_data_out[4]~9 .BypassEn = 1'b0;
+defparam \mcu_data_out[4]~9 .CarryEnb = 1'b1;
+defparam \mcu_data_out[4]~9 .AsyncResetMux = 2'bxx;
+defparam \mcu_data_out[4]~9 .SyncResetMux = 2'bxx;
+defparam \mcu_data_out[4]~9 .SyncLoadMux = 2'bxx;
+defparam \mcu_data_out[4]~9 .coord_x = 1;
+defparam \mcu_data_out[4]~9 .coord_y = 23;
+defparam \mcu_data_out[4]~9 .coord_z = 7;
+// Location: LCCOMB_X1_Y23_N16
+// alta_lcell_comb \mcu_data_out[2]~5 (
+alta_slice \mcu_data_out[2]~5 (
+	.A(\SW_D~input_o ),
+	.B(\MCU_IO_STBX~input_o ),
+	.C(\mcu_data_out[2]~4_combout ),
+	.D(\MCU_DIR~input_o ),
+	.Cin(),
+	.Qin(),
+	.Clk(),
+	.AsyncReset(),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\mcu_data_out[2]~5_combout ),
+	.Cout(),
+	.Q());
+defparam \mcu_data_out[2]~5 .mask = 16'hD1F0;
+defparam \mcu_data_out[2]~5 .mode = "logic";
+defparam \mcu_data_out[2]~5 .modeMux = 1'b0;
+defparam \mcu_data_out[2]~5 .FeedbackMux = 1'b0;
+defparam \mcu_data_out[2]~5 .ShiftMux = 1'b0;
+defparam \mcu_data_out[2]~5 .BypassEn = 1'b0;
+defparam \mcu_data_out[2]~5 .CarryEnb = 1'b1;
+defparam \mcu_data_out[2]~5 .AsyncResetMux = 2'bxx;
+defparam \mcu_data_out[2]~5 .SyncResetMux = 2'bxx;
+defparam \mcu_data_out[2]~5 .SyncLoadMux = 2'bxx;
+defparam \mcu_data_out[2]~5 .coord_x = 1;
+defparam \mcu_data_out[2]~5 .coord_y = 23;
+defparam \mcu_data_out[2]~5 .coord_z = 8;
+// Location: LCCOMB_X1_Y23_N30
+// alta_lcell_comb \mcu_data_out[5]~11 (
+alta_slice \mcu_data_out[5]~11 (
+	.A(\MCU_DIR~input_o ),
+	.B(\SW_ROT_A~input_o ),
+	.C(\MCU_IO_STBX~input_o ),
+	.D(\mcu_data_out[5]~10_combout ),
+	.Cin(),
+	.Qin(),
+	.Clk(),
+	.AsyncReset(),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\mcu_data_out[5]~11_combout ),
+	.Cout(),
+	.Q());
+defparam \mcu_data_out[5]~11 .mask = 16'hF702;
+defparam \mcu_data_out[5]~11 .mode = "logic";
+defparam \mcu_data_out[5]~11 .modeMux = 1'b0;
+defparam \mcu_data_out[5]~11 .FeedbackMux = 1'b0;
+defparam \mcu_data_out[5]~11 .ShiftMux = 1'b0;
+defparam \mcu_data_out[5]~11 .BypassEn = 1'b0;
+defparam \mcu_data_out[5]~11 .CarryEnb = 1'b1;
+defparam \mcu_data_out[5]~11 .AsyncResetMux = 2'bxx;
+defparam \mcu_data_out[5]~11 .SyncResetMux = 2'bxx;
+defparam \mcu_data_out[5]~11 .SyncLoadMux = 2'bxx;
+defparam \mcu_data_out[5]~11 .coord_x = 1;
+defparam \mcu_data_out[5]~11 .coord_y = 23;
+defparam \mcu_data_out[5]~11 .coord_z = 15;
+// Location: FF_X1_Y24_N30
+// alta_lcell_ff \lcd_data_in_q[2] (
+// Location: LCCOMB_X1_Y24_N30
+// alta_lcell_comb \mcu_data_out[2]~4 (
+alta_slice \lcd_data_in_q[2] (
+	.A(\LCD_DB[10]~input_o ),
+	.B(vcc),
+	.C(\LCD_DB[2]~input_o ),
+	.D(\MCU_LCD_RDX~input_o ),
+	.Cin(),
+	.Qin(lcd_data_in_q[2]),
+	.Clk(\MCU_LCD_RDX~inputclkctrl_outclk_X1_Y24_SIG_VCC ),
+	.AsyncReset(AsyncReset_X1_Y24_GND),
+	.SyncReset(SyncReset_X1_Y24_GND),
+	.ShiftData(),
+	.SyncLoad(SyncLoad_X1_Y24_VCC),
+	.LutOut(\mcu_data_out[2]~4_combout ),
+	.Cout(),
+	.Q(lcd_data_in_q[2]));
+defparam \lcd_data_in_q[2] .mask = 16'hF0AA;
+defparam \lcd_data_in_q[2] .mode = "logic";
+defparam \lcd_data_in_q[2] .modeMux = 1'b0;
+defparam \lcd_data_in_q[2] .FeedbackMux = 1'b1;
+defparam \lcd_data_in_q[2] .ShiftMux = 1'b0;
+defparam \lcd_data_in_q[2] .BypassEn = 1'b1;
+defparam \lcd_data_in_q[2] .CarryEnb = 1'b1;
+defparam \lcd_data_in_q[2] .AsyncResetMux = 2'b00;
+defparam \lcd_data_in_q[2] .SyncResetMux = 2'b00;
+defparam \lcd_data_in_q[2] .SyncLoadMux = 2'b01;
+
+defparam \lcd_data_in_q[2] .coord_x = 1;
+defparam \lcd_data_in_q[2] .coord_y = 24;
+defparam \lcd_data_in_q[2] .coord_z = 15;
+// Location: CLKENCTRL_X1_Y24_N0
+alta_clkenctrl clken_ctrl_X1_Y24_N0(.ClkIn(\MCU_LCD_RDX~inputclkctrl_outclk ), .ClkEn(), .ClkOut(\MCU_LCD_RDX~inputclkctrl_outclk_X1_Y24_SIG_VCC ));
+defparam clken_ctrl_X1_Y24_N0.ClkMux = 2'b10;
+defparam clken_ctrl_X1_Y24_N0.ClkEnMux = 2'b01;
+
+defparam clken_ctrl_X1_Y24_N0.coord_x = 1;
+defparam clken_ctrl_X1_Y24_N0.coord_y = 24;
+defparam clken_ctrl_X1_Y24_N0.coord_z = 0;
+// Location: ASYNCCTRL_X1_Y24_N0
+alta_asyncctrl asyncreset_ctrl_X1_Y24_N0(.Din(), .Dout(AsyncReset_X1_Y24_GND));
+defparam asyncreset_ctrl_X1_Y24_N0.AsyncCtrlMux = 2'b00;
+
+defparam asyncreset_ctrl_X1_Y24_N0.coord_x = 1;
+defparam asyncreset_ctrl_X1_Y24_N0.coord_y = 24;
+defparam asyncreset_ctrl_X1_Y24_N0.coord_z = 0;
+// Location: SYNCCTRL_X1_Y24_N0
+alta_syncctrl syncreset_ctrl_X1_Y24(.Din(), .Dout(SyncReset_X1_Y24_GND));
+defparam syncreset_ctrl_X1_Y24.SyncCtrlMux = 2'b00;
+
+defparam syncreset_ctrl_X1_Y24.coord_x = 1;
+defparam syncreset_ctrl_X1_Y24.coord_y = 24;
+defparam syncreset_ctrl_X1_Y24.coord_z = 0;
+// Location: SYNCCTRL_X1_Y24_N1
+alta_syncctrl syncload_ctrl_X1_Y24(.Din(), .Dout(SyncLoad_X1_Y24_VCC));
+defparam syncload_ctrl_X1_Y24.SyncCtrlMux = 2'b01;
+defparam syncload_ctrl_X1_Y24.coord_x = 1;
+defparam syncload_ctrl_X1_Y24.coord_y = 24;
+defparam syncload_ctrl_X1_Y24.coord_z = 1;
+// Location: FF_X1_Y26_N10
+// alta_lcell_ff \lcd_data_in_q[4] (
+// Location: LCCOMB_X1_Y26_N10
+// alta_lcell_comb \mcu_data_out[4]~8 (
+alta_slice \lcd_data_in_q[4] (
+	.A(\MCU_LCD_RDX~input_o ),
+	.B(\LCD_DB[12]~input_o ),
+	.C(\LCD_DB[4]~input_o ),
+	.D(vcc),
+	.Cin(),
+	.Qin(lcd_data_in_q[4]),
+	.Clk(\MCU_LCD_RDX~inputclkctrl_outclk_X1_Y26_SIG_VCC ),
+	.AsyncReset(AsyncReset_X1_Y26_GND),
+	.SyncReset(SyncReset_X1_Y26_GND),
+	.ShiftData(),
+	.SyncLoad(SyncLoad_X1_Y26_VCC),
+	.LutOut(\mcu_data_out[4]~8_combout ),
+	.Cout(),
+	.Q(lcd_data_in_q[4]));
+defparam \lcd_data_in_q[4] .mask = 16'hE4E4;
+defparam \lcd_data_in_q[4] .mode = "logic";
+defparam \lcd_data_in_q[4] .modeMux = 1'b0;
+defparam \lcd_data_in_q[4] .FeedbackMux = 1'b1;
+defparam \lcd_data_in_q[4] .ShiftMux = 1'b0;
+defparam \lcd_data_in_q[4] .BypassEn = 1'b1;
+defparam \lcd_data_in_q[4] .CarryEnb = 1'b1;
+defparam \lcd_data_in_q[4] .AsyncResetMux = 2'b00;
+defparam \lcd_data_in_q[4] .SyncResetMux = 2'b00;
+defparam \lcd_data_in_q[4] .SyncLoadMux = 2'b01;
+defparam \lcd_data_in_q[4] .coord_x = 1;
+defparam \lcd_data_in_q[4] .coord_y = 26;
+defparam \lcd_data_in_q[4] .coord_z = 5;
+// Location: FF_X1_Y26_N12
+// alta_lcell_ff \lcd_data_out_q[4] (
+// Location: LCCOMB_X1_Y26_N12
+// alta_lcell_comb \lcd_data_out_q[4]~feeder (
+alta_slice \lcd_data_out_q[4] (
+	.A(vcc),
+	.B(vcc),
+	.C(vcc),
+	.D(\MCU_D[4]~input_o ),
+	.Cin(),
+	.Qin(lcd_data_out_q[4]),
+	.Clk(\MCU_LCD_WRX~inputclkctrl_outclk_X1_Y26_INV_VCC ),
+	.AsyncReset(AsyncReset_X1_Y26_GND),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\lcd_data_out_q[4]~feeder_combout ),
+	.Cout(),
+	.Q(lcd_data_out_q[4]));
+defparam \lcd_data_out_q[4] .mask = 16'hFF00;
+defparam \lcd_data_out_q[4] .mode = "logic";
+defparam \lcd_data_out_q[4] .modeMux = 1'b0;
+defparam \lcd_data_out_q[4] .FeedbackMux = 1'b0;
+defparam \lcd_data_out_q[4] .ShiftMux = 1'b0;
+defparam \lcd_data_out_q[4] .BypassEn = 1'b0;
+defparam \lcd_data_out_q[4] .CarryEnb = 1'b1;
+defparam \lcd_data_out_q[4] .AsyncResetMux = 2'b00;
+defparam \lcd_data_out_q[4] .SyncResetMux = 2'bxx;
+defparam \lcd_data_out_q[4] .SyncLoadMux = 2'bxx;
+defparam \lcd_data_out_q[4] .coord_x = 1;
+defparam \lcd_data_out_q[4] .coord_y = 26;
+defparam \lcd_data_out_q[4] .coord_z = 6;
+// Location: FF_X1_Y26_N14
+// alta_lcell_ff \lcd_data_out_q[3] (
+alta_slice \lcd_data_out_q[3] (
+	.A(),
+	.B(),
+	.C(\MCU_D[3]~input_o ),
+	.D(),
+	.Cin(),
+	.Qin(lcd_data_out_q[3]),
+	.Clk(\MCU_LCD_WRX~inputclkctrl_outclk_X1_Y26_INV_VCC ),
+	.AsyncReset(AsyncReset_X1_Y26_GND),
+	.SyncReset(SyncReset_X1_Y26_GND),
+	.ShiftData(),
+	.SyncLoad(SyncLoad_X1_Y26_VCC),
+	.LutOut(),
+	.Cout(),
+	.Q(lcd_data_out_q[3]));
+defparam \lcd_data_out_q[3] .mask = 16'hFFFF;
+defparam \lcd_data_out_q[3] .mode = "ripple";
+defparam \lcd_data_out_q[3] .modeMux = 1'b1;
+defparam \lcd_data_out_q[3] .FeedbackMux = 1'b0;
+defparam \lcd_data_out_q[3] .ShiftMux = 1'b0;
+defparam \lcd_data_out_q[3] .BypassEn = 1'b1;
+defparam \lcd_data_out_q[3] .CarryEnb = 1'b1;
+defparam \lcd_data_out_q[3] .AsyncResetMux = 2'b00;
+defparam \lcd_data_out_q[3] .SyncResetMux = 2'b00;
+defparam \lcd_data_out_q[3] .SyncLoadMux = 2'b01;
+defparam \lcd_data_out_q[3] .coord_x = 1;
+defparam \lcd_data_out_q[3] .coord_y = 26;
+defparam \lcd_data_out_q[3] .coord_z = 7;
+// Location: FF_X1_Y26_N4
+// alta_lcell_ff \lcd_data_out_q[5] (
+alta_slice \lcd_data_out_q[5] (
+	.A(),
+	.B(),
+	.C(\MCU_D[5]~input_o ),
+	.D(),
+	.Cin(),
+	.Qin(lcd_data_out_q[5]),
+	.Clk(\MCU_LCD_WRX~inputclkctrl_outclk_X1_Y26_INV_VCC ),
+	.AsyncReset(AsyncReset_X1_Y26_GND),
+	.SyncReset(SyncReset_X1_Y26_GND),
+	.ShiftData(),
+	.SyncLoad(SyncLoad_X1_Y26_VCC),
+	.LutOut(),
+	.Cout(),
+	.Q(lcd_data_out_q[5]));
+defparam \lcd_data_out_q[5] .mask = 16'hFFFF;
+defparam \lcd_data_out_q[5] .mode = "ripple";
+defparam \lcd_data_out_q[5] .modeMux = 1'b1;
+defparam \lcd_data_out_q[5] .FeedbackMux = 1'b0;
+defparam \lcd_data_out_q[5] .ShiftMux = 1'b0;
+defparam \lcd_data_out_q[5] .BypassEn = 1'b1;
+defparam \lcd_data_out_q[5] .CarryEnb = 1'b1;
+defparam \lcd_data_out_q[5] .AsyncResetMux = 2'b00;
+defparam \lcd_data_out_q[5] .SyncResetMux = 2'b00;
+defparam \lcd_data_out_q[5] .SyncLoadMux = 2'b01;
+defparam \lcd_data_out_q[5] .coord_x = 1;
+defparam \lcd_data_out_q[5] .coord_y = 26;
+defparam \lcd_data_out_q[5] .coord_z = 2;
+// Location: FF_X1_Y26_N6
+// alta_lcell_ff \lcd_data_in_q[3] (
+// Location: LCCOMB_X1_Y26_N6
+// alta_lcell_comb \mcu_data_out[3]~6 (
+alta_slice \lcd_data_in_q[3] (
+	.A(\MCU_LCD_RDX~input_o ),
+	.B(\LCD_DB[11]~input_o ),
+	.C(\LCD_DB[3]~input_o ),
+	.D(vcc),
+	.Cin(),
+	.Qin(lcd_data_in_q[3]),
+	.Clk(\MCU_LCD_RDX~inputclkctrl_outclk_X1_Y26_SIG_VCC ),
+	.AsyncReset(AsyncReset_X1_Y26_GND),
+	.SyncReset(SyncReset_X1_Y26_GND),
+	.ShiftData(),
+	.SyncLoad(SyncLoad_X1_Y26_VCC),
+	.LutOut(\mcu_data_out[3]~6_combout ),
+	.Cout(),
+	.Q(lcd_data_in_q[3]));
+defparam \lcd_data_in_q[3] .mask = 16'hE4E4;
+defparam \lcd_data_in_q[3] .mode = "logic";
+defparam \lcd_data_in_q[3] .modeMux = 1'b0;
+defparam \lcd_data_in_q[3] .FeedbackMux = 1'b1;
+defparam \lcd_data_in_q[3] .ShiftMux = 1'b0;
+defparam \lcd_data_in_q[3] .BypassEn = 1'b1;
+defparam \lcd_data_in_q[3] .CarryEnb = 1'b1;
+defparam \lcd_data_in_q[3] .AsyncResetMux = 2'b00;
+defparam \lcd_data_in_q[3] .SyncResetMux = 2'b00;
+defparam \lcd_data_in_q[3] .SyncLoadMux = 2'b01;
+defparam \lcd_data_in_q[3] .coord_x = 1;
+defparam \lcd_data_in_q[3] .coord_y = 26;
+defparam \lcd_data_in_q[3] .coord_z = 3;
+// Location: FF_X1_Y26_N8
+// alta_lcell_ff \lcd_data_in_q[5] (
+// Location: LCCOMB_X1_Y26_N8
+// alta_lcell_comb \mcu_data_out[5]~10 (
+alta_slice \lcd_data_in_q[5] (
+	.A(\MCU_LCD_RDX~input_o ),
+	.B(vcc),
+	.C(\LCD_DB[5]~input_o ),
+	.D(\LCD_DB[13]~input_o ),
+	.Cin(),
+	.Qin(lcd_data_in_q[5]),
+	.Clk(\MCU_LCD_RDX~inputclkctrl_outclk_X1_Y26_SIG_VCC ),
+	.AsyncReset(AsyncReset_X1_Y26_GND),
+	.SyncReset(SyncReset_X1_Y26_GND),
+	.ShiftData(),
+	.SyncLoad(SyncLoad_X1_Y26_VCC),
+	.LutOut(\mcu_data_out[5]~10_combout ),
+	.Cout(),
+	.Q(lcd_data_in_q[5]));
+defparam \lcd_data_in_q[5] .mask = 16'hF5A0;
+defparam \lcd_data_in_q[5] .mode = "logic";
+defparam \lcd_data_in_q[5] .modeMux = 1'b0;
+defparam \lcd_data_in_q[5] .FeedbackMux = 1'b1;
+defparam \lcd_data_in_q[5] .ShiftMux = 1'b0;
+defparam \lcd_data_in_q[5] .BypassEn = 1'b1;
+defparam \lcd_data_in_q[5] .CarryEnb = 1'b1;
+defparam \lcd_data_in_q[5] .AsyncResetMux = 2'b00;
+defparam \lcd_data_in_q[5] .SyncResetMux = 2'b00;
+defparam \lcd_data_in_q[5] .SyncLoadMux = 2'b01;
+
+defparam \lcd_data_in_q[5] .coord_x = 1;
+defparam \lcd_data_in_q[5] .coord_y = 26;
+defparam \lcd_data_in_q[5] .coord_z = 4;
+// Location: CLKENCTRL_X1_Y26_N0
+alta_clkenctrl clken_ctrl_X1_Y26_N0(.ClkIn(\MCU_LCD_RDX~inputclkctrl_outclk ), .ClkEn(), .ClkOut(\MCU_LCD_RDX~inputclkctrl_outclk_X1_Y26_SIG_VCC ));
+defparam clken_ctrl_X1_Y26_N0.ClkMux = 2'b10;
+defparam clken_ctrl_X1_Y26_N0.ClkEnMux = 2'b01;
+
+defparam clken_ctrl_X1_Y26_N0.coord_x = 1;
+defparam clken_ctrl_X1_Y26_N0.coord_y = 26;
+defparam clken_ctrl_X1_Y26_N0.coord_z = 0;
+// Location: ASYNCCTRL_X1_Y26_N0
+alta_asyncctrl asyncreset_ctrl_X1_Y26_N0(.Din(), .Dout(AsyncReset_X1_Y26_GND));
+defparam asyncreset_ctrl_X1_Y26_N0.AsyncCtrlMux = 2'b00;
+
+defparam asyncreset_ctrl_X1_Y26_N0.coord_x = 1;
+defparam asyncreset_ctrl_X1_Y26_N0.coord_y = 26;
+defparam asyncreset_ctrl_X1_Y26_N0.coord_z = 0;
+// Location: CLKENCTRL_X1_Y26_N1
+alta_clkenctrl clken_ctrl_X1_Y26_N1(.ClkIn(\MCU_LCD_WRX~inputclkctrl_outclk ), .ClkEn(), .ClkOut(\MCU_LCD_WRX~inputclkctrl_outclk_X1_Y26_INV_VCC ));
+defparam clken_ctrl_X1_Y26_N1.ClkMux = 2'b11;
+defparam clken_ctrl_X1_Y26_N1.ClkEnMux = 2'b01;
+
+defparam clken_ctrl_X1_Y26_N1.coord_x = 1;
+defparam clken_ctrl_X1_Y26_N1.coord_y = 26;
+defparam clken_ctrl_X1_Y26_N1.coord_z = 1;
+// Location: SYNCCTRL_X1_Y26_N0
+alta_syncctrl syncreset_ctrl_X1_Y26(.Din(), .Dout(SyncReset_X1_Y26_GND));
+defparam syncreset_ctrl_X1_Y26.SyncCtrlMux = 2'b00;
+
+defparam syncreset_ctrl_X1_Y26.coord_x = 1;
+defparam syncreset_ctrl_X1_Y26.coord_y = 26;
+defparam syncreset_ctrl_X1_Y26.coord_z = 0;
+// Location: SYNCCTRL_X1_Y26_N1
+alta_syncctrl syncload_ctrl_X1_Y26(.Din(), .Dout(SyncLoad_X1_Y26_VCC));
+defparam syncload_ctrl_X1_Y26.SyncCtrlMux = 2'b01;
+defparam syncload_ctrl_X1_Y26.coord_x = 1;
+defparam syncload_ctrl_X1_Y26.coord_y = 26;
+defparam syncload_ctrl_X1_Y26.coord_z = 1;
+endmodule
+
diff --git a/hardware/portapack_h4m/CPLD/Supra/alta_db/flatten.vx b/hardware/portapack_h4m/CPLD/Supra/alta_db/flatten.vx
new file mode 100644
index 00000000..3b7eac7d
--- /dev/null
+++ b/hardware/portapack_h4m/CPLD/Supra/alta_db/flatten.vx
@@ -0,0 +1,1975 @@
+`timescale 1 ps/ 1 ps
+
+module top(
+	MCU_D,
+	MCU_DIR,
+	MCU_IO_STBX,
+	MCU_LCD_WRX,
+	MCU_ADDR,
+	MCU_LCD_TE,
+	MCU_P2_8,
+	MCU_LCD_RDX,
+	TP_U,
+	TP_D,
+	TP_L,
+	TP_R,
+	SW_SEL,
+	SW_ROT_A,
+	SW_ROT_B,
+	SW_U,
+	SW_D,
+	SW_L,
+	SW_R,
+	LCD_RESETX,
+	LCD_RS,
+	LCD_WRX,
+	LCD_RDX,
+	LCD_DB,
+	LCD_TE,
+	LCD_BACKLIGHT,
+	SYSOFF,
+	AUDIO_RESETX,
+	REF_EN,
+	GPS_RESETX,
+	GPS_TX_READY,
+	GPS_TIMEPULSE,
+	DEVICE_RESET,
+	DEVICE_RESET_V);
+output	[7:0] MCU_D;
+input	MCU_DIR;
+input	MCU_IO_STBX;
+input	MCU_LCD_WRX;
+input	MCU_ADDR;
+output	MCU_LCD_TE;
+input	MCU_P2_8;
+input	MCU_LCD_RDX;
+output	TP_U;
+output	TP_D;
+output	TP_L;
+output	TP_R;
+input	SW_SEL;
+input	SW_ROT_A;
+input	SW_ROT_B;
+input	SW_U;
+input	SW_D;
+input	SW_L;
+input	SW_R;
+output	LCD_RESETX;
+output	LCD_RS;
+output	LCD_WRX;
+output	LCD_RDX;
+output	[15:0] LCD_DB;
+input	LCD_TE;
+output	LCD_BACKLIGHT;
+output	SYSOFF;
+output	AUDIO_RESETX;
+output	REF_EN;
+output	GPS_RESETX;
+input	GPS_TX_READY;
+input	GPS_TIMEPULSE;
+input	DEVICE_RESET;
+input	DEVICE_RESET_V;
+
+// module hard_block
+// Design Ports Information
+// ~ALTERA_ASDO_DATA1~	=>  Location: PIN_F4,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// ~ALTERA_FLASH_nCE_nCSO~	=>  Location: PIN_E2,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// ~ALTERA_DCLK~	=>  Location: PIN_P3,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// ~ALTERA_DATA0~	=>  Location: PIN_N7,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// ~ALTERA_nCEO~	=>  Location: PIN_P28,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+
+// module top
+// Design Ports Information
+// MCU_LCD_TE	=>  Location: PIN_AC4,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// MCU_P2_8	=>  Location: PIN_D6,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// TP_U	=>  Location: PIN_AA4,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// TP_D	=>  Location: PIN_AB3,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// TP_L	=>  Location: PIN_AA3,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// TP_R	=>  Location: PIN_AD1,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LCD_RESETX	=>  Location: PIN_AB4,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LCD_RS	=>  Location: PIN_AF2,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LCD_WRX	=>  Location: PIN_M1,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LCD_RDX	=>  Location: PIN_R6,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LCD_BACKLIGHT	=>  Location: PIN_W3,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// SYSOFF	=>  Location: PIN_AE2,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// AUDIO_RESETX	=>  Location: PIN_AE1,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// REF_EN	=>  Location: PIN_AC5,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// GPS_RESETX	=>  Location: PIN_AC26,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// GPS_TX_READY	=>  Location: PIN_D9,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// GPS_TIMEPULSE	=>  Location: PIN_E25,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// DEVICE_RESET	=>  Location: PIN_AF15,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// DEVICE_RESET_V	=>  Location: PIN_AE25,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// MCU_D[0]	=>  Location: PIN_AC1,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// MCU_D[1]	=>  Location: PIN_AC3,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// MCU_D[2]	=>  Location: PIN_AD3,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// MCU_D[3]	=>  Location: PIN_V3,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// MCU_D[4]	=>  Location: PIN_V2,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// MCU_D[5]	=>  Location: PIN_V1,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// MCU_D[6]	=>  Location: PIN_Y3,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// MCU_D[7]	=>  Location: PIN_AC2,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LCD_DB[0]	=>  Location: PIN_U5,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LCD_DB[1]	=>  Location: PIN_AB1,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LCD_DB[2]	=>  Location: PIN_U2,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LCD_DB[3]	=>  Location: PIN_T3,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LCD_DB[4]	=>  Location: PIN_R5,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LCD_DB[5]	=>  Location: PIN_T4,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LCD_DB[6]	=>  Location: PIN_Y4,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LCD_DB[7]	=>  Location: PIN_AB2,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LCD_DB[8]	=>  Location: PIN_U6,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LCD_DB[9]	=>  Location: PIN_U1,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LCD_DB[10]	=>  Location: PIN_V4,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LCD_DB[11]	=>  Location: PIN_R2,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LCD_DB[12]	=>  Location: PIN_R1,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LCD_DB[13]	=>  Location: PIN_R4,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LCD_DB[14]	=>  Location: PIN_W2,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LCD_DB[15]	=>  Location: PIN_W1,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LCD_TE	=>  Location: PIN_AB6,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// MCU_ADDR	=>  Location: PIN_AB5,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// MCU_LCD_WRX	=>  Location: PIN_Y1,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// MCU_LCD_RDX	=>  Location: PIN_Y2,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// MCU_IO_STBX	=>  Location: PIN_J1,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// MCU_DIR	=>  Location: PIN_AD2,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW_R	=>  Location: PIN_U8,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW_L	=>  Location: PIN_U7,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW_D	=>  Location: PIN_T7,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW_U	=>  Location: PIN_R3,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW_SEL	=>  Location: PIN_U3,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW_ROT_A	=>  Location: PIN_U4,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW_ROT_B	=>  Location: PIN_T8,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+
+//wire	gnd;
+//wire	gnd;
+//wire	vcc;
+//wire	vcc;
+//wire	\AUDIO_RESETX~output_o ;
+wire	\DEVICE_RESET_V~input_o ;
+wire	\DEVICE_RESET~input_o ;
+//wire	\GPS_RESETX~output_o ;
+wire	\GPS_TIMEPULSE~input_o ;
+wire	\GPS_TX_READY~input_o ;
+//wire	\LCD_BACKLIGHT~output_o ;
+//wire	\LCD_DB[0]~output_o ;
+wire	\LCD_DB[0]~input_o ;
+//wire	\LCD_DB[10]~output_o ;
+wire	\LCD_DB[10]~input_o ;
+//wire	\LCD_DB[11]~output_o ;
+wire	\LCD_DB[11]~input_o ;
+//wire	\LCD_DB[12]~output_o ;
+wire	\LCD_DB[12]~input_o ;
+//wire	\LCD_DB[13]~output_o ;
+wire	\LCD_DB[13]~input_o ;
+//wire	\LCD_DB[14]~output_o ;
+wire	\LCD_DB[14]~input_o ;
+//wire	\LCD_DB[15]~output_o ;
+wire	\LCD_DB[15]~input_o ;
+//wire	\LCD_DB[1]~output_o ;
+wire	\LCD_DB[1]~input_o ;
+//wire	\LCD_DB[2]~output_o ;
+wire	\LCD_DB[2]~input_o ;
+//wire	\LCD_DB[3]~output_o ;
+wire	\LCD_DB[3]~input_o ;
+//wire	\LCD_DB[4]~output_o ;
+wire	\LCD_DB[4]~input_o ;
+//wire	\LCD_DB[5]~output_o ;
+wire	\LCD_DB[5]~input_o ;
+//wire	\LCD_DB[6]~output_o ;
+wire	\LCD_DB[6]~input_o ;
+//wire	\LCD_DB[7]~output_o ;
+wire	\LCD_DB[7]~input_o ;
+//wire	\LCD_DB[8]~output_o ;
+wire	\LCD_DB[8]~input_o ;
+//wire	\LCD_DB[9]~output_o ;
+wire	\LCD_DB[9]~input_o ;
+//wire	\LCD_RDX~output_o ;
+//wire	\LCD_RESETX~output_o ;
+//wire	\LCD_RS~output_o ;
+wire	\LCD_TE~input_o ;
+//wire	\LCD_WRX~output_o ;
+wire	\MCU_ADDR~input_o ;
+wire	\MCU_DIR~input_o ;
+//wire	\MCU_D[0]~output_o ;
+wire	\MCU_D[0]~input_o ;
+//wire	\MCU_D[1]~output_o ;
+wire	\MCU_D[1]~input_o ;
+//wire	\MCU_D[2]~output_o ;
+wire	\MCU_D[2]~input_o ;
+//wire	\MCU_D[3]~output_o ;
+wire	\MCU_D[3]~input_o ;
+//wire	\MCU_D[4]~output_o ;
+wire	\MCU_D[4]~input_o ;
+//wire	\MCU_D[5]~output_o ;
+wire	\MCU_D[5]~input_o ;
+//wire	\MCU_D[6]~output_o ;
+wire	\MCU_D[6]~input_o ;
+//wire	\MCU_D[7]~output_o ;
+wire	\MCU_D[7]~input_o ;
+wire	\MCU_IO_STBX~input_o ;
+wire	\MCU_IO_STBX~inputclkctrl_outclk ;
+wire	\MCU_LCD_RDX~input_o ;
+wire	\MCU_LCD_RDX~inputclkctrl_outclk ;
+//wire	\MCU_LCD_TE~output_o ;
+wire	\MCU_LCD_WRX~input_o ;
+wire	\MCU_LCD_WRX~inputclkctrl_outclk ;
+wire	\MCU_P2_8~input_o ;
+//wire	\REF_EN~output_o ;
+wire	\SW_D~input_o ;
+wire	\SW_L~input_o ;
+wire	\SW_ROT_A~input_o ;
+wire	\SW_ROT_B~input_o ;
+wire	\SW_R~input_o ;
+wire	\SW_SEL~input_o ;
+wire	\SW_U~input_o ;
+//wire	\SYSOFF~output_o ;
+//wire	\TP_D~output_o ;
+//wire	\TP_L~output_o ;
+//wire	\TP_R~output_o ;
+//wire	\TP_U~output_o ;
+wire	\audio_reset_q~0_combout ;
+wire	\audio_reset_q~q ;
+//wire	devclrn;
+tri1	devclrn;
+//wire	devoe;
+tri1	devoe;
+//wire	devpor;
+tri1	devpor;
+wire	\lcd_backlight_q~feeder_combout ;
+wire	\lcd_backlight_q~q ;
+wire	[7:0] lcd_data_in_q;
+//wire	lcd_data_in_q[0];
+//wire	lcd_data_in_q[1];
+//wire	lcd_data_in_q[2];
+//wire	lcd_data_in_q[3];
+//wire	lcd_data_in_q[4];
+//wire	lcd_data_in_q[5];
+//wire	lcd_data_in_q[6];
+//wire	lcd_data_in_q[7];
+wire	[7:0] lcd_data_out_q;
+//wire	lcd_data_out_q[0];
+wire	\lcd_data_out_q[0]~feeder_combout ;
+//wire	lcd_data_out_q[1];
+wire	\lcd_data_out_q[1]~feeder_combout ;
+//wire	lcd_data_out_q[2];
+wire	\lcd_data_out_q[2]~feeder_combout ;
+//wire	lcd_data_out_q[3];
+//wire	lcd_data_out_q[4];
+wire	\lcd_data_out_q[4]~feeder_combout ;
+//wire	lcd_data_out_q[5];
+//wire	lcd_data_out_q[6];
+//wire	lcd_data_out_q[7];
+wire	\lcd_data_out_q[7]~feeder_combout ;
+wire	\lcd_reset_q~0_combout ;
+wire	\lcd_reset_q~1_combout ;
+wire	\lcd_reset_q~q ;
+wire	\mcu_data_out[0]~0_combout ;
+wire	\mcu_data_out[0]~1_combout ;
+wire	\mcu_data_out[1]~2_combout ;
+wire	\mcu_data_out[1]~3_combout ;
+wire	\mcu_data_out[2]~4_combout ;
+wire	\mcu_data_out[2]~5_combout ;
+wire	\mcu_data_out[3]~6_combout ;
+wire	\mcu_data_out[3]~7_combout ;
+wire	\mcu_data_out[4]~8_combout ;
+wire	\mcu_data_out[4]~9_combout ;
+wire	\mcu_data_out[5]~10_combout ;
+wire	\mcu_data_out[5]~11_combout ;
+wire	\mcu_data_out[6]~12_combout ;
+wire	\mcu_data_out[6]~13_combout ;
+wire	\mcu_data_out[7]~14_combout ;
+wire	\mcu_data_out[7]~15_combout ;
+wire	\ref_en_q~feeder_combout ;
+wire	\ref_en_q~q ;
+wire	\sysoff_q~feeder_combout ;
+wire	\sysoff_q~q ;
+wire	[7:0] tp_q;
+//wire	tp_q[0];
+//wire	tp_q[1];
+//wire	tp_q[2];
+wire	\tp_q[2]~feeder_combout ;
+//wire	tp_q[3];
+wire	\tp_q[3]~0_combout ;
+//wire	tp_q[4];
+wire	\tp_q[4]~feeder_combout ;
+//wire	tp_q[5];
+//wire	tp_q[6];
+wire	\tp_q[6]~feeder_combout ;
+//wire	tp_q[7];
+wire	\tp_q[7]~feeder_combout ;
+wire	unknown;
+wire	unknown;
+wire	\~ALTERA_ASDO_DATA1~~ibuf_o ;
+wire	\~ALTERA_ASDO_DATA1~~padout ;
+wire	\~ALTERA_DATA0~~ibuf_o ;
+wire	\~ALTERA_DATA0~~padout ;
+wire	\~ALTERA_FLASH_nCE_nCSO~~ibuf_o ;
+wire	\~ALTERA_FLASH_nCE_nCSO~~padout ;
+
+wire vcc;
+wire gnd;
+assign vcc = 1'b1;
+assign gnd = 1'b0;
+
+// Location: IOOBUF_X0_Y9_N16
+cycloneive_io_obuf \AUDIO_RESETX~output (
+	.i(\audio_reset_q~q ),
+	.oe(vcc),
+	.seriesterminationcontrol({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
+	.devoe(devoe),
+	.o(AUDIO_RESETX),
+	.obar());
+defparam \AUDIO_RESETX~output .bus_hold = "false";
+defparam \AUDIO_RESETX~output .open_drain_output = "false";
+
+// Location: IOIBUF_X78_Y0_N8
+cycloneive_io_ibuf \DEVICE_RESET_V~input (
+	.i(DEVICE_RESET_V),
+	.ibar(gnd),
+	.o(\DEVICE_RESET_V~input_o ));
+defparam \DEVICE_RESET_V~input .bus_hold = "false";
+defparam \DEVICE_RESET_V~input .simulate_z_as = "z";
+
+// Location: IOIBUF_X51_Y0_N1
+cycloneive_io_ibuf \DEVICE_RESET~input (
+	.i(DEVICE_RESET),
+	.ibar(gnd),
+	.o(\DEVICE_RESET~input_o ));
+defparam \DEVICE_RESET~input .bus_hold = "false";
+defparam \DEVICE_RESET~input .simulate_z_as = "z";
+
+// Location: IOOBUF_X94_Y9_N16
+cycloneive_io_obuf \GPS_RESETX~output (
+	.i(vcc),
+	.oe(vcc),
+	.seriesterminationcontrol({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
+	.devoe(devoe),
+	.o(GPS_RESETX),
+	.obar());
+defparam \GPS_RESETX~output .bus_hold = "false";
+defparam \GPS_RESETX~output .open_drain_output = "false";
+
+// Location: IOIBUF_X56_Y62_N1
+cycloneive_io_ibuf \GPS_TIMEPULSE~input (
+	.i(GPS_TIMEPULSE),
+	.ibar(gnd),
+	.o(\GPS_TIMEPULSE~input_o ));
+defparam \GPS_TIMEPULSE~input .bus_hold = "false";
+defparam \GPS_TIMEPULSE~input .simulate_z_as = "z";
+
+// Location: IOIBUF_X23_Y62_N22
+cycloneive_io_ibuf \GPS_TX_READY~input (
+	.i(GPS_TX_READY),
+	.ibar(gnd),
+	.o(\GPS_TX_READY~input_o ));
+defparam \GPS_TX_READY~input .bus_hold = "false";
+defparam \GPS_TX_READY~input .simulate_z_as = "z";
+
+// Location: IOOBUF_X0_Y8_N23
+cycloneive_io_obuf \LCD_BACKLIGHT~output (
+	.i(\lcd_backlight_q~q ),
+	.oe(vcc),
+	.seriesterminationcontrol({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
+	.devoe(devoe),
+	.o(LCD_BACKLIGHT),
+	.obar());
+defparam \LCD_BACKLIGHT~output .bus_hold = "false";
+defparam \LCD_BACKLIGHT~output .open_drain_output = "false";
+
+// Location: IOIBUF_X0_Y19_N15
+cycloneive_io_ibuf \LCD_DB[0]~input (
+	.i(LCD_DB[0]),
+	.ibar(gnd),
+	.o(\LCD_DB[0]~input_o ));
+defparam \LCD_DB[0]~input .bus_hold = "false";
+defparam \LCD_DB[0]~input .simulate_z_as = "z";
+
+// Location: IOOBUF_X0_Y19_N16
+cycloneive_io_obuf \LCD_DB[0]~output (
+	.i(\MCU_D[0]~input_o ),
+	.oe(\MCU_LCD_RDX~input_o ),
+	.seriesterminationcontrol({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
+	.devoe(devoe),
+	.o(LCD_DB[0]),
+	.obar());
+defparam \LCD_DB[0]~output .bus_hold = "false";
+defparam \LCD_DB[0]~output .open_drain_output = "false";
+
+// Location: IOIBUF_X0_Y24_N22
+cycloneive_io_ibuf \LCD_DB[10]~input (
+	.i(LCD_DB[10]),
+	.ibar(gnd),
+	.o(\LCD_DB[10]~input_o ));
+defparam \LCD_DB[10]~input .bus_hold = "false";
+defparam \LCD_DB[10]~input .simulate_z_as = "z";
+
+// Location: IOOBUF_X0_Y24_N23
+cycloneive_io_obuf \LCD_DB[10]~output (
+	.i(lcd_data_out_q[2]),
+	.oe(\MCU_LCD_RDX~input_o ),
+	.seriesterminationcontrol({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
+	.devoe(devoe),
+	.o(LCD_DB[10]),
+	.obar());
+defparam \LCD_DB[10]~output .bus_hold = "false";
+defparam \LCD_DB[10]~output .open_drain_output = "false";
+
+// Location: IOIBUF_X0_Y29_N1
+cycloneive_io_ibuf \LCD_DB[11]~input (
+	.i(LCD_DB[11]),
+	.ibar(gnd),
+	.o(\LCD_DB[11]~input_o ));
+defparam \LCD_DB[11]~input .bus_hold = "false";
+defparam \LCD_DB[11]~input .simulate_z_as = "z";
+
+// Location: IOOBUF_X0_Y29_N2
+cycloneive_io_obuf \LCD_DB[11]~output (
+	.i(lcd_data_out_q[3]),
+	.oe(\MCU_LCD_RDX~input_o ),
+	.seriesterminationcontrol({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
+	.devoe(devoe),
+	.o(LCD_DB[11]),
+	.obar());
+defparam \LCD_DB[11]~output .bus_hold = "false";
+defparam \LCD_DB[11]~output .open_drain_output = "false";
+
+// Location: IOIBUF_X0_Y29_N8
+cycloneive_io_ibuf \LCD_DB[12]~input (
+	.i(LCD_DB[12]),
+	.ibar(gnd),
+	.o(\LCD_DB[12]~input_o ));
+defparam \LCD_DB[12]~input .bus_hold = "false";
+defparam \LCD_DB[12]~input .simulate_z_as = "z";
+
+// Location: IOOBUF_X0_Y29_N9
+cycloneive_io_obuf \LCD_DB[12]~output (
+	.i(lcd_data_out_q[4]),
+	.oe(\MCU_LCD_RDX~input_o ),
+	.seriesterminationcontrol({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
+	.devoe(devoe),
+	.o(LCD_DB[12]),
+	.obar());
+defparam \LCD_DB[12]~output .bus_hold = "false";
+defparam \LCD_DB[12]~output .open_drain_output = "false";
+
+// Location: IOIBUF_X0_Y26_N1
+cycloneive_io_ibuf \LCD_DB[13]~input (
+	.i(LCD_DB[13]),
+	.ibar(gnd),
+	.o(\LCD_DB[13]~input_o ));
+defparam \LCD_DB[13]~input .bus_hold = "false";
+defparam \LCD_DB[13]~input .simulate_z_as = "z";
+
+// Location: IOOBUF_X0_Y26_N2
+cycloneive_io_obuf \LCD_DB[13]~output (
+	.i(lcd_data_out_q[5]),
+	.oe(\MCU_LCD_RDX~input_o ),
+	.seriesterminationcontrol({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
+	.devoe(devoe),
+	.o(LCD_DB[13]),
+	.obar());
+defparam \LCD_DB[13]~output .bus_hold = "false";
+defparam \LCD_DB[13]~output .open_drain_output = "false";
+
+// Location: IOIBUF_X0_Y20_N1
+cycloneive_io_ibuf \LCD_DB[14]~input (
+	.i(LCD_DB[14]),
+	.ibar(gnd),
+	.o(\LCD_DB[14]~input_o ));
+defparam \LCD_DB[14]~input .bus_hold = "false";
+defparam \LCD_DB[14]~input .simulate_z_as = "z";
+
+// Location: IOOBUF_X0_Y20_N2
+cycloneive_io_obuf \LCD_DB[14]~output (
+	.i(lcd_data_out_q[6]),
+	.oe(\MCU_LCD_RDX~input_o ),
+	.seriesterminationcontrol({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
+	.devoe(devoe),
+	.o(LCD_DB[14]),
+	.obar());
+defparam \LCD_DB[14]~output .bus_hold = "false";
+defparam \LCD_DB[14]~output .open_drain_output = "false";
+
+// Location: IOIBUF_X0_Y20_N8
+cycloneive_io_ibuf \LCD_DB[15]~input (
+	.i(LCD_DB[15]),
+	.ibar(gnd),
+	.o(\LCD_DB[15]~input_o ));
+defparam \LCD_DB[15]~input .bus_hold = "false";
+defparam \LCD_DB[15]~input .simulate_z_as = "z";
+
+// Location: IOOBUF_X0_Y20_N9
+cycloneive_io_obuf \LCD_DB[15]~output (
+	.i(lcd_data_out_q[7]),
+	.oe(\MCU_LCD_RDX~input_o ),
+	.seriesterminationcontrol({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
+	.devoe(devoe),
+	.o(LCD_DB[15]),
+	.obar());
+defparam \LCD_DB[15]~output .bus_hold = "false";
+defparam \LCD_DB[15]~output .open_drain_output = "false";
+
+// Location: IOIBUF_X0_Y21_N8
+cycloneive_io_ibuf \LCD_DB[1]~input (
+	.i(LCD_DB[1]),
+	.ibar(gnd),
+	.o(\LCD_DB[1]~input_o ));
+defparam \LCD_DB[1]~input .bus_hold = "false";
+defparam \LCD_DB[1]~input .simulate_z_as = "z";
+
+// Location: IOOBUF_X0_Y21_N9
+cycloneive_io_obuf \LCD_DB[1]~output (
+	.i(\MCU_D[1]~input_o ),
+	.oe(\MCU_LCD_RDX~input_o ),
+	.seriesterminationcontrol({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
+	.devoe(devoe),
+	.o(LCD_DB[1]),
+	.obar());
+defparam \LCD_DB[1]~output .bus_hold = "false";
+defparam \LCD_DB[1]~output .open_drain_output = "false";
+
+// Location: IOIBUF_X0_Y24_N1
+cycloneive_io_ibuf \LCD_DB[2]~input (
+	.i(LCD_DB[2]),
+	.ibar(gnd),
+	.o(\LCD_DB[2]~input_o ));
+defparam \LCD_DB[2]~input .bus_hold = "false";
+defparam \LCD_DB[2]~input .simulate_z_as = "z";
+
+// Location: IOOBUF_X0_Y24_N2
+cycloneive_io_obuf \LCD_DB[2]~output (
+	.i(\MCU_D[2]~input_o ),
+	.oe(\MCU_LCD_RDX~input_o ),
+	.seriesterminationcontrol({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
+	.devoe(devoe),
+	.o(LCD_DB[2]),
+	.obar());
+defparam \LCD_DB[2]~output .bus_hold = "false";
+defparam \LCD_DB[2]~output .open_drain_output = "false";
+
+// Location: IOIBUF_X0_Y26_N15
+cycloneive_io_ibuf \LCD_DB[3]~input (
+	.i(LCD_DB[3]),
+	.ibar(gnd),
+	.o(\LCD_DB[3]~input_o ));
+defparam \LCD_DB[3]~input .bus_hold = "false";
+defparam \LCD_DB[3]~input .simulate_z_as = "z";
+
+// Location: IOOBUF_X0_Y26_N16
+cycloneive_io_obuf \LCD_DB[3]~output (
+	.i(\MCU_D[3]~input_o ),
+	.oe(\MCU_LCD_RDX~input_o ),
+	.seriesterminationcontrol({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
+	.devoe(devoe),
+	.o(LCD_DB[3]),
+	.obar());
+defparam \LCD_DB[3]~output .bus_hold = "false";
+defparam \LCD_DB[3]~output .open_drain_output = "false";
+
+// Location: IOIBUF_X0_Y26_N22
+cycloneive_io_ibuf \LCD_DB[4]~input (
+	.i(LCD_DB[4]),
+	.ibar(gnd),
+	.o(\LCD_DB[4]~input_o ));
+defparam \LCD_DB[4]~input .bus_hold = "false";
+defparam \LCD_DB[4]~input .simulate_z_as = "z";
+
+// Location: IOOBUF_X0_Y26_N23
+cycloneive_io_obuf \LCD_DB[4]~output (
+	.i(\MCU_D[4]~input_o ),
+	.oe(\MCU_LCD_RDX~input_o ),
+	.seriesterminationcontrol({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
+	.devoe(devoe),
+	.o(LCD_DB[4]),
+	.obar());
+defparam \LCD_DB[4]~output .bus_hold = "false";
+defparam \LCD_DB[4]~output .open_drain_output = "false";
+
+// Location: IOIBUF_X0_Y26_N8
+cycloneive_io_ibuf \LCD_DB[5]~input (
+	.i(LCD_DB[5]),
+	.ibar(gnd),
+	.o(\LCD_DB[5]~input_o ));
+defparam \LCD_DB[5]~input .bus_hold = "false";
+defparam \LCD_DB[5]~input .simulate_z_as = "z";
+
+// Location: IOOBUF_X0_Y26_N9
+cycloneive_io_obuf \LCD_DB[5]~output (
+	.i(\MCU_D[5]~input_o ),
+	.oe(\MCU_LCD_RDX~input_o ),
+	.seriesterminationcontrol({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
+	.devoe(devoe),
+	.o(LCD_DB[5]),
+	.obar());
+defparam \LCD_DB[5]~output .bus_hold = "false";
+defparam \LCD_DB[5]~output .open_drain_output = "false";
+
+// Location: IOIBUF_X0_Y19_N22
+cycloneive_io_ibuf \LCD_DB[6]~input (
+	.i(LCD_DB[6]),
+	.ibar(gnd),
+	.o(\LCD_DB[6]~input_o ));
+defparam \LCD_DB[6]~input .bus_hold = "false";
+defparam \LCD_DB[6]~input .simulate_z_as = "z";
+
+// Location: IOOBUF_X0_Y19_N23
+cycloneive_io_obuf \LCD_DB[6]~output (
+	.i(\MCU_D[6]~input_o ),
+	.oe(\MCU_LCD_RDX~input_o ),
+	.seriesterminationcontrol({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
+	.devoe(devoe),
+	.o(LCD_DB[6]),
+	.obar());
+defparam \LCD_DB[6]~output .bus_hold = "false";
+defparam \LCD_DB[6]~output .open_drain_output = "false";
+
+// Location: IOIBUF_X0_Y21_N1
+cycloneive_io_ibuf \LCD_DB[7]~input (
+	.i(LCD_DB[7]),
+	.ibar(gnd),
+	.o(\LCD_DB[7]~input_o ));
+defparam \LCD_DB[7]~input .bus_hold = "false";
+defparam \LCD_DB[7]~input .simulate_z_as = "z";
+
+// Location: IOOBUF_X0_Y21_N2
+cycloneive_io_obuf \LCD_DB[7]~output (
+	.i(\MCU_D[7]~input_o ),
+	.oe(\MCU_LCD_RDX~input_o ),
+	.seriesterminationcontrol({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
+	.devoe(devoe),
+	.o(LCD_DB[7]),
+	.obar());
+defparam \LCD_DB[7]~output .bus_hold = "false";
+defparam \LCD_DB[7]~output .open_drain_output = "false";
+
+// Location: IOIBUF_X0_Y19_N1
+cycloneive_io_ibuf \LCD_DB[8]~input (
+	.i(LCD_DB[8]),
+	.ibar(gnd),
+	.o(\LCD_DB[8]~input_o ));
+defparam \LCD_DB[8]~input .bus_hold = "false";
+defparam \LCD_DB[8]~input .simulate_z_as = "z";
+
+// Location: IOOBUF_X0_Y19_N2
+cycloneive_io_obuf \LCD_DB[8]~output (
+	.i(lcd_data_out_q[0]),
+	.oe(\MCU_LCD_RDX~input_o ),
+	.seriesterminationcontrol({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
+	.devoe(devoe),
+	.o(LCD_DB[8]),
+	.obar());
+defparam \LCD_DB[8]~output .bus_hold = "false";
+defparam \LCD_DB[8]~output .open_drain_output = "false";
+
+// Location: IOIBUF_X0_Y24_N8
+cycloneive_io_ibuf \LCD_DB[9]~input (
+	.i(LCD_DB[9]),
+	.ibar(gnd),
+	.o(\LCD_DB[9]~input_o ));
+defparam \LCD_DB[9]~input .bus_hold = "false";
+defparam \LCD_DB[9]~input .simulate_z_as = "z";
+
+// Location: IOOBUF_X0_Y24_N9
+cycloneive_io_obuf \LCD_DB[9]~output (
+	.i(lcd_data_out_q[1]),
+	.oe(\MCU_LCD_RDX~input_o ),
+	.seriesterminationcontrol({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
+	.devoe(devoe),
+	.o(LCD_DB[9]),
+	.obar());
+defparam \LCD_DB[9]~output .bus_hold = "false";
+defparam \LCD_DB[9]~output .open_drain_output = "false";
+
+// Location: IOOBUF_X0_Y29_N16
+cycloneive_io_obuf \LCD_RDX~output (
+	.i(\MCU_LCD_RDX~input_o ),
+	.oe(vcc),
+	.seriesterminationcontrol({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
+	.devoe(devoe),
+	.o(LCD_RDX),
+	.obar());
+defparam \LCD_RDX~output .bus_hold = "false";
+defparam \LCD_RDX~output .open_drain_output = "false";
+
+// Location: IOOBUF_X0_Y7_N2
+cycloneive_io_obuf \LCD_RESETX~output (
+	.i(\lcd_reset_q~q ),
+	.oe(vcc),
+	.seriesterminationcontrol({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
+	.devoe(devoe),
+	.o(LCD_RESETX),
+	.obar());
+defparam \LCD_RESETX~output .bus_hold = "false";
+defparam \LCD_RESETX~output .open_drain_output = "false";
+
+// Location: IOOBUF_X0_Y4_N16
+cycloneive_io_obuf \LCD_RS~output (
+	.i(\MCU_ADDR~input_o ),
+	.oe(vcc),
+	.seriesterminationcontrol({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
+	.devoe(devoe),
+	.o(LCD_RS),
+	.obar());
+defparam \LCD_RS~output .bus_hold = "false";
+defparam \LCD_RS~output .open_drain_output = "false";
+
+// Location: IOIBUF_X0_Y6_N22
+cycloneive_io_ibuf \LCD_TE~input (
+	.i(LCD_TE),
+	.ibar(gnd),
+	.o(\LCD_TE~input_o ));
+defparam \LCD_TE~input .bus_hold = "false";
+defparam \LCD_TE~input .simulate_z_as = "z";
+
+// Location: IOOBUF_X0_Y37_N2
+cycloneive_io_obuf \LCD_WRX~output (
+	.i(\MCU_LCD_WRX~input_o ),
+	.oe(vcc),
+	.seriesterminationcontrol({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
+	.devoe(devoe),
+	.o(LCD_WRX),
+	.obar());
+defparam \LCD_WRX~output .bus_hold = "false";
+defparam \LCD_WRX~output .open_drain_output = "false";
+
+// Location: IOIBUF_X0_Y4_N22
+cycloneive_io_ibuf \MCU_ADDR~input (
+	.i(MCU_ADDR),
+	.ibar(gnd),
+	.o(\MCU_ADDR~input_o ));
+defparam \MCU_ADDR~input .bus_hold = "false";
+defparam \MCU_ADDR~input .simulate_z_as = "z";
+
+// Location: IOIBUF_X0_Y16_N22
+cycloneive_io_ibuf \MCU_DIR~input (
+	.i(MCU_DIR),
+	.ibar(gnd),
+	.o(\MCU_DIR~input_o ));
+defparam \MCU_DIR~input .bus_hold = "false";
+defparam \MCU_DIR~input .simulate_z_as = "z";
+
+// Location: IOIBUF_X0_Y17_N8
+cycloneive_io_ibuf \MCU_D[0]~input (
+	.i(MCU_D[0]),
+	.ibar(gnd),
+	.o(\MCU_D[0]~input_o ));
+defparam \MCU_D[0]~input .bus_hold = "false";
+defparam \MCU_D[0]~input .simulate_z_as = "z";
+
+// Location: IOOBUF_X0_Y17_N9
+cycloneive_io_obuf \MCU_D[0]~output (
+	.i(\mcu_data_out[0]~1_combout ),
+	.oe(\MCU_DIR~input_o ),
+	.seriesterminationcontrol({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
+	.devoe(devoe),
+	.o(MCU_D[0]),
+	.obar());
+defparam \MCU_D[0]~output .bus_hold = "false";
+defparam \MCU_D[0]~output .open_drain_output = "false";
+
+// Location: IOIBUF_X0_Y16_N8
+cycloneive_io_ibuf \MCU_D[1]~input (
+	.i(MCU_D[1]),
+	.ibar(gnd),
+	.o(\MCU_D[1]~input_o ));
+defparam \MCU_D[1]~input .bus_hold = "false";
+defparam \MCU_D[1]~input .simulate_z_as = "z";
+
+// Location: IOOBUF_X0_Y16_N9
+cycloneive_io_obuf \MCU_D[1]~output (
+	.i(\mcu_data_out[1]~3_combout ),
+	.oe(\MCU_DIR~input_o ),
+	.seriesterminationcontrol({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
+	.devoe(devoe),
+	.o(MCU_D[1]),
+	.obar());
+defparam \MCU_D[1]~output .bus_hold = "false";
+defparam \MCU_D[1]~output .open_drain_output = "false";
+
+// Location: IOIBUF_X0_Y16_N15
+cycloneive_io_ibuf \MCU_D[2]~input (
+	.i(MCU_D[2]),
+	.ibar(gnd),
+	.o(\MCU_D[2]~input_o ));
+defparam \MCU_D[2]~input .bus_hold = "false";
+defparam \MCU_D[2]~input .simulate_z_as = "z";
+
+// Location: IOOBUF_X0_Y16_N16
+cycloneive_io_obuf \MCU_D[2]~output (
+	.i(\mcu_data_out[2]~5_combout ),
+	.oe(\MCU_DIR~input_o ),
+	.seriesterminationcontrol({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
+	.devoe(devoe),
+	.o(MCU_D[2]),
+	.obar());
+defparam \MCU_D[2]~output .bus_hold = "false";
+defparam \MCU_D[2]~output .open_drain_output = "false";
+
+// Location: IOIBUF_X0_Y23_N1
+cycloneive_io_ibuf \MCU_D[3]~input (
+	.i(MCU_D[3]),
+	.ibar(gnd),
+	.o(\MCU_D[3]~input_o ));
+defparam \MCU_D[3]~input .bus_hold = "false";
+defparam \MCU_D[3]~input .simulate_z_as = "z";
+
+// Location: IOOBUF_X0_Y23_N2
+cycloneive_io_obuf \MCU_D[3]~output (
+	.i(\mcu_data_out[3]~7_combout ),
+	.oe(\MCU_DIR~input_o ),
+	.seriesterminationcontrol({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
+	.devoe(devoe),
+	.o(MCU_D[3]),
+	.obar());
+defparam \MCU_D[3]~output .bus_hold = "false";
+defparam \MCU_D[3]~output .open_drain_output = "false";
+
+// Location: IOIBUF_X0_Y23_N8
+cycloneive_io_ibuf \MCU_D[4]~input (
+	.i(MCU_D[4]),
+	.ibar(gnd),
+	.o(\MCU_D[4]~input_o ));
+defparam \MCU_D[4]~input .bus_hold = "false";
+defparam \MCU_D[4]~input .simulate_z_as = "z";
+
+// Location: IOOBUF_X0_Y23_N9
+cycloneive_io_obuf \MCU_D[4]~output (
+	.i(\mcu_data_out[4]~9_combout ),
+	.oe(\MCU_DIR~input_o ),
+	.seriesterminationcontrol({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
+	.devoe(devoe),
+	.o(MCU_D[4]),
+	.obar());
+defparam \MCU_D[4]~output .bus_hold = "false";
+defparam \MCU_D[4]~output .open_drain_output = "false";
+
+// Location: IOIBUF_X0_Y22_N8
+cycloneive_io_ibuf \MCU_D[5]~input (
+	.i(MCU_D[5]),
+	.ibar(gnd),
+	.o(\MCU_D[5]~input_o ));
+defparam \MCU_D[5]~input .bus_hold = "false";
+defparam \MCU_D[5]~input .simulate_z_as = "z";
+
+// Location: IOOBUF_X0_Y22_N9
+cycloneive_io_obuf \MCU_D[5]~output (
+	.i(\mcu_data_out[5]~11_combout ),
+	.oe(\MCU_DIR~input_o ),
+	.seriesterminationcontrol({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
+	.devoe(devoe),
+	.o(MCU_D[5]),
+	.obar());
+defparam \MCU_D[5]~output .bus_hold = "false";
+defparam \MCU_D[5]~output .open_drain_output = "false";
+
+// Location: IOIBUF_X0_Y18_N15
+cycloneive_io_ibuf \MCU_D[6]~input (
+	.i(MCU_D[6]),
+	.ibar(gnd),
+	.o(\MCU_D[6]~input_o ));
+defparam \MCU_D[6]~input .bus_hold = "false";
+defparam \MCU_D[6]~input .simulate_z_as = "z";
+
+// Location: IOOBUF_X0_Y18_N16
+cycloneive_io_obuf \MCU_D[6]~output (
+	.i(\mcu_data_out[6]~13_combout ),
+	.oe(\MCU_DIR~input_o ),
+	.seriesterminationcontrol({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
+	.devoe(devoe),
+	.o(MCU_D[6]),
+	.obar());
+defparam \MCU_D[6]~output .bus_hold = "false";
+defparam \MCU_D[6]~output .open_drain_output = "false";
+
+// Location: IOIBUF_X0_Y18_N22
+cycloneive_io_ibuf \MCU_D[7]~input (
+	.i(MCU_D[7]),
+	.ibar(gnd),
+	.o(\MCU_D[7]~input_o ));
+defparam \MCU_D[7]~input .bus_hold = "false";
+defparam \MCU_D[7]~input .simulate_z_as = "z";
+
+// Location: IOOBUF_X0_Y18_N23
+cycloneive_io_obuf \MCU_D[7]~output (
+	.i(\mcu_data_out[7]~15_combout ),
+	.oe(\MCU_DIR~input_o ),
+	.seriesterminationcontrol({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
+	.devoe(devoe),
+	.o(MCU_D[7]),
+	.obar());
+defparam \MCU_D[7]~output .bus_hold = "false";
+defparam \MCU_D[7]~output .open_drain_output = "false";
+
+// Location: IOIBUF_X0_Y30_N8
+cycloneive_io_ibuf \MCU_IO_STBX~input (
+	.i(MCU_IO_STBX),
+	.ibar(gnd),
+	.o(\MCU_IO_STBX~input_o ));
+defparam \MCU_IO_STBX~input .bus_hold = "false";
+defparam \MCU_IO_STBX~input .simulate_z_as = "z";
+
+// Location: CLKCTRL_G2
+cycloneive_clkctrl \MCU_IO_STBX~inputclkctrl (
+	.inclk({vcc, vcc, vcc, \MCU_IO_STBX~input_o }),
+	.clkselect({gnd, gnd}),
+	.ena(vcc),
+	.devpor(devpor),
+	.devclrn(devclrn),
+	.outclk(\MCU_IO_STBX~inputclkctrl_outclk ));
+defparam \MCU_IO_STBX~inputclkctrl .clock_type = "global clock";
+defparam \MCU_IO_STBX~inputclkctrl .ena_register_mode = "none";
+
+// Location: IOIBUF_X0_Y30_N15
+cycloneive_io_ibuf \MCU_LCD_RDX~input (
+	.i(MCU_LCD_RDX),
+	.ibar(gnd),
+	.o(\MCU_LCD_RDX~input_o ));
+defparam \MCU_LCD_RDX~input .bus_hold = "false";
+defparam \MCU_LCD_RDX~input .simulate_z_as = "z";
+
+// Location: CLKCTRL_G4
+cycloneive_clkctrl \MCU_LCD_RDX~inputclkctrl (
+	.inclk({vcc, vcc, vcc, \MCU_LCD_RDX~input_o }),
+	.clkselect({gnd, gnd}),
+	.ena(vcc),
+	.devpor(devpor),
+	.devclrn(devclrn),
+	.outclk(\MCU_LCD_RDX~inputclkctrl_outclk ));
+defparam \MCU_LCD_RDX~inputclkctrl .clock_type = "global clock";
+defparam \MCU_LCD_RDX~inputclkctrl .ena_register_mode = "none";
+
+// Location: IOOBUF_X0_Y6_N16
+cycloneive_io_obuf \MCU_LCD_TE~output (
+	.i(\LCD_TE~input_o ),
+	.oe(vcc),
+	.seriesterminationcontrol({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
+	.devoe(devoe),
+	.o(MCU_LCD_TE),
+	.obar());
+defparam \MCU_LCD_TE~output .bus_hold = "false";
+defparam \MCU_LCD_TE~output .open_drain_output = "false";
+
+// Location: IOIBUF_X0_Y30_N22
+cycloneive_io_ibuf \MCU_LCD_WRX~input (
+	.i(MCU_LCD_WRX),
+	.ibar(gnd),
+	.o(\MCU_LCD_WRX~input_o ));
+defparam \MCU_LCD_WRX~input .bus_hold = "false";
+defparam \MCU_LCD_WRX~input .simulate_z_as = "z";
+
+// Location: CLKCTRL_G3
+cycloneive_clkctrl \MCU_LCD_WRX~inputclkctrl (
+	.inclk({vcc, vcc, vcc, \MCU_LCD_WRX~input_o }),
+	.clkselect({gnd, gnd}),
+	.ena(vcc),
+	.devpor(devpor),
+	.devclrn(devclrn),
+	.outclk(\MCU_LCD_WRX~inputclkctrl_outclk ));
+defparam \MCU_LCD_WRX~inputclkctrl .clock_type = "global clock";
+defparam \MCU_LCD_WRX~inputclkctrl .ena_register_mode = "none";
+
+// Location: IOIBUF_X18_Y62_N15
+cycloneive_io_ibuf \MCU_P2_8~input (
+	.i(MCU_P2_8),
+	.ibar(gnd),
+	.o(\MCU_P2_8~input_o ));
+defparam \MCU_P2_8~input .bus_hold = "false";
+defparam \MCU_P2_8~input .simulate_z_as = "z";
+
+// Location: IOOBUF_X0_Y7_N9
+cycloneive_io_obuf \REF_EN~output (
+	.i(\ref_en_q~q ),
+	.oe(vcc),
+	.seriesterminationcontrol({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
+	.devoe(devoe),
+	.o(REF_EN),
+	.obar());
+defparam \REF_EN~output .bus_hold = "false";
+defparam \REF_EN~output .open_drain_output = "false";
+
+// Location: IOIBUF_X0_Y25_N15
+cycloneive_io_ibuf \SW_D~input (
+	.i(SW_D),
+	.ibar(gnd),
+	.o(\SW_D~input_o ));
+defparam \SW_D~input .bus_hold = "false";
+defparam \SW_D~input .simulate_z_as = "z";
+
+// Location: IOIBUF_X0_Y10_N1
+cycloneive_io_ibuf \SW_L~input (
+	.i(SW_L),
+	.ibar(gnd),
+	.o(\SW_L~input_o ));
+defparam \SW_L~input .bus_hold = "false";
+defparam \SW_L~input .simulate_z_as = "z";
+
+// Location: IOIBUF_X0_Y28_N8
+cycloneive_io_ibuf \SW_ROT_A~input (
+	.i(SW_ROT_A),
+	.ibar(gnd),
+	.o(\SW_ROT_A~input_o ));
+defparam \SW_ROT_A~input .bus_hold = "false";
+defparam \SW_ROT_A~input .simulate_z_as = "z";
+
+// Location: IOIBUF_X0_Y14_N8
+cycloneive_io_ibuf \SW_ROT_B~input (
+	.i(SW_ROT_B),
+	.ibar(gnd),
+	.o(\SW_ROT_B~input_o ));
+defparam \SW_ROT_B~input .bus_hold = "false";
+defparam \SW_ROT_B~input .simulate_z_as = "z";
+
+// Location: IOIBUF_X0_Y10_N8
+cycloneive_io_ibuf \SW_R~input (
+	.i(SW_R),
+	.ibar(gnd),
+	.o(\SW_R~input_o ));
+defparam \SW_R~input .bus_hold = "false";
+defparam \SW_R~input .simulate_z_as = "z";
+
+// Location: IOIBUF_X0_Y29_N22
+cycloneive_io_ibuf \SW_SEL~input (
+	.i(SW_SEL),
+	.ibar(gnd),
+	.o(\SW_SEL~input_o ));
+defparam \SW_SEL~input .bus_hold = "false";
+defparam \SW_SEL~input .simulate_z_as = "z";
+
+// Location: IOIBUF_X0_Y28_N15
+cycloneive_io_ibuf \SW_U~input (
+	.i(SW_U),
+	.ibar(gnd),
+	.o(\SW_U~input_o ));
+defparam \SW_U~input .bus_hold = "false";
+defparam \SW_U~input .simulate_z_as = "z";
+
+// Location: IOOBUF_X0_Y9_N9
+cycloneive_io_obuf \SYSOFF~output (
+	.i(\sysoff_q~q ),
+	.oe(vcc),
+	.seriesterminationcontrol({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
+	.devoe(devoe),
+	.o(SYSOFF),
+	.obar());
+defparam \SYSOFF~output .bus_hold = "false";
+defparam \SYSOFF~output .open_drain_output = "false";
+
+// Location: IOOBUF_X0_Y15_N23
+cycloneive_io_obuf \TP_D~output (
+	.i(tp_q[2]),
+	.oe(tp_q[6]),
+	.seriesterminationcontrol({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
+	.devoe(devoe),
+	.o(TP_D),
+	.obar());
+defparam \TP_D~output .bus_hold = "false";
+defparam \TP_D~output .open_drain_output = "false";
+
+// Location: IOOBUF_X0_Y11_N9
+cycloneive_io_obuf \TP_L~output (
+	.i(tp_q[1]),
+	.oe(tp_q[5]),
+	.seriesterminationcontrol({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
+	.devoe(devoe),
+	.o(TP_L),
+	.obar());
+defparam \TP_L~output .bus_hold = "false";
+defparam \TP_L~output .open_drain_output = "false";
+
+// Location: IOOBUF_X0_Y15_N16
+cycloneive_io_obuf \TP_R~output (
+	.i(tp_q[0]),
+	.oe(tp_q[4]),
+	.seriesterminationcontrol({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
+	.devoe(devoe),
+	.o(TP_R),
+	.obar());
+defparam \TP_R~output .bus_hold = "false";
+defparam \TP_R~output .open_drain_output = "false";
+
+// Location: IOOBUF_X0_Y11_N2
+cycloneive_io_obuf \TP_U~output (
+	.i(tp_q[3]),
+	.oe(tp_q[7]),
+	.seriesterminationcontrol({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
+	.devoe(devoe),
+	.o(TP_U),
+	.obar());
+defparam \TP_U~output .bus_hold = "false";
+defparam \TP_U~output .open_drain_output = "false";
+
+// Location: FF_X1_Y15_N23
+dffeas audio_reset_q(
+	.clk(\MCU_IO_STBX~inputclkctrl_outclk ),
+	.d(\audio_reset_q~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\lcd_reset_q~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\audio_reset_q~q ),
+	.prn(vcc));
+defparam audio_reset_q.is_wysiwyg = "true";
+defparam audio_reset_q.power_up = "low";
+
+// Location: LCCOMB_X1_Y15_N22
+cycloneive_lcell_comb \audio_reset_q~0 (
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\MCU_D[1]~input_o ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\audio_reset_q~0_combout ),
+	.cout());
+defparam \audio_reset_q~0 .lut_mask = 16'h0F0F;
+defparam \audio_reset_q~0 .sum_lutc_input = "datac";
+
+// Location: FF_X1_Y15_N17
+dffeas lcd_backlight_q(
+	.clk(\MCU_IO_STBX~inputclkctrl_outclk ),
+	.d(\lcd_backlight_q~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\lcd_reset_q~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\lcd_backlight_q~q ),
+	.prn(vcc));
+defparam lcd_backlight_q.is_wysiwyg = "true";
+defparam lcd_backlight_q.power_up = "low";
+
+// Location: LCCOMB_X1_Y15_N16
+cycloneive_lcell_comb \lcd_backlight_q~feeder (
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\MCU_D[7]~input_o ),
+	.cin(gnd),
+	.combout(\lcd_backlight_q~feeder_combout ),
+	.cout());
+defparam \lcd_backlight_q~feeder .lut_mask = 16'hFF00;
+defparam \lcd_backlight_q~feeder .sum_lutc_input = "datac";
+
+// Location: FF_X1_Y19_N31
+dffeas \lcd_data_in_q[0] (
+	.clk(\MCU_LCD_RDX~inputclkctrl_outclk ),
+	.d(gnd),
+	.asdata(\LCD_DB[0]~input_o ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(lcd_data_in_q[0]),
+	.prn(vcc));
+defparam \lcd_data_in_q[0] .is_wysiwyg = "true";
+defparam \lcd_data_in_q[0] .power_up = "low";
+
+// Location: FF_X1_Y21_N5
+dffeas \lcd_data_in_q[1] (
+	.clk(\MCU_LCD_RDX~inputclkctrl_outclk ),
+	.d(gnd),
+	.asdata(\LCD_DB[1]~input_o ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(lcd_data_in_q[1]),
+	.prn(vcc));
+defparam \lcd_data_in_q[1] .is_wysiwyg = "true";
+defparam \lcd_data_in_q[1] .power_up = "low";
+
+// Location: FF_X1_Y24_N31
+dffeas \lcd_data_in_q[2] (
+	.clk(\MCU_LCD_RDX~inputclkctrl_outclk ),
+	.d(gnd),
+	.asdata(\LCD_DB[2]~input_o ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(lcd_data_in_q[2]),
+	.prn(vcc));
+defparam \lcd_data_in_q[2] .is_wysiwyg = "true";
+defparam \lcd_data_in_q[2] .power_up = "low";
+
+// Location: FF_X1_Y26_N7
+dffeas \lcd_data_in_q[3] (
+	.clk(\MCU_LCD_RDX~inputclkctrl_outclk ),
+	.d(gnd),
+	.asdata(\LCD_DB[3]~input_o ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(lcd_data_in_q[3]),
+	.prn(vcc));
+defparam \lcd_data_in_q[3] .is_wysiwyg = "true";
+defparam \lcd_data_in_q[3] .power_up = "low";
+
+// Location: FF_X1_Y26_N11
+dffeas \lcd_data_in_q[4] (
+	.clk(\MCU_LCD_RDX~inputclkctrl_outclk ),
+	.d(gnd),
+	.asdata(\LCD_DB[4]~input_o ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(lcd_data_in_q[4]),
+	.prn(vcc));
+defparam \lcd_data_in_q[4] .is_wysiwyg = "true";
+defparam \lcd_data_in_q[4] .power_up = "low";
+
+// Location: FF_X1_Y26_N9
+dffeas \lcd_data_in_q[5] (
+	.clk(\MCU_LCD_RDX~inputclkctrl_outclk ),
+	.d(gnd),
+	.asdata(\LCD_DB[5]~input_o ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(lcd_data_in_q[5]),
+	.prn(vcc));
+defparam \lcd_data_in_q[5] .is_wysiwyg = "true";
+defparam \lcd_data_in_q[5] .power_up = "low";
+
+// Location: FF_X1_Y19_N5
+dffeas \lcd_data_in_q[6] (
+	.clk(\MCU_LCD_RDX~inputclkctrl_outclk ),
+	.d(gnd),
+	.asdata(\LCD_DB[6]~input_o ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(lcd_data_in_q[6]),
+	.prn(vcc));
+defparam \lcd_data_in_q[6] .is_wysiwyg = "true";
+defparam \lcd_data_in_q[6] .power_up = "low";
+
+// Location: FF_X1_Y21_N29
+dffeas \lcd_data_in_q[7] (
+	.clk(\MCU_LCD_RDX~inputclkctrl_outclk ),
+	.d(gnd),
+	.asdata(\LCD_DB[7]~input_o ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(lcd_data_in_q[7]),
+	.prn(vcc));
+defparam \lcd_data_in_q[7] .is_wysiwyg = "true";
+defparam \lcd_data_in_q[7] .power_up = "low";
+
+// Location: FF_X1_Y20_N31
+dffeas \lcd_data_out_q[0] (
+	.clk(!\MCU_LCD_WRX~inputclkctrl_outclk ),
+	.d(\lcd_data_out_q[0]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(lcd_data_out_q[0]),
+	.prn(vcc));
+defparam \lcd_data_out_q[0] .is_wysiwyg = "true";
+defparam \lcd_data_out_q[0] .power_up = "low";
+
+// Location: LCCOMB_X1_Y20_N30
+cycloneive_lcell_comb \lcd_data_out_q[0]~feeder (
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\MCU_D[0]~input_o ),
+	.cin(gnd),
+	.combout(\lcd_data_out_q[0]~feeder_combout ),
+	.cout());
+defparam \lcd_data_out_q[0]~feeder .lut_mask = 16'hFF00;
+defparam \lcd_data_out_q[0]~feeder .sum_lutc_input = "datac";
+
+// Location: FF_X1_Y20_N1
+dffeas \lcd_data_out_q[1] (
+	.clk(!\MCU_LCD_WRX~inputclkctrl_outclk ),
+	.d(\lcd_data_out_q[1]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(lcd_data_out_q[1]),
+	.prn(vcc));
+defparam \lcd_data_out_q[1] .is_wysiwyg = "true";
+defparam \lcd_data_out_q[1] .power_up = "low";
+
+// Location: LCCOMB_X1_Y20_N0
+cycloneive_lcell_comb \lcd_data_out_q[1]~feeder (
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\MCU_D[1]~input_o ),
+	.cin(gnd),
+	.combout(\lcd_data_out_q[1]~feeder_combout ),
+	.cout());
+defparam \lcd_data_out_q[1]~feeder .lut_mask = 16'hFF00;
+defparam \lcd_data_out_q[1]~feeder .sum_lutc_input = "datac";
+
+// Location: FF_X1_Y20_N11
+dffeas \lcd_data_out_q[2] (
+	.clk(!\MCU_LCD_WRX~inputclkctrl_outclk ),
+	.d(\lcd_data_out_q[2]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(lcd_data_out_q[2]),
+	.prn(vcc));
+defparam \lcd_data_out_q[2] .is_wysiwyg = "true";
+defparam \lcd_data_out_q[2] .power_up = "low";
+
+// Location: LCCOMB_X1_Y20_N10
+cycloneive_lcell_comb \lcd_data_out_q[2]~feeder (
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\MCU_D[2]~input_o ),
+	.cin(gnd),
+	.combout(\lcd_data_out_q[2]~feeder_combout ),
+	.cout());
+defparam \lcd_data_out_q[2]~feeder .lut_mask = 16'hFF00;
+defparam \lcd_data_out_q[2]~feeder .sum_lutc_input = "datac";
+
+// Location: FF_X1_Y26_N15
+dffeas \lcd_data_out_q[3] (
+	.clk(!\MCU_LCD_WRX~inputclkctrl_outclk ),
+	.d(gnd),
+	.asdata(\MCU_D[3]~input_o ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(lcd_data_out_q[3]),
+	.prn(vcc));
+defparam \lcd_data_out_q[3] .is_wysiwyg = "true";
+defparam \lcd_data_out_q[3] .power_up = "low";
+
+// Location: FF_X1_Y26_N13
+dffeas \lcd_data_out_q[4] (
+	.clk(!\MCU_LCD_WRX~inputclkctrl_outclk ),
+	.d(\lcd_data_out_q[4]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(lcd_data_out_q[4]),
+	.prn(vcc));
+defparam \lcd_data_out_q[4] .is_wysiwyg = "true";
+defparam \lcd_data_out_q[4] .power_up = "low";
+
+// Location: LCCOMB_X1_Y26_N12
+cycloneive_lcell_comb \lcd_data_out_q[4]~feeder (
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\MCU_D[4]~input_o ),
+	.cin(gnd),
+	.combout(\lcd_data_out_q[4]~feeder_combout ),
+	.cout());
+defparam \lcd_data_out_q[4]~feeder .lut_mask = 16'hFF00;
+defparam \lcd_data_out_q[4]~feeder .sum_lutc_input = "datac";
+
+// Location: FF_X1_Y26_N5
+dffeas \lcd_data_out_q[5] (
+	.clk(!\MCU_LCD_WRX~inputclkctrl_outclk ),
+	.d(gnd),
+	.asdata(\MCU_D[5]~input_o ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(lcd_data_out_q[5]),
+	.prn(vcc));
+defparam \lcd_data_out_q[5] .is_wysiwyg = "true";
+defparam \lcd_data_out_q[5] .power_up = "low";
+
+// Location: FF_X1_Y20_N13
+dffeas \lcd_data_out_q[6] (
+	.clk(!\MCU_LCD_WRX~inputclkctrl_outclk ),
+	.d(gnd),
+	.asdata(\MCU_D[6]~input_o ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(lcd_data_out_q[6]),
+	.prn(vcc));
+defparam \lcd_data_out_q[6] .is_wysiwyg = "true";
+defparam \lcd_data_out_q[6] .power_up = "low";
+
+// Location: FF_X1_Y20_N15
+dffeas \lcd_data_out_q[7] (
+	.clk(!\MCU_LCD_WRX~inputclkctrl_outclk ),
+	.d(\lcd_data_out_q[7]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(lcd_data_out_q[7]),
+	.prn(vcc));
+defparam \lcd_data_out_q[7] .is_wysiwyg = "true";
+defparam \lcd_data_out_q[7] .power_up = "low";
+
+// Location: LCCOMB_X1_Y20_N14
+cycloneive_lcell_comb \lcd_data_out_q[7]~feeder (
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\MCU_D[7]~input_o ),
+	.cin(gnd),
+	.combout(\lcd_data_out_q[7]~feeder_combout ),
+	.cout());
+defparam \lcd_data_out_q[7]~feeder .lut_mask = 16'hFF00;
+defparam \lcd_data_out_q[7]~feeder .sum_lutc_input = "datac";
+
+// Location: FF_X1_Y15_N3
+dffeas lcd_reset_q(
+	.clk(\MCU_IO_STBX~inputclkctrl_outclk ),
+	.d(\lcd_reset_q~1_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\lcd_reset_q~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\lcd_reset_q~q ),
+	.prn(vcc));
+defparam lcd_reset_q.is_wysiwyg = "true";
+defparam lcd_reset_q.power_up = "low";
+
+// Location: LCCOMB_X1_Y15_N10
+cycloneive_lcell_comb \lcd_reset_q~0 (
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\MCU_ADDR~input_o ),
+	.datad(\MCU_DIR~input_o ),
+	.cin(gnd),
+	.combout(\lcd_reset_q~0_combout ),
+	.cout());
+defparam \lcd_reset_q~0 .lut_mask = 16'h00F0;
+defparam \lcd_reset_q~0 .sum_lutc_input = "datac";
+
+// Location: LCCOMB_X1_Y15_N2
+cycloneive_lcell_comb \lcd_reset_q~1 (
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\MCU_D[0]~input_o ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\lcd_reset_q~1_combout ),
+	.cout());
+defparam \lcd_reset_q~1 .lut_mask = 16'h0F0F;
+defparam \lcd_reset_q~1 .sum_lutc_input = "datac";
+
+// Location: LCCOMB_X1_Y19_N30
+cycloneive_lcell_comb \mcu_data_out[0]~0 (
+	.dataa(\LCD_DB[8]~input_o ),
+	.datab(gnd),
+	.datac(lcd_data_in_q[0]),
+	.datad(\MCU_LCD_RDX~input_o ),
+	.cin(gnd),
+	.combout(\mcu_data_out[0]~0_combout ),
+	.cout());
+defparam \mcu_data_out[0]~0 .lut_mask = 16'hF0AA;
+defparam \mcu_data_out[0]~0 .sum_lutc_input = "datac";
+
+// Location: LCCOMB_X1_Y18_N30
+cycloneive_lcell_comb \mcu_data_out[0]~1 (
+	.dataa(\SW_R~input_o ),
+	.datab(\MCU_IO_STBX~input_o ),
+	.datac(\mcu_data_out[0]~0_combout ),
+	.datad(\MCU_DIR~input_o ),
+	.cin(gnd),
+	.combout(\mcu_data_out[0]~1_combout ),
+	.cout());
+defparam \mcu_data_out[0]~1 .lut_mask = 16'hD1F0;
+defparam \mcu_data_out[0]~1 .sum_lutc_input = "datac";
+
+// Location: LCCOMB_X1_Y21_N4
+cycloneive_lcell_comb \mcu_data_out[1]~2 (
+	.dataa(\LCD_DB[9]~input_o ),
+	.datab(\MCU_LCD_RDX~input_o ),
+	.datac(lcd_data_in_q[1]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\mcu_data_out[1]~2_combout ),
+	.cout());
+defparam \mcu_data_out[1]~2 .lut_mask = 16'hE2E2;
+defparam \mcu_data_out[1]~2 .sum_lutc_input = "datac";
+
+// Location: LCCOMB_X1_Y18_N28
+cycloneive_lcell_comb \mcu_data_out[1]~3 (
+	.dataa(\SW_L~input_o ),
+	.datab(\MCU_DIR~input_o ),
+	.datac(\MCU_IO_STBX~input_o ),
+	.datad(\mcu_data_out[1]~2_combout ),
+	.cin(gnd),
+	.combout(\mcu_data_out[1]~3_combout ),
+	.cout());
+defparam \mcu_data_out[1]~3 .lut_mask = 16'hF704;
+defparam \mcu_data_out[1]~3 .sum_lutc_input = "datac";
+
+// Location: LCCOMB_X1_Y24_N30
+cycloneive_lcell_comb \mcu_data_out[2]~4 (
+	.dataa(\LCD_DB[10]~input_o ),
+	.datab(gnd),
+	.datac(lcd_data_in_q[2]),
+	.datad(\MCU_LCD_RDX~input_o ),
+	.cin(gnd),
+	.combout(\mcu_data_out[2]~4_combout ),
+	.cout());
+defparam \mcu_data_out[2]~4 .lut_mask = 16'hF0AA;
+defparam \mcu_data_out[2]~4 .sum_lutc_input = "datac";
+
+// Location: LCCOMB_X1_Y23_N16
+cycloneive_lcell_comb \mcu_data_out[2]~5 (
+	.dataa(\SW_D~input_o ),
+	.datab(\MCU_IO_STBX~input_o ),
+	.datac(\mcu_data_out[2]~4_combout ),
+	.datad(\MCU_DIR~input_o ),
+	.cin(gnd),
+	.combout(\mcu_data_out[2]~5_combout ),
+	.cout());
+defparam \mcu_data_out[2]~5 .lut_mask = 16'hD1F0;
+defparam \mcu_data_out[2]~5 .sum_lutc_input = "datac";
+
+// Location: LCCOMB_X1_Y26_N6
+cycloneive_lcell_comb \mcu_data_out[3]~6 (
+	.dataa(\MCU_LCD_RDX~input_o ),
+	.datab(\LCD_DB[11]~input_o ),
+	.datac(lcd_data_in_q[3]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\mcu_data_out[3]~6_combout ),
+	.cout());
+defparam \mcu_data_out[3]~6 .lut_mask = 16'hE4E4;
+defparam \mcu_data_out[3]~6 .sum_lutc_input = "datac";
+
+// Location: LCCOMB_X1_Y23_N12
+cycloneive_lcell_comb \mcu_data_out[3]~7 (
+	.dataa(\SW_U~input_o ),
+	.datab(\MCU_IO_STBX~input_o ),
+	.datac(\MCU_DIR~input_o ),
+	.datad(\mcu_data_out[3]~6_combout ),
+	.cin(gnd),
+	.combout(\mcu_data_out[3]~7_combout ),
+	.cout());
+defparam \mcu_data_out[3]~7 .lut_mask = 16'hDF10;
+defparam \mcu_data_out[3]~7 .sum_lutc_input = "datac";
+
+// Location: LCCOMB_X1_Y26_N10
+cycloneive_lcell_comb \mcu_data_out[4]~8 (
+	.dataa(\MCU_LCD_RDX~input_o ),
+	.datab(\LCD_DB[12]~input_o ),
+	.datac(lcd_data_in_q[4]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\mcu_data_out[4]~8_combout ),
+	.cout());
+defparam \mcu_data_out[4]~8 .lut_mask = 16'hE4E4;
+defparam \mcu_data_out[4]~8 .sum_lutc_input = "datac";
+
+// Location: LCCOMB_X1_Y23_N14
+cycloneive_lcell_comb \mcu_data_out[4]~9 (
+	.dataa(\MCU_DIR~input_o ),
+	.datab(\SW_SEL~input_o ),
+	.datac(\MCU_IO_STBX~input_o ),
+	.datad(\mcu_data_out[4]~8_combout ),
+	.cin(gnd),
+	.combout(\mcu_data_out[4]~9_combout ),
+	.cout());
+defparam \mcu_data_out[4]~9 .lut_mask = 16'hF702;
+defparam \mcu_data_out[4]~9 .sum_lutc_input = "datac";
+
+// Location: LCCOMB_X1_Y26_N8
+cycloneive_lcell_comb \mcu_data_out[5]~10 (
+	.dataa(\MCU_LCD_RDX~input_o ),
+	.datab(gnd),
+	.datac(lcd_data_in_q[5]),
+	.datad(\LCD_DB[13]~input_o ),
+	.cin(gnd),
+	.combout(\mcu_data_out[5]~10_combout ),
+	.cout());
+defparam \mcu_data_out[5]~10 .lut_mask = 16'hF5A0;
+defparam \mcu_data_out[5]~10 .sum_lutc_input = "datac";
+
+// Location: LCCOMB_X1_Y23_N30
+cycloneive_lcell_comb \mcu_data_out[5]~11 (
+	.dataa(\MCU_DIR~input_o ),
+	.datab(\SW_ROT_A~input_o ),
+	.datac(\MCU_IO_STBX~input_o ),
+	.datad(\mcu_data_out[5]~10_combout ),
+	.cin(gnd),
+	.combout(\mcu_data_out[5]~11_combout ),
+	.cout());
+defparam \mcu_data_out[5]~11 .lut_mask = 16'hF702;
+defparam \mcu_data_out[5]~11 .sum_lutc_input = "datac";
+
+// Location: LCCOMB_X1_Y19_N4
+cycloneive_lcell_comb \mcu_data_out[6]~12 (
+	.dataa(\LCD_DB[14]~input_o ),
+	.datab(gnd),
+	.datac(lcd_data_in_q[6]),
+	.datad(\MCU_LCD_RDX~input_o ),
+	.cin(gnd),
+	.combout(\mcu_data_out[6]~12_combout ),
+	.cout());
+defparam \mcu_data_out[6]~12 .lut_mask = 16'hF0AA;
+defparam \mcu_data_out[6]~12 .sum_lutc_input = "datac";
+
+// Location: LCCOMB_X1_Y18_N16
+cycloneive_lcell_comb \mcu_data_out[6]~13 (
+	.dataa(\SW_ROT_B~input_o ),
+	.datab(\MCU_IO_STBX~input_o ),
+	.datac(\mcu_data_out[6]~12_combout ),
+	.datad(\MCU_DIR~input_o ),
+	.cin(gnd),
+	.combout(\mcu_data_out[6]~13_combout ),
+	.cout());
+defparam \mcu_data_out[6]~13 .lut_mask = 16'hD1F0;
+defparam \mcu_data_out[6]~13 .sum_lutc_input = "datac";
+
+// Location: LCCOMB_X1_Y21_N28
+cycloneive_lcell_comb \mcu_data_out[7]~14 (
+	.dataa(\LCD_DB[15]~input_o ),
+	.datab(\MCU_LCD_RDX~input_o ),
+	.datac(lcd_data_in_q[7]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\mcu_data_out[7]~14_combout ),
+	.cout());
+defparam \mcu_data_out[7]~14 .lut_mask = 16'hE2E2;
+defparam \mcu_data_out[7]~14 .sum_lutc_input = "datac";
+
+// Location: LCCOMB_X1_Y18_N14
+cycloneive_lcell_comb \mcu_data_out[7]~15 (
+	.dataa(\LCD_TE~input_o ),
+	.datab(\MCU_DIR~input_o ),
+	.datac(\MCU_IO_STBX~input_o ),
+	.datad(\mcu_data_out[7]~14_combout ),
+	.cin(gnd),
+	.combout(\mcu_data_out[7]~15_combout ),
+	.cout());
+defparam \mcu_data_out[7]~15 .lut_mask = 16'hFB08;
+defparam \mcu_data_out[7]~15 .sum_lutc_input = "datac";
+
+// Location: FF_X1_Y15_N31
+dffeas ref_en_q(
+	.clk(\MCU_IO_STBX~inputclkctrl_outclk ),
+	.d(\ref_en_q~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\lcd_reset_q~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\ref_en_q~q ),
+	.prn(vcc));
+defparam ref_en_q.is_wysiwyg = "true";
+defparam ref_en_q.power_up = "low";
+
+// Location: LCCOMB_X1_Y15_N30
+cycloneive_lcell_comb \ref_en_q~feeder (
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\MCU_D[6]~input_o ),
+	.cin(gnd),
+	.combout(\ref_en_q~feeder_combout ),
+	.cout());
+defparam \ref_en_q~feeder .lut_mask = 16'hFF00;
+defparam \ref_en_q~feeder .sum_lutc_input = "datac";
+
+// Location: FF_X1_Y15_N7
+dffeas sysoff_q(
+	.clk(\MCU_IO_STBX~inputclkctrl_outclk ),
+	.d(\sysoff_q~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\lcd_reset_q~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\sysoff_q~q ),
+	.prn(vcc));
+defparam sysoff_q.is_wysiwyg = "true";
+defparam sysoff_q.power_up = "low";
+
+// Location: LCCOMB_X1_Y15_N6
+cycloneive_lcell_comb \sysoff_q~feeder (
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\MCU_D[2]~input_o ),
+	.cin(gnd),
+	.combout(\sysoff_q~feeder_combout ),
+	.cout());
+defparam \sysoff_q~feeder .lut_mask = 16'hFF00;
+defparam \sysoff_q~feeder .sum_lutc_input = "datac";
+
+// Location: FF_X1_Y15_N19
+dffeas \tp_q[0] (
+	.clk(\MCU_IO_STBX~inputclkctrl_outclk ),
+	.d(gnd),
+	.asdata(\MCU_D[0]~input_o ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\tp_q[3]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(tp_q[0]),
+	.prn(vcc));
+defparam \tp_q[0] .is_wysiwyg = "true";
+defparam \tp_q[0] .power_up = "low";
+
+// Location: FF_X1_Y15_N21
+dffeas \tp_q[1] (
+	.clk(\MCU_IO_STBX~inputclkctrl_outclk ),
+	.d(gnd),
+	.asdata(\MCU_D[1]~input_o ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\tp_q[3]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(tp_q[1]),
+	.prn(vcc));
+defparam \tp_q[1] .is_wysiwyg = "true";
+defparam \tp_q[1] .power_up = "low";
+
+// Location: FF_X1_Y15_N27
+dffeas \tp_q[2] (
+	.clk(\MCU_IO_STBX~inputclkctrl_outclk ),
+	.d(\tp_q[2]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\tp_q[3]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(tp_q[2]),
+	.prn(vcc));
+defparam \tp_q[2] .is_wysiwyg = "true";
+defparam \tp_q[2] .power_up = "low";
+
+// Location: LCCOMB_X1_Y15_N26
+cycloneive_lcell_comb \tp_q[2]~feeder (
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\MCU_D[2]~input_o ),
+	.cin(gnd),
+	.combout(\tp_q[2]~feeder_combout ),
+	.cout());
+defparam \tp_q[2]~feeder .lut_mask = 16'hFF00;
+defparam \tp_q[2]~feeder .sum_lutc_input = "datac";
+
+// Location: FF_X1_Y15_N13
+dffeas \tp_q[3] (
+	.clk(\MCU_IO_STBX~inputclkctrl_outclk ),
+	.d(gnd),
+	.asdata(\MCU_D[3]~input_o ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\tp_q[3]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(tp_q[3]),
+	.prn(vcc));
+defparam \tp_q[3] .is_wysiwyg = "true";
+defparam \tp_q[3] .power_up = "low";
+
+// Location: LCCOMB_X1_Y15_N4
+cycloneive_lcell_comb \tp_q[3]~0 (
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\MCU_ADDR~input_o ),
+	.datad(\MCU_DIR~input_o ),
+	.cin(gnd),
+	.combout(\tp_q[3]~0_combout ),
+	.cout());
+defparam \tp_q[3]~0 .lut_mask = 16'h000F;
+defparam \tp_q[3]~0 .sum_lutc_input = "datac";
+
+// Location: FF_X1_Y15_N15
+dffeas \tp_q[4] (
+	.clk(\MCU_IO_STBX~inputclkctrl_outclk ),
+	.d(\tp_q[4]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\tp_q[3]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(tp_q[4]),
+	.prn(vcc));
+defparam \tp_q[4] .is_wysiwyg = "true";
+defparam \tp_q[4] .power_up = "low";
+
+// Location: LCCOMB_X1_Y15_N14
+cycloneive_lcell_comb \tp_q[4]~feeder (
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\MCU_D[4]~input_o ),
+	.cin(gnd),
+	.combout(\tp_q[4]~feeder_combout ),
+	.cout());
+defparam \tp_q[4]~feeder .lut_mask = 16'hFF00;
+defparam \tp_q[4]~feeder .sum_lutc_input = "datac";
+
+// Location: FF_X1_Y15_N29
+dffeas \tp_q[5] (
+	.clk(\MCU_IO_STBX~inputclkctrl_outclk ),
+	.d(gnd),
+	.asdata(\MCU_D[5]~input_o ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\tp_q[3]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(tp_q[5]),
+	.prn(vcc));
+defparam \tp_q[5] .is_wysiwyg = "true";
+defparam \tp_q[5] .power_up = "low";
+
+// Location: FF_X1_Y15_N9
+dffeas \tp_q[6] (
+	.clk(\MCU_IO_STBX~inputclkctrl_outclk ),
+	.d(\tp_q[6]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\tp_q[3]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(tp_q[6]),
+	.prn(vcc));
+defparam \tp_q[6] .is_wysiwyg = "true";
+defparam \tp_q[6] .power_up = "low";
+
+// Location: LCCOMB_X1_Y15_N8
+cycloneive_lcell_comb \tp_q[6]~feeder (
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\MCU_D[6]~input_o ),
+	.cin(gnd),
+	.combout(\tp_q[6]~feeder_combout ),
+	.cout());
+defparam \tp_q[6]~feeder .lut_mask = 16'hFF00;
+defparam \tp_q[6]~feeder .sum_lutc_input = "datac";
+
+// Location: FF_X1_Y15_N25
+dffeas \tp_q[7] (
+	.clk(\MCU_IO_STBX~inputclkctrl_outclk ),
+	.d(\tp_q[7]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\tp_q[3]~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(tp_q[7]),
+	.prn(vcc));
+defparam \tp_q[7] .is_wysiwyg = "true";
+defparam \tp_q[7] .power_up = "low";
+
+// Location: LCCOMB_X1_Y15_N24
+cycloneive_lcell_comb \tp_q[7]~feeder (
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\MCU_D[7]~input_o ),
+	.cin(gnd),
+	.combout(\tp_q[7]~feeder_combout ),
+	.cout());
+defparam \tp_q[7]~feeder .lut_mask = 16'hFF00;
+defparam \tp_q[7]~feeder .sum_lutc_input = "datac";
+
+endmodule
diff --git a/hardware/portapack_h4m/CPLD/Supra/alta_db/fmax.rpt b/hardware/portapack_h4m/CPLD/Supra/alta_db/fmax.rpt
new file mode 100644
index 00000000..e69de29b
diff --git a/hardware/portapack_h4m/CPLD/Supra/alta_db/hold.rpt.gz b/hardware/portapack_h4m/CPLD/Supra/alta_db/hold.rpt.gz
new file mode 100644
index 00000000..8c9a6c32
Binary files /dev/null and b/hardware/portapack_h4m/CPLD/Supra/alta_db/hold.rpt.gz differ
diff --git a/hardware/portapack_h4m/CPLD/Supra/alta_db/hold_summary.rpt.gz b/hardware/portapack_h4m/CPLD/Supra/alta_db/hold_summary.rpt.gz
new file mode 100644
index 00000000..22ccfac1
Binary files /dev/null and b/hardware/portapack_h4m/CPLD/Supra/alta_db/hold_summary.rpt.gz differ
diff --git a/hardware/portapack_h4m/CPLD/Supra/alta_db/io.asf b/hardware/portapack_h4m/CPLD/Supra/alta_db/io.asf
new file mode 100644
index 00000000..c3c3ca05
--- /dev/null
+++ b/hardware/portapack_h4m/CPLD/Supra/alta_db/io.asf
@@ -0,0 +1,112 @@
+set_location_assignment -to MCU_D[7] PIN_26
+set_location_assignment -to MCU_D[6] PIN_27
+set_location_assignment -to MCU_D[5] PIN_29
+set_location_assignment -to MCU_D[4] PIN_28
+set_location_assignment -to MCU_D[3] PIN_30
+set_location_assignment -to MCU_D[2] PIN_33
+set_location_assignment -to MCU_D[1] PIN_36
+set_location_assignment -to MCU_D[0] PIN_35
+set_location_assignment -to MCU_DIR PIN_72
+set_location_assignment -to MCU_IO_STBX PIN_41
+set_location_assignment -to MCU_LCD_WRX PIN_71
+set_location_assignment -to MCU_ADDR PIN_42
+set_location_assignment -to MCU_LCD_TE PIN_40
+set_location_assignment -to MCU_P2_8 PIN_43
+set_location_assignment -to MCU_LCD_RDX PIN_39
+set_location_assignment -to TP_U PIN_8
+set_location_assignment -to TP_D PIN_6
+set_location_assignment -to TP_L PIN_7
+set_location_assignment -to TP_R PIN_5
+set_location_assignment -to SW_SEL PIN_17
+set_location_assignment -to SW_ROT_A PIN_15
+set_location_assignment -to SW_ROT_B PIN_16
+set_location_assignment -to SW_U PIN_34
+set_location_assignment -to SW_D PIN_14
+set_location_assignment -to SW_L PIN_37
+set_location_assignment -to SW_R PIN_12
+set_location_assignment -to LCD_RESETX PIN_100
+set_location_assignment -to LCD_RS PIN_3
+set_location_assignment -to LCD_WRX PIN_2
+set_location_assignment -to LCD_RDX PIN_1
+set_location_assignment -to LCD_DB[15] PIN_82
+set_location_assignment -to LCD_DB[14] PIN_83
+set_location_assignment -to LCD_DB[13] PIN_84
+set_location_assignment -to LCD_DB[12] PIN_85
+set_location_assignment -to LCD_DB[11] PIN_86
+set_location_assignment -to LCD_DB[10] PIN_87
+set_location_assignment -to LCD_DB[9] PIN_88
+set_location_assignment -to LCD_DB[8] PIN_89
+set_location_assignment -to LCD_DB[7] PIN_90
+set_location_assignment -to LCD_DB[6] PIN_91
+set_location_assignment -to LCD_DB[5] PIN_92
+set_location_assignment -to LCD_DB[4] PIN_95
+set_location_assignment -to LCD_DB[3] PIN_96
+set_location_assignment -to LCD_DB[2] PIN_97
+set_location_assignment -to LCD_DB[1] PIN_98
+set_location_assignment -to LCD_DB[0] PIN_99
+set_location_assignment -to LCD_TE PIN_4
+set_location_assignment -to LCD_BACKLIGHT PIN_76
+set_location_assignment -to SYSOFF PIN_47
+set_location_assignment -to AUDIO_RESETX PIN_57
+set_location_assignment -to REF_EN PIN_58
+set_location_assignment -to GPS_RESETX PIN_73
+set_location_assignment -to GPS_TX_READY PIN_75
+set_location_assignment -to GPS_TIMEPULSE PIN_74
+set_location_assignment -to DEVICE_RESET PIN_44
+set_location_assignment -to DEVICE_RESET_V PIN_38
+set_instance_assignment -name IO_STANDARD -to MCU_D[7] "3.3-V LVCMOS"
+set_instance_assignment -name IO_STANDARD -to MCU_D[6] "3.3-V LVCMOS"
+set_instance_assignment -name IO_STANDARD -to MCU_D[5] "3.3-V LVCMOS"
+set_instance_assignment -name IO_STANDARD -to MCU_D[4] "3.3-V LVCMOS"
+set_instance_assignment -name IO_STANDARD -to MCU_D[3] "3.3-V LVCMOS"
+set_instance_assignment -name IO_STANDARD -to MCU_D[2] "3.3-V LVCMOS"
+set_instance_assignment -name IO_STANDARD -to MCU_D[1] "3.3-V LVCMOS"
+set_instance_assignment -name IO_STANDARD -to MCU_D[0] "3.3-V LVCMOS"
+set_instance_assignment -name IO_STANDARD -to MCU_DIR "3.3-V LVCMOS"
+set_instance_assignment -name IO_STANDARD -to MCU_IO_STBX "3.3-V LVCMOS"
+set_instance_assignment -name IO_STANDARD -to MCU_LCD_WRX "3.3-V LVCMOS"
+set_instance_assignment -name IO_STANDARD -to MCU_ADDR "3.3-V LVCMOS"
+set_instance_assignment -name IO_STANDARD -to MCU_LCD_TE "3.3-V LVCMOS"
+set_instance_assignment -name IO_STANDARD -to MCU_P2_8 "3.3-V LVCMOS"
+set_instance_assignment -name IO_STANDARD -to MCU_LCD_RDX "3.3-V LVCMOS"
+set_instance_assignment -name IO_STANDARD -to TP_U "3.3-V LVCMOS"
+set_instance_assignment -name IO_STANDARD -to TP_D "3.3-V LVCMOS"
+set_instance_assignment -name IO_STANDARD -to TP_L "3.3-V LVCMOS"
+set_instance_assignment -name IO_STANDARD -to TP_R "3.3-V LVCMOS"
+set_instance_assignment -name IO_STANDARD -to SW_SEL "3.3V Schmitt Trigger Input"
+set_instance_assignment -name IO_STANDARD -to SW_ROT_A "3.3V Schmitt Trigger Input"
+set_instance_assignment -name IO_STANDARD -to SW_ROT_B "3.3V Schmitt Trigger Input"
+set_instance_assignment -name IO_STANDARD -to SW_U "3.3V Schmitt Trigger Input"
+set_instance_assignment -name IO_STANDARD -to SW_D "3.3V Schmitt Trigger Input"
+set_instance_assignment -name IO_STANDARD -to SW_L "3.3V Schmitt Trigger Input"
+set_instance_assignment -name IO_STANDARD -to SW_R "3.3V Schmitt Trigger Input"
+set_instance_assignment -name IO_STANDARD -to LCD_RESETX "3.3-V LVCMOS"
+set_instance_assignment -name IO_STANDARD -to LCD_RS "3.3-V LVCMOS"
+set_instance_assignment -name IO_STANDARD -to LCD_WRX "3.3-V LVCMOS"
+set_instance_assignment -name IO_STANDARD -to LCD_RDX "3.3-V LVCMOS"
+set_instance_assignment -name IO_STANDARD -to LCD_DB[15] "3.3-V LVCMOS"
+set_instance_assignment -name IO_STANDARD -to LCD_DB[14] "3.3-V LVCMOS"
+set_instance_assignment -name IO_STANDARD -to LCD_DB[13] "3.3-V LVCMOS"
+set_instance_assignment -name IO_STANDARD -to LCD_DB[12] "3.3-V LVCMOS"
+set_instance_assignment -name IO_STANDARD -to LCD_DB[11] "3.3-V LVCMOS"
+set_instance_assignment -name IO_STANDARD -to LCD_DB[10] "3.3-V LVCMOS"
+set_instance_assignment -name IO_STANDARD -to LCD_DB[9] "3.3-V LVCMOS"
+set_instance_assignment -name IO_STANDARD -to LCD_DB[8] "3.3-V LVCMOS"
+set_instance_assignment -name IO_STANDARD -to LCD_DB[7] "3.3-V LVCMOS"
+set_instance_assignment -name IO_STANDARD -to LCD_DB[6] "3.3-V LVCMOS"
+set_instance_assignment -name IO_STANDARD -to LCD_DB[5] "3.3-V LVCMOS"
+set_instance_assignment -name IO_STANDARD -to LCD_DB[4] "3.3-V LVCMOS"
+set_instance_assignment -name IO_STANDARD -to LCD_DB[3] "3.3-V LVCMOS"
+set_instance_assignment -name IO_STANDARD -to LCD_DB[2] "3.3-V LVCMOS"
+set_instance_assignment -name IO_STANDARD -to LCD_DB[1] "3.3-V LVCMOS"
+set_instance_assignment -name IO_STANDARD -to LCD_DB[0] "3.3-V LVCMOS"
+set_instance_assignment -name IO_STANDARD -to LCD_TE "3.3-V LVCMOS"
+set_instance_assignment -name IO_STANDARD -to LCD_BACKLIGHT "3.3-V LVCMOS"
+set_instance_assignment -name IO_STANDARD -to SYSOFF "3.3-V LVCMOS"
+set_instance_assignment -name IO_STANDARD -to AUDIO_RESETX "3.3-V LVCMOS"
+set_instance_assignment -name IO_STANDARD -to REF_EN "3.3-V LVCMOS"
+set_instance_assignment -name IO_STANDARD -to GPS_RESETX "3.3-V LVCMOS"
+set_instance_assignment -name IO_STANDARD -to GPS_TX_READY "3.3-V LVCMOS"
+set_instance_assignment -name IO_STANDARD -to GPS_TIMEPULSE "3.3-V LVCMOS"
+set_instance_assignment -name IO_STANDARD -to DEVICE_RESET "3.3-V LVCMOS"
+set_instance_assignment -name IO_STANDARD -to DEVICE_RESET_V "3.3-V LVCMOS"
diff --git a/hardware/portapack_h4m/CPLD/Supra/alta_db/packed.vx b/hardware/portapack_h4m/CPLD/Supra/alta_db/packed.vx
new file mode 100644
index 00000000..4347c04f
--- /dev/null
+++ b/hardware/portapack_h4m/CPLD/Supra/alta_db/packed.vx
@@ -0,0 +1,2565 @@
+`timescale 1 ps/ 1 ps
+
+module top(
+	MCU_D,
+	MCU_DIR,
+	MCU_IO_STBX,
+	MCU_LCD_WRX,
+	MCU_ADDR,
+	MCU_LCD_TE,
+	MCU_P2_8,
+	MCU_LCD_RDX,
+	TP_U,
+	TP_D,
+	TP_L,
+	TP_R,
+	SW_SEL,
+	SW_ROT_A,
+	SW_ROT_B,
+	SW_U,
+	SW_D,
+	SW_L,
+	SW_R,
+	LCD_RESETX,
+	LCD_RS,
+	LCD_WRX,
+	LCD_RDX,
+	LCD_DB,
+	LCD_TE,
+	LCD_BACKLIGHT,
+	SYSOFF,
+	AUDIO_RESETX,
+	REF_EN,
+	GPS_RESETX,
+	GPS_TX_READY,
+	GPS_TIMEPULSE,
+	DEVICE_RESET,
+	DEVICE_RESET_V);
+output	[7:0] MCU_D;
+input	MCU_DIR;
+input	MCU_IO_STBX;
+input	MCU_LCD_WRX;
+input	MCU_ADDR;
+output	MCU_LCD_TE;
+input	MCU_P2_8;
+input	MCU_LCD_RDX;
+output	TP_U;
+output	TP_D;
+output	TP_L;
+output	TP_R;
+input	SW_SEL;
+input	SW_ROT_A;
+input	SW_ROT_B;
+input	SW_U;
+input	SW_D;
+input	SW_L;
+input	SW_R;
+output	LCD_RESETX;
+output	LCD_RS;
+output	LCD_WRX;
+output	LCD_RDX;
+output	[15:0] LCD_DB;
+input	LCD_TE;
+output	LCD_BACKLIGHT;
+output	SYSOFF;
+output	AUDIO_RESETX;
+output	REF_EN;
+output	GPS_RESETX;
+input	GPS_TX_READY;
+input	GPS_TIMEPULSE;
+input	DEVICE_RESET;
+input	DEVICE_RESET_V;
+
+// module hard_block
+// Design Ports Information
+// ~ALTERA_ASDO_DATA1~	=>  Location: PIN_F4,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// ~ALTERA_FLASH_nCE_nCSO~	=>  Location: PIN_E2,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// ~ALTERA_DCLK~	=>  Location: PIN_P3,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// ~ALTERA_DATA0~	=>  Location: PIN_N7,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// ~ALTERA_nCEO~	=>  Location: PIN_P28,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+
+// module top
+// Design Ports Information
+// MCU_LCD_TE	=>  Location: PIN_AC4,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// MCU_P2_8	=>  Location: PIN_D6,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// TP_U	=>  Location: PIN_AA4,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// TP_D	=>  Location: PIN_AB3,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// TP_L	=>  Location: PIN_AA3,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// TP_R	=>  Location: PIN_AD1,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LCD_RESETX	=>  Location: PIN_AB4,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LCD_RS	=>  Location: PIN_AF2,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LCD_WRX	=>  Location: PIN_M1,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LCD_RDX	=>  Location: PIN_R6,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LCD_BACKLIGHT	=>  Location: PIN_W3,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// SYSOFF	=>  Location: PIN_AE2,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// AUDIO_RESETX	=>  Location: PIN_AE1,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// REF_EN	=>  Location: PIN_AC5,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// GPS_RESETX	=>  Location: PIN_AC26,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// GPS_TX_READY	=>  Location: PIN_D9,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// GPS_TIMEPULSE	=>  Location: PIN_E25,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// DEVICE_RESET	=>  Location: PIN_AF15,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// DEVICE_RESET_V	=>  Location: PIN_AE25,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// MCU_D[0]	=>  Location: PIN_AC1,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// MCU_D[1]	=>  Location: PIN_AC3,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// MCU_D[2]	=>  Location: PIN_AD3,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// MCU_D[3]	=>  Location: PIN_V3,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// MCU_D[4]	=>  Location: PIN_V2,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// MCU_D[5]	=>  Location: PIN_V1,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// MCU_D[6]	=>  Location: PIN_Y3,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// MCU_D[7]	=>  Location: PIN_AC2,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LCD_DB[0]	=>  Location: PIN_U5,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LCD_DB[1]	=>  Location: PIN_AB1,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LCD_DB[2]	=>  Location: PIN_U2,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LCD_DB[3]	=>  Location: PIN_T3,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LCD_DB[4]	=>  Location: PIN_R5,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LCD_DB[5]	=>  Location: PIN_T4,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LCD_DB[6]	=>  Location: PIN_Y4,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LCD_DB[7]	=>  Location: PIN_AB2,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LCD_DB[8]	=>  Location: PIN_U6,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LCD_DB[9]	=>  Location: PIN_U1,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LCD_DB[10]	=>  Location: PIN_V4,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LCD_DB[11]	=>  Location: PIN_R2,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LCD_DB[12]	=>  Location: PIN_R1,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LCD_DB[13]	=>  Location: PIN_R4,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LCD_DB[14]	=>  Location: PIN_W2,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LCD_DB[15]	=>  Location: PIN_W1,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LCD_TE	=>  Location: PIN_AB6,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// MCU_ADDR	=>  Location: PIN_AB5,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// MCU_LCD_WRX	=>  Location: PIN_Y1,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// MCU_LCD_RDX	=>  Location: PIN_Y2,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// MCU_IO_STBX	=>  Location: PIN_J1,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// MCU_DIR	=>  Location: PIN_AD2,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW_R	=>  Location: PIN_U8,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW_L	=>  Location: PIN_U7,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW_D	=>  Location: PIN_T7,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW_U	=>  Location: PIN_R3,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW_SEL	=>  Location: PIN_U3,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW_ROT_A	=>  Location: PIN_U4,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW_ROT_B	=>  Location: PIN_T8,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+
+//wire	gnd;
+//wire	gnd;
+//wire	vcc;
+//wire	vcc;
+//wire	\AUDIO_RESETX~output_o ;
+wire	\DEVICE_RESET_V~input_o ;
+wire	\DEVICE_RESET~input_o ;
+//wire	\GPS_RESETX~output_o ;
+wire	\GPS_TIMEPULSE~input_o ;
+wire	\GPS_TX_READY~input_o ;
+//wire	\LCD_BACKLIGHT~output_o ;
+//wire	\LCD_DB[0]~output_o ;
+wire	\LCD_DB[0]~input_o ;
+//wire	\LCD_DB[10]~output_o ;
+wire	\LCD_DB[10]~input_o ;
+//wire	\LCD_DB[11]~output_o ;
+wire	\LCD_DB[11]~input_o ;
+//wire	\LCD_DB[12]~output_o ;
+wire	\LCD_DB[12]~input_o ;
+//wire	\LCD_DB[13]~output_o ;
+wire	\LCD_DB[13]~input_o ;
+//wire	\LCD_DB[14]~output_o ;
+wire	\LCD_DB[14]~input_o ;
+//wire	\LCD_DB[15]~output_o ;
+wire	\LCD_DB[15]~input_o ;
+//wire	\LCD_DB[1]~output_o ;
+wire	\LCD_DB[1]~input_o ;
+//wire	\LCD_DB[2]~output_o ;
+wire	\LCD_DB[2]~input_o ;
+//wire	\LCD_DB[3]~output_o ;
+wire	\LCD_DB[3]~input_o ;
+//wire	\LCD_DB[4]~output_o ;
+wire	\LCD_DB[4]~input_o ;
+//wire	\LCD_DB[5]~output_o ;
+wire	\LCD_DB[5]~input_o ;
+//wire	\LCD_DB[6]~output_o ;
+wire	\LCD_DB[6]~input_o ;
+//wire	\LCD_DB[7]~output_o ;
+wire	\LCD_DB[7]~input_o ;
+//wire	\LCD_DB[8]~output_o ;
+wire	\LCD_DB[8]~input_o ;
+//wire	\LCD_DB[9]~output_o ;
+wire	\LCD_DB[9]~input_o ;
+//wire	\LCD_RDX~output_o ;
+//wire	\LCD_RESETX~output_o ;
+//wire	\LCD_RS~output_o ;
+wire	\LCD_TE~input_o ;
+//wire	\LCD_WRX~output_o ;
+wire	\MCU_ADDR~input_o ;
+wire	\MCU_DIR~input_o ;
+//wire	\MCU_D[0]~output_o ;
+wire	\MCU_D[0]~input_o ;
+//wire	\MCU_D[1]~output_o ;
+wire	\MCU_D[1]~input_o ;
+//wire	\MCU_D[2]~output_o ;
+wire	\MCU_D[2]~input_o ;
+//wire	\MCU_D[3]~output_o ;
+wire	\MCU_D[3]~input_o ;
+//wire	\MCU_D[4]~output_o ;
+wire	\MCU_D[4]~input_o ;
+//wire	\MCU_D[5]~output_o ;
+wire	\MCU_D[5]~input_o ;
+//wire	\MCU_D[6]~output_o ;
+wire	\MCU_D[6]~input_o ;
+//wire	\MCU_D[7]~output_o ;
+wire	\MCU_D[7]~input_o ;
+wire	\MCU_IO_STBX~input_o ;
+wire	\MCU_IO_STBX~inputclkctrl_outclk ;
+wire	\MCU_LCD_RDX~input_o ;
+wire	\MCU_LCD_RDX~inputclkctrl_outclk ;
+//wire	\MCU_LCD_TE~output_o ;
+wire	\MCU_LCD_WRX~input_o ;
+wire	\MCU_LCD_WRX~inputclkctrl_outclk ;
+wire	\MCU_P2_8~input_o ;
+//wire	\REF_EN~output_o ;
+wire	\SW_D~input_o ;
+wire	\SW_L~input_o ;
+wire	\SW_ROT_A~input_o ;
+wire	\SW_ROT_B~input_o ;
+wire	\SW_R~input_o ;
+wire	\SW_SEL~input_o ;
+wire	\SW_U~input_o ;
+//wire	\SYSOFF~output_o ;
+//wire	\TP_D~output_o ;
+//wire	\TP_L~output_o ;
+//wire	\TP_R~output_o ;
+//wire	\TP_U~output_o ;
+wire	\audio_reset_q~0_combout ;
+wire	\audio_reset_q~q ;
+//wire	devclrn;
+tri1	devclrn;
+//wire	devoe;
+tri1	devoe;
+//wire	devpor;
+tri1	devpor;
+wire	\lcd_backlight_q~feeder_combout ;
+wire	\lcd_backlight_q~q ;
+wire	[7:0] lcd_data_in_q;
+//wire	lcd_data_in_q[0];
+//wire	lcd_data_in_q[1];
+//wire	lcd_data_in_q[2];
+//wire	lcd_data_in_q[3];
+//wire	lcd_data_in_q[4];
+//wire	lcd_data_in_q[5];
+//wire	lcd_data_in_q[6];
+//wire	lcd_data_in_q[7];
+wire	[7:0] lcd_data_out_q;
+//wire	lcd_data_out_q[0];
+wire	\lcd_data_out_q[0]~feeder_combout ;
+//wire	lcd_data_out_q[1];
+wire	\lcd_data_out_q[1]~feeder_combout ;
+//wire	lcd_data_out_q[2];
+wire	\lcd_data_out_q[2]~feeder_combout ;
+//wire	lcd_data_out_q[3];
+//wire	lcd_data_out_q[4];
+wire	\lcd_data_out_q[4]~feeder_combout ;
+//wire	lcd_data_out_q[5];
+//wire	lcd_data_out_q[6];
+//wire	lcd_data_out_q[7];
+wire	\lcd_data_out_q[7]~feeder_combout ;
+wire	\lcd_reset_q~0_combout ;
+wire	\lcd_reset_q~1_combout ;
+wire	\lcd_reset_q~q ;
+wire	\mcu_data_out[0]~0_combout ;
+wire	\mcu_data_out[0]~1_combout ;
+wire	\mcu_data_out[1]~2_combout ;
+wire	\mcu_data_out[1]~3_combout ;
+wire	\mcu_data_out[2]~4_combout ;
+wire	\mcu_data_out[2]~5_combout ;
+wire	\mcu_data_out[3]~6_combout ;
+wire	\mcu_data_out[3]~7_combout ;
+wire	\mcu_data_out[4]~8_combout ;
+wire	\mcu_data_out[4]~9_combout ;
+wire	\mcu_data_out[5]~10_combout ;
+wire	\mcu_data_out[5]~11_combout ;
+wire	\mcu_data_out[6]~12_combout ;
+wire	\mcu_data_out[6]~13_combout ;
+wire	\mcu_data_out[7]~14_combout ;
+wire	\mcu_data_out[7]~15_combout ;
+wire	\ref_en_q~feeder_combout ;
+wire	\ref_en_q~q ;
+wire	\sysoff_q~feeder_combout ;
+wire	\sysoff_q~q ;
+wire	[7:0] tp_q;
+//wire	tp_q[0];
+//wire	tp_q[1];
+//wire	tp_q[2];
+wire	\tp_q[2]~feeder_combout ;
+//wire	tp_q[3];
+wire	\tp_q[3]~0_combout ;
+//wire	tp_q[4];
+wire	\tp_q[4]~feeder_combout ;
+//wire	tp_q[5];
+//wire	tp_q[6];
+wire	\tp_q[6]~feeder_combout ;
+//wire	tp_q[7];
+wire	\tp_q[7]~feeder_combout ;
+wire	unknown;
+wire	unknown;
+wire	\~ALTERA_ASDO_DATA1~~ibuf_o ;
+wire	\~ALTERA_ASDO_DATA1~~padout ;
+wire	\~ALTERA_DATA0~~ibuf_o ;
+wire	\~ALTERA_DATA0~~padout ;
+wire	\~ALTERA_FLASH_nCE_nCSO~~ibuf_o ;
+wire	\~ALTERA_FLASH_nCE_nCSO~~padout ;
+
+wire vcc;
+wire gnd;
+assign vcc = 1'b1;
+assign gnd = 1'b0;
+
+// Location: IOIBUF_X0_Y10_N0
+// alta_io_ibuf \SW_L~input (
+alta_io \SW_L~input (
+	.datain(gnd),
+	.oe(gnd),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\SW_L~input_o ),
+	.regout(),
+	.padio(SW_L));
+defparam \SW_L~input .CFG_KEEP = 2'b00;
+// defparam \SW_L~input .simulate_z_as = "z";
+
+// Location: IOIBUF_X0_Y10_N1
+// alta_io_ibuf \SW_R~input (
+alta_io \SW_R~input (
+	.datain(gnd),
+	.oe(gnd),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\SW_R~input_o ),
+	.regout(),
+	.padio(SW_R));
+defparam \SW_R~input .CFG_KEEP = 2'b00;
+// defparam \SW_R~input .simulate_z_as = "z";
+
+// Location: IOOBUF_X0_Y11_N0
+// alta_io_obuf \TP_U~output (
+alta_io \TP_U~output (
+	.datain(tp_q[3]),
+	.oe(tp_q[7]),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(),
+	.regout(),
+	.padio(TP_U));
+defparam \TP_U~output .CFG_KEEP = 2'b00;
+// defparam \TP_U~output .open_drain_output = "false";
+
+// Location: IOOBUF_X0_Y11_N1
+// alta_io_obuf \TP_L~output (
+alta_io \TP_L~output (
+	.datain(tp_q[1]),
+	.oe(tp_q[5]),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(),
+	.regout(),
+	.padio(TP_L));
+defparam \TP_L~output .CFG_KEEP = 2'b00;
+// defparam \TP_L~output .open_drain_output = "false";
+
+// Location: IOIBUF_X0_Y14_N1
+// alta_io_ibuf \SW_ROT_B~input (
+alta_io \SW_ROT_B~input (
+	.datain(gnd),
+	.oe(gnd),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\SW_ROT_B~input_o ),
+	.regout(),
+	.padio(SW_ROT_B));
+defparam \SW_ROT_B~input .CFG_KEEP = 2'b00;
+// defparam \SW_ROT_B~input .simulate_z_as = "z";
+
+// Location: IOOBUF_X0_Y15_N2
+// alta_io_obuf \TP_R~output (
+alta_io \TP_R~output (
+	.datain(tp_q[0]),
+	.oe(tp_q[4]),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(),
+	.regout(),
+	.padio(TP_R));
+defparam \TP_R~output .CFG_KEEP = 2'b00;
+// defparam \TP_R~output .open_drain_output = "false";
+
+// Location: IOOBUF_X0_Y15_N3
+// alta_io_obuf \TP_D~output (
+alta_io \TP_D~output (
+	.datain(tp_q[2]),
+	.oe(tp_q[6]),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(),
+	.regout(),
+	.padio(TP_D));
+defparam \TP_D~output .CFG_KEEP = 2'b00;
+// defparam \TP_D~output .open_drain_output = "false";
+
+// Location: IOIBUF_X0_Y16_N1
+// alta_io_ibuf \MCU_D[1]~input (
+// Location: IOOBUF_X0_Y16_N1
+// alta_io_obuf \MCU_D[1]~output (
+alta_io \MCU_D[1]~output (
+	.datain(\mcu_data_out[1]~3_combout ),
+	.oe(\MCU_DIR~input_o ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\MCU_D[1]~input_o ),
+	.regout(),
+	.padio(MCU_D[1]));
+defparam \MCU_D[1]~output .CFG_KEEP = 2'b00;
+// defparam \MCU_D[1]~input .simulate_z_as = "z";
+// defparam \MCU_D[1]~output .open_drain_output = "false";
+
+// Location: IOIBUF_X0_Y16_N2
+// alta_io_ibuf \MCU_D[2]~input (
+// Location: IOOBUF_X0_Y16_N2
+// alta_io_obuf \MCU_D[2]~output (
+alta_io \MCU_D[2]~output (
+	.datain(\mcu_data_out[2]~5_combout ),
+	.oe(\MCU_DIR~input_o ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\MCU_D[2]~input_o ),
+	.regout(),
+	.padio(MCU_D[2]));
+defparam \MCU_D[2]~output .CFG_KEEP = 2'b00;
+// defparam \MCU_D[2]~input .simulate_z_as = "z";
+// defparam \MCU_D[2]~output .open_drain_output = "false";
+
+// Location: IOIBUF_X0_Y16_N3
+// alta_io_ibuf \MCU_DIR~input (
+alta_io \MCU_DIR~input (
+	.datain(gnd),
+	.oe(gnd),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\MCU_DIR~input_o ),
+	.regout(),
+	.padio(MCU_DIR));
+defparam \MCU_DIR~input .CFG_KEEP = 2'b00;
+// defparam \MCU_DIR~input .simulate_z_as = "z";
+
+// Location: IOIBUF_X0_Y17_N1
+// alta_io_ibuf \MCU_D[0]~input (
+// Location: IOOBUF_X0_Y17_N1
+// alta_io_obuf \MCU_D[0]~output (
+alta_io \MCU_D[0]~output (
+	.datain(\mcu_data_out[0]~1_combout ),
+	.oe(\MCU_DIR~input_o ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\MCU_D[0]~input_o ),
+	.regout(),
+	.padio(MCU_D[0]));
+defparam \MCU_D[0]~output .CFG_KEEP = 2'b00;
+// defparam \MCU_D[0]~input .simulate_z_as = "z";
+// defparam \MCU_D[0]~output .open_drain_output = "false";
+
+// Location: IOIBUF_X0_Y18_N2
+// alta_io_ibuf \MCU_D[6]~input (
+// Location: IOOBUF_X0_Y18_N2
+// alta_io_obuf \MCU_D[6]~output (
+alta_io \MCU_D[6]~output (
+	.datain(\mcu_data_out[6]~13_combout ),
+	.oe(\MCU_DIR~input_o ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\MCU_D[6]~input_o ),
+	.regout(),
+	.padio(MCU_D[6]));
+defparam \MCU_D[6]~output .CFG_KEEP = 2'b00;
+// defparam \MCU_D[6]~input .simulate_z_as = "z";
+// defparam \MCU_D[6]~output .open_drain_output = "false";
+
+// Location: IOIBUF_X0_Y18_N3
+// alta_io_ibuf \MCU_D[7]~input (
+// Location: IOOBUF_X0_Y18_N3
+// alta_io_obuf \MCU_D[7]~output (
+alta_io \MCU_D[7]~output (
+	.datain(\mcu_data_out[7]~15_combout ),
+	.oe(\MCU_DIR~input_o ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\MCU_D[7]~input_o ),
+	.regout(),
+	.padio(MCU_D[7]));
+defparam \MCU_D[7]~output .CFG_KEEP = 2'b00;
+// defparam \MCU_D[7]~input .simulate_z_as = "z";
+// defparam \MCU_D[7]~output .open_drain_output = "false";
+
+// Location: IOIBUF_X0_Y19_N0
+// alta_io_ibuf \LCD_DB[8]~input (
+// Location: IOOBUF_X0_Y19_N0
+// alta_io_obuf \LCD_DB[8]~output (
+alta_io \LCD_DB[8]~output (
+	.datain(lcd_data_out_q[0]),
+	.oe(\MCU_LCD_RDX~input_o ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\LCD_DB[8]~input_o ),
+	.regout(),
+	.padio(LCD_DB[8]));
+defparam \LCD_DB[8]~output .CFG_KEEP = 2'b00;
+// defparam \LCD_DB[8]~input .simulate_z_as = "z";
+// defparam \LCD_DB[8]~output .open_drain_output = "false";
+
+// Location: IOIBUF_X0_Y19_N2
+// alta_io_ibuf \LCD_DB[0]~input (
+// Location: IOOBUF_X0_Y19_N2
+// alta_io_obuf \LCD_DB[0]~output (
+alta_io \LCD_DB[0]~output (
+	.datain(\MCU_D[0]~input_o ),
+	.oe(\MCU_LCD_RDX~input_o ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\LCD_DB[0]~input_o ),
+	.regout(),
+	.padio(LCD_DB[0]));
+defparam \LCD_DB[0]~output .CFG_KEEP = 2'b00;
+// defparam \LCD_DB[0]~input .simulate_z_as = "z";
+// defparam \LCD_DB[0]~output .open_drain_output = "false";
+
+// Location: IOIBUF_X0_Y19_N3
+// alta_io_ibuf \LCD_DB[6]~input (
+// Location: IOOBUF_X0_Y19_N3
+// alta_io_obuf \LCD_DB[6]~output (
+alta_io \LCD_DB[6]~output (
+	.datain(\MCU_D[6]~input_o ),
+	.oe(\MCU_LCD_RDX~input_o ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\LCD_DB[6]~input_o ),
+	.regout(),
+	.padio(LCD_DB[6]));
+defparam \LCD_DB[6]~output .CFG_KEEP = 2'b00;
+// defparam \LCD_DB[6]~input .simulate_z_as = "z";
+// defparam \LCD_DB[6]~output .open_drain_output = "false";
+
+// Location: IOIBUF_X0_Y20_N0
+// alta_io_ibuf \LCD_DB[14]~input (
+// Location: IOOBUF_X0_Y20_N0
+// alta_io_obuf \LCD_DB[14]~output (
+alta_io \LCD_DB[14]~output (
+	.datain(lcd_data_out_q[6]),
+	.oe(\MCU_LCD_RDX~input_o ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\LCD_DB[14]~input_o ),
+	.regout(),
+	.padio(LCD_DB[14]));
+defparam \LCD_DB[14]~output .CFG_KEEP = 2'b00;
+// defparam \LCD_DB[14]~input .simulate_z_as = "z";
+// defparam \LCD_DB[14]~output .open_drain_output = "false";
+
+// Location: IOIBUF_X0_Y20_N1
+// alta_io_ibuf \LCD_DB[15]~input (
+// Location: IOOBUF_X0_Y20_N1
+// alta_io_obuf \LCD_DB[15]~output (
+alta_io \LCD_DB[15]~output (
+	.datain(lcd_data_out_q[7]),
+	.oe(\MCU_LCD_RDX~input_o ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\LCD_DB[15]~input_o ),
+	.regout(),
+	.padio(LCD_DB[15]));
+defparam \LCD_DB[15]~output .CFG_KEEP = 2'b00;
+// defparam \LCD_DB[15]~input .simulate_z_as = "z";
+// defparam \LCD_DB[15]~output .open_drain_output = "false";
+
+// Location: IOIBUF_X0_Y21_N0
+// alta_io_ibuf \LCD_DB[7]~input (
+// Location: IOOBUF_X0_Y21_N0
+// alta_io_obuf \LCD_DB[7]~output (
+alta_io \LCD_DB[7]~output (
+	.datain(\MCU_D[7]~input_o ),
+	.oe(\MCU_LCD_RDX~input_o ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\LCD_DB[7]~input_o ),
+	.regout(),
+	.padio(LCD_DB[7]));
+defparam \LCD_DB[7]~output .CFG_KEEP = 2'b00;
+// defparam \LCD_DB[7]~input .simulate_z_as = "z";
+// defparam \LCD_DB[7]~output .open_drain_output = "false";
+
+// Location: IOIBUF_X0_Y21_N1
+// alta_io_ibuf \LCD_DB[1]~input (
+// Location: IOOBUF_X0_Y21_N1
+// alta_io_obuf \LCD_DB[1]~output (
+alta_io \LCD_DB[1]~output (
+	.datain(\MCU_D[1]~input_o ),
+	.oe(\MCU_LCD_RDX~input_o ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\LCD_DB[1]~input_o ),
+	.regout(),
+	.padio(LCD_DB[1]));
+defparam \LCD_DB[1]~output .CFG_KEEP = 2'b00;
+// defparam \LCD_DB[1]~input .simulate_z_as = "z";
+// defparam \LCD_DB[1]~output .open_drain_output = "false";
+
+// Location: IOIBUF_X0_Y22_N1
+// alta_io_ibuf \MCU_D[5]~input (
+// Location: IOOBUF_X0_Y22_N1
+// alta_io_obuf \MCU_D[5]~output (
+alta_io \MCU_D[5]~output (
+	.datain(\mcu_data_out[5]~11_combout ),
+	.oe(\MCU_DIR~input_o ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\MCU_D[5]~input_o ),
+	.regout(),
+	.padio(MCU_D[5]));
+defparam \MCU_D[5]~output .CFG_KEEP = 2'b00;
+// defparam \MCU_D[5]~input .simulate_z_as = "z";
+// defparam \MCU_D[5]~output .open_drain_output = "false";
+
+// Location: IOIBUF_X0_Y23_N0
+// alta_io_ibuf \MCU_D[3]~input (
+// Location: IOOBUF_X0_Y23_N0
+// alta_io_obuf \MCU_D[3]~output (
+alta_io \MCU_D[3]~output (
+	.datain(\mcu_data_out[3]~7_combout ),
+	.oe(\MCU_DIR~input_o ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\MCU_D[3]~input_o ),
+	.regout(),
+	.padio(MCU_D[3]));
+defparam \MCU_D[3]~output .CFG_KEEP = 2'b00;
+// defparam \MCU_D[3]~input .simulate_z_as = "z";
+// defparam \MCU_D[3]~output .open_drain_output = "false";
+
+// Location: IOIBUF_X0_Y23_N1
+// alta_io_ibuf \MCU_D[4]~input (
+// Location: IOOBUF_X0_Y23_N1
+// alta_io_obuf \MCU_D[4]~output (
+alta_io \MCU_D[4]~output (
+	.datain(\mcu_data_out[4]~9_combout ),
+	.oe(\MCU_DIR~input_o ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\MCU_D[4]~input_o ),
+	.regout(),
+	.padio(MCU_D[4]));
+defparam \MCU_D[4]~output .CFG_KEEP = 2'b00;
+// defparam \MCU_D[4]~input .simulate_z_as = "z";
+// defparam \MCU_D[4]~output .open_drain_output = "false";
+
+// Location: IOIBUF_X0_Y24_N0
+// alta_io_ibuf \LCD_DB[2]~input (
+// Location: IOOBUF_X0_Y24_N0
+// alta_io_obuf \LCD_DB[2]~output (
+alta_io \LCD_DB[2]~output (
+	.datain(\MCU_D[2]~input_o ),
+	.oe(\MCU_LCD_RDX~input_o ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\LCD_DB[2]~input_o ),
+	.regout(),
+	.padio(LCD_DB[2]));
+defparam \LCD_DB[2]~output .CFG_KEEP = 2'b00;
+// defparam \LCD_DB[2]~input .simulate_z_as = "z";
+// defparam \LCD_DB[2]~output .open_drain_output = "false";
+
+// Location: IOIBUF_X0_Y24_N1
+// alta_io_ibuf \LCD_DB[9]~input (
+// Location: IOOBUF_X0_Y24_N1
+// alta_io_obuf \LCD_DB[9]~output (
+alta_io \LCD_DB[9]~output (
+	.datain(lcd_data_out_q[1]),
+	.oe(\MCU_LCD_RDX~input_o ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\LCD_DB[9]~input_o ),
+	.regout(),
+	.padio(LCD_DB[9]));
+defparam \LCD_DB[9]~output .CFG_KEEP = 2'b00;
+// defparam \LCD_DB[9]~input .simulate_z_as = "z";
+// defparam \LCD_DB[9]~output .open_drain_output = "false";
+
+// Location: IOIBUF_X0_Y24_N3
+// alta_io_ibuf \LCD_DB[10]~input (
+// Location: IOOBUF_X0_Y24_N3
+// alta_io_obuf \LCD_DB[10]~output (
+alta_io \LCD_DB[10]~output (
+	.datain(lcd_data_out_q[2]),
+	.oe(\MCU_LCD_RDX~input_o ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\LCD_DB[10]~input_o ),
+	.regout(),
+	.padio(LCD_DB[10]));
+defparam \LCD_DB[10]~output .CFG_KEEP = 2'b00;
+// defparam \LCD_DB[10]~input .simulate_z_as = "z";
+// defparam \LCD_DB[10]~output .open_drain_output = "false";
+
+// Location: IOIBUF_X0_Y25_N2
+// alta_io_ibuf \SW_D~input (
+alta_io \SW_D~input (
+	.datain(gnd),
+	.oe(gnd),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\SW_D~input_o ),
+	.regout(),
+	.padio(SW_D));
+defparam \SW_D~input .CFG_KEEP = 2'b00;
+// defparam \SW_D~input .simulate_z_as = "z";
+
+// Location: IOIBUF_X0_Y26_N0
+// alta_io_ibuf \LCD_DB[13]~input (
+// Location: IOOBUF_X0_Y26_N0
+// alta_io_obuf \LCD_DB[13]~output (
+alta_io \LCD_DB[13]~output (
+	.datain(lcd_data_out_q[5]),
+	.oe(\MCU_LCD_RDX~input_o ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\LCD_DB[13]~input_o ),
+	.regout(),
+	.padio(LCD_DB[13]));
+defparam \LCD_DB[13]~output .CFG_KEEP = 2'b00;
+// defparam \LCD_DB[13]~input .simulate_z_as = "z";
+// defparam \LCD_DB[13]~output .open_drain_output = "false";
+
+// Location: IOIBUF_X0_Y26_N1
+// alta_io_ibuf \LCD_DB[5]~input (
+// Location: IOOBUF_X0_Y26_N1
+// alta_io_obuf \LCD_DB[5]~output (
+alta_io \LCD_DB[5]~output (
+	.datain(\MCU_D[5]~input_o ),
+	.oe(\MCU_LCD_RDX~input_o ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\LCD_DB[5]~input_o ),
+	.regout(),
+	.padio(LCD_DB[5]));
+defparam \LCD_DB[5]~output .CFG_KEEP = 2'b00;
+// defparam \LCD_DB[5]~input .simulate_z_as = "z";
+// defparam \LCD_DB[5]~output .open_drain_output = "false";
+
+// Location: IOIBUF_X0_Y26_N2
+// alta_io_ibuf \LCD_DB[3]~input (
+// Location: IOOBUF_X0_Y26_N2
+// alta_io_obuf \LCD_DB[3]~output (
+alta_io \LCD_DB[3]~output (
+	.datain(\MCU_D[3]~input_o ),
+	.oe(\MCU_LCD_RDX~input_o ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\LCD_DB[3]~input_o ),
+	.regout(),
+	.padio(LCD_DB[3]));
+defparam \LCD_DB[3]~output .CFG_KEEP = 2'b00;
+// defparam \LCD_DB[3]~input .simulate_z_as = "z";
+// defparam \LCD_DB[3]~output .open_drain_output = "false";
+
+// Location: IOIBUF_X0_Y26_N3
+// alta_io_ibuf \LCD_DB[4]~input (
+// Location: IOOBUF_X0_Y26_N3
+// alta_io_obuf \LCD_DB[4]~output (
+alta_io \LCD_DB[4]~output (
+	.datain(\MCU_D[4]~input_o ),
+	.oe(\MCU_LCD_RDX~input_o ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\LCD_DB[4]~input_o ),
+	.regout(),
+	.padio(LCD_DB[4]));
+defparam \LCD_DB[4]~output .CFG_KEEP = 2'b00;
+// defparam \LCD_DB[4]~input .simulate_z_as = "z";
+// defparam \LCD_DB[4]~output .open_drain_output = "false";
+
+// Location: IOIBUF_X0_Y28_N1
+// alta_io_ibuf \SW_ROT_A~input (
+alta_io \SW_ROT_A~input (
+	.datain(gnd),
+	.oe(gnd),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\SW_ROT_A~input_o ),
+	.regout(),
+	.padio(SW_ROT_A));
+defparam \SW_ROT_A~input .CFG_KEEP = 2'b00;
+// defparam \SW_ROT_A~input .simulate_z_as = "z";
+
+// Location: IOIBUF_X0_Y28_N2
+// alta_io_ibuf \SW_U~input (
+alta_io \SW_U~input (
+	.datain(gnd),
+	.oe(gnd),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\SW_U~input_o ),
+	.regout(),
+	.padio(SW_U));
+defparam \SW_U~input .CFG_KEEP = 2'b00;
+// defparam \SW_U~input .simulate_z_as = "z";
+
+// Location: IOIBUF_X0_Y29_N0
+// alta_io_ibuf \LCD_DB[11]~input (
+// Location: IOOBUF_X0_Y29_N0
+// alta_io_obuf \LCD_DB[11]~output (
+alta_io \LCD_DB[11]~output (
+	.datain(lcd_data_out_q[3]),
+	.oe(\MCU_LCD_RDX~input_o ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\LCD_DB[11]~input_o ),
+	.regout(),
+	.padio(LCD_DB[11]));
+defparam \LCD_DB[11]~output .CFG_KEEP = 2'b00;
+// defparam \LCD_DB[11]~input .simulate_z_as = "z";
+// defparam \LCD_DB[11]~output .open_drain_output = "false";
+
+// Location: IOIBUF_X0_Y29_N1
+// alta_io_ibuf \LCD_DB[12]~input (
+// Location: IOOBUF_X0_Y29_N1
+// alta_io_obuf \LCD_DB[12]~output (
+alta_io \LCD_DB[12]~output (
+	.datain(lcd_data_out_q[4]),
+	.oe(\MCU_LCD_RDX~input_o ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\LCD_DB[12]~input_o ),
+	.regout(),
+	.padio(LCD_DB[12]));
+defparam \LCD_DB[12]~output .CFG_KEEP = 2'b00;
+// defparam \LCD_DB[12]~input .simulate_z_as = "z";
+// defparam \LCD_DB[12]~output .open_drain_output = "false";
+
+// Location: IOOBUF_X0_Y29_N2
+// alta_io_obuf \LCD_RDX~output (
+alta_io \LCD_RDX~output (
+	.datain(\MCU_LCD_RDX~input_o ),
+	.oe(vcc),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(),
+	.regout(),
+	.padio(LCD_RDX));
+defparam \LCD_RDX~output .CFG_KEEP = 2'b00;
+// defparam \LCD_RDX~output .open_drain_output = "false";
+
+// Location: IOIBUF_X0_Y29_N3
+// alta_io_ibuf \SW_SEL~input (
+alta_io \SW_SEL~input (
+	.datain(gnd),
+	.oe(gnd),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\SW_SEL~input_o ),
+	.regout(),
+	.padio(SW_SEL));
+defparam \SW_SEL~input .CFG_KEEP = 2'b00;
+// defparam \SW_SEL~input .simulate_z_as = "z";
+
+// Location: IOIBUF_X0_Y30_N1
+// alta_io_ibuf \MCU_IO_STBX~input (
+alta_io \MCU_IO_STBX~input (
+	.datain(gnd),
+	.oe(gnd),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\MCU_IO_STBX~input_o ),
+	.regout(),
+	.padio(MCU_IO_STBX));
+defparam \MCU_IO_STBX~input .CFG_KEEP = 2'b00;
+// defparam \MCU_IO_STBX~input .simulate_z_as = "z";
+
+// Location: IOIBUF_X0_Y30_N2
+// alta_io_ibuf \MCU_LCD_RDX~input (
+alta_io \MCU_LCD_RDX~input (
+	.datain(gnd),
+	.oe(gnd),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\MCU_LCD_RDX~input_o ),
+	.regout(),
+	.padio(MCU_LCD_RDX));
+defparam \MCU_LCD_RDX~input .CFG_KEEP = 2'b00;
+// defparam \MCU_LCD_RDX~input .simulate_z_as = "z";
+
+// Location: IOIBUF_X0_Y30_N3
+// alta_io_ibuf \MCU_LCD_WRX~input (
+alta_io \MCU_LCD_WRX~input (
+	.datain(gnd),
+	.oe(gnd),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\MCU_LCD_WRX~input_o ),
+	.regout(),
+	.padio(MCU_LCD_WRX));
+defparam \MCU_LCD_WRX~input .CFG_KEEP = 2'b00;
+// defparam \MCU_LCD_WRX~input .simulate_z_as = "z";
+
+// Location: IOOBUF_X0_Y37_N0
+// alta_io_obuf \LCD_WRX~output (
+alta_io \LCD_WRX~output (
+	.datain(\MCU_LCD_WRX~input_o ),
+	.oe(vcc),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(),
+	.regout(),
+	.padio(LCD_WRX));
+defparam \LCD_WRX~output .CFG_KEEP = 2'b00;
+// defparam \LCD_WRX~output .open_drain_output = "false";
+
+// Location: IOOBUF_X0_Y4_N2
+// alta_io_obuf \LCD_RS~output (
+alta_io \LCD_RS~output (
+	.datain(\MCU_ADDR~input_o ),
+	.oe(vcc),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(),
+	.regout(),
+	.padio(LCD_RS));
+defparam \LCD_RS~output .CFG_KEEP = 2'b00;
+// defparam \LCD_RS~output .open_drain_output = "false";
+
+// Location: IOIBUF_X0_Y4_N3
+// alta_io_ibuf \MCU_ADDR~input (
+alta_io \MCU_ADDR~input (
+	.datain(gnd),
+	.oe(gnd),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\MCU_ADDR~input_o ),
+	.regout(),
+	.padio(MCU_ADDR));
+defparam \MCU_ADDR~input .CFG_KEEP = 2'b00;
+// defparam \MCU_ADDR~input .simulate_z_as = "z";
+
+// Location: IOOBUF_X0_Y6_N2
+// alta_io_obuf \MCU_LCD_TE~output (
+alta_io \MCU_LCD_TE~output (
+	.datain(\LCD_TE~input_o ),
+	.oe(vcc),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(),
+	.regout(),
+	.padio(MCU_LCD_TE));
+defparam \MCU_LCD_TE~output .CFG_KEEP = 2'b00;
+// defparam \MCU_LCD_TE~output .open_drain_output = "false";
+
+// Location: IOIBUF_X0_Y6_N3
+// alta_io_ibuf \LCD_TE~input (
+alta_io \LCD_TE~input (
+	.datain(gnd),
+	.oe(gnd),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\LCD_TE~input_o ),
+	.regout(),
+	.padio(LCD_TE));
+defparam \LCD_TE~input .CFG_KEEP = 2'b00;
+// defparam \LCD_TE~input .simulate_z_as = "z";
+
+// Location: IOOBUF_X0_Y7_N0
+// alta_io_obuf \LCD_RESETX~output (
+alta_io \LCD_RESETX~output (
+	.datain(\lcd_reset_q~q ),
+	.oe(vcc),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(),
+	.regout(),
+	.padio(LCD_RESETX));
+defparam \LCD_RESETX~output .CFG_KEEP = 2'b00;
+// defparam \LCD_RESETX~output .open_drain_output = "false";
+
+// Location: IOOBUF_X0_Y7_N1
+// alta_io_obuf \REF_EN~output (
+alta_io \REF_EN~output (
+	.datain(\ref_en_q~q ),
+	.oe(vcc),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(),
+	.regout(),
+	.padio(REF_EN));
+defparam \REF_EN~output .CFG_KEEP = 2'b00;
+// defparam \REF_EN~output .open_drain_output = "false";
+
+// Location: IOOBUF_X0_Y8_N3
+// alta_io_obuf \LCD_BACKLIGHT~output (
+alta_io \LCD_BACKLIGHT~output (
+	.datain(\lcd_backlight_q~q ),
+	.oe(vcc),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(),
+	.regout(),
+	.padio(LCD_BACKLIGHT));
+defparam \LCD_BACKLIGHT~output .CFG_KEEP = 2'b00;
+// defparam \LCD_BACKLIGHT~output .open_drain_output = "false";
+
+// Location: IOOBUF_X0_Y9_N1
+// alta_io_obuf \SYSOFF~output (
+alta_io \SYSOFF~output (
+	.datain(\sysoff_q~q ),
+	.oe(vcc),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(),
+	.regout(),
+	.padio(SYSOFF));
+defparam \SYSOFF~output .CFG_KEEP = 2'b00;
+// defparam \SYSOFF~output .open_drain_output = "false";
+
+// Location: IOOBUF_X0_Y9_N2
+// alta_io_obuf \AUDIO_RESETX~output (
+alta_io \AUDIO_RESETX~output (
+	.datain(\audio_reset_q~q ),
+	.oe(vcc),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(),
+	.regout(),
+	.padio(AUDIO_RESETX));
+defparam \AUDIO_RESETX~output .CFG_KEEP = 2'b00;
+// defparam \AUDIO_RESETX~output .open_drain_output = "false";
+
+// Location: IOIBUF_X18_Y62_N2
+// alta_io_ibuf \MCU_P2_8~input (
+alta_io \MCU_P2_8~input (
+	.datain(gnd),
+	.oe(gnd),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\MCU_P2_8~input_o ),
+	.regout(),
+	.padio(MCU_P2_8));
+defparam \MCU_P2_8~input .CFG_KEEP = 2'b00;
+// defparam \MCU_P2_8~input .simulate_z_as = "z";
+
+// Location: IOIBUF_X23_Y62_N3
+// alta_io_ibuf \GPS_TX_READY~input (
+alta_io \GPS_TX_READY~input (
+	.datain(gnd),
+	.oe(gnd),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\GPS_TX_READY~input_o ),
+	.regout(),
+	.padio(GPS_TX_READY));
+defparam \GPS_TX_READY~input .CFG_KEEP = 2'b00;
+// defparam \GPS_TX_READY~input .simulate_z_as = "z";
+
+// Location: IOIBUF_X51_Y0_N0
+// alta_io_ibuf \DEVICE_RESET~input (
+alta_io \DEVICE_RESET~input (
+	.datain(gnd),
+	.oe(gnd),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\DEVICE_RESET~input_o ),
+	.regout(),
+	.padio(DEVICE_RESET));
+defparam \DEVICE_RESET~input .CFG_KEEP = 2'b00;
+// defparam \DEVICE_RESET~input .simulate_z_as = "z";
+
+// Location: IOIBUF_X56_Y62_N0
+// alta_io_ibuf \GPS_TIMEPULSE~input (
+alta_io \GPS_TIMEPULSE~input (
+	.datain(gnd),
+	.oe(gnd),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\GPS_TIMEPULSE~input_o ),
+	.regout(),
+	.padio(GPS_TIMEPULSE));
+defparam \GPS_TIMEPULSE~input .CFG_KEEP = 2'b00;
+// defparam \GPS_TIMEPULSE~input .simulate_z_as = "z";
+
+// Location: IOIBUF_X78_Y0_N1
+// alta_io_ibuf \DEVICE_RESET_V~input (
+alta_io \DEVICE_RESET_V~input (
+	.datain(gnd),
+	.oe(gnd),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\DEVICE_RESET_V~input_o ),
+	.regout(),
+	.padio(DEVICE_RESET_V));
+defparam \DEVICE_RESET_V~input .CFG_KEEP = 2'b00;
+// defparam \DEVICE_RESET_V~input .simulate_z_as = "z";
+
+// Location: IOOBUF_X94_Y9_N2
+// alta_io_obuf \GPS_RESETX~output (
+alta_io \GPS_RESETX~output (
+	.datain(vcc),
+	.oe(vcc),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(),
+	.regout(),
+	.padio(GPS_RESETX));
+defparam \GPS_RESETX~output .CFG_KEEP = 2'b00;
+// defparam \GPS_RESETX~output .open_drain_output = "false";
+
+// Location: CLKCTRL_G2
+alta_io_gclk \MCU_IO_STBX~inputclkctrl (
+	.inclk (\MCU_IO_STBX~input_o ),
+	.outclk(\MCU_IO_STBX~inputclkctrl_outclk ));
+//defparam \MCU_IO_STBX~inputclkctrl .clock_type = "global clock";
+//defparam \MCU_IO_STBX~inputclkctrl .ena_register_mode = "none";
+
+// Location: CLKCTRL_G3
+alta_io_gclk \MCU_LCD_WRX~inputclkctrl (
+	.inclk (\MCU_LCD_WRX~input_o ),
+	.outclk(\MCU_LCD_WRX~inputclkctrl_outclk ));
+//defparam \MCU_LCD_WRX~inputclkctrl .clock_type = "global clock";
+//defparam \MCU_LCD_WRX~inputclkctrl .ena_register_mode = "none";
+
+// Location: CLKCTRL_G4
+alta_io_gclk \MCU_LCD_RDX~inputclkctrl (
+	.inclk (\MCU_LCD_RDX~input_o ),
+	.outclk(\MCU_LCD_RDX~inputclkctrl_outclk ));
+//defparam \MCU_LCD_RDX~inputclkctrl .clock_type = "global clock";
+//defparam \MCU_LCD_RDX~inputclkctrl .ena_register_mode = "none";
+
+// Location: LCCOMB_X1_Y15_N10
+// alta_lcell_comb \lcd_reset_q~0 (
+alta_slice \lcd_reset_q~0 (
+	.A(vcc),
+	.B(vcc),
+	.C(\MCU_ADDR~input_o ),
+	.D(\MCU_DIR~input_o ),
+	.Cin(),
+	.Qin(),
+	.Clk(),
+	.AsyncReset(),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\lcd_reset_q~0_combout ),
+	.Cout(),
+	.Q());
+defparam \lcd_reset_q~0 .mask = 16'h00F0;
+defparam \lcd_reset_q~0 .mode = "logic";
+defparam \lcd_reset_q~0 .modeMux = 1'b0;
+defparam \lcd_reset_q~0 .FeedbackMux = 1'b0;
+defparam \lcd_reset_q~0 .ShiftMux = 1'b0;
+defparam \lcd_reset_q~0 .BypassEn = 1'b0;
+defparam \lcd_reset_q~0 .CarryEnb = 1'b1;
+defparam \lcd_reset_q~0 .AsyncResetMux = 2'bxx;
+defparam \lcd_reset_q~0 .SyncResetMux = 2'bxx;
+defparam \lcd_reset_q~0 .SyncLoadMux = 2'bxx;
+// Location: FF_X1_Y15_N12
+// alta_lcell_ff \tp_q[3] (
+alta_slice \tp_q[3] (
+	.A(),
+	.B(),
+	.C(\MCU_D[3]~input_o ),
+	.D(),
+	.Cin(),
+	.Qin(tp_q[3]),
+	.Clk(\MCU_IO_STBX~inputclkctrl_outclk__tp_q[3]~0_combout_X1_Y15_SIG_SIG ),
+	.AsyncReset(AsyncReset_X1_Y15_GND),
+	.SyncReset(SyncReset_X1_Y15_GND),
+	.ShiftData(),
+	.SyncLoad(SyncLoad_X1_Y15_VCC),
+	.LutOut(),
+	.Cout(),
+	.Q(tp_q[3]));
+defparam \tp_q[3] .mask = 16'hFFFF;
+defparam \tp_q[3] .mode = "ripple";
+defparam \tp_q[3] .modeMux = 1'b1;
+defparam \tp_q[3] .FeedbackMux = 1'b0;
+defparam \tp_q[3] .ShiftMux = 1'b0;
+defparam \tp_q[3] .BypassEn = 1'b1;
+defparam \tp_q[3] .CarryEnb = 1'b1;
+defparam \tp_q[3] .AsyncResetMux = 2'b00;
+defparam \tp_q[3] .SyncResetMux = 2'b00;
+defparam \tp_q[3] .SyncLoadMux = 2'b01;
+// Location: FF_X1_Y15_N14
+// alta_lcell_ff \tp_q[4] (
+// Location: LCCOMB_X1_Y15_N14
+// alta_lcell_comb \tp_q[4]~feeder (
+alta_slice \tp_q[4] (
+	.A(vcc),
+	.B(vcc),
+	.C(vcc),
+	.D(\MCU_D[4]~input_o ),
+	.Cin(),
+	.Qin(tp_q[4]),
+	.Clk(\MCU_IO_STBX~inputclkctrl_outclk__tp_q[3]~0_combout_X1_Y15_SIG_SIG ),
+	.AsyncReset(AsyncReset_X1_Y15_GND),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\tp_q[4]~feeder_combout ),
+	.Cout(),
+	.Q(tp_q[4]));
+defparam \tp_q[4] .mask = 16'hFF00;
+defparam \tp_q[4] .mode = "logic";
+defparam \tp_q[4] .modeMux = 1'b0;
+defparam \tp_q[4] .FeedbackMux = 1'b0;
+defparam \tp_q[4] .ShiftMux = 1'b0;
+defparam \tp_q[4] .BypassEn = 1'b0;
+defparam \tp_q[4] .CarryEnb = 1'b1;
+defparam \tp_q[4] .AsyncResetMux = 2'b00;
+defparam \tp_q[4] .SyncResetMux = 2'bxx;
+defparam \tp_q[4] .SyncLoadMux = 2'bxx;
+// Location: FF_X1_Y15_N16
+// alta_lcell_ff lcd_backlight_q(
+// Location: LCCOMB_X1_Y15_N16
+// alta_lcell_comb \lcd_backlight_q~feeder (
+alta_slice lcd_backlight_q(
+	.A(vcc),
+	.B(vcc),
+	.C(vcc),
+	.D(\MCU_D[7]~input_o ),
+	.Cin(),
+	.Qin(\lcd_backlight_q~q ),
+	.Clk(\MCU_IO_STBX~inputclkctrl_outclk__lcd_reset_q~0_combout_X1_Y15_SIG_SIG ),
+	.AsyncReset(AsyncReset_X1_Y15_GND),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\lcd_backlight_q~feeder_combout ),
+	.Cout(),
+	.Q(\lcd_backlight_q~q ));
+defparam lcd_backlight_q.mask = 16'hFF00;
+defparam lcd_backlight_q.mode = "logic";
+defparam lcd_backlight_q.modeMux = 1'b0;
+defparam lcd_backlight_q.FeedbackMux = 1'b0;
+defparam lcd_backlight_q.ShiftMux = 1'b0;
+defparam lcd_backlight_q.BypassEn = 1'b0;
+defparam lcd_backlight_q.CarryEnb = 1'b1;
+defparam lcd_backlight_q.AsyncResetMux = 2'b00;
+defparam lcd_backlight_q.SyncResetMux = 2'bxx;
+defparam lcd_backlight_q.SyncLoadMux = 2'bxx;
+// Location: FF_X1_Y15_N18
+// alta_lcell_ff \tp_q[0] (
+alta_slice \tp_q[0] (
+	.A(),
+	.B(),
+	.C(\MCU_D[0]~input_o ),
+	.D(),
+	.Cin(),
+	.Qin(tp_q[0]),
+	.Clk(\MCU_IO_STBX~inputclkctrl_outclk__tp_q[3]~0_combout_X1_Y15_SIG_SIG ),
+	.AsyncReset(AsyncReset_X1_Y15_GND),
+	.SyncReset(SyncReset_X1_Y15_GND),
+	.ShiftData(),
+	.SyncLoad(SyncLoad_X1_Y15_VCC),
+	.LutOut(),
+	.Cout(),
+	.Q(tp_q[0]));
+defparam \tp_q[0] .mask = 16'hFFFF;
+defparam \tp_q[0] .mode = "ripple";
+defparam \tp_q[0] .modeMux = 1'b1;
+defparam \tp_q[0] .FeedbackMux = 1'b0;
+defparam \tp_q[0] .ShiftMux = 1'b0;
+defparam \tp_q[0] .BypassEn = 1'b1;
+defparam \tp_q[0] .CarryEnb = 1'b1;
+defparam \tp_q[0] .AsyncResetMux = 2'b00;
+defparam \tp_q[0] .SyncResetMux = 2'b00;
+defparam \tp_q[0] .SyncLoadMux = 2'b01;
+// Location: FF_X1_Y15_N2
+// alta_lcell_ff lcd_reset_q(
+// Location: LCCOMB_X1_Y15_N2
+// alta_lcell_comb \lcd_reset_q~1 (
+alta_slice lcd_reset_q(
+	.A(vcc),
+	.B(vcc),
+	.C(\MCU_D[0]~input_o ),
+	.D(vcc),
+	.Cin(),
+	.Qin(\lcd_reset_q~q ),
+	.Clk(\MCU_IO_STBX~inputclkctrl_outclk__lcd_reset_q~0_combout_X1_Y15_SIG_SIG ),
+	.AsyncReset(AsyncReset_X1_Y15_GND),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\lcd_reset_q~1_combout ),
+	.Cout(),
+	.Q(\lcd_reset_q~q ));
+defparam lcd_reset_q.mask = 16'h0F0F;
+defparam lcd_reset_q.mode = "logic";
+defparam lcd_reset_q.modeMux = 1'b0;
+defparam lcd_reset_q.FeedbackMux = 1'b0;
+defparam lcd_reset_q.ShiftMux = 1'b0;
+defparam lcd_reset_q.BypassEn = 1'b0;
+defparam lcd_reset_q.CarryEnb = 1'b1;
+defparam lcd_reset_q.AsyncResetMux = 2'b00;
+defparam lcd_reset_q.SyncResetMux = 2'bxx;
+defparam lcd_reset_q.SyncLoadMux = 2'bxx;
+// Location: FF_X1_Y15_N20
+// alta_lcell_ff \tp_q[1] (
+alta_slice \tp_q[1] (
+	.A(),
+	.B(),
+	.C(\MCU_D[1]~input_o ),
+	.D(),
+	.Cin(),
+	.Qin(tp_q[1]),
+	.Clk(\MCU_IO_STBX~inputclkctrl_outclk__tp_q[3]~0_combout_X1_Y15_SIG_SIG ),
+	.AsyncReset(AsyncReset_X1_Y15_GND),
+	.SyncReset(SyncReset_X1_Y15_GND),
+	.ShiftData(),
+	.SyncLoad(SyncLoad_X1_Y15_VCC),
+	.LutOut(),
+	.Cout(),
+	.Q(tp_q[1]));
+defparam \tp_q[1] .mask = 16'hFFFF;
+defparam \tp_q[1] .mode = "ripple";
+defparam \tp_q[1] .modeMux = 1'b1;
+defparam \tp_q[1] .FeedbackMux = 1'b0;
+defparam \tp_q[1] .ShiftMux = 1'b0;
+defparam \tp_q[1] .BypassEn = 1'b1;
+defparam \tp_q[1] .CarryEnb = 1'b1;
+defparam \tp_q[1] .AsyncResetMux = 2'b00;
+defparam \tp_q[1] .SyncResetMux = 2'b00;
+defparam \tp_q[1] .SyncLoadMux = 2'b01;
+// Location: FF_X1_Y15_N22
+// alta_lcell_ff audio_reset_q(
+// Location: LCCOMB_X1_Y15_N22
+// alta_lcell_comb \audio_reset_q~0 (
+alta_slice audio_reset_q(
+	.A(vcc),
+	.B(vcc),
+	.C(\MCU_D[1]~input_o ),
+	.D(vcc),
+	.Cin(),
+	.Qin(\audio_reset_q~q ),
+	.Clk(\MCU_IO_STBX~inputclkctrl_outclk__lcd_reset_q~0_combout_X1_Y15_SIG_SIG ),
+	.AsyncReset(AsyncReset_X1_Y15_GND),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\audio_reset_q~0_combout ),
+	.Cout(),
+	.Q(\audio_reset_q~q ));
+defparam audio_reset_q.mask = 16'h0F0F;
+defparam audio_reset_q.mode = "logic";
+defparam audio_reset_q.modeMux = 1'b0;
+defparam audio_reset_q.FeedbackMux = 1'b0;
+defparam audio_reset_q.ShiftMux = 1'b0;
+defparam audio_reset_q.BypassEn = 1'b0;
+defparam audio_reset_q.CarryEnb = 1'b1;
+defparam audio_reset_q.AsyncResetMux = 2'b00;
+defparam audio_reset_q.SyncResetMux = 2'bxx;
+defparam audio_reset_q.SyncLoadMux = 2'bxx;
+// Location: FF_X1_Y15_N24
+// alta_lcell_ff \tp_q[7] (
+// Location: LCCOMB_X1_Y15_N24
+// alta_lcell_comb \tp_q[7]~feeder (
+alta_slice \tp_q[7] (
+	.A(vcc),
+	.B(vcc),
+	.C(vcc),
+	.D(\MCU_D[7]~input_o ),
+	.Cin(),
+	.Qin(tp_q[7]),
+	.Clk(\MCU_IO_STBX~inputclkctrl_outclk__tp_q[3]~0_combout_X1_Y15_SIG_SIG ),
+	.AsyncReset(AsyncReset_X1_Y15_GND),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\tp_q[7]~feeder_combout ),
+	.Cout(),
+	.Q(tp_q[7]));
+defparam \tp_q[7] .mask = 16'hFF00;
+defparam \tp_q[7] .mode = "logic";
+defparam \tp_q[7] .modeMux = 1'b0;
+defparam \tp_q[7] .FeedbackMux = 1'b0;
+defparam \tp_q[7] .ShiftMux = 1'b0;
+defparam \tp_q[7] .BypassEn = 1'b0;
+defparam \tp_q[7] .CarryEnb = 1'b1;
+defparam \tp_q[7] .AsyncResetMux = 2'b00;
+defparam \tp_q[7] .SyncResetMux = 2'bxx;
+defparam \tp_q[7] .SyncLoadMux = 2'bxx;
+// Location: FF_X1_Y15_N26
+// alta_lcell_ff \tp_q[2] (
+// Location: LCCOMB_X1_Y15_N26
+// alta_lcell_comb \tp_q[2]~feeder (
+alta_slice \tp_q[2] (
+	.A(vcc),
+	.B(vcc),
+	.C(vcc),
+	.D(\MCU_D[2]~input_o ),
+	.Cin(),
+	.Qin(tp_q[2]),
+	.Clk(\MCU_IO_STBX~inputclkctrl_outclk__tp_q[3]~0_combout_X1_Y15_SIG_SIG ),
+	.AsyncReset(AsyncReset_X1_Y15_GND),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\tp_q[2]~feeder_combout ),
+	.Cout(),
+	.Q(tp_q[2]));
+defparam \tp_q[2] .mask = 16'hFF00;
+defparam \tp_q[2] .mode = "logic";
+defparam \tp_q[2] .modeMux = 1'b0;
+defparam \tp_q[2] .FeedbackMux = 1'b0;
+defparam \tp_q[2] .ShiftMux = 1'b0;
+defparam \tp_q[2] .BypassEn = 1'b0;
+defparam \tp_q[2] .CarryEnb = 1'b1;
+defparam \tp_q[2] .AsyncResetMux = 2'b00;
+defparam \tp_q[2] .SyncResetMux = 2'bxx;
+defparam \tp_q[2] .SyncLoadMux = 2'bxx;
+// Location: FF_X1_Y15_N28
+// alta_lcell_ff \tp_q[5] (
+alta_slice \tp_q[5] (
+	.A(),
+	.B(),
+	.C(\MCU_D[5]~input_o ),
+	.D(),
+	.Cin(),
+	.Qin(tp_q[5]),
+	.Clk(\MCU_IO_STBX~inputclkctrl_outclk__tp_q[3]~0_combout_X1_Y15_SIG_SIG ),
+	.AsyncReset(AsyncReset_X1_Y15_GND),
+	.SyncReset(SyncReset_X1_Y15_GND),
+	.ShiftData(),
+	.SyncLoad(SyncLoad_X1_Y15_VCC),
+	.LutOut(),
+	.Cout(),
+	.Q(tp_q[5]));
+defparam \tp_q[5] .mask = 16'hFFFF;
+defparam \tp_q[5] .mode = "ripple";
+defparam \tp_q[5] .modeMux = 1'b1;
+defparam \tp_q[5] .FeedbackMux = 1'b0;
+defparam \tp_q[5] .ShiftMux = 1'b0;
+defparam \tp_q[5] .BypassEn = 1'b1;
+defparam \tp_q[5] .CarryEnb = 1'b1;
+defparam \tp_q[5] .AsyncResetMux = 2'b00;
+defparam \tp_q[5] .SyncResetMux = 2'b00;
+defparam \tp_q[5] .SyncLoadMux = 2'b01;
+// Location: FF_X1_Y15_N30
+// alta_lcell_ff ref_en_q(
+// Location: LCCOMB_X1_Y15_N30
+// alta_lcell_comb \ref_en_q~feeder (
+alta_slice ref_en_q(
+	.A(vcc),
+	.B(vcc),
+	.C(vcc),
+	.D(\MCU_D[6]~input_o ),
+	.Cin(),
+	.Qin(\ref_en_q~q ),
+	.Clk(\MCU_IO_STBX~inputclkctrl_outclk__lcd_reset_q~0_combout_X1_Y15_SIG_SIG ),
+	.AsyncReset(AsyncReset_X1_Y15_GND),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\ref_en_q~feeder_combout ),
+	.Cout(),
+	.Q(\ref_en_q~q ));
+defparam ref_en_q.mask = 16'hFF00;
+defparam ref_en_q.mode = "logic";
+defparam ref_en_q.modeMux = 1'b0;
+defparam ref_en_q.FeedbackMux = 1'b0;
+defparam ref_en_q.ShiftMux = 1'b0;
+defparam ref_en_q.BypassEn = 1'b0;
+defparam ref_en_q.CarryEnb = 1'b1;
+defparam ref_en_q.AsyncResetMux = 2'b00;
+defparam ref_en_q.SyncResetMux = 2'bxx;
+defparam ref_en_q.SyncLoadMux = 2'bxx;
+// Location: LCCOMB_X1_Y15_N4
+// alta_lcell_comb \tp_q[3]~0 (
+alta_slice \tp_q[3]~0 (
+	.A(vcc),
+	.B(vcc),
+	.C(\MCU_ADDR~input_o ),
+	.D(\MCU_DIR~input_o ),
+	.Cin(),
+	.Qin(),
+	.Clk(),
+	.AsyncReset(),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\tp_q[3]~0_combout ),
+	.Cout(),
+	.Q());
+defparam \tp_q[3]~0 .mask = 16'h000F;
+defparam \tp_q[3]~0 .mode = "logic";
+defparam \tp_q[3]~0 .modeMux = 1'b0;
+defparam \tp_q[3]~0 .FeedbackMux = 1'b0;
+defparam \tp_q[3]~0 .ShiftMux = 1'b0;
+defparam \tp_q[3]~0 .BypassEn = 1'b0;
+defparam \tp_q[3]~0 .CarryEnb = 1'b1;
+defparam \tp_q[3]~0 .AsyncResetMux = 2'bxx;
+defparam \tp_q[3]~0 .SyncResetMux = 2'bxx;
+defparam \tp_q[3]~0 .SyncLoadMux = 2'bxx;
+// Location: FF_X1_Y15_N6
+// alta_lcell_ff sysoff_q(
+// Location: LCCOMB_X1_Y15_N6
+// alta_lcell_comb \sysoff_q~feeder (
+alta_slice sysoff_q(
+	.A(vcc),
+	.B(vcc),
+	.C(vcc),
+	.D(\MCU_D[2]~input_o ),
+	.Cin(),
+	.Qin(\sysoff_q~q ),
+	.Clk(\MCU_IO_STBX~inputclkctrl_outclk__lcd_reset_q~0_combout_X1_Y15_SIG_SIG ),
+	.AsyncReset(AsyncReset_X1_Y15_GND),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\sysoff_q~feeder_combout ),
+	.Cout(),
+	.Q(\sysoff_q~q ));
+defparam sysoff_q.mask = 16'hFF00;
+defparam sysoff_q.mode = "logic";
+defparam sysoff_q.modeMux = 1'b0;
+defparam sysoff_q.FeedbackMux = 1'b0;
+defparam sysoff_q.ShiftMux = 1'b0;
+defparam sysoff_q.BypassEn = 1'b0;
+defparam sysoff_q.CarryEnb = 1'b1;
+defparam sysoff_q.AsyncResetMux = 2'b00;
+defparam sysoff_q.SyncResetMux = 2'bxx;
+defparam sysoff_q.SyncLoadMux = 2'bxx;
+// Location: FF_X1_Y15_N8
+// alta_lcell_ff \tp_q[6] (
+// Location: LCCOMB_X1_Y15_N8
+// alta_lcell_comb \tp_q[6]~feeder (
+alta_slice \tp_q[6] (
+	.A(vcc),
+	.B(vcc),
+	.C(vcc),
+	.D(\MCU_D[6]~input_o ),
+	.Cin(),
+	.Qin(tp_q[6]),
+	.Clk(\MCU_IO_STBX~inputclkctrl_outclk__tp_q[3]~0_combout_X1_Y15_SIG_SIG ),
+	.AsyncReset(AsyncReset_X1_Y15_GND),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\tp_q[6]~feeder_combout ),
+	.Cout(),
+	.Q(tp_q[6]));
+defparam \tp_q[6] .mask = 16'hFF00;
+defparam \tp_q[6] .mode = "logic";
+defparam \tp_q[6] .modeMux = 1'b0;
+defparam \tp_q[6] .FeedbackMux = 1'b0;
+defparam \tp_q[6] .ShiftMux = 1'b0;
+defparam \tp_q[6] .BypassEn = 1'b0;
+defparam \tp_q[6] .CarryEnb = 1'b1;
+defparam \tp_q[6] .AsyncResetMux = 2'b00;
+defparam \tp_q[6] .SyncResetMux = 2'bxx;
+defparam \tp_q[6] .SyncLoadMux = 2'bxx;
+
+// Location: CLKENCTRL_X1_Y15_N0
+alta_clkenctrl clken_ctrl_X1_Y15_N0(.ClkIn(\MCU_IO_STBX~inputclkctrl_outclk ), .ClkEn(\tp_q[3]~0_combout ), .ClkOut(\MCU_IO_STBX~inputclkctrl_outclk__tp_q[3]~0_combout_X1_Y15_SIG_SIG ));
+defparam clken_ctrl_X1_Y15_N0.ClkMux = 2'b10;
+defparam clken_ctrl_X1_Y15_N0.ClkEnMux = 2'b10;
+
+// Location: ASYNCCTRL_X1_Y15_N0
+alta_asyncctrl asyncreset_ctrl_X1_Y15_N0(.Din(), .Dout(AsyncReset_X1_Y15_GND));
+defparam asyncreset_ctrl_X1_Y15_N0.AsyncCtrlMux = 2'b00;
+
+// Location: CLKENCTRL_X1_Y15_N1
+alta_clkenctrl clken_ctrl_X1_Y15_N1(.ClkIn(\MCU_IO_STBX~inputclkctrl_outclk ), .ClkEn(\lcd_reset_q~0_combout ), .ClkOut(\MCU_IO_STBX~inputclkctrl_outclk__lcd_reset_q~0_combout_X1_Y15_SIG_SIG ));
+defparam clken_ctrl_X1_Y15_N1.ClkMux = 2'b10;
+defparam clken_ctrl_X1_Y15_N1.ClkEnMux = 2'b10;
+
+// Location: SYNCCTRL_X1_Y15_N0
+alta_syncctrl syncreset_ctrl_X1_Y15(.Din(), .Dout(SyncReset_X1_Y15_GND));
+defparam syncreset_ctrl_X1_Y15.SyncCtrlMux = 2'b00;
+
+// Location: SYNCCTRL_X1_Y15_N1
+alta_syncctrl syncload_ctrl_X1_Y15(.Din(), .Dout(SyncLoad_X1_Y15_VCC));
+defparam syncload_ctrl_X1_Y15.SyncCtrlMux = 2'b01;
+// Location: LCCOMB_X1_Y18_N14
+// alta_lcell_comb \mcu_data_out[7]~15 (
+alta_slice \mcu_data_out[7]~15 (
+	.A(\LCD_TE~input_o ),
+	.B(\MCU_DIR~input_o ),
+	.C(\MCU_IO_STBX~input_o ),
+	.D(\mcu_data_out[7]~14_combout ),
+	.Cin(),
+	.Qin(),
+	.Clk(),
+	.AsyncReset(),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\mcu_data_out[7]~15_combout ),
+	.Cout(),
+	.Q());
+defparam \mcu_data_out[7]~15 .mask = 16'hFB08;
+defparam \mcu_data_out[7]~15 .mode = "logic";
+defparam \mcu_data_out[7]~15 .modeMux = 1'b0;
+defparam \mcu_data_out[7]~15 .FeedbackMux = 1'b0;
+defparam \mcu_data_out[7]~15 .ShiftMux = 1'b0;
+defparam \mcu_data_out[7]~15 .BypassEn = 1'b0;
+defparam \mcu_data_out[7]~15 .CarryEnb = 1'b1;
+defparam \mcu_data_out[7]~15 .AsyncResetMux = 2'bxx;
+defparam \mcu_data_out[7]~15 .SyncResetMux = 2'bxx;
+defparam \mcu_data_out[7]~15 .SyncLoadMux = 2'bxx;
+// Location: LCCOMB_X1_Y18_N16
+// alta_lcell_comb \mcu_data_out[6]~13 (
+alta_slice \mcu_data_out[6]~13 (
+	.A(\SW_ROT_B~input_o ),
+	.B(\MCU_IO_STBX~input_o ),
+	.C(\mcu_data_out[6]~12_combout ),
+	.D(\MCU_DIR~input_o ),
+	.Cin(),
+	.Qin(),
+	.Clk(),
+	.AsyncReset(),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\mcu_data_out[6]~13_combout ),
+	.Cout(),
+	.Q());
+defparam \mcu_data_out[6]~13 .mask = 16'hD1F0;
+defparam \mcu_data_out[6]~13 .mode = "logic";
+defparam \mcu_data_out[6]~13 .modeMux = 1'b0;
+defparam \mcu_data_out[6]~13 .FeedbackMux = 1'b0;
+defparam \mcu_data_out[6]~13 .ShiftMux = 1'b0;
+defparam \mcu_data_out[6]~13 .BypassEn = 1'b0;
+defparam \mcu_data_out[6]~13 .CarryEnb = 1'b1;
+defparam \mcu_data_out[6]~13 .AsyncResetMux = 2'bxx;
+defparam \mcu_data_out[6]~13 .SyncResetMux = 2'bxx;
+defparam \mcu_data_out[6]~13 .SyncLoadMux = 2'bxx;
+// Location: LCCOMB_X1_Y18_N28
+// alta_lcell_comb \mcu_data_out[1]~3 (
+alta_slice \mcu_data_out[1]~3 (
+	.A(\SW_L~input_o ),
+	.B(\MCU_DIR~input_o ),
+	.C(\MCU_IO_STBX~input_o ),
+	.D(\mcu_data_out[1]~2_combout ),
+	.Cin(),
+	.Qin(),
+	.Clk(),
+	.AsyncReset(),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\mcu_data_out[1]~3_combout ),
+	.Cout(),
+	.Q());
+defparam \mcu_data_out[1]~3 .mask = 16'hF704;
+defparam \mcu_data_out[1]~3 .mode = "logic";
+defparam \mcu_data_out[1]~3 .modeMux = 1'b0;
+defparam \mcu_data_out[1]~3 .FeedbackMux = 1'b0;
+defparam \mcu_data_out[1]~3 .ShiftMux = 1'b0;
+defparam \mcu_data_out[1]~3 .BypassEn = 1'b0;
+defparam \mcu_data_out[1]~3 .CarryEnb = 1'b1;
+defparam \mcu_data_out[1]~3 .AsyncResetMux = 2'bxx;
+defparam \mcu_data_out[1]~3 .SyncResetMux = 2'bxx;
+defparam \mcu_data_out[1]~3 .SyncLoadMux = 2'bxx;
+// Location: LCCOMB_X1_Y18_N30
+// alta_lcell_comb \mcu_data_out[0]~1 (
+alta_slice \mcu_data_out[0]~1 (
+	.A(\SW_R~input_o ),
+	.B(\MCU_IO_STBX~input_o ),
+	.C(\mcu_data_out[0]~0_combout ),
+	.D(\MCU_DIR~input_o ),
+	.Cin(),
+	.Qin(),
+	.Clk(),
+	.AsyncReset(),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\mcu_data_out[0]~1_combout ),
+	.Cout(),
+	.Q());
+defparam \mcu_data_out[0]~1 .mask = 16'hD1F0;
+defparam \mcu_data_out[0]~1 .mode = "logic";
+defparam \mcu_data_out[0]~1 .modeMux = 1'b0;
+defparam \mcu_data_out[0]~1 .FeedbackMux = 1'b0;
+defparam \mcu_data_out[0]~1 .ShiftMux = 1'b0;
+defparam \mcu_data_out[0]~1 .BypassEn = 1'b0;
+defparam \mcu_data_out[0]~1 .CarryEnb = 1'b1;
+defparam \mcu_data_out[0]~1 .AsyncResetMux = 2'bxx;
+defparam \mcu_data_out[0]~1 .SyncResetMux = 2'bxx;
+defparam \mcu_data_out[0]~1 .SyncLoadMux = 2'bxx;
+// Location: FF_X1_Y19_N30
+// alta_lcell_ff \lcd_data_in_q[0] (
+// Location: LCCOMB_X1_Y19_N30
+// alta_lcell_comb \mcu_data_out[0]~0 (
+alta_slice \lcd_data_in_q[0] (
+	.A(\LCD_DB[8]~input_o ),
+	.B(vcc),
+	.C(\LCD_DB[0]~input_o ),
+	.D(\MCU_LCD_RDX~input_o ),
+	.Cin(),
+	.Qin(lcd_data_in_q[0]),
+	.Clk(\MCU_LCD_RDX~inputclkctrl_outclk_X1_Y19_SIG_VCC ),
+	.AsyncReset(AsyncReset_X1_Y19_GND),
+	.SyncReset(SyncReset_X1_Y19_GND),
+	.ShiftData(),
+	.SyncLoad(SyncLoad_X1_Y19_VCC),
+	.LutOut(\mcu_data_out[0]~0_combout ),
+	.Cout(),
+	.Q(lcd_data_in_q[0]));
+defparam \lcd_data_in_q[0] .mask = 16'hF0AA;
+defparam \lcd_data_in_q[0] .mode = "logic";
+defparam \lcd_data_in_q[0] .modeMux = 1'b0;
+defparam \lcd_data_in_q[0] .FeedbackMux = 1'b1;
+defparam \lcd_data_in_q[0] .ShiftMux = 1'b0;
+defparam \lcd_data_in_q[0] .BypassEn = 1'b1;
+defparam \lcd_data_in_q[0] .CarryEnb = 1'b1;
+defparam \lcd_data_in_q[0] .AsyncResetMux = 2'b00;
+defparam \lcd_data_in_q[0] .SyncResetMux = 2'b00;
+defparam \lcd_data_in_q[0] .SyncLoadMux = 2'b01;
+// Location: FF_X1_Y19_N4
+// alta_lcell_ff \lcd_data_in_q[6] (
+// Location: LCCOMB_X1_Y19_N4
+// alta_lcell_comb \mcu_data_out[6]~12 (
+alta_slice \lcd_data_in_q[6] (
+	.A(\LCD_DB[14]~input_o ),
+	.B(vcc),
+	.C(\LCD_DB[6]~input_o ),
+	.D(\MCU_LCD_RDX~input_o ),
+	.Cin(),
+	.Qin(lcd_data_in_q[6]),
+	.Clk(\MCU_LCD_RDX~inputclkctrl_outclk_X1_Y19_SIG_VCC ),
+	.AsyncReset(AsyncReset_X1_Y19_GND),
+	.SyncReset(SyncReset_X1_Y19_GND),
+	.ShiftData(),
+	.SyncLoad(SyncLoad_X1_Y19_VCC),
+	.LutOut(\mcu_data_out[6]~12_combout ),
+	.Cout(),
+	.Q(lcd_data_in_q[6]));
+defparam \lcd_data_in_q[6] .mask = 16'hF0AA;
+defparam \lcd_data_in_q[6] .mode = "logic";
+defparam \lcd_data_in_q[6] .modeMux = 1'b0;
+defparam \lcd_data_in_q[6] .FeedbackMux = 1'b1;
+defparam \lcd_data_in_q[6] .ShiftMux = 1'b0;
+defparam \lcd_data_in_q[6] .BypassEn = 1'b1;
+defparam \lcd_data_in_q[6] .CarryEnb = 1'b1;
+defparam \lcd_data_in_q[6] .AsyncResetMux = 2'b00;
+defparam \lcd_data_in_q[6] .SyncResetMux = 2'b00;
+defparam \lcd_data_in_q[6] .SyncLoadMux = 2'b01;
+
+// Location: CLKENCTRL_X1_Y19_N0
+alta_clkenctrl clken_ctrl_X1_Y19_N0(.ClkIn(\MCU_LCD_RDX~inputclkctrl_outclk ), .ClkEn(), .ClkOut(\MCU_LCD_RDX~inputclkctrl_outclk_X1_Y19_SIG_VCC ));
+defparam clken_ctrl_X1_Y19_N0.ClkMux = 2'b10;
+defparam clken_ctrl_X1_Y19_N0.ClkEnMux = 2'b01;
+
+// Location: ASYNCCTRL_X1_Y19_N0
+alta_asyncctrl asyncreset_ctrl_X1_Y19_N0(.Din(), .Dout(AsyncReset_X1_Y19_GND));
+defparam asyncreset_ctrl_X1_Y19_N0.AsyncCtrlMux = 2'b00;
+
+// Location: SYNCCTRL_X1_Y19_N0
+alta_syncctrl syncreset_ctrl_X1_Y19(.Din(), .Dout(SyncReset_X1_Y19_GND));
+defparam syncreset_ctrl_X1_Y19.SyncCtrlMux = 2'b00;
+
+// Location: SYNCCTRL_X1_Y19_N1
+alta_syncctrl syncload_ctrl_X1_Y19(.Din(), .Dout(SyncLoad_X1_Y19_VCC));
+defparam syncload_ctrl_X1_Y19.SyncCtrlMux = 2'b01;
+// Location: FF_X1_Y20_N0
+// alta_lcell_ff \lcd_data_out_q[1] (
+// Location: LCCOMB_X1_Y20_N0
+// alta_lcell_comb \lcd_data_out_q[1]~feeder (
+alta_slice \lcd_data_out_q[1] (
+	.A(vcc),
+	.B(vcc),
+	.C(vcc),
+	.D(\MCU_D[1]~input_o ),
+	.Cin(),
+	.Qin(lcd_data_out_q[1]),
+	.Clk(\MCU_LCD_WRX~inputclkctrl_outclk_X1_Y20_INV_VCC ),
+	.AsyncReset(AsyncReset_X1_Y20_GND),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\lcd_data_out_q[1]~feeder_combout ),
+	.Cout(),
+	.Q(lcd_data_out_q[1]));
+defparam \lcd_data_out_q[1] .mask = 16'hFF00;
+defparam \lcd_data_out_q[1] .mode = "logic";
+defparam \lcd_data_out_q[1] .modeMux = 1'b0;
+defparam \lcd_data_out_q[1] .FeedbackMux = 1'b0;
+defparam \lcd_data_out_q[1] .ShiftMux = 1'b0;
+defparam \lcd_data_out_q[1] .BypassEn = 1'b0;
+defparam \lcd_data_out_q[1] .CarryEnb = 1'b1;
+defparam \lcd_data_out_q[1] .AsyncResetMux = 2'b00;
+defparam \lcd_data_out_q[1] .SyncResetMux = 2'bxx;
+defparam \lcd_data_out_q[1] .SyncLoadMux = 2'bxx;
+// Location: FF_X1_Y20_N10
+// alta_lcell_ff \lcd_data_out_q[2] (
+// Location: LCCOMB_X1_Y20_N10
+// alta_lcell_comb \lcd_data_out_q[2]~feeder (
+alta_slice \lcd_data_out_q[2] (
+	.A(vcc),
+	.B(vcc),
+	.C(vcc),
+	.D(\MCU_D[2]~input_o ),
+	.Cin(),
+	.Qin(lcd_data_out_q[2]),
+	.Clk(\MCU_LCD_WRX~inputclkctrl_outclk_X1_Y20_INV_VCC ),
+	.AsyncReset(AsyncReset_X1_Y20_GND),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\lcd_data_out_q[2]~feeder_combout ),
+	.Cout(),
+	.Q(lcd_data_out_q[2]));
+defparam \lcd_data_out_q[2] .mask = 16'hFF00;
+defparam \lcd_data_out_q[2] .mode = "logic";
+defparam \lcd_data_out_q[2] .modeMux = 1'b0;
+defparam \lcd_data_out_q[2] .FeedbackMux = 1'b0;
+defparam \lcd_data_out_q[2] .ShiftMux = 1'b0;
+defparam \lcd_data_out_q[2] .BypassEn = 1'b0;
+defparam \lcd_data_out_q[2] .CarryEnb = 1'b1;
+defparam \lcd_data_out_q[2] .AsyncResetMux = 2'b00;
+defparam \lcd_data_out_q[2] .SyncResetMux = 2'bxx;
+defparam \lcd_data_out_q[2] .SyncLoadMux = 2'bxx;
+// Location: FF_X1_Y20_N12
+// alta_lcell_ff \lcd_data_out_q[6] (
+alta_slice \lcd_data_out_q[6] (
+	.A(),
+	.B(),
+	.C(\MCU_D[6]~input_o ),
+	.D(),
+	.Cin(),
+	.Qin(lcd_data_out_q[6]),
+	.Clk(\MCU_LCD_WRX~inputclkctrl_outclk_X1_Y20_INV_VCC ),
+	.AsyncReset(AsyncReset_X1_Y20_GND),
+	.SyncReset(SyncReset_X1_Y20_GND),
+	.ShiftData(),
+	.SyncLoad(SyncLoad_X1_Y20_VCC),
+	.LutOut(),
+	.Cout(),
+	.Q(lcd_data_out_q[6]));
+defparam \lcd_data_out_q[6] .mask = 16'hFFFF;
+defparam \lcd_data_out_q[6] .mode = "ripple";
+defparam \lcd_data_out_q[6] .modeMux = 1'b1;
+defparam \lcd_data_out_q[6] .FeedbackMux = 1'b0;
+defparam \lcd_data_out_q[6] .ShiftMux = 1'b0;
+defparam \lcd_data_out_q[6] .BypassEn = 1'b1;
+defparam \lcd_data_out_q[6] .CarryEnb = 1'b1;
+defparam \lcd_data_out_q[6] .AsyncResetMux = 2'b00;
+defparam \lcd_data_out_q[6] .SyncResetMux = 2'b00;
+defparam \lcd_data_out_q[6] .SyncLoadMux = 2'b01;
+// Location: FF_X1_Y20_N14
+// alta_lcell_ff \lcd_data_out_q[7] (
+// Location: LCCOMB_X1_Y20_N14
+// alta_lcell_comb \lcd_data_out_q[7]~feeder (
+alta_slice \lcd_data_out_q[7] (
+	.A(vcc),
+	.B(vcc),
+	.C(vcc),
+	.D(\MCU_D[7]~input_o ),
+	.Cin(),
+	.Qin(lcd_data_out_q[7]),
+	.Clk(\MCU_LCD_WRX~inputclkctrl_outclk_X1_Y20_INV_VCC ),
+	.AsyncReset(AsyncReset_X1_Y20_GND),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\lcd_data_out_q[7]~feeder_combout ),
+	.Cout(),
+	.Q(lcd_data_out_q[7]));
+defparam \lcd_data_out_q[7] .mask = 16'hFF00;
+defparam \lcd_data_out_q[7] .mode = "logic";
+defparam \lcd_data_out_q[7] .modeMux = 1'b0;
+defparam \lcd_data_out_q[7] .FeedbackMux = 1'b0;
+defparam \lcd_data_out_q[7] .ShiftMux = 1'b0;
+defparam \lcd_data_out_q[7] .BypassEn = 1'b0;
+defparam \lcd_data_out_q[7] .CarryEnb = 1'b1;
+defparam \lcd_data_out_q[7] .AsyncResetMux = 2'b00;
+defparam \lcd_data_out_q[7] .SyncResetMux = 2'bxx;
+defparam \lcd_data_out_q[7] .SyncLoadMux = 2'bxx;
+// Location: FF_X1_Y20_N30
+// alta_lcell_ff \lcd_data_out_q[0] (
+// Location: LCCOMB_X1_Y20_N30
+// alta_lcell_comb \lcd_data_out_q[0]~feeder (
+alta_slice \lcd_data_out_q[0] (
+	.A(vcc),
+	.B(vcc),
+	.C(vcc),
+	.D(\MCU_D[0]~input_o ),
+	.Cin(),
+	.Qin(lcd_data_out_q[0]),
+	.Clk(\MCU_LCD_WRX~inputclkctrl_outclk_X1_Y20_INV_VCC ),
+	.AsyncReset(AsyncReset_X1_Y20_GND),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\lcd_data_out_q[0]~feeder_combout ),
+	.Cout(),
+	.Q(lcd_data_out_q[0]));
+defparam \lcd_data_out_q[0] .mask = 16'hFF00;
+defparam \lcd_data_out_q[0] .mode = "logic";
+defparam \lcd_data_out_q[0] .modeMux = 1'b0;
+defparam \lcd_data_out_q[0] .FeedbackMux = 1'b0;
+defparam \lcd_data_out_q[0] .ShiftMux = 1'b0;
+defparam \lcd_data_out_q[0] .BypassEn = 1'b0;
+defparam \lcd_data_out_q[0] .CarryEnb = 1'b1;
+defparam \lcd_data_out_q[0] .AsyncResetMux = 2'b00;
+defparam \lcd_data_out_q[0] .SyncResetMux = 2'bxx;
+defparam \lcd_data_out_q[0] .SyncLoadMux = 2'bxx;
+
+// Location: CLKENCTRL_X1_Y20_N0
+alta_clkenctrl clken_ctrl_X1_Y20_N0(.ClkIn(\MCU_LCD_WRX~inputclkctrl_outclk ), .ClkEn(), .ClkOut(\MCU_LCD_WRX~inputclkctrl_outclk_X1_Y20_INV_VCC ));
+defparam clken_ctrl_X1_Y20_N0.ClkMux = 2'b11;
+defparam clken_ctrl_X1_Y20_N0.ClkEnMux = 2'b01;
+
+// Location: ASYNCCTRL_X1_Y20_N0
+alta_asyncctrl asyncreset_ctrl_X1_Y20_N0(.Din(), .Dout(AsyncReset_X1_Y20_GND));
+defparam asyncreset_ctrl_X1_Y20_N0.AsyncCtrlMux = 2'b00;
+
+// Location: SYNCCTRL_X1_Y20_N0
+alta_syncctrl syncreset_ctrl_X1_Y20(.Din(), .Dout(SyncReset_X1_Y20_GND));
+defparam syncreset_ctrl_X1_Y20.SyncCtrlMux = 2'b00;
+
+// Location: SYNCCTRL_X1_Y20_N1
+alta_syncctrl syncload_ctrl_X1_Y20(.Din(), .Dout(SyncLoad_X1_Y20_VCC));
+defparam syncload_ctrl_X1_Y20.SyncCtrlMux = 2'b01;
+// Location: FF_X1_Y21_N28
+// alta_lcell_ff \lcd_data_in_q[7] (
+// Location: LCCOMB_X1_Y21_N28
+// alta_lcell_comb \mcu_data_out[7]~14 (
+alta_slice \lcd_data_in_q[7] (
+	.A(\LCD_DB[15]~input_o ),
+	.B(\MCU_LCD_RDX~input_o ),
+	.C(\LCD_DB[7]~input_o ),
+	.D(vcc),
+	.Cin(),
+	.Qin(lcd_data_in_q[7]),
+	.Clk(\MCU_LCD_RDX~inputclkctrl_outclk_X1_Y21_SIG_VCC ),
+	.AsyncReset(AsyncReset_X1_Y21_GND),
+	.SyncReset(SyncReset_X1_Y21_GND),
+	.ShiftData(),
+	.SyncLoad(SyncLoad_X1_Y21_VCC),
+	.LutOut(\mcu_data_out[7]~14_combout ),
+	.Cout(),
+	.Q(lcd_data_in_q[7]));
+defparam \lcd_data_in_q[7] .mask = 16'hE2E2;
+defparam \lcd_data_in_q[7] .mode = "logic";
+defparam \lcd_data_in_q[7] .modeMux = 1'b0;
+defparam \lcd_data_in_q[7] .FeedbackMux = 1'b1;
+defparam \lcd_data_in_q[7] .ShiftMux = 1'b0;
+defparam \lcd_data_in_q[7] .BypassEn = 1'b1;
+defparam \lcd_data_in_q[7] .CarryEnb = 1'b1;
+defparam \lcd_data_in_q[7] .AsyncResetMux = 2'b00;
+defparam \lcd_data_in_q[7] .SyncResetMux = 2'b00;
+defparam \lcd_data_in_q[7] .SyncLoadMux = 2'b01;
+// Location: FF_X1_Y21_N4
+// alta_lcell_ff \lcd_data_in_q[1] (
+// Location: LCCOMB_X1_Y21_N4
+// alta_lcell_comb \mcu_data_out[1]~2 (
+alta_slice \lcd_data_in_q[1] (
+	.A(\LCD_DB[9]~input_o ),
+	.B(\MCU_LCD_RDX~input_o ),
+	.C(\LCD_DB[1]~input_o ),
+	.D(vcc),
+	.Cin(),
+	.Qin(lcd_data_in_q[1]),
+	.Clk(\MCU_LCD_RDX~inputclkctrl_outclk_X1_Y21_SIG_VCC ),
+	.AsyncReset(AsyncReset_X1_Y21_GND),
+	.SyncReset(SyncReset_X1_Y21_GND),
+	.ShiftData(),
+	.SyncLoad(SyncLoad_X1_Y21_VCC),
+	.LutOut(\mcu_data_out[1]~2_combout ),
+	.Cout(),
+	.Q(lcd_data_in_q[1]));
+defparam \lcd_data_in_q[1] .mask = 16'hE2E2;
+defparam \lcd_data_in_q[1] .mode = "logic";
+defparam \lcd_data_in_q[1] .modeMux = 1'b0;
+defparam \lcd_data_in_q[1] .FeedbackMux = 1'b1;
+defparam \lcd_data_in_q[1] .ShiftMux = 1'b0;
+defparam \lcd_data_in_q[1] .BypassEn = 1'b1;
+defparam \lcd_data_in_q[1] .CarryEnb = 1'b1;
+defparam \lcd_data_in_q[1] .AsyncResetMux = 2'b00;
+defparam \lcd_data_in_q[1] .SyncResetMux = 2'b00;
+defparam \lcd_data_in_q[1] .SyncLoadMux = 2'b01;
+
+// Location: CLKENCTRL_X1_Y21_N0
+alta_clkenctrl clken_ctrl_X1_Y21_N0(.ClkIn(\MCU_LCD_RDX~inputclkctrl_outclk ), .ClkEn(), .ClkOut(\MCU_LCD_RDX~inputclkctrl_outclk_X1_Y21_SIG_VCC ));
+defparam clken_ctrl_X1_Y21_N0.ClkMux = 2'b10;
+defparam clken_ctrl_X1_Y21_N0.ClkEnMux = 2'b01;
+
+// Location: ASYNCCTRL_X1_Y21_N0
+alta_asyncctrl asyncreset_ctrl_X1_Y21_N0(.Din(), .Dout(AsyncReset_X1_Y21_GND));
+defparam asyncreset_ctrl_X1_Y21_N0.AsyncCtrlMux = 2'b00;
+
+// Location: SYNCCTRL_X1_Y21_N0
+alta_syncctrl syncreset_ctrl_X1_Y21(.Din(), .Dout(SyncReset_X1_Y21_GND));
+defparam syncreset_ctrl_X1_Y21.SyncCtrlMux = 2'b00;
+
+// Location: SYNCCTRL_X1_Y21_N1
+alta_syncctrl syncload_ctrl_X1_Y21(.Din(), .Dout(SyncLoad_X1_Y21_VCC));
+defparam syncload_ctrl_X1_Y21.SyncCtrlMux = 2'b01;
+// Location: LCCOMB_X1_Y23_N12
+// alta_lcell_comb \mcu_data_out[3]~7 (
+alta_slice \mcu_data_out[3]~7 (
+	.A(\SW_U~input_o ),
+	.B(\MCU_IO_STBX~input_o ),
+	.C(\MCU_DIR~input_o ),
+	.D(\mcu_data_out[3]~6_combout ),
+	.Cin(),
+	.Qin(),
+	.Clk(),
+	.AsyncReset(),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\mcu_data_out[3]~7_combout ),
+	.Cout(),
+	.Q());
+defparam \mcu_data_out[3]~7 .mask = 16'hDF10;
+defparam \mcu_data_out[3]~7 .mode = "logic";
+defparam \mcu_data_out[3]~7 .modeMux = 1'b0;
+defparam \mcu_data_out[3]~7 .FeedbackMux = 1'b0;
+defparam \mcu_data_out[3]~7 .ShiftMux = 1'b0;
+defparam \mcu_data_out[3]~7 .BypassEn = 1'b0;
+defparam \mcu_data_out[3]~7 .CarryEnb = 1'b1;
+defparam \mcu_data_out[3]~7 .AsyncResetMux = 2'bxx;
+defparam \mcu_data_out[3]~7 .SyncResetMux = 2'bxx;
+defparam \mcu_data_out[3]~7 .SyncLoadMux = 2'bxx;
+// Location: LCCOMB_X1_Y23_N14
+// alta_lcell_comb \mcu_data_out[4]~9 (
+alta_slice \mcu_data_out[4]~9 (
+	.A(\MCU_DIR~input_o ),
+	.B(\SW_SEL~input_o ),
+	.C(\MCU_IO_STBX~input_o ),
+	.D(\mcu_data_out[4]~8_combout ),
+	.Cin(),
+	.Qin(),
+	.Clk(),
+	.AsyncReset(),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\mcu_data_out[4]~9_combout ),
+	.Cout(),
+	.Q());
+defparam \mcu_data_out[4]~9 .mask = 16'hF702;
+defparam \mcu_data_out[4]~9 .mode = "logic";
+defparam \mcu_data_out[4]~9 .modeMux = 1'b0;
+defparam \mcu_data_out[4]~9 .FeedbackMux = 1'b0;
+defparam \mcu_data_out[4]~9 .ShiftMux = 1'b0;
+defparam \mcu_data_out[4]~9 .BypassEn = 1'b0;
+defparam \mcu_data_out[4]~9 .CarryEnb = 1'b1;
+defparam \mcu_data_out[4]~9 .AsyncResetMux = 2'bxx;
+defparam \mcu_data_out[4]~9 .SyncResetMux = 2'bxx;
+defparam \mcu_data_out[4]~9 .SyncLoadMux = 2'bxx;
+// Location: LCCOMB_X1_Y23_N16
+// alta_lcell_comb \mcu_data_out[2]~5 (
+alta_slice \mcu_data_out[2]~5 (
+	.A(\SW_D~input_o ),
+	.B(\MCU_IO_STBX~input_o ),
+	.C(\mcu_data_out[2]~4_combout ),
+	.D(\MCU_DIR~input_o ),
+	.Cin(),
+	.Qin(),
+	.Clk(),
+	.AsyncReset(),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\mcu_data_out[2]~5_combout ),
+	.Cout(),
+	.Q());
+defparam \mcu_data_out[2]~5 .mask = 16'hD1F0;
+defparam \mcu_data_out[2]~5 .mode = "logic";
+defparam \mcu_data_out[2]~5 .modeMux = 1'b0;
+defparam \mcu_data_out[2]~5 .FeedbackMux = 1'b0;
+defparam \mcu_data_out[2]~5 .ShiftMux = 1'b0;
+defparam \mcu_data_out[2]~5 .BypassEn = 1'b0;
+defparam \mcu_data_out[2]~5 .CarryEnb = 1'b1;
+defparam \mcu_data_out[2]~5 .AsyncResetMux = 2'bxx;
+defparam \mcu_data_out[2]~5 .SyncResetMux = 2'bxx;
+defparam \mcu_data_out[2]~5 .SyncLoadMux = 2'bxx;
+// Location: LCCOMB_X1_Y23_N30
+// alta_lcell_comb \mcu_data_out[5]~11 (
+alta_slice \mcu_data_out[5]~11 (
+	.A(\MCU_DIR~input_o ),
+	.B(\SW_ROT_A~input_o ),
+	.C(\MCU_IO_STBX~input_o ),
+	.D(\mcu_data_out[5]~10_combout ),
+	.Cin(),
+	.Qin(),
+	.Clk(),
+	.AsyncReset(),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\mcu_data_out[5]~11_combout ),
+	.Cout(),
+	.Q());
+defparam \mcu_data_out[5]~11 .mask = 16'hF702;
+defparam \mcu_data_out[5]~11 .mode = "logic";
+defparam \mcu_data_out[5]~11 .modeMux = 1'b0;
+defparam \mcu_data_out[5]~11 .FeedbackMux = 1'b0;
+defparam \mcu_data_out[5]~11 .ShiftMux = 1'b0;
+defparam \mcu_data_out[5]~11 .BypassEn = 1'b0;
+defparam \mcu_data_out[5]~11 .CarryEnb = 1'b1;
+defparam \mcu_data_out[5]~11 .AsyncResetMux = 2'bxx;
+defparam \mcu_data_out[5]~11 .SyncResetMux = 2'bxx;
+defparam \mcu_data_out[5]~11 .SyncLoadMux = 2'bxx;
+// Location: FF_X1_Y24_N30
+// alta_lcell_ff \lcd_data_in_q[2] (
+// Location: LCCOMB_X1_Y24_N30
+// alta_lcell_comb \mcu_data_out[2]~4 (
+alta_slice \lcd_data_in_q[2] (
+	.A(\LCD_DB[10]~input_o ),
+	.B(vcc),
+	.C(\LCD_DB[2]~input_o ),
+	.D(\MCU_LCD_RDX~input_o ),
+	.Cin(),
+	.Qin(lcd_data_in_q[2]),
+	.Clk(\MCU_LCD_RDX~inputclkctrl_outclk_X1_Y24_SIG_VCC ),
+	.AsyncReset(AsyncReset_X1_Y24_GND),
+	.SyncReset(SyncReset_X1_Y24_GND),
+	.ShiftData(),
+	.SyncLoad(SyncLoad_X1_Y24_VCC),
+	.LutOut(\mcu_data_out[2]~4_combout ),
+	.Cout(),
+	.Q(lcd_data_in_q[2]));
+defparam \lcd_data_in_q[2] .mask = 16'hF0AA;
+defparam \lcd_data_in_q[2] .mode = "logic";
+defparam \lcd_data_in_q[2] .modeMux = 1'b0;
+defparam \lcd_data_in_q[2] .FeedbackMux = 1'b1;
+defparam \lcd_data_in_q[2] .ShiftMux = 1'b0;
+defparam \lcd_data_in_q[2] .BypassEn = 1'b1;
+defparam \lcd_data_in_q[2] .CarryEnb = 1'b1;
+defparam \lcd_data_in_q[2] .AsyncResetMux = 2'b00;
+defparam \lcd_data_in_q[2] .SyncResetMux = 2'b00;
+defparam \lcd_data_in_q[2] .SyncLoadMux = 2'b01;
+
+// Location: CLKENCTRL_X1_Y24_N0
+alta_clkenctrl clken_ctrl_X1_Y24_N0(.ClkIn(\MCU_LCD_RDX~inputclkctrl_outclk ), .ClkEn(), .ClkOut(\MCU_LCD_RDX~inputclkctrl_outclk_X1_Y24_SIG_VCC ));
+defparam clken_ctrl_X1_Y24_N0.ClkMux = 2'b10;
+defparam clken_ctrl_X1_Y24_N0.ClkEnMux = 2'b01;
+
+// Location: ASYNCCTRL_X1_Y24_N0
+alta_asyncctrl asyncreset_ctrl_X1_Y24_N0(.Din(), .Dout(AsyncReset_X1_Y24_GND));
+defparam asyncreset_ctrl_X1_Y24_N0.AsyncCtrlMux = 2'b00;
+
+// Location: SYNCCTRL_X1_Y24_N0
+alta_syncctrl syncreset_ctrl_X1_Y24(.Din(), .Dout(SyncReset_X1_Y24_GND));
+defparam syncreset_ctrl_X1_Y24.SyncCtrlMux = 2'b00;
+
+// Location: SYNCCTRL_X1_Y24_N1
+alta_syncctrl syncload_ctrl_X1_Y24(.Din(), .Dout(SyncLoad_X1_Y24_VCC));
+defparam syncload_ctrl_X1_Y24.SyncCtrlMux = 2'b01;
+// Location: FF_X1_Y26_N10
+// alta_lcell_ff \lcd_data_in_q[4] (
+// Location: LCCOMB_X1_Y26_N10
+// alta_lcell_comb \mcu_data_out[4]~8 (
+alta_slice \lcd_data_in_q[4] (
+	.A(\MCU_LCD_RDX~input_o ),
+	.B(\LCD_DB[12]~input_o ),
+	.C(\LCD_DB[4]~input_o ),
+	.D(vcc),
+	.Cin(),
+	.Qin(lcd_data_in_q[4]),
+	.Clk(\MCU_LCD_RDX~inputclkctrl_outclk_X1_Y26_SIG_VCC ),
+	.AsyncReset(AsyncReset_X1_Y26_GND),
+	.SyncReset(SyncReset_X1_Y26_GND),
+	.ShiftData(),
+	.SyncLoad(SyncLoad_X1_Y26_VCC),
+	.LutOut(\mcu_data_out[4]~8_combout ),
+	.Cout(),
+	.Q(lcd_data_in_q[4]));
+defparam \lcd_data_in_q[4] .mask = 16'hE4E4;
+defparam \lcd_data_in_q[4] .mode = "logic";
+defparam \lcd_data_in_q[4] .modeMux = 1'b0;
+defparam \lcd_data_in_q[4] .FeedbackMux = 1'b1;
+defparam \lcd_data_in_q[4] .ShiftMux = 1'b0;
+defparam \lcd_data_in_q[4] .BypassEn = 1'b1;
+defparam \lcd_data_in_q[4] .CarryEnb = 1'b1;
+defparam \lcd_data_in_q[4] .AsyncResetMux = 2'b00;
+defparam \lcd_data_in_q[4] .SyncResetMux = 2'b00;
+defparam \lcd_data_in_q[4] .SyncLoadMux = 2'b01;
+// Location: FF_X1_Y26_N12
+// alta_lcell_ff \lcd_data_out_q[4] (
+// Location: LCCOMB_X1_Y26_N12
+// alta_lcell_comb \lcd_data_out_q[4]~feeder (
+alta_slice \lcd_data_out_q[4] (
+	.A(vcc),
+	.B(vcc),
+	.C(vcc),
+	.D(\MCU_D[4]~input_o ),
+	.Cin(),
+	.Qin(lcd_data_out_q[4]),
+	.Clk(\MCU_LCD_WRX~inputclkctrl_outclk_X1_Y26_INV_VCC ),
+	.AsyncReset(AsyncReset_X1_Y26_GND),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\lcd_data_out_q[4]~feeder_combout ),
+	.Cout(),
+	.Q(lcd_data_out_q[4]));
+defparam \lcd_data_out_q[4] .mask = 16'hFF00;
+defparam \lcd_data_out_q[4] .mode = "logic";
+defparam \lcd_data_out_q[4] .modeMux = 1'b0;
+defparam \lcd_data_out_q[4] .FeedbackMux = 1'b0;
+defparam \lcd_data_out_q[4] .ShiftMux = 1'b0;
+defparam \lcd_data_out_q[4] .BypassEn = 1'b0;
+defparam \lcd_data_out_q[4] .CarryEnb = 1'b1;
+defparam \lcd_data_out_q[4] .AsyncResetMux = 2'b00;
+defparam \lcd_data_out_q[4] .SyncResetMux = 2'bxx;
+defparam \lcd_data_out_q[4] .SyncLoadMux = 2'bxx;
+// Location: FF_X1_Y26_N14
+// alta_lcell_ff \lcd_data_out_q[3] (
+alta_slice \lcd_data_out_q[3] (
+	.A(),
+	.B(),
+	.C(\MCU_D[3]~input_o ),
+	.D(),
+	.Cin(),
+	.Qin(lcd_data_out_q[3]),
+	.Clk(\MCU_LCD_WRX~inputclkctrl_outclk_X1_Y26_INV_VCC ),
+	.AsyncReset(AsyncReset_X1_Y26_GND),
+	.SyncReset(SyncReset_X1_Y26_GND),
+	.ShiftData(),
+	.SyncLoad(SyncLoad_X1_Y26_VCC),
+	.LutOut(),
+	.Cout(),
+	.Q(lcd_data_out_q[3]));
+defparam \lcd_data_out_q[3] .mask = 16'hFFFF;
+defparam \lcd_data_out_q[3] .mode = "ripple";
+defparam \lcd_data_out_q[3] .modeMux = 1'b1;
+defparam \lcd_data_out_q[3] .FeedbackMux = 1'b0;
+defparam \lcd_data_out_q[3] .ShiftMux = 1'b0;
+defparam \lcd_data_out_q[3] .BypassEn = 1'b1;
+defparam \lcd_data_out_q[3] .CarryEnb = 1'b1;
+defparam \lcd_data_out_q[3] .AsyncResetMux = 2'b00;
+defparam \lcd_data_out_q[3] .SyncResetMux = 2'b00;
+defparam \lcd_data_out_q[3] .SyncLoadMux = 2'b01;
+// Location: FF_X1_Y26_N4
+// alta_lcell_ff \lcd_data_out_q[5] (
+alta_slice \lcd_data_out_q[5] (
+	.A(),
+	.B(),
+	.C(\MCU_D[5]~input_o ),
+	.D(),
+	.Cin(),
+	.Qin(lcd_data_out_q[5]),
+	.Clk(\MCU_LCD_WRX~inputclkctrl_outclk_X1_Y26_INV_VCC ),
+	.AsyncReset(AsyncReset_X1_Y26_GND),
+	.SyncReset(SyncReset_X1_Y26_GND),
+	.ShiftData(),
+	.SyncLoad(SyncLoad_X1_Y26_VCC),
+	.LutOut(),
+	.Cout(),
+	.Q(lcd_data_out_q[5]));
+defparam \lcd_data_out_q[5] .mask = 16'hFFFF;
+defparam \lcd_data_out_q[5] .mode = "ripple";
+defparam \lcd_data_out_q[5] .modeMux = 1'b1;
+defparam \lcd_data_out_q[5] .FeedbackMux = 1'b0;
+defparam \lcd_data_out_q[5] .ShiftMux = 1'b0;
+defparam \lcd_data_out_q[5] .BypassEn = 1'b1;
+defparam \lcd_data_out_q[5] .CarryEnb = 1'b1;
+defparam \lcd_data_out_q[5] .AsyncResetMux = 2'b00;
+defparam \lcd_data_out_q[5] .SyncResetMux = 2'b00;
+defparam \lcd_data_out_q[5] .SyncLoadMux = 2'b01;
+// Location: FF_X1_Y26_N6
+// alta_lcell_ff \lcd_data_in_q[3] (
+// Location: LCCOMB_X1_Y26_N6
+// alta_lcell_comb \mcu_data_out[3]~6 (
+alta_slice \lcd_data_in_q[3] (
+	.A(\MCU_LCD_RDX~input_o ),
+	.B(\LCD_DB[11]~input_o ),
+	.C(\LCD_DB[3]~input_o ),
+	.D(vcc),
+	.Cin(),
+	.Qin(lcd_data_in_q[3]),
+	.Clk(\MCU_LCD_RDX~inputclkctrl_outclk_X1_Y26_SIG_VCC ),
+	.AsyncReset(AsyncReset_X1_Y26_GND),
+	.SyncReset(SyncReset_X1_Y26_GND),
+	.ShiftData(),
+	.SyncLoad(SyncLoad_X1_Y26_VCC),
+	.LutOut(\mcu_data_out[3]~6_combout ),
+	.Cout(),
+	.Q(lcd_data_in_q[3]));
+defparam \lcd_data_in_q[3] .mask = 16'hE4E4;
+defparam \lcd_data_in_q[3] .mode = "logic";
+defparam \lcd_data_in_q[3] .modeMux = 1'b0;
+defparam \lcd_data_in_q[3] .FeedbackMux = 1'b1;
+defparam \lcd_data_in_q[3] .ShiftMux = 1'b0;
+defparam \lcd_data_in_q[3] .BypassEn = 1'b1;
+defparam \lcd_data_in_q[3] .CarryEnb = 1'b1;
+defparam \lcd_data_in_q[3] .AsyncResetMux = 2'b00;
+defparam \lcd_data_in_q[3] .SyncResetMux = 2'b00;
+defparam \lcd_data_in_q[3] .SyncLoadMux = 2'b01;
+// Location: FF_X1_Y26_N8
+// alta_lcell_ff \lcd_data_in_q[5] (
+// Location: LCCOMB_X1_Y26_N8
+// alta_lcell_comb \mcu_data_out[5]~10 (
+alta_slice \lcd_data_in_q[5] (
+	.A(\MCU_LCD_RDX~input_o ),
+	.B(vcc),
+	.C(\LCD_DB[5]~input_o ),
+	.D(\LCD_DB[13]~input_o ),
+	.Cin(),
+	.Qin(lcd_data_in_q[5]),
+	.Clk(\MCU_LCD_RDX~inputclkctrl_outclk_X1_Y26_SIG_VCC ),
+	.AsyncReset(AsyncReset_X1_Y26_GND),
+	.SyncReset(SyncReset_X1_Y26_GND),
+	.ShiftData(),
+	.SyncLoad(SyncLoad_X1_Y26_VCC),
+	.LutOut(\mcu_data_out[5]~10_combout ),
+	.Cout(),
+	.Q(lcd_data_in_q[5]));
+defparam \lcd_data_in_q[5] .mask = 16'hF5A0;
+defparam \lcd_data_in_q[5] .mode = "logic";
+defparam \lcd_data_in_q[5] .modeMux = 1'b0;
+defparam \lcd_data_in_q[5] .FeedbackMux = 1'b1;
+defparam \lcd_data_in_q[5] .ShiftMux = 1'b0;
+defparam \lcd_data_in_q[5] .BypassEn = 1'b1;
+defparam \lcd_data_in_q[5] .CarryEnb = 1'b1;
+defparam \lcd_data_in_q[5] .AsyncResetMux = 2'b00;
+defparam \lcd_data_in_q[5] .SyncResetMux = 2'b00;
+defparam \lcd_data_in_q[5] .SyncLoadMux = 2'b01;
+
+// Location: CLKENCTRL_X1_Y26_N0
+alta_clkenctrl clken_ctrl_X1_Y26_N0(.ClkIn(\MCU_LCD_RDX~inputclkctrl_outclk ), .ClkEn(), .ClkOut(\MCU_LCD_RDX~inputclkctrl_outclk_X1_Y26_SIG_VCC ));
+defparam clken_ctrl_X1_Y26_N0.ClkMux = 2'b10;
+defparam clken_ctrl_X1_Y26_N0.ClkEnMux = 2'b01;
+
+// Location: ASYNCCTRL_X1_Y26_N0
+alta_asyncctrl asyncreset_ctrl_X1_Y26_N0(.Din(), .Dout(AsyncReset_X1_Y26_GND));
+defparam asyncreset_ctrl_X1_Y26_N0.AsyncCtrlMux = 2'b00;
+
+// Location: CLKENCTRL_X1_Y26_N1
+alta_clkenctrl clken_ctrl_X1_Y26_N1(.ClkIn(\MCU_LCD_WRX~inputclkctrl_outclk ), .ClkEn(), .ClkOut(\MCU_LCD_WRX~inputclkctrl_outclk_X1_Y26_INV_VCC ));
+defparam clken_ctrl_X1_Y26_N1.ClkMux = 2'b11;
+defparam clken_ctrl_X1_Y26_N1.ClkEnMux = 2'b01;
+
+// Location: SYNCCTRL_X1_Y26_N0
+alta_syncctrl syncreset_ctrl_X1_Y26(.Din(), .Dout(SyncReset_X1_Y26_GND));
+defparam syncreset_ctrl_X1_Y26.SyncCtrlMux = 2'b00;
+
+// Location: SYNCCTRL_X1_Y26_N1
+alta_syncctrl syncload_ctrl_X1_Y26(.Din(), .Dout(SyncLoad_X1_Y26_VCC));
+defparam syncload_ctrl_X1_Y26.SyncCtrlMux = 2'b01;
+endmodule
diff --git a/hardware/portapack_h4m/CPLD/Supra/alta_db/place.tx b/hardware/portapack_h4m/CPLD/Supra/alta_db/place.tx
new file mode 100644
index 00000000..f308aa97
--- /dev/null
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diff --git a/hardware/portapack_h4m/CPLD/Supra/alta_db/route.tx b/hardware/portapack_h4m/CPLD/Supra/alta_db/route.tx
new file mode 100644
index 00000000..2502f33e
--- /dev/null
+++ b/hardware/portapack_h4m/CPLD/Supra/alta_db/route.tx
@@ -0,0 +1,8170 @@
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+%%%9;{:;}{((%$fL]RQJGfwV][!EZ{4}8	G_,;CCZCxgCbC_CwCw
+000=T3wT~ngg0|>B7u8P_>m@NBCFew3J74Z	% EEeEa.E\E	EfEf
+WWW>T<RTb&Z<Wo=5G\f/I=:Djx`;)<JR0VK5\Guu)u\ ucuLuwQ`w&NuL
+ttt^{R {DNlNtq+*L8!@F+y`;Myzp.#0n!XB<OHHpH5fHGH<HBHB
+)))@3KB3'm;|)^f?{lqPUfh57I"1KV_j%b!^^(88K8lR8s8C8^8^
+```T4SU4R=!t`%s*(2g\$se)&H!p60VT2nYzsdKK6KerKuK+KzKz
+:::ioSvoY}&v:cA~b!^aDA\.:*|^; /B7c-{|$%%;%(a%x%,%{%{
+CCC,Zw]Z~k_gC;|2rf&?A|P#w}<:T*zv.ho3c|00T0p]060g0303
+EEEdefNe^U	dE 6&?P*r,6[6RDX;T{Y!P+L<RoWWTW^-WdWZW<W<
+uuu&)Lj)[w5NuG$Xqvgd=$Ek"mRV{9C?a&_llqtt{tG"t/tltRtR
+HHH~pB;p4m<5HOARoYq+dAbdNXK>3t-R]k1;K^))3)zN)8);)K)K
+888AK^7K[<^C8(`v	.Gy `N]5,S[4fWk8G/!=%``4`;5`Y`!`S`S
+KKKg6z&6LszzKdP	lQ|[~Pa7#%S8oMV2q["&fc::o:	#:s:&:S:S
+%%%9;{:;}C{C%$fL]RQJGfwVg[wEZ{4}8	G_v;CCZCxgCbC_CwCw
+000=T3wT~n3<0|>B7u8P_>m@.BfFew3J74Z	N EEeEa.E\E	EfEf
+WWW>T<RTb&<MWo=5G\f/I=:D xL;)<JR0VK5 Guu)u\ ucu5uLuL
+ttt^{R {DNR tq+*L8!@F+y`fMBzp.#0n!X<~OHHpH5fHGH<HBHB
+)))@3KB3'mKN)^f?{lqPUfh5RI^1KV_j%b!C@(88K8lR8s8C8^8^
+```T4SU4R=ST`%s*(2g\$se)rHzp60VT2nY+edKK6KerKuK+KzKz
+:::ioSvoY}Su:cA~b!^aDA\.a*{^; /B7c-{,$%%;%(a%x%,%{%{
+CCC,Zw]Z~kwxC;|2rf&?A|P#]}3:T*zv.ho33|00T0p]060g0303
+EEEdefNe^UU	E 6&?P*r,6[6-D<;T{Y!P+L<&oWWTW^-WdWZW<W<
+uuu&)Lj)[wwLuG$Xqvgd=$Ek"mRV{9C?a&_RJqtt{tG"t/tltRtR
+HHH~pB;p4mmmHOARoYq+dAbdNXK>3t-R]k1KM^))3)zN)8);)K)K
+888AK^7K[<<"8(`v	.Gy `N]5,S[4fWk8G/SU%``4`;5`Y`!`S`S
+KKKg6z&6Lss1KdP	lQ|[~Pa7#%}8oMV2q["&&c::o:	#:s:&:S:S
+%%%9;{:;}CC:%$fL]RQJGfwVg[kEZ{4}8	G_w;CCZCxgCbC_CwCw
+000=T3wT~nn]0|>B7u8P_>m@.BUFew3J74Z	U EEeEa.E\E	EfEf
+WWW>T<RTb&&>Wo=5G\f/I=:D xw;)<JR0VK5`Guu)u\ ucu5uLuL
+ttt^{R {DNNZtq+*L8!@F+y`fMmzp.#0n!X<	OHHpH5fHGH<HBHB
+)))@3KB3'mmz)^f?{lqPUfh5RI<1KV_j%b!C7(88K8lR8s8C8^8^
+```T4SU4R=Q!`%s*(2g\$se)rHsp60VT2nY+rdKK6KerKuK+KzKz
+:::ioSvoY}fS:cA~b!^aDA\.a*C^; /B7c-,9$%%;%(a%x%,%{%{
+CCC,Zw]Z~k!kC;|2rf&?A|P#]}n:T*zv.hogi|00T0p]060g0303
+EEEdefNe^UCCE 6&?P*r,6[6-D&;T{Y!P+LZ^oWWTW^-WdWZW<W<
+uuu&)Lj)[w`	uG$Xqvgd=$Ek"mNV{9C?a&_Rlqtt{tG"t/tltRtR
+HHH~pB;p4my;HOARoYq+dAbdNXm>3t-R]k1KK^))3)zN)8);)K)K
+888AK^7K[<"R8(`v	.Gy `N]5,=[4fWk8G/S=%``4`;5`Y`!`S`S
+KKKg6z&6Ls!gKdP	lQ|[~Pa7#%}8oMV2q["Sfc::o:	#:s:&:S:S
+%%%9;{:;}C|~%$fL]RQJGfwVg[kEZ{4}8	Gwv;CCZCxgCbC_CwCw
+000=T3wT~n<p0|>B7u8P_>m@.BUFew3J74ZfN EEeEa.E\E	EfEf
+WWW>T<RTb&MZWo=5G\f/I=:D x`;)<JR0VK55Guu)u\ ucu5uLuL
+ttt^{R {DNHRtq+*L8!@F+y`fMyzp.#0n!X<BOHHpH5fHGH<HBHB
+)))@3KB3'mMm)^f?{lqPUfh5RI"1KV_j%b!C<(88K8lR8s8C8^8^
+```T4SU4R=tQ`%s*(2g\$se)rH!p60VT2nY+!dKK6KerKuK+KzKz
+:::ioSvoY}OO:cA~b!^aDA\.a*|^; /B7c-,i$%%;%(a%x%,%{%{
+CCC,Zw]Z~kv]C;|2rf&?A|P#]}<:T*zv.hogw|00T0p]060g0303
+EEEdefNe^UI.E 6&?P*r,6[6-DX;T{Y!P+LZ-oWWTW^-WdWZW<W<
+uuu&)Lj)[w	&uG$Xqvgd=$Ek"mJV{9C?a&_l^qtt{tG"t/tltRtR
+HHH~pB;p4m	:HOARoYq+dAbdNX|>3t-R]k1;C^))3)zN)8);)K)K
+888AK^7K[<-l8(`v	.Gy `N]5,Q[4fWk8G/!;%``4`;5`Y`!`S`S
+KKKg6z&6Ls&+KdP	lQ|[~Pa7#%f8oMV2q["S&c::o:	#:s:&:S:S
+%%%9;{:;}C:{%$fL]RQJGfwVg[!EZ{4}8	Gww;CCZCxgCbC_CwCw
+000=T3wT~nwn0|>B7u8P_>m@.BCFew3J74ZfU EEeEa.E\E	EfEf
+WWW>T<RTb&RXWo=5G\f/I=:D x`;)<JR0VKL`Guu)u\ ucu5uLuL
+ttt^{R {DN Htq+*L8!@F+y`fMyzp.#0n!XB	OHHpH5fHGH<HBHB
+)))@3KB3'mBB)^f?{lqPUfh5RI"1KV_j%b!^7(88K8lR8s8C8^8^
+```T4S54R!`%s*(2g\$se)zHsp6q38{|2nY++dKK6KerKuK+KzKz
+:::ioS#oYS:cA~b!^aDA\.{*C^;s	oKQ7c-,{$%%;%(a%x%,%{%{
+CCC,ZwgZ~kC;|2rf&?A|P#3}n:T[(kd8.hogn|00T0p]060g0303
+EEEdef.e^CE 6&?P*r,6[6<D&;TN7*HfP+LZXoWWTW^-WdWZW<W<
+uuu&)L )[	uG$Xqvgd=$EkRmNV{	4$\!a&_lHqtt{tG"t/tltRtR
+HHH~pBfp4;HOARoYq+dAbdKXm>3ysw0q]k1;B^))3)zN)8);)K)K
+888AK^RK[R8(`v	.Gy `N]S,=[4P{#pg8G/!5%``4`;5`Y`!`S`S
+KKKg6zr6LgKdP	lQ|[~Pa7S%}8o?d0`^q["&ic::o:	#:s:&:S:S
+%%%9;{a;}~%$fL]RQJGfwVw[kEZN=Mp&8	G_X;CCZCxgCbC_CwCw
+000=T3]T~p0|>B7u8P_>m@fBUFeg1X5*74Z	a EEeEa.E\E	EfEf
+WWW>T<-Tb<ZWo=5G\f/I=:DLxw;)Z'-7g0VKL5Guu)u\ ucu5uLuL
+ttt^{R"{DRRtq+*L8!@F+y`BMmzp]{ITqn!XBBOHHpH5fHGH<HBHB
+)))@3KN3'Km)^f?{lqPUfh5^I<1KFcH0G%b!^<(88K8lR8s8C8^8^
+```T4S54RSQ`%s*(2g\$se)zHsp6q38{|2nYz!dKK6KerKuK+KzKz
+:::ioS#oYSO:cA~b!^aDA\.{*C^;s	oKQ7c-{i$%%;%(a%x%,%{%{
+CCC,ZwgZ~w]C;|2rf&?A|P#3}n:T[(kd8.ho3w|00T0p]060g0303
+EEEdef.e^f.E 6&?P*r,6[6<DX;TN7*HfP+LZZoWWTW^-WdWZW<W<
+uuu&)L )[L&uG$Xqvgd=$EkRmJV{	4$\!a&_lRqtt{tG"t/tltRtR
+HHH~pBfp4B:HOARoYq+dAbdKX|>3ysw0q]k1;m^))3)zN)8);)K)K
+888AK^RK[^l8(`v	.Gy `N]S,Q[4P{#pg8G/!Q%``4`;5`Y`!`S`S
+KKKg6zr6Ls+KdP	lQ|[~Pa7S%f8o?d0`^q["&Oc::o:	#:s:&:S:S
+%%%9;{a;}C{%$fL]RQJGfwVw[!EZN=Mp&8	G_];CCZCxgCbC_CwCw
+000=T3]T~nn0|>B7u8P_>m@fBCFeg1X5*74Z	. EEeEa.E\E	EfEf
+WWW>T<-Tb&XWo=5G\f/I=:DLx`;)Z'-7g0VK5&Guu)u\ ucu5uLuL
+ttt^{R"{DNHtq+*L8!@F+y`BMyzp]{ITqn!X<:OHHpH5fHGH<HBHB
+)))@3KN3'mB)^f?{lqPUfh5^I"1KFcH0G%b!Cl(88K8lR8s8C8^8^
+```T4S54R=5`%s*(2g\$se)zH!p6q38{|2nYz+dKK6KerKuK+KzKz
+:::ioS#oY}i:cA~b!^aDA\.{*|^;s	oKQ7c-{{$%%;%(a%x%,%{%{
+CCC,ZwgZ~kXC;|2rf&?A|P#3}<:T[(kd8.ho3n|00T0p]060g0303
+EEEdef.e^UaE 6&?P*r,6[6<DX;TN7*HfP+L<XoWWTW^-WdWZW<W<
+uuu&)L )[`5uG$Xqvgd=$EkRmJV{	4$\!a&_RHqtt{tG"t/tltRtR
+HHH~pBfp4yBHOARoYq+dAbdKX|>3ysw0q]k1KB^))3)zN)8);)K)K
+888AK^RK["<8(`v	.Gy `N]=,=[4P{#pg8G/!!%``4`;5`Y`!`S`S
+KKKg6zr6L!!KdP	lQ|[~Pa7}%}8o?d0`^q["&Sc::o:	#:s:&:S:S
+%%%9;{a;}|i%$fL]RQJGfwVk[kEZN=Mp&8	G_k;CCZCxgCbC_CwCw
+000=T3]T~<w0|>B7u8P_>m@UBUFeg1X5*74Z	C EEeEa.E\E	EfEf
+WWW>T<-TbX-Wo=5G\f/I=:Dwxw;)Z'-7g0VK5	Guu)u\ ucu5uLuL
+ttt^{R"{DJ^tq+*L8!@F+y`mMmzp]{ITqn!X<;OHHpH5fHGH<HBHB
+)))@3KN3'|C)^f?{lqPUfh5<I<1KFcH0G%b!CR(88K8lR8s8C8^8^
+```T4S54RQ;`%s*(2g\$se)sHsp6q38{|2nY+gdKK6KerKuK+KzKz
+:::ioS#oYO&:cA~b!^aDA\.C*C^;s	oKQ7c-,~$%%;%(a%x%,%{%{
+CCC,ZwgZ~vwC;|2rf&?A|P#n}n:T[(kd8.hogp|00T0p]060g0303
+EEEdef.e^IUE 6&?P*r,6[6&D&;TN7*HfP+L<ZoWWTW^-WdWZW<W<
+uuu&)L )[	`uG$Xqvgd=$EkNmNV{	4$\!a&_RRqtt{tG"t/tltRtR
+HHH~pBfp4		HOARoYq+dAbdmXm>3ysw0q]k1Km^))3)zN)8);)K)K
+888AK^RK[-78(`v	.Gy `N]=,=[4P{#pg8G/SQ%``4`;5`Y`!`S`S
+KKKg6zr6L1rKdP	lQ|[~Pa7}%}8o?d0`^q["SOc::o:	#:s:&:S:S
+%%%9;{a;}i9%$fL]RQJGfwVk[kEZN=Mp&8	Gw];CCZCxgCbC_CwCw
+000=T3]T~ci0|>B7u8P_>m@UBCFeg1X5*74Z		 EEeEa.E\E	EfEf
+WWW>T<-TbM^Wo=5G\f/I=:Dwx`;)Z'-7g0VK5LGuu)u\ ucu5uLuL
+ttt^{R"{D ltq+*L8!@F+y`mMyzp]{ITqn!X<mOHHpH5fHGH<HBHB
+)))@3KN3'BK)^f?{lqPUfh5<I"1KFcH0G%b!C"(88K8lR8s8C8^8^
+```T4S54RU=`%s*(2g\$se)sH!p6q38{|2nY+1dKK6KerKuK+KzKz
+:::ioS#oYvf:cA~b!^aDA\.C*|^;s	oKQ7c-,:$%%;%(a%x%,%{%{
+CCC,ZwgZ~]vC;|2rf&?A|P#n}<:T[(kd8.hog]|00T0p]060g0303
+EEEdef.e^NNE 6&?P*r,6[6&DX;TN7*HfP+LZ>oWWTW^-WdWZW<W<
+uuu&)L )[j uG$Xqvgd=$EkNmJV{	4$\!a&_lZqtt{tG"t/tltRtR
+HHH~pBfp4;~HOARoYq+dAbdmX|>3ysw0q]k1;z^))3)zN)8);)K)K
+888AK^RK[7@8(`v	.Gy `N]=,Q[4P{#pg8G/S!%``4`;5`Y`!`S`S
+KKKg6zr6L&eKdP	lQ|[~Pa7}%f8o?d0`^q["SSc::o:	#:s:&:S:S
+%%%9;{a;}a,%$fL]RQJGfwVk[!EZN=Mp&8	Gwk;CCZCxgCbC_CwCw
+000=T3]T~]30|>B7u8P_>m@UBCFeg1X5*74ZfC EEeEa.E\E	EfEf
+WWW>T<-Tb-&Wo=5G\f/I=:Dwx`;)Z'-7g0VKL	Guu)u\ ucu5uLuL
+ttt^{R"{D"Jtq+*L8!@F+y`mMyzp]{ITqn!XB;OHHpH5fHGH<HBHB
+)))@3KN3'NM)^f?{lqPUfh5"I^1KFcH0G%b!CC(88K8lR8s8C8^8^
+```T4S54R5U`%s*(2g\$se)!Hzp6q38{|2nY+zdKK6KerKuK+KzKz
+:::ioS#oY##:cA~b!^aDA\.|*{^;s	oKQ7c-,C$%%;%(a%x%{%C?{i~(~%{
+CCC,ZwgZ~g,C;|2rf&?A|P#<}3:T[(kd8.hog<|00T0p]060g0303
+EEEdef.e^.%E 6&?P*r,6[6XD<;TN7*HfP+LZMoWWTW^-WdWZW<W<
+uuu&)L )[ \uG$Xqvgd=$EkJmRV{	4$\!a&_l qtt{tG"t/tltRtR
+HHH~pBfp4~<HOARoYq+dAbd|XK>3ysw0q]k1;N^))3)zN)8);)K)K
+888AK^RK[A^8(`v	.Gy `N]Q,S[4P{#pg8G/!T%``4`;5`Y`!`S`S
+KKKg6zr6LgsKdP	lQ|[~Pa7f%S8o?d0`^q["&uc::o:	#:s:&:S:S
+%%%9;{a;}9|%$fL]RQJGfwV![wEZN=Mp&8	G_x;CCZCxgCbC_CwCw
+000=T3]T~=c0|>B7u8P_>m@CBfFeg1X5*74Zf	 EEeEa.E\E	EfEf
+WWW>T<-Tb>RWo=5G\f/I=:D`xL;)Z'-7g0VKLLGuu)u\ ucu5uLuL
+ttt^{R"{D^"tq+*L8!@F+y`yMBzp]{ITqn!XBmOHHpH5fHGH<HBHB
+)))@3KN3'@@)^f?{lqPUfh5"I^1KFcH0G%b!^"(88K8lR8s8C8^8^
+```T4S54RT9`%s*(2g\$se)!Hzp6q38{|2nYz1dKK6KerKuK+KzKz
+:::ioS#oYi	:cA~b!^aDA\.|*{^;s	oKQ7c-{:$%%;%(a%x%{%C?|CC9:%{
+CCC,ZwgZ~X_C;|2rf&?A|P#<}n:T[(kd8.hogg|00T0p]060g0303
+EEEdef.e^%fE 6&?P*r,6[6XD&;TN7*HfP+LZ<oWWTW^-WdWZW<W<
+uuu&)L )[NwuG$Xqvgd=$EkJmNV{	4$\!a&_lNqtt{tG"t/tRtNsNJlZJtR
+HHH~pBfp4:yHOARoYq+dAbd|Xm>3ysw0q]k1;|^))3)zN)8)K)m:mzK;B)K
+888AK^RK[@-8(`v	.Gy `N]Q,=[4P{#pg8G/!t%``4`;5`Y`S`=Vt559`S
+KKKg6zr6Lf&KdP	lQ|[~Pa7f%}8o?d0`^q["&vc::o:	#:s:S:}.&vffu:S
+%%%9;{a;}~a%$fL]RQJGfwV![kEZN=Mp&8	G_g;CCZCxgCbCwCkKvwXg,Cw
+000=T3]T~i=0|>B7u8P_>m@CBUFeg1X5*74Z	d EEeEa.E\EfEU=IadNfEf
+WWW>T<-TbccWo=5G\f/I=:D`xw;)Z'-7g0VK5NGuu)u\ ucu5uLuL
+ttt^{R"{DZGtq+*L8!@F+y`yMmzp]{ITqn!X<5OHHpH5fHGH<HBHB
+)))@3KN3'z;)^f?{lqPUfh5"I<1KFcH0G%b!^C(88K8lR8s8C8^8^
+```T4S54R;S`%s*(2g\$se)!Hsp6q38{|2nYzzdKK6KerKuK+KzKz
+:::ioS#oY	}:cA~b!^aDA\.|*C^;s	oKQ7c-{C$%%;%(a%x%,%{%{
+CCC,ZwgZ~x!C;|2rf&?A|P#<}n:T[(kd8.ho3<|00T0p]060g0303
+EEEdef.e^aIE 6&?P*r,6[6XD&;TN7*HfP+L<MoWWTW^-WdWZW<W<
+uuu&)L )[\juG$Xqvgd=$EkJmNV{	4$\!a&_R qtt{tG"t/tltRtR
+HHH~pBfp45fHOARoYq+dAbd|X|>3ysw0q]k1;;^))3)zN)8);)K)K
+888AK^RK[lA8(`v	.Gy `N]Q,Q[4P{#pg8G/!S%``4`;5`Y`S`=Vt5;;T`S
+KKKg6zr6LefKdP	lQ|[~Pa7f%f8o?d0`^q["&}c::o:	#:s:S:}.ffSvO:S
+%%%9;{a;}((%$fL]RQJGfwV![!EZN=Mp&8	G_!;CCZCxgCbC_CwCw
+000=T3]T~3gg0|>B7u8P_>m@CBCFeg1X5*74Z	I EEeEa.E\EfEU=ICfNaEf
+WWW>T<-Tb<Z<Wo=5G\f/I=:D`x`;)Z'-7g0VK5jGuu)u\ ucuLuwQLLwL uL
+ttt^{R"{DRlNtq+*L8!@F+y`yMyzp]{ITqn!X<fOHHpH5fHGHBHmPm	f<BHB
+)))@3KN3'K;|)^f?{lqPUfh5"I"1KFcH0G%b!CA(88K8lR8s8C8^8^
+```T4S54RS!t`%s*(2g\$se)!H!p6q38{|2nY+fdKK6KerKuKzKsSsfs1Kz
+:::ioS#oYS&v:cA~b!^aDA\.|*|^;s	oKQ7c-,($%%;%(a%x%{%C?CCi{a%{
+CCC,ZwgZ~w_gC;|2rf&?A|P#<}<:T[(kd8.ho3g|00T0p]06030nbggcw<03
+EEEdef.e^f	dE 6&?P*r,6[6XDX;TN7*HfP+L<<oWWTW^-WdW<W&JMR<-W<
+uuu&)L )[L5NuG$Xqvgd=$EkJmJV{	4$\!a&_RNqtt{tG"t/tRtNsH R"GtR
+HHH~pBfp4B<5HOARoYq+dAbd|X|>3ysw0q]k1K|^))3)zN)8)K)m:MN|NM)K
+888AK^RK[^^C8(`v	.Gy `N]Q,Q[4P{#pg8G/St%``4`;5`Y`S`=V=TSQS`S
+KKKg6zr6LzzzKdP	lQ|[~Pa7f%f8o?d0`^q["Svc::o:	#:s:S:}.S&fui:S
+%%%9;{a;}{{C%$fL]RQJGfwVv[wEZN=Mp&8	G__;CCZCxgCbC_CwCw
+000=T3]T~33<0|>B7u8P_>m@IBfFeg1X5*74Z	f EEeEa.E\E	EfEf
+WWW>T<-Tb<<MWo=5G\f/I=:D	xL;)Z'-7g0VK5wGuu)u\ ucu5uLuL
+ttt^{R"{DRR tq+*L8!@F+y`	MBzp]{ITqn!X<yOHHpH5fHGH<HBHB
+)))@3KN3'KKN)^f?{lqPUfh5-I^1KFcH0G%b!C-(88K8lR8s8C8^8^
+```T4S54RSST`%s*(2g\$se)1Hzp6q38{|2nY+&dKK6KerKuK+KzKz
+:::ioS#oYSSu:cA~b!^aDA\.i*{^;s	oKQ7c-,a$%%;%(a%x%,%{%{
+CCC,ZwgZ~wwxC;|2rf&?A|P#c}3:T[(kd8.hog=|00T0p]060g0303
+EEEdef.e^fU	E 6&?P*r,6[6MD<;TN7*HfP+LZcoWWTW^-WdWZW<W<
+uuu&)L )[LwLuG$Xqvgd=$EkHmRV{	4$\!a&_lGqtt{tG"t/tltRtR
+HHH~pBfp4BmmHOARoYq+dAbdMXK>3ysw0q]k1K;^))3)zN)8);)K)K
+888AK^RK[^<"8(`v	.Gy `N]t,S[4P{#pg8G/SS%``4`;5`Y`!`S`S
+KKKg6zr6Lzs1KdP	lQ|[~Pa7O%S8o?d0`^q["S}c::o:	#:s:&:S:S
+%%%9;{a;}{C:%$fL]RQJGfwVv[wEZN=Mp&8	Gw!;CCZCxgCbC_CwCw
+000=T3]T~3n]0|>B7u8P_>m@IBfFeg1X5*74ZfI EEeEa.E\E	EfEf
+WWW>T<-Tb<&>Wo=5G\f/I=:D	xL;)Z'-7g0VKLjGuu)u\ ucu5uLuL
+ttt^{R"{DRNZtq+*L8!@F+y`	Mmzp]{ITqn!X<<OHHpH5fHGH<HBHB
+)))@3KN3'Kmz)^f?{lqPUfh5-I<1KFcH0G%b!C^(88K8lR8s8C8^8^
+```T4S54RSQ!`%s*(2g\$se)1Hsp6q38{|2nY+sdKK6KerKuK+KzKz
+:::ioS#oYSfS:cA~b!^aDA\.i*C^;s	oKQ7c-,|$%%;%(a%x%,%{%{
+CCC,ZwgZ~w!kC;|2rf&?A|P#c}n:T[(kd8.hogc|00T0p]060g0303
+EEEdef.e^fCCE 6&?P*r,6[6MD&;TN7*HfP+LZRoWWTW^-WdWZW<W<
+uuu&)L )[L`	uG$Xqvgd=$EkHmNV{	4$\!a&_l"qtt{tG"t/tltRtR
+HHH~pBfp4By;HOARoYq+dAbdMXm>3ysw0q]k1;@^))3)zN)8);)K)K
+888AK^RK[^"R8(`v	.Gy `N]t,=[4P{#pg8G/!9%``4`;5`Y`!`S`S
+KKKg6zr6Lz!gKdP	lQ|[~Pa7O%}8o?d0`^q["&	c::o:	#:s:&:S:S
+%%%9;{a;}{|~%$fL]RQJGfwVv[kEZN=Mp&8	Gw_;CCZCxgCbC_CwCw
+000=T3]T~3<p0|>B7u8P_>m@IBUFeg1X5*74Zff EEeEa.E\E	EfEf
+WWW>T<-Tb<MZWo=5G\f/I=:D	xw;)Z'-7g0VKLwGuu)u\ ucu5uLuL
+ttt^{R"{DRHRtq+*L8!@F+y`	Mmzp]{ITqn!XByOHHpH5fHGH<HBHB
+)))@3KN3'KMm)^f?{lqPUfh5-I<1KFcH0G%b!^-(88K8lR8s8C8^8^
+```T4S54RStQ`%s*(2g\$se)1Hsp6q38{|2nYz&dKK6KerKuK+KzKz
+:::ioS#oYSOO:cA~b!^aDA\.i*|^;s	oKQ7c-,,$%%;%(a%x%{%C?|a(%{
+CCC,ZwgZ~wv]C;|2rf&?A|P#c}<:T[(kd8.hog3|00T0p]060g0303
+EEEdef.e^fI.E 6&?P*r,6[6MDX;TN7*HfP+LZ&oWWTW^-WdWZW<W<
+uuu&)L )[L	&uG$Xqvgd=$EkHmJV{	4$\!a&_lJqtt{tG"t/tltRtR
+HHH~pBfp4B	:HOARoYq+dAbdMX|>3ysw0q]k1;M^))3)zN)8);)K)K
+888AK^RK[^-l8(`v	.Gy `N]t,Q[4P{#pg8G/!U%``4`;5`Y`S`=VSS5`S
+KKKg6zr6Lz&+KdP	lQ|[~Pa7O%f8o?d0`^q["&#c::o:	#:s:S:}.f&&#}:S
+%%%9;{a;}{:{%$fL]RQJGfwVv[!EZN=Mp&8	G_,;CCZCxgCbC_CwCw
+000=T3]T~3wn0|>B7u8P_>m@IBCFeg1X5*74Z	% EEeEa.E\E	EfEf
+WWW>T<-Tb<RXWo=5G\f/I=:D	x`;)Z'-7g0VK5\Guu)u\ ucu5uLuL
+ttt^{R"{DR Htq+*L8!@F+y`	Myzp]{ITqn!XB<OHHpH5fHGHBHmP	y:B;HB
+)))@3KN3'KBB)^f?{lqPUfh5-I"1KFcH0G%b!^^(88K8lR8s8C8^8^
+```T4S54RSU5`%s*(2g\$se)1H!p6q38{|2nYzsdKK6KerKuK+KzKz
+:::ioS#oYSvi:cA~b!^aDA\.i*|^;s	oKQ7c-{|$%%;%(a%x%,%{%{
+CCC,ZwgZ~w]XC;|2rf&?A|P#c}<:T[(kd8.ho3c|00T0p]060g0303
+EEEdef.e^fNaE 6&?P*r,6[6MDX;TN7*HfP+L<RoWWTW^-WdW<W&JMXM<-W<
+uuu&)L )[L 5uG$Xqvgd=$Ek mRV{	4$\!a&_llqtt{tG"t/tltRtR
+HHH~pBfp4BfBHOARoYq+dAbdBXK>3ysw0q]k1;K^))3)zN)8);)K)K
+888AK^RK[^R<8(`v	.Gy `N]U,S[4P{#pg8G/!=%``4`;5`Y`!`S`S
+KKKg6zr6Lzr!KdP	lQ|[~Pa7v%S8o?d0`^q["&fc::o:	#:s:&:S:S
+%%%9;{a;}{ai%$fL]RQJGfwV][wEZN=Mp&8	G_v;CCZCxgCbC_CwCw
+000=T3]T~3]w0|>B7u8P_>m@NBfFeg1X5*74Z	N EEeEa.E\E	EfEf
+WWW>T<-Tb<--Wo=5G\f/I=:DjxL;)Z'-7g0VK5 Guu)u\ ucu5uLuL
+ttt^{R"{DR"^tq+*L8!@F+y`;MBzp]{ITqn!X<~OHHpH5fHGH<HBHB
+)))@3KN3'KNC)^f?{lqPUfh57I^1KFcH0G%b!C@(88K8lR8s8C8^8^
+```T4S54RS5;`%s*(2g\$se)&Hzp6q38{|2nY+edKK6KerKuK+KzKz
+:::ioS#oYSi&:cA~b!^aDA\.:*{^;s	oKQ7c-{,$%%;%(a%x%,%{%{
+CCC,ZwgZ~w,wC;|2rf&?A|P#w}3:T[(kd8.ho33|00T0p]060g0303
+EEEdef.e^fdUE 6&?P*r,6[6RD<;TN7*HfP+L<&oWWTW^-WdWZW<W<
+uuu&)L )[L&`uG$Xqvgd=$Ek mRV{	4$\!a&_RJqtt{tG"t/tltRtR
+HHH~pBfp4B~	HOARoYq+dAbdBXK>3ysw0q]k1KM^))3)zN)8);)K)K
+888AK^RK[^A78(`v	.Gy `N]U,S[4P{#pg8G/SU%``4`;5`Y`!`S`S
+KKKg6zr6LzgrKdP	lQ|[~Pa7v%}8o?d0`^q["&&c::o:	#:s:&:S:S
+%%%9;{a;}{99%$fL]RQJGfwV][kEZN=Mp&8	G_w;CCZCxgCbC_CwCw
+000=T3]T~3=i0|>B7u8P_>m@NBUFeg1X5*74Z	U EEeEa.E\E	EfEf
+WWW>T<-Tb<>^Wo=5G\f/I=:Djxw;)Z'-7g0VK5`Guu)u\ ucu5uLuL
+ttt^{R"{DRZltq+*L8!@F+y`;Mmzp]{ITqn!X<	OHHpH5fHGH<HBHB
+)))@3KN3'KCK)^f?{lqPUfh57I<1KFcH0G%b!C7(88K8lR8s8C8^8^
+```T4S54RS9=`%s*(2g\$se)&Hsp6q38{|2nY+rdKK6KerKuK+KzKz
+:::ioS#oYSuf:cA~b!^aDA\.:*C^;s	oKQ7c-,9$%%;%(a%x%,%{%{
+CCC,ZwgZ~wXvC;|2rf&?A|P#w}n:T[(kd8.hogi|00T0p]060g0303
+EEEdef.e^f%NE 6&?P*r,6[6RD&;TN7*HfP+LZ^oWWTW^-WdWZW<W<
+uuu&)L )[LN uG$Xqvgd=$Ek mNV{	4$\!a&_Rlqtt{tG"t/tltRtR
+HHH~pBfp4B:~HOARoYq+dAbdBXm>3ysw0q]k1KK^))3)zN)8);)K)K
+888AK^RK[^@@8(`v	.Gy `N]U,=[4P{#pg8G/S=%``4`;5`Y`!`S`S
+KKKg6zr6LzfeKdP	lQ|[~Pa7v%}8o?d0`^q["Sfc::o:	#:s:&:S:S
+%%%9;{a;}{(,%$fL]RQJGfwV][kEZN=Mp&8	Gwv;CCZCxgCbC_CwCw
+000=T3]T~3p30|>B7u8P_>m@NBUFeg1X5*74ZfN EEeEa.E\EfEU=I..ddEf
+WWW>T<-Tb<^&Wo=5G\f/I=:Djx`;)Z'-7g0VK55Guu)u\ ucu5uLuL
+ttt^{R"{DRGJtq+*L8!@F+y`;Myzp]{ITqn!X<BOHHpH5fHGH<HBHB
+)))@3KN3'KzM)^f?{lqPUfh57I"1KFcH0G%b!C<(88K8lR8s8C8^8^
+```T4S54RS;U`%s*(2g\$se)&H!p6q38{|2nY+!dKK6KerKuK+KzKz
+:::ioS#oYS	#:cA~b!^aDA\.:*|^;s	oKQ7c-,i$%%;%(a%x%,%{%{
+CCC,ZwgZ~wx,C;|2rf&?A|P#w}<:T[(kd8.hogw|00T0p]06030nbg]i3]03
+EEEdef.e^fa%E 6&?P*r,6[6RDX;TN7*HfP+LZ-oWWTW^-WdWZW<W<
+uuu&)L )[L\\uG$Xqvgd=$Ek mJV{	4$\!a&_l^qtt{tG"t/tltRtR
+HHH~pBfp4m<<HOARoYq+dAbdBX|>3ysw0q]k1;C^))3)zN)8);)K)K
+888AK^RK[<C^8(`v	.Gy `N]U,Q[4P{#pg8G/!;%``4`;5`Y`S`=Vt=959`S
+KKKg6zr6Ls+sKdP	lQ|[~Pa7v%f8o?d0`^q["S&c::o:	#:s:&:S:S
+%%%9;{a;}C,|%$fL]RQJGfwV][!EZN=Mp&8	Gww;CCZCxgCbC_CwCw
+000=T3]T~ngc0|>B7u8P_>m@NBCFeg1X5*74ZfU EEeEa.E\E	EfEf
+WWW>T<-Tb&ZRWo=5G\f/I=:Djx`;)Z'-7g0VKL`Guu)u\ ucu5uLuL
+ttt^{R"{DNl"tq+*L8!@F+y`;Myzp]{ITqn!XB	OHHpH5fHGH<HBHB
+)))@3KN3'm;@)^f?{lqPUfh57I"1KFcH0G%b!^7(88K8lR8s8C8^8^
+```T4S54R=!9`%s*(2g\$se)rHzp6q38{|2nY++dKK6KerKuK+KzKz
+:::ioS#oY}&	:cA~b!^aDA\.a*{^;s	oKQ7c-,{$%%;%(a%x%,%{%{
+CCC,ZwgZ~kw_C;|2rf&?A|P#]}3:T[(kd8.hogn|00T0p]060g0303
+EEEdef.e^UffE 6&?P*r,6[6-D<;TN7*HfP+LZXoWWTW^-WdWZW<W<
+uuu&)L )[wLwuG$Xqvgd=$Ek"mRV{	4$\!a&_lHqtt{tG"t/tltRtR
+HHH~pBfp4mByHOARoYq+dAbdNXK>3ysw0q]k1;B^))3)zN)8);)K)K
+888AK^RK[<^-8(`v	.Gy `N]5,S[4P{#pg8G/!5%``4`;5`Y`!`S`S
+KKKg6zr6Lsz&KdP	lQ|[~Pa7#%S8o?d0`^q["&ic::o:	#:s:&:S:S
+%%%9;{a;}C{a%$fL]RQJGfwVg[wEZN=Mp&8	G_X;CCZCxgCbC_CwCw
+000=T3]T~n3=0|>B7u8P_>m@.BfFeg1X5*74Z	a EEeEa.E\E	EfEf
+WWW>T<-Tb&<cWo=5G\f/I=:D xL;)Z'-7g0VKL5Guu)u\ ucu5uLuL
+ttt^{R"{DNRGtq+*L8!@F+y`fMBzp]{ITqn!XBBOHHpH5fHGH<HBHB
+)))@3KN3'mm;)^f?{lqPUfh5RI^1KFcH0G%b!^<(88K8lR8s8C8^8^
+```T4S54R==S`%s*(2g\$se)rHzp6q38{|2nYz!dKK6KerKuK+KzKz
+:::ioS#oY}}}:cA~b!^aDA\.a*{^;s	oKQ7c-{i$%%;%(a%x%,%{%{
+CCC,ZwgZ~kk!C;|2rf&?A|P#]}3:T[(kd8.ho3w|00T0p]060g0303
+EEEdef.e^UUIE 6&?P*r,6[6-D&;TN7*HfP+LZZoWWTW^-WdWZW<W<
+uuu&)L )[wwjuG$Xqvgd=$Ek"mNV{	4$\!a&_lRqtt{tG"t/tltRtR
+HHH~pBfp4mmfHOARoYq+dAbdNXm>3ysw0q]k1;m^))3)zN)8);)K)K
+888AK^RK[<<A8(`v	.Gy `N]5,=[4P{#pg8G/!Q%``4`;5`Y`!`S`S
+KKKg6zr6LssfKdP	lQ|[~Pa7#%}8o?d0`^q["&Oc::o:	#:s:&:S:S
+%%%9;{a;}CC(%$fL]RQJGfwVg[kEZN=Mp&8	G_];CCZCxgCbC_CwCw
+000=T3]T~n<g0|>B7u8P_>m@.BUFeg1X5*74Z	. EEeEa.E\E	EfEf
+WWW>T<-Tb&X<Wo=5G\f/I=:D xw;)Z'-7g0VK5&Guu)u\ ucu5uLuL
+ttt^{R"{DNJNtq+*L8!@F+y`fMmzp]{ITqn!X<:OHHpH5fHGH<HBHB
+)))@3KN3'm||)^f?{lqPUfh5RI<1KFcH0G%b!Cl(88K8lR8s8C8^8^
+```T4S54R=Qt`%s*(2g\$se)rHsp6q38{|2nYz+dKK6KerKuK+KzKz
+:::ioS#oY}fv:cA~b!^aDA\.a*C^;s	oKQ7c-{{$%%;%(a%x%,%{%{
+CCC,ZwgZ~k!gC;|2rf&?A|P#]}n:T[(kd8.ho3n|00T0p]060g0303
+EEEdef.e^UCdE 6&?P*r,6[6-D&;TN7*HfP+L<XoWWTW^-WdWZW<W<
+uuu&)L )[w`NuG$Xqvgd=$Ek"mNV{	4$\!a&_RHqtt{tG"t/tltRtR
+HHH~pBfp4my5HOARoYq+dAbdNXm>3ysw0q]k1KB^))3)zN)8);)K)K
+888AK^RK[<-C8(`v	.Gy `N]5,Q[4P{#pg8G/!!%``4`;5`Y`!`S`S
+KKKg6zr6Ls1zKdP	lQ|[~Pa7#%f8o?d0`^q["&Sc::o:	#:s:&:S:S
+%%%9;{a;}CiC%$fL]RQJGfwVg[!EZN=Mp&8	G_k;CCZCxgCbC_CwCw
+000=T3]T~nc<0|>B7u8P_>m@.BCFeg1X5*74Z	C EEeEa.E\E	EfEf
+WWW>T<-Tb&MMWo=5G\f/I=:D x`;)Z'-7g0VK5	Guu)u\ ucu5uLuL
+ttt^{R"{DNH tq+*L8!@F+y`fMyzp]{ITqn!X<;OHHpH5fHGH<HBHB
+)))@3KN3'mMN)^f?{lqPUfh5RI"1KFcH0G%b!CR(88K8lR8s8C8^8^
+```T4S54R=tT`%s*(2g\$se)rH!p6q38{|2nY+gdKK6KerKuK+KzKz
+:::ioS#oY}Ou:cA~b!^aDA\.a*|^;s	oKQ7c-,~$%%;%(a%x%,%{%{
+CCC,ZwgZ~kvxC;|2rf&?A|P#]}<:T[(kd8.hogp|00T0p]060g0303
+EEEdef.e^UN	E 6&?P*r,6[6-DX;TN7*HfP+L<ZoWWTW^-WdWZW<W<
+uuu&)L )[wjLuG$Xqvgd=$Ek"mJV{	4$\!a&_RRqtt{tG"t/tltRtR
+HHH~pBfp4m;mHOARoYq+dAbdNX|>3ysw0q]k1Km^))3)zN)8);)K)K
+888AK^RK[<7"8(`v	.Gy `N]5,Q[4P{#pg8G/SQ%``4`;5`Y`!`S`S
+KKKg6zr6Ls&1KdP	lQ|[~Pa7#%f8o?d0`^q["SOc::o:	#:s:&:S:S
+%%%9;{a;}C::%$fL]RQJGfwVg[!EZN=Mp&8	Gw];CCZCxgCbC_CwCw
+000=T<cT~g0|>B7u8P_>m@fBUFe,1&74Zx1oqs5ZZoWWTW<^&WdWZW<W<
+uuu&)`	)[LuG$Xqvgd=$EkRmNV{F4*a&_P4-l/R<BOHHpHB5mHGH<HBHB
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+KKKg6!16L!KdP	lQ|[~Pa7S%}8oDd~q["Wd|j\L,|$%%;%{(C%x%,%{%{
+CCC,Z!vZ~vC;|2rf&?A|P#3}<:T_(B.ho\(N)}&		 EEeEfaUE\E	EfEf
+WWW>TXMTbRWo=5G\f/I=:DLx`;)='X0VKW'*1A*lRqtt{tRGNt/tltRtR
+HHH~py	p4fHOARoYq+dAbdKX|>3Us?]k1`s=DTvC<(88K8^l<8s8C8^8^
+```T4Qt4RT`%s*(2g\$se)zH!p6~3	2nYJ3`Kl~&fc::o:S	}:s:&:S:S
+%%%9;|i;}~%$fL]RQJGfwVk[kEZA=28	G'=/;)Bgg|00T03pn060g0303
+EEEdeCIe^aE 6&?P*r,6[6&D&;TI75P+L(7yM{X5LGuu)uL\wucu5uLuL
+ttt^{JH{DRltq+*L8!@F+y`mMmzpd{Rn!X({gp.?;m^))3)Kzm)8);)K)K
+888AK"-K[^^8(`v	.Gy `N]=,=[4${*8G/E{: U	+!dKK6KzesKuK+KzKz
+:::iofOoYS}:cA~b!^aDA\.C*|^;G	L7c-U	r9%2__;CCZCwxkCbC_CwCw
+000=T<cT~3<0|>B7u8P_>m@UBCFe,1&74Zx1oqs5Z<oWWTW<^&WdWZW<W<
+uuu&)`	)[L	uG$Xqvgd=$EkNmJV{F4*a&_P4-l/R<mOHHpHB5mHGH<HBHB
+)))@3|M3'KB)^f?{lqPUfh5<I"1K cv%b!6cY-F*!Q%``4`S;=`Y`!`S`S
+KKKg6!16LzrKdP	lQ|[~Pa7f%S8oDd~q["Wd|j\L,,$%%;%{(C%x%,%{%{
+CCC,Z!vZ~w,C;|2rf&?A|P#<}3:T_(B.ho\(N)}&	f EEeEfaUE\E	EfEf
+WWW>TXMTb<cWo=5G\f/I=:D`xL;)='X0VKW'*1A*lNqtt{tRGNt/tltRtR
+HHH~py	p4B5HOARoYq+dAbd|XK>3Us?]k1`s=DTvC"(88K8^l<8s8C8^8^
+```T4Qt4R=!`%s*(2g\$se)!Hsp6~3	2nYJ3`Kl~&&c::o:S	}:s:&:S:S
+%%%9;|i;}C{%$fL]RQJGfwV![kEZA=28	G'=/;)Bg3|00T03pn060g0303
+EEEdeCIe^UUE 6&?P*r,6[6XD&;TI75P+L(7yM{X5wGuu)uL\wucu5uLuL
+ttt^{JH{DNJtq+*L8!@F+y`yMmzpd{Rn!X({gp.?;|^))3)Kzm)8);)K)K
+888AK"-K[<-8(`v	.Gy `N]Q,Q[4${*8G/E{: U	++dKK6KzesKuK+KzKz
+:::iofOoY}v:cA~b!^aDA\.|*|^;G	L7c-U	r9%2_w;CCZCwxkCbC_CwCw
+000=T<cT~n]0|>B7u8P_>m@CBCFe,1&74Zx1oqs5Z&oWWTW<^&WdWZW<W<
+uuu&)`	)[w&uG$Xqvgd=$EkJmJV{F4*a&_P4-l/R<yOHHpHB5mHGH<HBHB
+)))@3|M3'mC)^f?{lqPUfh5-I^1K cv%b!6cY-F*!!%``4`S;=`Y`!`S`S
+KKKg6!16LseKdP	lQ|[~Pa7O%S8oDd~q["Wd|j\L,{$%%;%{(C%x%,%{%{
+CCC,Z!vZ~!_C;|2rf&?A|P#c}3:T_(B.ho\(N)}&	U EEeEfaUE\E	EfEf
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+```T4tS4RT`%s*(2g\$se)sH!p69Vc9A|VT``^pCV&Sc::o:u&:s:&:S:S
+%%%9;i{;}~%$fL]RQJGfwV![wEZS4aSy&4}/d89+zgg|00T0ig060g0303
+EEEdeIfe^aE 6&?P*r,6[6XD<;TKYBK0fY!y7gkIJ5LGuu)uN5ucu5uLuL
+ttt^{HR{DRltq+*L8!@F+y`yMmzpW#SWiq#0g0q2&-;;^))3)C;)8);)K)K
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+:::ioO}oY	:cA~b!^aDA\.|*{^;1/N1A1	oKQQN`/,{$%%;%~,%x%,%{%{
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+000=TcnT~3=0|>B7u8P_>m@IBUFe23j2b21X5**jk3	f EEeE%	E\E	EfEf
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+)))@3Mm3'm;)^f?{lqPUfh57I^1Kw_dwQwcH0GGdS_CC(88K8@C8s8C8^8^
+```T4t=4R=S`%s*(2g\$se)&Hzp69Vc9A938{||cjV+zdKK6Kf+KuK+KzKz
+:::ioO}oY}}:cA~b!^aDA\.:*C^;1/N1A1	oKQQN`/,,$%%;%~,%x%,%{%{
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+888AK-<K[<A8(`v	.Gy `N]5,S[4wWxwiw{#pggx|W!S%``4`9!`Y`!`S`S
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+000=TcnT~<g0|>B7u8P_>m@.BCFe23j2b21X5**jk3		 EEeE%	E\E	EfEf
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+)))@3M|3'K)^f?{lqPUfh5^I<1Kw_dwQcH0GGdS_C^(88K8@C8s8C8^8^
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+:::ioOfoYf:cA~b!^aDA\.{*|^;1/N1A	oKQQN`/,{$%%;%~,%x%,%{%{
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diff --git a/hardware/portapack_h4m/CPLD/Supra/alta_db/setup.rpt.gz b/hardware/portapack_h4m/CPLD/Supra/alta_db/setup.rpt.gz
new file mode 100644
index 00000000..8c9a6c32
Binary files /dev/null and b/hardware/portapack_h4m/CPLD/Supra/alta_db/setup.rpt.gz differ
diff --git a/hardware/portapack_h4m/CPLD/Supra/alta_db/setup_summary.rpt.gz b/hardware/portapack_h4m/CPLD/Supra/alta_db/setup_summary.rpt.gz
new file mode 100644
index 00000000..22ccfac1
Binary files /dev/null and b/hardware/portapack_h4m/CPLD/Supra/alta_db/setup_summary.rpt.gz differ
diff --git a/hardware/portapack_h4m/CPLD/Supra/alta_db/xfer.rpt b/hardware/portapack_h4m/CPLD/Supra/alta_db/xfer.rpt
new file mode 100644
index 00000000..e69de29b
diff --git a/hardware/portapack_h4m/CPLD/Supra/portapack_h4m_cpld.asf b/hardware/portapack_h4m/CPLD/Supra/portapack_h4m_cpld.asf
new file mode 100644
index 00000000..e69de29b
diff --git a/hardware/portapack_h4m/CPLD/Supra/portapack_h4m_cpld.bin b/hardware/portapack_h4m/CPLD/Supra/portapack_h4m_cpld.bin
new file mode 100644
index 00000000..63f3159b
Binary files /dev/null and b/hardware/portapack_h4m/CPLD/Supra/portapack_h4m_cpld.bin differ
diff --git a/hardware/portapack_h4m/CPLD/Supra/portapack_h4m_cpld.post.asf b/hardware/portapack_h4m/CPLD/Supra/portapack_h4m_cpld.post.asf
new file mode 100644
index 00000000..e69de29b
diff --git a/hardware/portapack_h4m/CPLD/Supra/portapack_h4m_cpld.pre.asf b/hardware/portapack_h4m/CPLD/Supra/portapack_h4m_cpld.pre.asf
new file mode 100644
index 00000000..e69de29b
diff --git a/hardware/portapack_h4m/CPLD/Supra/portapack_h4m_cpld.prg b/hardware/portapack_h4m/CPLD/Supra/portapack_h4m_cpld.prg
new file mode 100644
index 00000000..2e047d01
--- /dev/null
+++ b/hardware/portapack_h4m/CPLD/Supra/portapack_h4m_cpld.prg
@@ -0,0 +1,5448 @@
+set sh_continue_on_error false
+usb_connect
+if { ! [jtag_device_id] } {
+  exit
+}
+runtest -tck 1
+sir 10 -tdi 3f8
+runtest -tck 100
+sir 10 -tdi 3f9
+runtest -tck 100
+sir 10 -tdi 3f8
+runtest -tck 100
+sir 10 -tdi 3fc
+runtest -tck 100
+sdr 8 -tdi 00
+sir 10 -tdi 3fa
+runtest -tck 100
+sdr 64 \
+  -tdi  80000000203f0044 \
+  -tdo  0 \
+  -mask 0
+sir 10 -tdi 6
+runtest -tck 100
+sdr 32 -tdi 00000000 -tdo 00025610 -mask ffffffff
+sir 10 -tdi 3fc
+runtest -tck 100
+sdr 8 -tdi f0
+sir 10 -tdi 3fe
+runtest -tck 100
+runtest -sec 0.5
+sir 10 -tdi 3fc
+runtest -tck 100
+sdr 8 -tdi f0
+sir 10 -tdi 3fa
+runtest -tck 100
+sdr 64 -tdi 086a400000000040
+runtest -sec 0.002
+sdr 64 -tdi ffff000020000040
+runtest -sec 0.002
+sdr 64 -tdi 0400004510000040
+runtest -sec 0.002
+sdr 64 -tdi 04f0200030000040
+runtest -sec 0.002
+sdr 64 -tdi b385942c08000040
+runtest -sec 0.002
+sdr 64 -tdi c2ca165028000040
+runtest -sec 0.002
+sdr 64 -tdi 650b20f118000040
+runtest -sec 0.002
+sdr 64 -tdi 85942c8138000040
+runtest -sec 0.002
+sdr 64 -tdi 883c40b204000040
+runtest -sec 0.002
+sdr 64 -tdi 1ee0f70724000040
+runtest -sec 0.002
+sdr 64 -tdi 707b83dc14000040
+runtest -sec 0.002
+sdr 64 -tdi 3dc1ee0f34000040
+runtest -sec 0.002
+sdr 64 -tdi 20f707b80c000040
+runtest -sec 0.002
+sdr 64 -tdi 7b81640b2c000040
+runtest -sec 0.002
+sdr 64 -tdi c1ee0f701c000040
+runtest -sec 0.002
+sdr 64 -tdi f707b83d3c000040
+runtest -sec 0.002
+sdr 64 -tdi 83dc1ee002000040
+runtest -sec 0.002
+sdr 64 -tdi b285902c22000040
+runtest -sec 0.002
+sdr 64 -tdi 42ca164012000040
+runtest -sec 0.002
+sdr 64 -tdi dc1ee05932000040
+runtest -sec 0.002
+sdr 64 -tdi 85907b830a000040
+runtest -sec 0.002
+sdr 64 -tdi ca1650b22a000040
+runtest -sec 0.002
+sdr 64 -tdi 0b2859421a000040
+runtest -sec 0.002
+sdr 64 -tdi 942ca1653a000040
+runtest -sec 0.002
+sdr 64 -tdi 1650b28506000040
+runtest -sec 0.002
+sdr 64 -tdi 285942ca26000040
+runtest -sec 0.002
+sdr 64 -tdi 2ca1650b16000040
+runtest -sec 0.002
+sdr 64 -tdi 40b2059436000040
+runtest -sec 0.002
+sdr 64 -tdi 5902c8160e000040
+runtest -sec 0.002
+sdr 64 -tdi a3e51f202e000040
+runtest -sec 0.002
+sdr 64 -tdi b28f947c1e000040
+runtest -sec 0.002
+sdr 64 -tdi c2ce16703e000040
+runtest -sec 0.002
+sdr 64 -tdi df0b385901000040
+runtest -sec 0.002
+sdr 64 -tdi 0f707b8321000040
+runtest -sec 0.002
+sdr 64 -tdi ca1641ee11000040
+runtest -sec 0.002
+sdr 64 -tdi 0b28594231000040
+runtest -sec 0.002
+sdr 64 -tdi 0000a16509000040
+runtest -sec 0.002
+sdr 64 -tdi 0000004529000040
+runtest -sec 0.002
+sdr 64 -tdi 04ffdb0019000040
+runtest -sec 0.002
+sdr 64 -tdi 001fffff39000040
+runtest -sec 0.002
+sdr 64 -tdi 0000000005000040
+runtest -sec 0.002
+sdr 64 -tdi 0000000025000040
+runtest -sec 0.002
+sdr 64 -tdi 0000000015000040
+runtest -sec 0.002
+sdr 64 -tdi 0000000035000040
+runtest -sec 0.002
+sdr 64 -tdi 000000000d000040
+runtest -sec 0.002
+sdr 64 -tdi 000000002d000040
+runtest -sec 0.002
+sdr 64 -tdi 0000007e1d000040
+runtest -sec 0.002
+sdr 64 -tdi 001fffff3d000040
+runtest -sec 0.002
+sdr 64 -tdi 0000000003000040
+runtest -sec 0.002
+sdr 64 -tdi 0000000023000040
+runtest -sec 0.002
+sdr 64 -tdi 0000000013000040
+runtest -sec 0.002
+sdr 64 -tdi 0000000033000040
+runtest -sec 0.002
+sdr 64 -tdi 000000000b000040
+runtest -sec 0.002
+sdr 64 -tdi 000000002b000040
+runtest -sec 0.002
+sdr 64 -tdi 0000007e1b000040
+runtest -sec 0.002
+sdr 64 -tdi 001fffff3b000040
+runtest -sec 0.002
+sdr 64 -tdi 0000000007000040
+runtest -sec 0.002
+sdr 64 -tdi 0000000027000040
+runtest -sec 0.002
+sdr 64 -tdi 0000000017000040
+runtest -sec 0.002
+sdr 64 -tdi 0000000037000040
+runtest -sec 0.002
+sdr 64 -tdi 000000000f000040
+runtest -sec 0.002
+sdr 64 -tdi 000000002f000040
+runtest -sec 0.002
+sdr 64 -tdi 0000007e1f000040
+runtest -sec 0.002
+sdr 64 -tdi 001fffff3f000040
+runtest -sec 0.002
+sdr 64 -tdi 0000000000800040
+runtest -sec 0.002
+sdr 64 -tdi 0000000020800040
+runtest -sec 0.002
+sdr 64 -tdi 0000000010800040
+runtest -sec 0.002
+sdr 64 -tdi 0000000030800040
+runtest -sec 0.002
+sdr 64 -tdi 0000000008800040
+runtest -sec 0.002
+sdr 64 -tdi 0000000028800040
+runtest -sec 0.002
+sdr 64 -tdi 0000007e18800040
+runtest -sec 0.002
+sdr 64 -tdi 011fffff38800040
+runtest -sec 0.002
+sdr 64 -tdi 0440210a04800040
+runtest -sec 0.002
+sdr 64 -tdi 1000842524800040
+runtest -sec 0.002
+sdr 64 -tdi 4041210a14800040
+runtest -sec 0.002
+sdr 64 -tdi 08a0105034800040
+runtest -sec 0.002
+sdr 64 -tdi 289220100c800040
+runtest -sec 0.002
+sdr 64 -tdi 620428042c800040
+runtest -sec 0.002
+sdr 64 -tdi 0000007e1c800040
+runtest -sec 0.002
+sdr 64 -tdi 001fffff3c800040
+runtest -sec 0.002
+sdr 64 -tdi 0000000002800040
+runtest -sec 0.002
+sdr 64 -tdi 0060000022800040
+runtest -sec 0.002
+sdr 64 -tdi 0118080012800040
+runtest -sec 0.002
+sdr 64 -tdi 0105080032800040
+runtest -sec 0.002
+sdr 64 -tdi 020040c40a800040
+runtest -sec 0.002
+sdr 64 -tdi 040000002a800040
+runtest -sec 0.002
+sdr 64 -tdi 0000007e1a800040
+runtest -sec 0.002
+sdr 64 -tdi 001fffff3a800040
+runtest -sec 0.002
+sdr 64 -tdi 0000000006800040
+runtest -sec 0.002
+sdr 64 -tdi 0050000026800040
+runtest -sec 0.002
+sdr 64 -tdi 0090840416800040
+runtest -sec 0.002
+sdr 64 -tdi 0242101036800040
+runtest -sec 0.002
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+sdr 64 -tdi 0000000010c000c0 -tdo 0402000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000030c000c0 -tdo 0010000200000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000008c000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000028c000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000018c000c0 -tdo 0000004000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000038c000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000004c000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000024c000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000014c000c0 -tdo e000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000034c000c0 -tdo 1800000300000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000cc000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002cc000c0 -tdo 0180000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001cc000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003cc000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000002c000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000022c000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000012c000c0 -tdo e000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000032c000c0 -tdo 0000000300000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000ac000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002ac000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001ac000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003ac000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000006c000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000026c000c0 -tdo 0000440000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000016c000c0 -tdo 6000100000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000036c000c0 -tdo 0000080800000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000ec000c0 -tdo 0010000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002ec000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001ec000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003ec000c0 -tdo 0000000100000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000001c000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000021c000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000011c000c0 -tdo 0001000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000031c000c0 -tdo 0004414000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000009c000c0 -tdo 0001000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000029c000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000019c000c0 -tdo 0000004000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000039c000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000005c000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000025c000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000015c000c0 -tdo 4000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000035c000c0 -tdo 0088200200000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000dc000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002dc000c0 -tdo 8000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001dc000c0 -tdo 0000002100000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003dc000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000003c000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000023c000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000013c000c0 -tdo c024000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000033c000c0 -tdo 0000010100000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000bc000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002bc000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001bc000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003bc000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000007c000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000027c000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000017c000c0 -tdo 2804000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000037c000c0 -tdo 0000000200000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000fc000c0 -tdo 0040000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002fc000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001fc000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003fc000c0 -tdo 0000000100000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000002000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000202000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000102000c0 -tdo 0002000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000302000c0 -tdo 0000000200000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000082000c0 -tdo 0020000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000282000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000182000c0 -tdo 0000001000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000382000c0 -tdo 0000010000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000042000c0 -tdo 3000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000242000c0 -tdo 0000800100000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000142000c0 -tdo 0000100000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000342000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000c2000c0 -tdo 0001000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002c2000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001c2000c0 -tdo 0000000800000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003c2000c0 -tdo 0000004000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000022000c0 -tdo 0700000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000222000c0 -tdo 1808000800000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000122000c0 -tdo 6001000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000322000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000a2000c0 -tdo 0004000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002a2000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001a2000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003a2000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000062000c0 -tdo 3000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000262000c0 -tdo da00004000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000162000c0 -tdo 6812000400000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000362000c0 -tdo 0008002300000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000e2000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002e2000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001e2000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003e2000c0 -tdo 0000000100000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000012000c0 -tdo 7800000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000212000c0 -tdo c000002800000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000112000c0 -tdo 0000002000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000312000c0 -tdo 0082808300000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000092000c0 -tdo 000a000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000292000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000192000c0 -tdo 0000000400000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000392000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000052000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000252000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000152000c0 -tdo 0c80000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000352000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000d2000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002d2000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001d2000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003d2000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000032000c0 -tdo 0001200000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000232000c0 -tdo 0402800000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000132000c0 -tdo 1001200000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000332000c0 -tdo 0904800000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000b2000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002b2000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001b2000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003b2000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000072000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000272000c0 -tdo 2200000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000172000c0 -tdo 8000008000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000372000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000f2000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002f2000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001f2000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003f2000c0 -tdo 0000000100000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000000a000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000020a000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000010a000c0 -tdo 0000004000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000030a000c0 -tdo 0990120000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000008a000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000028a000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000018a000c0 -tdo 0000004000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000038a000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000004a000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000024a000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000014a000c0 -tdo e080000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000034a000c0 -tdo 0000000300000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000ca000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002ca000c0 -tdo 0800000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001ca000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003ca000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000002a000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000022a000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000012a000c0 -tdo 8424000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000032a000c0 -tdo 0000000300000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000aa000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002aa000c0 -tdo 0080000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001aa000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003aa000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000006a000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000026a000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000016a000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000036a000c0 -tdo 0000080b00000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000ea000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002ea000c0 -tdo 0180000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001ea000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003ea000c0 -tdo 0000000100000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000001a000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000021a000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000011a000c0 -tdo 0024000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000031a000c0 -tdo 0000014300000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000009a000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000029a000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000019a000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000039a000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000005a000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000025a000c0 -tdo 0080000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000015a000c0 -tdo 2200000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000035a000c0 -tdo 0000008000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000da000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002da000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001da000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003da000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000003a000c0 -tdo 0400000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000023a000c0 -tdo 1880000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000013a000c0 -tdo 4000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000033a000c0 -tdo 0800400800000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000ba000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002ba000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001ba000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003ba000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000007a000c0 -tdo 0100000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000027a000c0 -tdo 0400000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000017a000c0 -tdo 1000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000037a000c0 -tdo 0000000400000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000fa000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002fa000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001fa000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003fa000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000006000c0 -tdo 0100000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000206000c0 -tdo 0400000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000106000c0 -tdo 9000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000306000c0 -tdo 0000008200000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000086000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000286000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000186000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000386000c0 -tdo 0000080000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000046000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000246000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000146000c0 -tdo 0800000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000346000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000c6000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002c6000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001c6000c0 -tdo 0000001200000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003c6000c0 -tdo 0000800000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000026000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000226000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000126000c0 -tdo 6240000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000326000c0 -tdo 0004800000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000a6000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002a6000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001a6000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003a6000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000066000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000266000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000166000c0 -tdo 7012000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000366000c0 -tdo 0008001300000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000e6000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002e6000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001e6000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003e6000c0 -tdo 0000000100000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000016000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000216000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000116000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000316000c0 -tdo 0080008300000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000096000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000296000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000196000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000396000c0 -tdo 0000004000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000056000c0 -tdo 3000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000256000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000156000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000356000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000d6000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002d6000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001d6000c0 -tdo 0000001000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003d6000c0 -tdo 0000040000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000036000c0 -tdo 3700000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000236000c0 -tdo 0000000900000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000136000c0 -tdo 1240000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000336000c0 -tdo 0004800000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000b6000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002b6000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001b6000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003b6000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000076000c0 -tdo 3000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000276000c0 -tdo 0000a40100000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000176000c0 -tdo 8800200000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000376000c0 -tdo 0000200000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000f6000c0 -tdo 0001000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002f6000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001f6000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003f6000c0 -tdo 0000000100000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000000e000c0 -tdo 0800000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000020e000c0 -tdo 000800a800000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000010e000c0 -tdo 0000100000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000030e000c0 -tdo 0000010000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000008e000c0 -tdo 0004000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000028e000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000018e000c0 -tdo 0000000200000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000038e000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000004e000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000024e000c0 -tdo 0200000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000014e000c0 -tdo 0800000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000034e000c0 -tdo 1000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000ce000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002ce000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001ce000c0 -tdo 0000003000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003ce000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000002e000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000022e000c0 -tdo 1890000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000012e000c0 -tdo 1000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000032e000c0 -tdo 0200000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000ae000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002ae000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001ae000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003ae000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000006e000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000026e000c0 -tdo d800000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000016e000c0 -tdo 8400000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000036e000c0 -tdo 1800000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000ee000c0 -tdo 6000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002ee000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001ee000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003ee000c0 -tdo 0000000100000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000001e000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000021e000c0 -tdo c000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000011e000c0 -tdo 0100002400000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000031e000c0 -tdo 0004610000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000009e000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000029e000c0 -tdo 1000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000019e000c0 -tdo 0000000100000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000039e000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000005e000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000025e000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000015e000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000035e000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000de000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002de000c0 -tdo 0180000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001de000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003de000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000003e000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000023e000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000013e000c0 -tdo 6024000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000033e000c0 -tdo 0900000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000be000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002be000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001be000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003be000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000007e000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000027e000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000017e000c0 -tdo 6801100000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000037e000c0 -tdo 0000001300000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000fe000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002fe000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001fe000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003fe000c0 -tdo 0000000100000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000001000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000201000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000101000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000301000c0 -tdo 0002808300000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000081000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000281000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000181000c0 -tdo 0000000c00000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000381000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000041000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000241000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000141000c0 -tdo a800000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000341000c0 -tdo 0000000100000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000c1000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002c1000c0 -tdo 8000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001c1000c0 -tdo 0000002900000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003c1000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000021000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000221000c0 -tdo 0000240000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000121000c0 -tdo 2000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000321000c0 -tdo 0000210200000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000a1000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002a1000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001a1000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003a1000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000061000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000261000c0 -tdo 0000100000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000161000c0 -tdo 5000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000361000c0 -tdo 0000000100000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000e1000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002e1000c0 -tdo 1000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001e1000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003e1000c0 -tdo 0000000100000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000011000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000211000c0 -tdo 0000040000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000111000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000311000c0 -tdo 0000000100000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000091000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000291000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000191000c0 -tdo 0000000100000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000391000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000051000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000251000c0 -tdo 0004000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000151000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000351000c0 -tdo 0018000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000d1000c0 -tdo 0060000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002d1000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001d1000c0 -tdo 0000000200000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003d1000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000031000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000231000c0 -tdo 0000800000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000131000c0 -tdo 6000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000331000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000b1000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002b1000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001b1000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003b1000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000071000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000271000c0 -tdo 0000040000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000171000c0 -tdo 7800000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000371000c0 -tdo 0008000b00000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000f1000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002f1000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001f1000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003f1000c0 -tdo 0000000100000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000009000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000209000c0 -tdo 0000200000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000109000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000309000c0 -tdo 0080008300000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000089000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000289000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000189000c0 -tdo 0000000800000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000389000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000049000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000249000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000149000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000349000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000c9000c0 -tdo 0080000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002c9000c0 -tdo 0180000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001c9000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003c9000c0 -tdo 0014000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000029000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000229000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000129000c0 -tdo 1000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000329000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000a9000c0 -tdo 0020000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002a9000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001a9000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003a9000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000069000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000269000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000169000c0 -tdo 8822000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000369000c0 -tdo 1200000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000e9000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002e9000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001e9000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003e9000c0 -tdo 0000000100000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000019000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000219000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000119000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000319000c0 -tdo 0000220000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000099000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000299000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000199000c0 -tdo 0000004000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000399000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000059000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000259000c0 -tdo 0200000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000159000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000359000c0 -tdo 0000400000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000d9000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002d9000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001d9000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003d9000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000039000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000239000c0 -tdo 1800000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000139000c0 -tdo 6000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000339000c0 -tdo 0002000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000b9000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002b9000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001b9000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003b9000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000079000c0 -tdo 0000800000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000279000c0 -tdo d800000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000179000c0 -tdo 6800000800000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000379000c0 -tdo 0000c00b00000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000f9000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002f9000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001f9000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003f9000c0 -tdo 0000000100000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000005000c0 -tdo 0000200000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000205000c0 -tdo c000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000105000c0 -tdo 0000002000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000305000c0 -tdo 0000008300000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000085000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000285000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000185000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000385000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000045000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000245000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000145000c0 -tdo 0012000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000345000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000c5000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002c5000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001c5000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003c5000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000025000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000225000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000125000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000325000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000a5000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002a5000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001a5000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003a5000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000065000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000265000c0 -tdo 0000100000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000165000c0 -tdo 0001000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000365000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000e5000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002e5000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001e5000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003e5000c0 -tdo 0000000100000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000015000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000215000c0 -tdo 0000040000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000115000c0 -tdo 0000200000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000315000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000095000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000295000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000195000c0 -tdo 0000004000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000395000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000055000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000255000c0 -tdo 0010000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000155000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000355000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000d5000c0 -tdo 0004000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002d5000c0 -tdo 0004000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001d5000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003d5000c0 -tdo 0000500000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000035000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000235000c0 -tdo 0080000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000135000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000335000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000b5000c0 -tdo 0002000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002b5000c0 -tdo 0020000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001b5000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003b5000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000075000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000275000c0 -tdo 0020000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000175000c0 -tdo 0400000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000375000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000f5000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002f5000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001f5000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003f5000c0 -tdo 0000000100000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000000d000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000020d000c0 -tdo 0100000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000010d000c0 -tdo 0080000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000030d000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000008d000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000028d000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000018d000c0 -tdo 0000004000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000038d000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000004d000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000024d000c0 -tdo 0018000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000014d000c0 -tdo 0902500000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000034d000c0 -tdo 0000c00000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000cd000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002cd000c0 -tdo 1000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001cd000c0 -tdo 0000000100000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003cd000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000002d000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000022d000c0 -tdo 0081000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000012d000c0 -tdo 1208000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000032d000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000ad000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002ad000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001ad000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003ad000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000006d000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000026d000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000016d000c0 -tdo 9100000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000036d000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000ed000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002ed000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001ed000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003ed000c0 -tdo 0000000100000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000001d000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000021d000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000011d000c0 -tdo 0400000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000031d000c0 -tdo 0000120000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000009d000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000029d000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000019d000c0 -tdo 0000004000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000039d000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000005d000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000025d000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000015d000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000035d000c0 -tdo 0400200300000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000dd000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002dd000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001dd000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003dd000c0 -tdo 000a000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000003d000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000023d000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000013d000c0 -tdo 5000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000033d000c0 -tdo 0800010300000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000bd000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002bd000c0 -tdo 0880000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001bd000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003bd000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000007d000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000027d000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000017d000c0 -tdo 2000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000037d000c0 -tdo 0000100a00000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000fd000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002fd000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001fd000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003fd000c0 -tdo 0012000100000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000003000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000203000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000103000c0 -tdo 8000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000303000c0 -tdo 0000028200000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000083000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000283000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000183000c0 -tdo 0000004000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000383000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000043000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000243000c0 -tdo 0008000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000143000c0 -tdo 0100000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000343000c0 -tdo 0000000300000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000c3000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002c3000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001c3000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003c3000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000023000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000223000c0 -tdo 0001000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000123000c0 -tdo 5200000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000323000c0 -tdo 0000210300000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000a3000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002a3000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001a3000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003a3000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000063000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000263000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000163000c0 -tdo 2012000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000363000c0 -tdo 0000080a00000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000e3000c0 -tdo 0060000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002e3000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001e3000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003e3000c0 -tdo 0000000100000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000013000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000213000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000113000c0 -tdo 8000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000313000c0 -tdo 0000018200000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000093000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000293000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000193000c0 -tdo 0000004000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000393000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000053000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000253000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000153000c0 -tdo 0000100000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000353000c0 -tdo 0000000b00000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000d3000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002d3000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001d3000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003d3000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000033000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000233000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000133000c0 -tdo 7000800000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000333000c0 -tdo 0000008000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000b3000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002b3000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001b3000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003b3000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000073000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000273000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000173000c0 -tdo 0100000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000373000c0 -tdo 0000020700000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000f3000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002f3000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001f3000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003f3000c0 -tdo 0000000100000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000000b000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000020b000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000010b000c0 -tdo 8400000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000030b000c0 -tdo 0000028300000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000008b000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000028b000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000018b000c0 -tdo 0000004000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000038b000c0 -tdo 0000002400000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000004b000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000024b000c0 -tdo 2000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000014b000c0 -tdo 0800000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000034b000c0 -tdo 1004000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000cb000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002cb000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001cb000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003cb000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000002b000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000022b000c0 -tdo e800000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000012b000c0 -tdo 6000046400000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000032b000c0 -tdo 0400800000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000ab000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002ab000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001ab000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003ab000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000006b000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000026b000c0 -tdo d000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000016b000c0 -tdo 7012120200000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000036b000c0 -tdo 0000002300000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000eb000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002eb000c0 -tdo 1000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001eb000c0 -tdo 0000000100000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003eb000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000001b000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000021b000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000011b000c0 -tdo 000100a000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000031b000c0 -tdo 0000008300000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000009b000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000029b000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000019b000c0 -tdo 0000004000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000039b000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000005b000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000025b000c0 -tdo 4008000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000015b000c0 -tdo 0c40020200000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000035b000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000db000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002db000c0 -tdo 0004000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001db000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003db000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000003b000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000023b000c0 -tdo 1801000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000013b000c0 -tdo 1000009000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000033b000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000bb000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002bb000c0 -tdo 0040000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001bb000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003bb000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000007b000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000027b000c0 -tdo 9800000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000017b000c0 -tdo 9008180000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000037b000c0 -tdo 0000400000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000fb000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002fb000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001fb000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003fb000c0 -tdo 000a000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000007000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000207000c0 -tdo c000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000107000c0 -tdo 0004806100000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000307000c0 -tdo 0001220000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000087000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000287000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000187000c0 -tdo 0000004000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000387000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000047000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000247000c0 -tdo 0080000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000147000c0 -tdo 2000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000347000c0 -tdo 0800400000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000c7000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002c7000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001c7000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003c7000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000027000c0 -tdo 0400000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000227000c0 -tdo 0080000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000127000c0 -tdo 4000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000327000c0 -tdo 0800000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000a7000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002a7000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001a7000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003a7000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000067000c0 -tdo 0100000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000267000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000167000c0 -tdo 1000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000367000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000e7000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002e7000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001e7000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003e7000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000017000c0 -tdo 0100000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000217000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000117000c0 -tdo 1000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000317000c0 -tdo 0000000100000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000097000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000297000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000197000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000397000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000057000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000257000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000157000c0 -tdo 0100000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000357000c0 -tdo 0084000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000d7000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002d7000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001d7000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003d7000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000037000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000237000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000137000c0 -tdo 0200000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000337000c0 -tdo 0010800000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000b7000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002b7000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001b7000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003b7000c0 -tdo 0000010000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000077000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000277000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000177000c0 -tdo 0020000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000377000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000f7000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002f7000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001f7000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003f7000c0 -tdo 000000a800000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000000f000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000020f000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000010f000c0 -tdo 0004000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000030f000c0 -tdo 0001400000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000008f000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000028f000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000018f000c0 -tdo 0000004000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000038f000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000004f000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000024f000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000014f000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000034f000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000cf000c0 -tdo 0004000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002cf000c0 -tdo 0480000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001cf000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003cf000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000002f000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000022f000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000012f000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000032f000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000af000c0 -tdo 0002000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002af000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001af000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003af000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000006f000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000026f000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000016f000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000036f000c0 -tdo 0002000000000000 -mask ffffffff00000000
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+sdr 64 -tdi 000000002ef000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001ef000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003ef000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000001f000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000021f000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000011f000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000031f000c0 -tdo 0000400000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000009f000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000029f000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000019f000c0 -tdo 0000004000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000039f000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000005f000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000025f000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000015f000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000035f000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000df000c0 -tdo 0080000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002df000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001df000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003df000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000003f000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000023f000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000013f000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000033f000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000bf000c0 -tdo 0040000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002bf000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001bf000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003bf000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000007f000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000027f000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000017f000c0 -tdo 0008400000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000037f000c0 -tdo 0008000000000000 -mask ffffffff00000000
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+sdr 64 -tdi 000000002ff000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001ff000c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003ff000c0 -tdo 0000000100000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000000800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000200800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000100800c0 -tdo 0002100000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000300800c0 -tdo 0020000000000000 -mask ffffffff00000000
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+sdr 64 -tdi 00000000280800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000180800c0 -tdo 0000004000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000380800c0 -tdo 0000000000000000 -mask ffffffff00000000
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+sdr 64 -tdi 00000000240800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000140800c0 -tdo 0100000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000340800c0 -tdo 0100000000000000 -mask ffffffff00000000
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+sdr 64 -tdi 000000003c0800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000020800c0 -tdo 0000000000000000 -mask ffffffff00000000
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+sdr 64 -tdi 00000000120800c0 -tdo 0400000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000320800c0 -tdo 0800000000000000 -mask ffffffff00000000
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+sdr 64 -tdi 000000003a0800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000060800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000260800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000160800c0 -tdo 0040000000000000 -mask ffffffff00000000
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+sdr 64 -tdi 00000000010800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000210800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000110800c0 -tdo 0400000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000310800c0 -tdo 0000000000000000 -mask ffffffff00000000
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+sdr 64 -tdi 00000000290800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000190800c0 -tdo 0000004000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000390800c0 -tdo 0000000000000000 -mask ffffffff00000000
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+sdr 64 -tdi 00000000250800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000150800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000350800c0 -tdo 0000000000000000 -mask ffffffff00000000
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+sdr 64 -tdi 000000001d0800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003d0800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000030800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000230800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000130800c0 -tdo 0000000000000000 -mask ffffffff00000000
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+sdr 64 -tdi 000000001b0800c0 -tdo 0000000000000000 -mask ffffffff00000000
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+sdr 64 -tdi 00000000070800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000270800c0 -tdo 0000000000000000 -mask ffffffff00000000
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+sdr 64 -tdi 00000000370800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000f0800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002f0800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001f0800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003f0800c0 -tdo 0000000100000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000008800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000208800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000108800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000308800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000088800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000288800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000188800c0 -tdo 0000004000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000388800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000048800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000248800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000148800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000348800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000c8800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002c8800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001c8800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003c8800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000028800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000228800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000128800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000328800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000a8800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002a8800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001a8800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003a8800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000068800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000268800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000168800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000368800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000e8800c0 -tdo 0080000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002e8800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001e8800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003e8800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000018800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000218800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000118800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000318800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000098800c0 -tdo 0040000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000298800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000198800c0 -tdo 0000004000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000398800c0 -tdo 0000002000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000058800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000258800c0 -tdo 2000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000158800c0 -tdo 0000020000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000358800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000d8800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002d8800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001d8800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003d8800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000038800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000238800c0 -tdo f800000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000138800c0 -tdo 000000a800000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000338800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000b8800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002b8800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001b8800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003b8800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000078800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000278800c0 -tdo 9000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000178800c0 -tdo 0480000200000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000378800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000f8800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002f8800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001f8800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003f8800c0 -tdo 0000000400000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000004800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000204800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000104800c0 -tdo 000004a000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000304800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000084800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000284800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000184800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000384800c0 -tdo 0000000200000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000044800c0 -tdo 3000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000244800c0 -tdo 9000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000144800c0 -tdo 0000108100000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000344800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000c4800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002c4800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001c4800c0 -tdo 0000001200000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003c4800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000024800c0 -tdo 3700000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000224800c0 -tdo 6000000900000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000124800c0 -tdo 0000805000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000324800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000a4800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002a4800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001a4800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003a4800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000064800c0 -tdo 3000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000264800c0 -tdo 9800800100000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000164800c0 -tdo 0000020200000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000364800c0 -tdo 0200000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000e4800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002e4800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001e4800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003e4800c0 -tdo 0000000400000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000014800c0 -tdo 0800000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000214800c0 -tdo 8004011800000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000114800c0 -tdo 000000a000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000314800c0 -tdo 1000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000094800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000294800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000194800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000394800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000054800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000254800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000154800c0 -tdo 0001000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000354800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000d4800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002d4800c0 -tdo 0080000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001d4800c0 -tdo 0000007f00000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003d4800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000034800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000234800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000134800c0 -tdo 0000100000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000334800c0 -tdo 0001800000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000b4800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002b4800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001b4800c0 -tdo 0000007e00000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003b4800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000074800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000274800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000174800c0 -tdo 0000900000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000374800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000f4800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002f4800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001f4800c0 -tdo 0000007e00000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003f4800c0 -tdo 0000000100000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000000c800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000020c800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000010c800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000030c800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000008c800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000028c800c0 -tdo 0084280400000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000018c800c0 -tdo 0000007f00000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000038c800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000004c800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000024c800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000014c800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000034c800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000cc800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002cc800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001cc800c0 -tdo 0000007e00000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003cc800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000002c800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000022c800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000012c800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000032c800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000ac800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002ac800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001ac800c0 -tdo 0000007e00000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003ac800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000006c800c0 -tdo 0000040000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000026c800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000016c800c0 -tdo 0001000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000036c800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000ec800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002ec800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001ec800c0 -tdo 0000007e00000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003ec800c0 -tdo 0000000100000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000001c800c0 -tdo 0000020000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000021c800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000011c800c0 -tdo 0000100000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000031c800c0 -tdo 0004400000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000009c800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000029c800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000019c800c0 -tdo 0000007e00000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000039c800c0 -tdo 0000200000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000005c800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000025c800c0 -tdo 0001000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000015c800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000035c800c0 -tdo 0000000300000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000dc800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002dc800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001dc800c0 -tdo 0000007e00000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003dc800c0 -tdo 0000100000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000003c800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000023c800c0 -tdo 0000800000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000013c800c0 -tdo 7000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000033c800c0 -tdo 0000004700000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000bc800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002bc800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001bc800c0 -tdo 0000007e00000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003bc800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000007c800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000027c800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000017c800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000037c800c0 -tdo 0800d00300000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000fc800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002fc800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001fc800c0 -tdo 0000007e00000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003fc800c0 -tdo 0000000100000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000002800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000202800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000102800c0 -tdo 8000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000302800c0 -tdo 0800018800000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000082800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000282800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000182800c0 -tdo 0000007e00000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000382800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000042800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000242800c0 -tdo 0000100000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000142800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000342800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000c2800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002c2800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001c2800c0 -tdo 0000007e00000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003c2800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000022800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000222800c0 -tdo 0000080000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000122800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000322800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000a2800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002a2800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001a2800c0 -tdo 0000007e00000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003a2800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000062800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000262800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000162800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000362800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000e2800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002e2800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001e2800c0 -tdo 0000007e00000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003e2800c0 -tdo 0000000100000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000012800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000212800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000112800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000312800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000092800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000292800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000192800c0 -tdo 0000007e00000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000392800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000052800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000252800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000152800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000352800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000d2800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002d2800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001d2800c0 -tdo 0000007e00000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003d2800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000032800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000232800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000132800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000332800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000b2800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002b2800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001b2800c0 -tdo 0000007e00000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003b2800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000072800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000272800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000172800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000372800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000f2800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002f2800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001f2800c0 -tdo 0000007e00000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003f2800c0 -tdo 0000000100000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000000a800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000020a800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000010a800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000030a800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000008a800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000028a800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000018a800c0 -tdo 0000007e00000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000038a800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000004a800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000024a800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000014a800c0 -tdo 0100000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000034a800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000ca800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002ca800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001ca800c0 -tdo 0000007e00000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003ca800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000002a800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000022a800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000012a800c0 -tdo 0200000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000032a800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000aa800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002aa800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001aa800c0 -tdo 0000007e00000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003aa800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000006a800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000026a800c0 -tdo 0000800000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000016a800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000036a800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000ea800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002ea800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001ea800c0 -tdo 0000007e00000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003ea800c0 -tdo 0000000100000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000001a800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000021a800c0 -tdo 0004000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000011a800c0 -tdo 0280000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000031a800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000009a800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000029a800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000019a800c0 -tdo 0000007e00000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000039a800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000005a800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000025a800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000015a800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000035a800c0 -tdo 0008000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000da800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002da800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001da800c0 -tdo 0000007e00000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003da800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000003a800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000023a800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000013a800c0 -tdo 0000a00000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000033a800c0 -tdo 0020000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000ba800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002ba800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001ba800c0 -tdo 0000007e00000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003ba800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000007a800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000027a800c0 -tdo 0001000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000017a800c0 -tdo 0000100000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000037a800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000fa800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002fa800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001fa800c0 -tdo 0000007e00000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003fa800c0 -tdo 0000000100000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000006800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000206800c0 -tdo 0000800000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000106800c0 -tdo 0000400000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000306800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000086800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000286800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000186800c0 -tdo 0000007e00000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000386800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000046800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000246800c0 -tdo 9000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000146800c0 -tdo 0000001000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000346800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000c6800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002c6800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001c6800c0 -tdo 0000007e00000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003c6800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000026800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000226800c0 -tdo 7800000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000126800c0 -tdo 0000086000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000326800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000a6800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002a6800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001a6800c0 -tdo 0000007e00000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003a6800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000066800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000266800c0 -tdo 8001000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000166800c0 -tdo 0000040000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000366800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000e6800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002e6800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001e6800c0 -tdo 0000007e00000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003e6800c0 -tdo 0000000100000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000016800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000216800c0 -tdo 8000800000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000116800c0 -tdo 0000006800000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000316800c0 -tdo 0002800000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000096800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000296800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000196800c0 -tdo 0000007e00000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000396800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000056800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000256800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000156800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000356800c0 -tdo 0800000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000d6800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002d6800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001d6800c0 -tdo 0000007e00000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003d6800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000036800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000236800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000136800c0 -tdo 4000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000336800c0 -tdo 0800000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000b6800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002b6800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001b6800c0 -tdo 0000007e00000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003b6800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000076800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000276800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000176800c0 -tdo 1000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000376800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000f6800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002f6800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001f6800c0 -tdo 0000007e00000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003f6800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000000e800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000020e800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000010e800c0 -tdo 1000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000030e800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000008e800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000028e800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000018e800c0 -tdo 0000007e00000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000038e800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000004e800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000024e800c0 -tdo 9000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000014e800c0 -tdo 0008200800000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000034e800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000ce800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002ce800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001ce800c0 -tdo 0000007e00000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003ce800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000002e800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000022e800c0 -tdo 6000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000012e800c0 -tdo 0002146000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000032e800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000ae800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002ae800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001ae800c0 -tdo 0000007e00000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003ae800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000006e800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000026e800c0 -tdo 9840000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000016e800c0 -tdo 0022040000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000036e800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000ee800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002ee800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001ee800c0 -tdo 0000007e00000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003ee800c0 -tdo 0000000100000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000001e800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000021e800c0 -tdo 8080000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000011e800c0 -tdo 0000006800000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000031e800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000009e800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000029e800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000019e800c0 -tdo 0000007e00000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000039e800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000005e800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000025e800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000015e800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000035e800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000de800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002de800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001de800c0 -tdo 0000007e00000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003de800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000003e800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000023e800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000013e800c0 -tdo 0000600000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000033e800c0 -tdo 0c00000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000be800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002be800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001be800c0 -tdo 0000007e00000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003be800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000007e800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000027e800c0 -tdo 0000000000000000 -mask ffffffff00000000
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+sdr 64 -tdi 0000000037e800c0 -tdo 0000000000000000 -mask ffffffff00000000
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+sdr 64 -tdi 000000002fe800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001fe800c0 -tdo 0000007e00000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003fe800c0 -tdo 0000000100000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000001800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000201800c0 -tdo 0000000000000000 -mask ffffffff00000000
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+sdr 64 -tdi 00000000241800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000141800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000341800c0 -tdo 0000400000000000 -mask ffffffff00000000
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+sdr 64 -tdi 000000001c1800c0 -tdo 0000007e00000000 -mask ffffffff00000000
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+sdr 64 -tdi 00000000021800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000221800c0 -tdo 0000000000000000 -mask ffffffff00000000
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+sdr 64 -tdi 000000001a1800c0 -tdo 0000007e00000000 -mask ffffffff00000000
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+sdr 64 -tdi 00000000061800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000261800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000161800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000361800c0 -tdo 0000000000000000 -mask ffffffff00000000
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+sdr 64 -tdi 000000001e1800c0 -tdo 0000007e00000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003e1800c0 -tdo 0000000100000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000011800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000211800c0 -tdo 0000000000000000 -mask ffffffff00000000
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+sdr 64 -tdi 00000000191800c0 -tdo 0000007e00000000 -mask ffffffff00000000
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+sdr 64 -tdi 00000000251800c0 -tdo 0000000000000000 -mask ffffffff00000000
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+sdr 64 -tdi 00000000009800c0 -tdo 0000000000000000 -mask ffffffff00000000
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+sdr 64 -tdi 00000000249800c0 -tdo 0040000000000000 -mask ffffffff00000000
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+sdr 64 -tdi 00000000229800c0 -tdo 0080000000000000 -mask ffffffff00000000
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+sdr 64 -tdi 00000000255800c0 -tdo 9000000000000000 -mask ffffffff00000000
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+sdr 64 -tdi 00000000355800c0 -tdo 0000000300000000 -mask ffffffff00000000
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+sdr 64 -tdi 00000000035800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000235800c0 -tdo 6000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000135800c0 -tdo 7000009000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000335800c0 -tdo 0000004b00000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000b5800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002b5800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001b5800c0 -tdo 0000007e00000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003b5800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000075800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000275800c0 -tdo 9800000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000175800c0 -tdo 0000040100000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000375800c0 -tdo 0000000300000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000f5800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002f5800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001f5800c0 -tdo 0000007e00000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003f5800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000000d800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000020d800c0 -tdo 8000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000010d800c0 -tdo 8000006000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000030d800c0 -tdo 00000a8800000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000008d800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000028d800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000018d800c0 -tdo 0000007e00000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000038d800c0 -tdo 001fffff00000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000004d800c0 -tdo 0040010a00000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000024d800c0 -tdo 1100042800000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000014d800c0 -tdo 0002002000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000034d800c0 -tdo e000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000cd800c0 -tdo ffffffff00000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002cd800c0 -tdo ffffffff00000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001cd800c0 -tdo 0000007f00000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003cd800c0 -tdo 001fffff00000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000002d800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000022d800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000012d800c0 -tdo 0180c60000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000032d800c0 -tdo e663183000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000ad800c0 -tdo ffffffff00000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002ad800c0 -tdo ffffffff00000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001ad800c0 -tdo 0000007f00000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003ad800c0 -tdo 001fffff00000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000006d800c0 -tdo 0001800000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000026d800c0 -tdo 0004000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000016d800c0 -tdo 0000080000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000036d800c0 -tdo e002080000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000ed800c0 -tdo ffffffff00000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002ed800c0 -tdo ffffffff00000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001ed800c0 -tdo 0000007f00000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003ed800c0 -tdo 011fffff00000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000001d800c0 -tdo 0440010a00000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000021d800c0 -tdo 1101042800000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000011d800c0 -tdo 4243422000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000031d800c0 -tdo e561104800000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000009d800c0 -tdo ffffffff00000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000029d800c0 -tdo ffffffff00000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000019d800c0 -tdo 0000007f00000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000039d800c0 -tdo 001fffff00000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000005d800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000025d800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000015d800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000035d800c0 -tdo e000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000dd800c0 -tdo ffffffff00000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002dd800c0 -tdo ffffffff00000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001dd800c0 -tdo 0000007f00000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003dd800c0 -tdo 001fffff00000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000003d800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000023d800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000013d800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000033d800c0 -tdo e000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000bd800c0 -tdo ffffffff00000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002bd800c0 -tdo ffffffff00000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001bd800c0 -tdo 0000007f00000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003bd800c0 -tdo 001fffff00000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000007d800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000027d800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000017d800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 0000000037d800c0 -tdo e000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 000000000fd800c0 -tdo ffffffff00000000 -mask ffffffff00000000
+sdr 64 -tdi 000000002fd800c0 -tdo ffffffff00000000 -mask ffffffff00000000
+sdr 64 -tdi 000000001fd800c0 -tdo 0000007f00000000 -mask ffffffff00000000
+sdr 64 -tdi 000000003fd800c0 -tdo 001fffff00000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000003800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000203800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000103800c0 -tdo 0000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000303800c0 -tdo e000000000000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000083800c0 -tdo ffffffff00000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000283800c0 -tdo ffffffff00000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000183800c0 -tdo 0000007f00000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000383800c0 -tdo 403f005400000000 -mask ffffffff00000000
+sdr 64 -tdi 00000000043800c0 -tdo f1f0000000000000 -mask ffffffff00000000
+sir 10 -tdi 3f7
+runtest -tck 100
+usb_close
diff --git a/hardware/portapack_h4m/CPLD/Supra/portapack_h4m_cpld.qpf b/hardware/portapack_h4m/CPLD/Supra/portapack_h4m_cpld.qpf
new file mode 100644
index 00000000..34382a2f
--- /dev/null
+++ b/hardware/portapack_h4m/CPLD/Supra/portapack_h4m_cpld.qpf
@@ -0,0 +1,3 @@
+#QUARTUS_VERSION = "11.1"
+PROJECT_REVISION = "portapack_h4m_cpld"
+
diff --git a/hardware/portapack_h4m/CPLD/Supra/portapack_h4m_cpld.qsf b/hardware/portapack_h4m/CPLD/Supra/portapack_h4m_cpld.qsf
new file mode 100644
index 00000000..382179d5
--- /dev/null
+++ b/hardware/portapack_h4m/CPLD/Supra/portapack_h4m_cpld.qsf
@@ -0,0 +1,115 @@
+# Design name Assignments, replace __design_name__ with actual design name
+# ========================
+set_global_assignment -name DEVICE EP4CE75F29C8
+set_global_assignment -name FAMILY "Cyclone IV E"
+
+set_global_assignment -name TOP_LEVEL_ENTITY "top"
+set_global_assignment -name SEARCH_PATH "A:\\Users\\jLynx\\Documents\\Code\\C\\portapack-mayhem\\hardware\\portapack_h4m\\CPLD\\AG256SL100\\."
+
+set_global_assignment -name VERILOG_FILE "A:\\Users\\jLynx\\Downloads\\Supra-2023.02.b0-7773ca8a-win64-all\\etc\\arch\\rodinia\\alta_sim.v"
+set_global_assignment -name VHDL_FILE "A:\\Users\\jLynx\\Documents\\Code\\C\\portapack-mayhem\\hardware\\portapack_h4m\\CPLD\\AG256SL100\\top.vhd"
+
+set_global_assignment -name SDC_FILE "A:\\Users\\jLynx\\Documents\\Code\\C\\portapack-mayhem\\hardware\\portapack_h4m\\CPLD\\AG256SL100\\portapack_h4m_cpld.sdc"
+
+set_global_assignment -name SDC_FILE .\\portapack_h4m_cpld_derate.sdc
+#set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_FILE "atom_netlists/__design_name__.vqm"
+
+# Project-Wide Assignments
+# ========================
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 11.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:37:04  JANUARY 04, 2013"
+set_global_assignment -name LAST_QUARTUS_VERSION "22.1std.1 Lite Edition"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY ./quartus_logs
+set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
+set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS ON
+#set_global_assignment -name SMART_RECOMPILE ON
+
+# Classic Timing Assignments
+# ==========================
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+
+# Analysis & Synthesis Assignments
+# ================================
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
+set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
+#set_global_assignment -name MAX_BALANCING_DSP_BLOCKS 0
+#set_global_assignment -name AUTO_ROM_RECOGNITION OFF
+#set_global_assignment -name AUTO_RAM_RECOGNITION OFF
+#set_global_assignment -name MAX_RAM_BLOCKS_M4K 0
+set_global_assignment -name AUTO_OPEN_DRAIN_PINS OFF
+# set_instance_assignment -name PRESERVE_REGISTER ON -to *
+#set_instance_assignment -name PRESERVE_PLL_COUNTER_ORDER ON -to *
+#set_instance_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS 0 -to *
+
+# Fitter Assignments
+# ==================
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name ROUTING_BACK_ANNOTATION_MODE OFF
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO PATHS AND MINIMUM TPD PATHS"
+set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
+set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
+set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 10
+set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 10
+set_global_assignment -name ECO_OPTIMIZE_TIMING ON
+set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
+set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION ALWAYS
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name IO_PLACEMENT_OPTIMIZATION ON
+set_global_assignment -name SEED 1
+set_global_assignment -name FIT_ONLY_ONE_ATTEMPT OFF
+set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED 4
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
+#set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
+#set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
+
+# EDA Netlist Writer Assignments
+# ==============================
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (Verilog)"
+
+# LogicLock Region Assignments
+# ============================
+set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF
+
+# Power Estimation Assignments
+# ============================
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+
+# start EDA_TOOL_SETTINGS(eda_simulation)
+# ---------------------------------------
+
+# EDA Netlist Writer Assignments
+# ==============================
+set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
+
+# end EDA_TOOL_SETTINGS(eda_simulation)
+# -------------------------------------
+
+# start DESIGN_PARTITION(Top)
+# ---------------------------
+
+# Incremental Compilation Assignments
+# ===================================
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name FLOW_DISABLE_ASSEMBLER ON
+
+# end DESIGN_PARTITION(Top)
+# -------------------------
+
+
+
+set_global_assignment -name MAX_BALANCING_DSP_BLOCKS 0
+set_global_assignment -name MAX_RAM_BLOCKS_M4K 0
+set_global_assignment -name AUTO_ROM_RECOGNITION OFF
+set_global_assignment -name AUTO_RAM_RECOGNITION OFF
+set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING OFF
+
+
+set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY PARTITION_ONLY -section_id eda_simulation
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/hardware/portapack_h4m/CPLD/Supra/portapack_h4m_cpld.sdc b/hardware/portapack_h4m/CPLD/Supra/portapack_h4m_cpld.sdc
new file mode 100644
index 00000000..57788149
--- /dev/null
+++ b/hardware/portapack_h4m/CPLD/Supra/portapack_h4m_cpld.sdc
@@ -0,0 +1 @@
+read_sdc -quiet "A:/Users/jLynx/Documents/Code/C/portapack-mayhem/hardware/portapack_h4m/CPLD/AG256SL100/portapack_h4m_cpld.sdc"
diff --git a/hardware/portapack_h4m/CPLD/Supra/portapack_h4m_cpld_assignment_defaults.qdf b/hardware/portapack_h4m/CPLD/Supra/portapack_h4m_cpld_assignment_defaults.qdf
new file mode 100644
index 00000000..ceb735be
--- /dev/null
+++ b/hardware/portapack_h4m/CPLD/Supra/portapack_h4m_cpld_assignment_defaults.qdf
@@ -0,0 +1,806 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2023  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and any partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details, at
+# https://fpgasoftware.intel.com/eula.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 22.1std.1 Build 917 02/14/2023 SC Lite Edition
+# Date created = 14:46:17  April 19, 2024
+#
+# -------------------------------------------------------------------------- #
+#
+# Note:
+#
+# 1) Do not modify this file. This file was generated
+#    automatically by the Quartus Prime software and is used
+#    to preserve global assignments across Quartus Prime versions.
+#
+# -------------------------------------------------------------------------- #
+
+set_global_assignment -name IP_COMPONENT_REPORT_HIERARCHY Off
+set_global_assignment -name IP_COMPONENT_INTERNAL Off
+set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On
+set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off
+set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off
+set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db
+set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off
+set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off
+set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off
+set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off
+set_global_assignment -name HC_OUTPUT_DIR hc_output
+set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off
+set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off
+set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On
+set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off
+set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings"
+set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On
+set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On
+set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off
+set_global_assignment -name REVISION_TYPE Base -family "Arria V"
+set_global_assignment -name REVISION_TYPE Base -family "Stratix V"
+set_global_assignment -name REVISION_TYPE Base -family "Arria V GZ"
+set_global_assignment -name REVISION_TYPE Base -family "Cyclone V"
+set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle"
+set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On
+set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On
+set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On
+set_global_assignment -name DO_COMBINED_ANALYSIS Off
+set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off
+set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING Off
+set_global_assignment -name EMIF_SOC_PHYCLK_ADVANCE_MODELING Off
+set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off
+set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On
+set_global_assignment -name TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone 10 LP"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "MAX 10"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix IV"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV E"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria 10"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX V"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix V"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V GZ"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX II"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GX"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GZ"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV GX"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone V"
+set_global_assignment -name TIMING_ANALYZER_DO_REPORT_TIMING Off
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone 10 LP"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "MAX 10"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria 10"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V"
+set_global_assignment -name TIMING_ANALYZER_REPORT_NUM_WORST_CASE_TIMING_PATHS 100
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone 10 LP"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "MAX 10"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV E"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix IV"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria 10"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX V"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix V"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V GZ"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX II"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GX"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GZ"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV GX"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone V"
+set_global_assignment -name OPTIMIZATION_MODE Balanced
+set_global_assignment -name ALLOW_REGISTER_MERGING On
+set_global_assignment -name ALLOW_REGISTER_DUPLICATION On
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Cyclone 10 LP"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX 10"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix IV"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV E"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Arria 10"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX V"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix V"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V GZ"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX II"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GX"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GZ"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV GX"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone V"
+set_global_assignment -name MUX_RESTRUCTURE Auto
+set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off
+set_global_assignment -name ENABLE_IP_DEBUG Off
+set_global_assignment -name SAVE_DISK_SPACE On
+set_global_assignment -name OCP_HW_EVAL -value OFF
+set_global_assignment -name DEVICE_FILTER_PACKAGE Any
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any
+set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
+set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001
+set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993
+set_global_assignment -name FAMILY -value "Cyclone V"
+set_global_assignment -name TRUE_WYSIWYG_FLOW Off
+set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off
+set_global_assignment -name STATE_MACHINE_PROCESSING Auto
+set_global_assignment -name SAFE_STATE_MACHINE Off
+set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On
+set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On
+set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off
+set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000
+set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250
+set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On
+set_global_assignment -name PARALLEL_SYNTHESIS On
+set_global_assignment -name DSP_BLOCK_BALANCING Auto
+set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)"
+set_global_assignment -name NOT_GATE_PUSH_BACK On
+set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On
+set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off
+set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On
+set_global_assignment -name IGNORE_CARRY_BUFFERS Off
+set_global_assignment -name IGNORE_CASCADE_BUFFERS Off
+set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_LCELL_BUFFERS Off
+set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO
+set_global_assignment -name IGNORE_SOFT_BUFFERS On
+set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off
+set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On
+set_global_assignment -name AUTO_GLOBAL_OE_MAX On
+set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off
+set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut
+set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed
+set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name ALLOW_XOR_GATE_USAGE On
+set_global_assignment -name AUTO_LCELL_INSERTION On
+set_global_assignment -name CARRY_CHAIN_LENGTH 48
+set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48
+set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name CASCADE_CHAIN_LENGTH 2
+set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16
+set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4
+set_global_assignment -name AUTO_CARRY_CHAINS On
+set_global_assignment -name AUTO_CASCADE_CHAINS On
+set_global_assignment -name AUTO_PARALLEL_EXPANDERS On
+set_global_assignment -name AUTO_OPEN_DRAIN_PINS On
+set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off
+set_global_assignment -name AUTO_ROM_RECOGNITION On
+set_global_assignment -name AUTO_RAM_RECOGNITION On
+set_global_assignment -name AUTO_DSP_RECOGNITION On
+set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto
+set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
+set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On
+set_global_assignment -name STRICT_RAM_RECOGNITION Off
+set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On
+set_global_assignment -name FORCE_SYNCH_CLEAR Off
+set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On
+set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off
+set_global_assignment -name AUTO_RESOURCE_SHARING Off
+set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name MAX7000_FANIN_PER_CELL 100
+set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On
+set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)"
+set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)"
+set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)"
+set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off
+set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone 10 LP"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "MAX 10"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria 10"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX"
+set_global_assignment -name REPORT_PARAMETER_SETTINGS On
+set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On
+set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On
+set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone 10 LP"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX 10"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria 10"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V"
+set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation"
+set_global_assignment -name HDL_MESSAGE_LEVEL Level2
+set_global_assignment -name USE_HIGH_SPEED_ADDER Auto
+set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED 100
+set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000
+set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000
+set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off
+set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000
+set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100
+set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On
+set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off
+set_global_assignment -name BLOCK_DESIGN_NAMING Auto
+set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off
+set_global_assignment -name SYNTHESIS_EFFORT Auto
+set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On
+set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off
+set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium
+set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone 10 LP"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "MAX 10"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX"
+set_global_assignment -name MAX_LABS "-1 (Unlimited)"
+set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On
+set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)"
+set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On
+set_global_assignment -name PRPOF_ID Off
+set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off
+set_global_assignment -name REPORT_PARAMETER_SETTINGS_PRO On
+set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_PRO On
+set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE Off
+set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off
+set_global_assignment -name AUTO_MERGE_PLLS On
+set_global_assignment -name IGNORE_MODE_FOR_MERGE Off
+set_global_assignment -name TXPMA_SLEW_RATE Low
+set_global_assignment -name ADCE_ENABLED Auto
+set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal
+set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off
+set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0
+set_global_assignment -name PHYSICAL_SYNTHESIS Off
+set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off
+set_global_assignment -name DEVICE AUTO
+set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off
+set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off
+set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On
+set_global_assignment -name ENABLE_NCEO_OUTPUT Off
+set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name STRATIXIII_UPDATE_MODE Standard
+set_global_assignment -name STRATIX_UPDATE_MODE Standard
+set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image"
+set_global_assignment -name CVP_MODE Off
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V"
+set_global_assignment -name VID_OPERATION_MODE "PMBus Slave"
+set_global_assignment -name USE_CONF_DONE AUTO
+set_global_assignment -name USE_PWRMGT_SCL AUTO
+set_global_assignment -name USE_PWRMGT_SDA AUTO
+set_global_assignment -name USE_PWRMGT_ALERT AUTO
+set_global_assignment -name USE_INIT_DONE AUTO
+set_global_assignment -name USE_CVP_CONFDONE AUTO
+set_global_assignment -name USE_SEU_ERROR AUTO
+set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name USER_START_UP_CLOCK Off
+set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off
+set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off
+set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On
+set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On
+set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC
+set_global_assignment -name ENABLE_VREFA_PIN Off
+set_global_assignment -name ENABLE_VREFB_PIN Off
+set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off
+set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"
+set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off
+set_global_assignment -name INIT_DONE_OPEN_DRAIN On
+set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name ENABLE_CONFIGURATION_PINS On
+set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off
+set_global_assignment -name ENABLE_NCE_PIN Off
+set_global_assignment -name ENABLE_BOOT_SEL_PIN On
+set_global_assignment -name CRC_ERROR_CHECKING Off
+set_global_assignment -name INTERNAL_SCRUBBING Off
+set_global_assignment -name PR_ERROR_OPEN_DRAIN On
+set_global_assignment -name PR_READY_OPEN_DRAIN On
+set_global_assignment -name ENABLE_CVP_CONFDONE Off
+set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On
+set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone 10 LP"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone 10 LP"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V"
+set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On
+set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto
+set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV"
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10"
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V"
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ"
+set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0
+set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On
+set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"
+set_global_assignment -name OPTIMIZE_SSN Off
+set_global_assignment -name OPTIMIZE_TIMING "Normal compilation"
+set_global_assignment -name ECO_OPTIMIZE_TIMING Off
+set_global_assignment -name ECO_REGENERATE_REPORT Off
+set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal
+set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off
+set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically
+set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically
+set_global_assignment -name SEED 1
+set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF
+set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off
+set_global_assignment -name SLOW_SLEW_RATE Off
+set_global_assignment -name PCI_IO Off
+set_global_assignment -name TURBO_BIT On
+set_global_assignment -name WEAK_PULL_UP_RESISTOR Off
+set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off
+set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off
+set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On
+set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto
+set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto
+set_global_assignment -name NORMAL_LCELL_INSERT On
+set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone 10 LP"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V"
+set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF
+set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off
+set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off
+set_global_assignment -name AUTO_TURBO_BIT ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off
+set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On
+set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off
+set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off
+set_global_assignment -name FITTER_EFFORT "Auto Fit"
+set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns
+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal
+set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto
+set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto
+set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK On
+set_global_assignment -name AUTO_GLOBAL_OE On
+set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off
+set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off
+set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off
+set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up"
+set_global_assignment -name ENABLE_HOLD_BACK_OFF On
+set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off
+set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto
+set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On
+set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone 10 LP"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V"
+set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX"
+set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off
+set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On
+set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off
+set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off
+set_global_assignment -name PR_DONE_OPEN_DRAIN On
+set_global_assignment -name NCEO_OPEN_DRAIN On
+set_global_assignment -name ENABLE_CRC_ERROR_PIN Off
+set_global_assignment -name ENABLE_PR_PINS Off
+set_global_assignment -name RESERVE_PR_PINS Off
+set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off
+set_global_assignment -name PR_PINS_OPEN_DRAIN Off
+set_global_assignment -name CLAMPING_DIODE Off
+set_global_assignment -name TRI_STATE_SPI_PINS Off
+set_global_assignment -name UNUSED_TSD_PINS_GND Off
+set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off
+set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off
+set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V"
+set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0
+set_global_assignment -name SEU_FIT_REPORT Off
+set_global_assignment -name HYPER_RETIMER Off -family "Arria 10"
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1"
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On
+set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
+set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<None>"
+set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
+set_global_assignment -name EDA_RESYNTHESIS_TOOL "<None>"
+set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On
+set_global_assignment -name COMPRESSION_MODE Off
+set_global_assignment -name CLOCK_SOURCE Internal
+set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"
+set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1
+set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off
+set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF
+set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
+set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name USE_CHECKSUM_AS_USERCODE On
+set_global_assignment -name SECURITY_BIT Off
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone 10 LP"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130"
+set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 0000000
+set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery"
+set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0
+set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0
+set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0
+set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto
+set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On
+set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off
+set_global_assignment -name GENERATE_TTF_FILE Off
+set_global_assignment -name GENERATE_RBF_FILE Off
+set_global_assignment -name GENERATE_HEX_FILE Off
+set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0
+set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal"
+set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off
+set_global_assignment -name AUTO_RESTART_CONFIGURATION On
+set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off
+set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off
+set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone 10 LP"
+set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V"
+set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF
+set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off
+set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off
+set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off
+set_global_assignment -name POR_SCHEME "Instant ON"
+set_global_assignment -name EN_USER_IO_WEAK_PULLUP On
+set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On
+set_global_assignment -name POF_VERIFY_PROTECT Off
+set_global_assignment -name ENABLE_SPI_MODE_CHECK Off
+set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On
+set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off
+set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0
+set_global_assignment -name GENERATE_PMSF_FILES On
+set_global_assignment -name START_TIME 0ns
+set_global_assignment -name SIMULATION_MODE TIMING
+set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off
+set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On
+set_global_assignment -name SETUP_HOLD_DETECTION Off
+set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off
+set_global_assignment -name CHECK_OUTPUTS Off
+set_global_assignment -name SIMULATION_COVERAGE On
+set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name GLITCH_DETECTION Off
+set_global_assignment -name GLITCH_INTERVAL 1ns
+set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off
+set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On
+set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off
+set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On
+set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
+set_global_assignment -name SIMULATION_NETLIST_VIEWER Off
+set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off
+set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO
+set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO
+set_global_assignment -name DRC_TOP_FANOUT 50
+set_global_assignment -name DRC_FANOUT_EXCEEDING 30
+set_global_assignment -name DRC_GATED_CLOCK_FEED 30
+set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY
+set_global_assignment -name ENABLE_DRC_SETTINGS Off
+set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25
+set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10
+set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30
+set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2
+set_global_assignment -name MERGE_HEX_FILE Off
+set_global_assignment -name GENERATE_SVF_FILE Off
+set_global_assignment -name GENERATE_ISC_FILE Off
+set_global_assignment -name GENERATE_JAM_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off
+set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off
+set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state"
+set_global_assignment -name HPS_EARLY_IO_RELEASE Off
+set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off
+set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off
+set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_USE_PVA On
+set_global_assignment -name POWER_USE_INPUT_FILE "No File"
+set_global_assignment -name POWER_USE_INPUT_FILES Off
+set_global_assignment -name POWER_VCD_FILTER_GLITCHES On
+set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off
+set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off
+set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL
+set_global_assignment -name POWER_AUTO_COMPUTE_TJ On
+set_global_assignment -name POWER_TJ_VALUE 25
+set_global_assignment -name POWER_USE_TA_VALUE 25
+set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off
+set_global_assignment -name POWER_BOARD_TEMPERATURE 25
+set_global_assignment -name POWER_HPS_ENABLE Off
+set_global_assignment -name POWER_HPS_PROC_FREQ 0.0
+set_global_assignment -name ENABLE_SMART_VOLTAGE_ID Off
+set_global_assignment -name IGNORE_PARTITIONS Off
+set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off
+set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On
+set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End"
+set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On
+set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On
+set_global_assignment -name RTLV_GROUP_RELATED_NODES On
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off
+set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On
+set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On
+set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On
+set_global_assignment -name EQC_BBOX_MERGE On
+set_global_assignment -name EQC_LVDS_MERGE On
+set_global_assignment -name EQC_RAM_UNMERGING On
+set_global_assignment -name EQC_DFF_SS_EMULATION On
+set_global_assignment -name EQC_RAM_REGISTER_UNPACK On
+set_global_assignment -name EQC_MAC_REGISTER_UNPACK On
+set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On
+set_global_assignment -name EQC_STRUCTURE_MATCHING On
+set_global_assignment -name EQC_AUTO_BREAK_CONE On
+set_global_assignment -name EQC_POWER_UP_COMPARE Off
+set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On
+set_global_assignment -name EQC_AUTO_INVERSION On
+set_global_assignment -name EQC_AUTO_TERMINATE On
+set_global_assignment -name EQC_SUB_CONE_REPORT Off
+set_global_assignment -name EQC_RENAMING_RULES On
+set_global_assignment -name EQC_PARAMETER_CHECK On
+set_global_assignment -name EQC_AUTO_PORTSWAP On
+set_global_assignment -name EQC_DETECT_DONT_CARES On
+set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off
+set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ?
+set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ?
+set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ?
+set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ?
+set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ?
+set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ?
+set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ?
+set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ?
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ?
+set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ?
+set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "<None>" -section_id ?
+set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ?
+set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ?
+set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ?
+set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ?
+set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ?
+set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ?
+set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ?
+set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ?
+set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ?
+set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ?
+set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ?
+set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ?
+set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ?
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST On -section_id ?
+set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ?
+set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ?
+set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ?
+set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ?
+set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ?
+set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ?
+set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ?
+set_global_assignment -name EDA_IBIS_EXTENDED_MODEL_SELECTOR Off -section_id ?
+set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ?
+set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ?
+set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ?
+set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
+set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
+set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p2 -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ?
+set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ?
+set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ?
+set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ?
+set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ?
+set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ?
+set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ?
+set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ?
+set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ?
+set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ?
+set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ?
+set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ?
diff --git a/hardware/portapack_h4m/CPLD/Supra/portapack_h4m_cpld_derate.sdc b/hardware/portapack_h4m/CPLD/Supra/portapack_h4m_cpld_derate.sdc
new file mode 100644
index 00000000..e3b239f5
--- /dev/null
+++ b/hardware/portapack_h4m/CPLD/Supra/portapack_h4m_cpld_derate.sdc
@@ -0,0 +1,2 @@
+set_timing_derate -late  2.0
+set_timing_derate -early 2.0
diff --git a/hardware/portapack_h4m/CPLD/Supra/portapack_h4m_cpld_download.svf b/hardware/portapack_h4m/CPLD/Supra/portapack_h4m_cpld_download.svf
new file mode 100644
index 00000000..069583a1
--- /dev/null
+++ b/hardware/portapack_h4m/CPLD/Supra/portapack_h4m_cpld_download.svf
@@ -0,0 +1,5437 @@
+ENDDR IDLE;
+ENDIR IDLE;
+STATE IDLE;
+RUNTEST 1 TCK;
+SIR 10 TDI (3f8);
+RUNTEST 100 TCK;
+SIR 10 TDI (3f9);
+RUNTEST 100 TCK;
+SIR 10 TDI (3f8);
+RUNTEST 100 TCK;
+SIR 10 TDI (6);
+RUNTEST 100 TCK;
+SDR 32 TDI (00000000) TDO (00057620) MASK (ffffffff);
+SIR 10 TDI (3fc);
+RUNTEST 100 TCK;
+SDR 8 TDI (f8);
+SIR 10 TDI (3fe);
+RUNTEST 100 TCK;
+RUNTEST 0.5 SEC;
+SIR 10 TDI (3fc);
+RUNTEST 100 TCK;
+SDR 8 TDI (f8);
+SIR 10 TDI (3fa);
+RUNTEST 100 TCK;
+SDR 64 TDI (90e0000000010040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (086a400020010040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (ffff000010010040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0400004530010040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (04f0200008010040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (b385942c28010040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (c2ca165018010040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (650b20f138010040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (85942c8104010040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (883c40b224010040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (1ee0f70714010040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (707b83dc34010040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (3dc1ee0f0c010040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (20f707b82c010040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (7b81640b1c010040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (c1ee0f703c010040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (f707b83d02010040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (83dc1ee022010040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (b285902c12010040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (42ca164032010040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (dc1ee0590a010040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (85907b832a010040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (ca1650b21a010040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0b2859423a010040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (942ca16506010040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (1650b28526010040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (285942ca16010040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (2ca1650b36010040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (40b205940e010040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (5902c8162e010040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (a3e51f201e010040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (b28f947c3e010040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (c2ce167001010040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (df0b385921010040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0f707b8311010040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (ca1641ee31010040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0b28594209010040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0000a16529010040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0000004519010040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (04ffdb0039010040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (001fffff05010040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0000000025010040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0000000015010040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0000000035010040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (000000000d010040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (000000002d010040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (000000001d010040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0000007e3d010040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (001fffff03010040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0000000023010040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0000000013010040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0000000033010040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (000000000b010040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (000000002b010040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (000000001b010040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0000007e3b010040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (001fffff07010040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0000000027010040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0000000017010040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0000000037010040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (000000000f010040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (000000002f010040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (000000001f010040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0000007e3f010040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (001fffff00810040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0000000020810040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0000000010810040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0000000030810040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0000000008810040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0000000028810040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0000000018810040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0000007e38810040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (011fffff04810040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0440210a24810040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (1000842514810040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (4041210a34810040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (08a010500c810040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (289220102c810040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (620428041c810040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0000007e3c810040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (001fffff02810040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0000000022810040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0060000012810040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0118080032810040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (010508000a810040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (020040c42a810040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (040000001a810040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0000007e3a810040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (001fffff06810040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0000000026810040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0050000016810040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0090840436810040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (024210100e810040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (000000002e810040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (000000001e810040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0000007e3e810040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (011fffff01810040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0000000221810040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0000842011810040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0108420831810040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0421082009810040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (018c60cc29810040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0000000019810040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0000007e39810040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0000000005810040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0000000025810040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0200000015810040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0000000035810040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (000000000d810040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (006000002d810040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (000000001d810040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0000000a3d810040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0000000003810040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0000000023810040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (1800000013810040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0240000033810040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (000000000b810040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (000000002b810040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (100000001b810040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (000000013b810040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0000000007810040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0000000027810040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (d800000017810040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0012000037810040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (000000000f810040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (000000002f810040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (808000001f810040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (000000013f810040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0000000000410040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0000000020410040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (c000000010410040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0000001230410040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0000000008410040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0000000028410040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0400000018410040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0000000038410040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0000000004410040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0000000024410040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0000000014410040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (e800000034410040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (000000030c410040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (000000002c410040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (000000001c410040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (000000003c410040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0000000002410040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0000000022410040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0099000012410040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (8264000032410040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (090000030a410040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (000000002a410040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (000000001a410040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (000000003a410040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0000000006410040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0000000026410040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0000000016410040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (1080000036410040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (000000040e410040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (000000002e410040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (000000001e410040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (000000003e410040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0000000001410040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0000000021410040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (00a9000011410040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0400000031410040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0090008009410040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0000000029410040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0000000019410040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0000000039410040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0000480005410040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0000000025410040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0000000015410040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (4800000035410040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (000020020d410040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (000000002d410040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (000000001d410040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (000000013d410040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0000000003410040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0000000023410040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0009000013410040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (c000000033410040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (090481010b410040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (000000002b410040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (100000001b410040);
+RUNTEST 0.002 SEC;
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+SDR 64 TDI (000000002ce90040);
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+SDR 64 TDI (000000001ce90040);
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+SDR 64 TDI (000000003ce90040);
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+SDR 64 TDI (0000007e02e90040);
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+SDR 64 TDI (0000000022e90040);
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+SDR 64 TDI (0000000012e90040);
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+SDR 64 TDI (6000000032e90040);
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+SDR 64 TDI (000214600ae90040);
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+SDR 64 TDI (000000001ae90040);
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+SDR 64 TDI (000000003ae90040);
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+SDR 64 TDI (0000007e06e90040);
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+SDR 64 TDI (0000000026e90040);
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+SDR 64 TDI (0000000016e90040);
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+SDR 64 TDI (9840000036e90040);
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+SDR 64 TDI (002204000ee90040);
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+SDR 64 TDI (000000002ee90040);
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+SDR 64 TDI (000000001ee90040);
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+SDR 64 TDI (000000003ee90040);
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+SDR 64 TDI (0000007e01e90040);
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+SDR 64 TDI (0000000121e90040);
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+SDR 64 TDI (0000000011e90040);
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+SDR 64 TDI (8080000031e90040);
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+SDR 64 TDI (0000006809e90040);
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+SDR 64 TDI (0000000029e90040);
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+SDR 64 TDI (0000000019e90040);
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+SDR 64 TDI (0000000039e90040);
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+SDR 64 TDI (0000000035e90040);
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+SDR 64 TDI (000000000de90040);
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+SDR 64 TDI (000000003de90040);
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+SDR 64 TDI (0000007e03e90040);
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+SDR 64 TDI (0000000023e90040);
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+SDR 64 TDI (000060000be90040);
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+SDR 64 TDI (0c0000002be90040);
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+SDR 64 TDI (0000000037e90040);
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+SDR 64 TDI (000000000fe90040);
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+SDR 64 TDI (000000003fe90040);
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+SDR 64 TDI (0000007e00190040);
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+SDR 64 TDI (0000000120190040);
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+SDR 64 TDI (0000000024190040);
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+SDR 64 TDI (0000007e02190040);
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+SDR 64 TDI (000000002e190040);
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+SDR 64 TDI (000000001e190040);
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+SDR 64 TDI (000000003e190040);
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+SDR 64 TDI (0000007e01190040);
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+SDR 64 TDI (0000000121190040);
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+SDR 64 TDI (0000000011190040);
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+SDR 64 TDI (0000000009190040);
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+SDR 64 TDI (0000000029190040);
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+SDR 64 TDI (0000000039190040);
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+SDR 64 TDI (0000007e05190040);
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+SDR 64 TDI (000000000b190040);
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+SDR 64 TDI (0000007e07190040);
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+SDR 64 TDI (0000000037190040);
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+SDR 64 TDI (000000000f190040);
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+SDR 64 TDI (000000002f190040);
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+SDR 64 TDI (000000000c990040);
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+SDR 64 TDI (180000002c590040);
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+SDR 64 TDI (9000000035590040);
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+SDR 64 TDI (000091010d590040);
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+SDR 64 TDI (000000032d590040);
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+SDR 64 TDI (700000900b590040);
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+SDR 64 TDI (0000007e07590040);
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+SDR 64 TDI (9800000037590040);
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+SDR 64 TDI (000004010f590040);
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+SDR 64 TDI (000000001f590040);
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+SDR 64 TDI (000000003f590040);
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+SDR 64 TDI (0000007e00d90040);
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+SDR 64 TDI (0000000020d90040);
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+SDR 64 TDI (0000000010d90040);
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+SDR 64 TDI (8000000030d90040);
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+SDR 64 TDI (00000a8828d90040);
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+SDR 64 TDI (0000007e04d90040);
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+SDR 64 TDI (001fffff24d90040);
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+SDR 64 TDI (0040010a14d90040);
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+SDR 64 TDI (1100042834d90040);
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+SDR 64 TDI (000200200cd90040);
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+SDR 64 TDI (e00000002cd90040);
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+SDR 64 TDI (ffffffff1cd90040);
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+SDR 64 TDI (ffffffff3cd90040);
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+SDR 64 TDI (0000007f02d90040);
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+SDR 64 TDI (001fffff22d90040);
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+SDR 64 TDI (0000000012d90040);
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+SDR 64 TDI (0000000032d90040);
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+SDR 64 TDI (0180c6000ad90040);
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+SDR 64 TDI (e66318302ad90040);
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+SDR 64 TDI (ffffffff1ad90040);
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+SDR 64 TDI (ffffffff3ad90040);
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+SDR 64 TDI (0000007f06d90040);
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+SDR 64 TDI (001fffff26d90040);
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+SDR 64 TDI (0001800016d90040);
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+SDR 64 TDI (0004000036d90040);
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+SDR 64 TDI (000008000ed90040);
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+SDR 64 TDI (e00208002ed90040);
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+SDR 64 TDI (ffffffff1ed90040);
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+SDR 64 TDI (0000007f01d90040);
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+SDR 64 TDI (011fffff21d90040);
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+SDR 64 TDI (0440010a11d90040);
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+SDR 64 TDI (1101042831d90040);
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+SDR 64 TDI (4243422009d90040);
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+SDR 64 TDI (e561104829d90040);
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+SDR 64 TDI (ffffffff19d90040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (ffffffff39d90040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (0000007f05d90040);
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+SDR 64 TDI (001fffff25d90040);
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+SDR 64 TDI (0000000015d90040);
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+SDR 64 TDI (0000000035d90040);
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+SDR 64 TDI (000000000dd90040);
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+SDR 64 TDI (e00000002dd90040);
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+SDR 64 TDI (ffffffff1dd90040);
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+SDR 64 TDI (ffffffff3dd90040);
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+SDR 64 TDI (0000007f03d90040);
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+SDR 64 TDI (001fffff23d90040);
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+SDR 64 TDI (0000000013d90040);
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+SDR 64 TDI (0000000033d90040);
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+SDR 64 TDI (000000000bd90040);
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+SDR 64 TDI (e00000002bd90040);
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+SDR 64 TDI (ffffffff1bd90040);
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+SDR 64 TDI (ffffffff3bd90040);
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+SDR 64 TDI (0000007f07d90040);
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+SDR 64 TDI (001fffff27d90040);
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+SDR 64 TDI (0000000017d90040);
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+SDR 64 TDI (0000000037d90040);
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+SDR 64 TDI (000000000fd90040);
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+SDR 64 TDI (e00000002fd90040);
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+SDR 64 TDI (ffffffff1fd90040);
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+SDR 64 TDI (ffffffff3fd90040);
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+SDR 64 TDI (0000007f00390040);
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+SDR 64 TDI (001fffff20390040);
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+SDR 64 TDI (0000000010390040);
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+SDR 64 TDI (0000000030390040);
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+SDR 64 TDI (0000000008390040);
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+SDR 64 TDI (e000000028390040);
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+SDR 64 TDI (ffffffff18390040);
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+SDR 64 TDI (ffffffff38390040);
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+SDR 64 TDI (0000007f04390040);
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+SDR 64 TDI (403f005424390040);
+RUNTEST 0.002 SEC;
+SDR 64 TDI (f1f0000014390040);
+RUNTEST 0.002 SEC;
+SIR 10 TDI (3fd);
+RUNTEST 100 TCK;
+SDR 64 TDI (00000000000100c0) TDO (90e0000000000000) MASK (ffffffff00000000);
+SDR 64 TDI (00000000200100c0) TDO (086a400000000000) MASK (ffffffff00000000);
+SDR 64 TDI (00000000100100c0) TDO (ffff000000000000) MASK (ffffffff00000000);
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+SDR 64 TDI (000000000ad900c0) TDO (0180c60000000000) MASK (ffffffff00000000);
+SDR 64 TDI (000000002ad900c0) TDO (e663183000000000) MASK (ffffffff00000000);
+SDR 64 TDI (000000001ad900c0) TDO (ffffffff00000000) MASK (ffffffff00000000);
+SDR 64 TDI (000000003ad900c0) TDO (ffffffff00000000) MASK (ffffffff00000000);
+SDR 64 TDI (0000000006d900c0) TDO (0000007f00000000) MASK (ffffffff00000000);
+SDR 64 TDI (0000000026d900c0) TDO (001fffff00000000) MASK (ffffffff00000000);
+SDR 64 TDI (0000000016d900c0) TDO (0001800000000000) MASK (ffffffff00000000);
+SDR 64 TDI (0000000036d900c0) TDO (0004000000000000) MASK (ffffffff00000000);
+SDR 64 TDI (000000000ed900c0) TDO (0000080000000000) MASK (ffffffff00000000);
+SDR 64 TDI (000000002ed900c0) TDO (e002080000000000) MASK (ffffffff00000000);
+SDR 64 TDI (000000001ed900c0) TDO (ffffffff00000000) MASK (ffffffff00000000);
+SDR 64 TDI (000000003ed900c0) TDO (ffffffff00000000) MASK (ffffffff00000000);
+SDR 64 TDI (0000000001d900c0) TDO (0000007f00000000) MASK (ffffffff00000000);
+SDR 64 TDI (0000000021d900c0) TDO (011fffff00000000) MASK (ffffffff00000000);
+SDR 64 TDI (0000000011d900c0) TDO (0440010a00000000) MASK (ffffffff00000000);
+SDR 64 TDI (0000000031d900c0) TDO (1101042800000000) MASK (ffffffff00000000);
+SDR 64 TDI (0000000009d900c0) TDO (4243422000000000) MASK (ffffffff00000000);
+SDR 64 TDI (0000000029d900c0) TDO (e561104800000000) MASK (ffffffff00000000);
+SDR 64 TDI (0000000019d900c0) TDO (ffffffff00000000) MASK (ffffffff00000000);
+SDR 64 TDI (0000000039d900c0) TDO (ffffffff00000000) MASK (ffffffff00000000);
+SDR 64 TDI (0000000005d900c0) TDO (0000007f00000000) MASK (ffffffff00000000);
+SDR 64 TDI (0000000025d900c0) TDO (001fffff00000000) MASK (ffffffff00000000);
+SDR 64 TDI (0000000015d900c0) TDO (0000000000000000) MASK (ffffffff00000000);
+SDR 64 TDI (0000000035d900c0) TDO (0000000000000000) MASK (ffffffff00000000);
+SDR 64 TDI (000000000dd900c0) TDO (0000000000000000) MASK (ffffffff00000000);
+SDR 64 TDI (000000002dd900c0) TDO (e000000000000000) MASK (ffffffff00000000);
+SDR 64 TDI (000000001dd900c0) TDO (ffffffff00000000) MASK (ffffffff00000000);
+SDR 64 TDI (000000003dd900c0) TDO (ffffffff00000000) MASK (ffffffff00000000);
+SDR 64 TDI (0000000003d900c0) TDO (0000007f00000000) MASK (ffffffff00000000);
+SDR 64 TDI (0000000023d900c0) TDO (001fffff00000000) MASK (ffffffff00000000);
+SDR 64 TDI (0000000013d900c0) TDO (0000000000000000) MASK (ffffffff00000000);
+SDR 64 TDI (0000000033d900c0) TDO (0000000000000000) MASK (ffffffff00000000);
+SDR 64 TDI (000000000bd900c0) TDO (0000000000000000) MASK (ffffffff00000000);
+SDR 64 TDI (000000002bd900c0) TDO (e000000000000000) MASK (ffffffff00000000);
+SDR 64 TDI (000000001bd900c0) TDO (ffffffff00000000) MASK (ffffffff00000000);
+SDR 64 TDI (000000003bd900c0) TDO (ffffffff00000000) MASK (ffffffff00000000);
+SDR 64 TDI (0000000007d900c0) TDO (0000007f00000000) MASK (ffffffff00000000);
+SDR 64 TDI (0000000027d900c0) TDO (001fffff00000000) MASK (ffffffff00000000);
+SDR 64 TDI (0000000017d900c0) TDO (0000000000000000) MASK (ffffffff00000000);
+SDR 64 TDI (0000000037d900c0) TDO (0000000000000000) MASK (ffffffff00000000);
+SDR 64 TDI (000000000fd900c0) TDO (0000000000000000) MASK (ffffffff00000000);
+SDR 64 TDI (000000002fd900c0) TDO (e000000000000000) MASK (ffffffff00000000);
+SDR 64 TDI (000000001fd900c0) TDO (ffffffff00000000) MASK (ffffffff00000000);
+SDR 64 TDI (000000003fd900c0) TDO (ffffffff00000000) MASK (ffffffff00000000);
+SDR 64 TDI (00000000003900c0) TDO (0000007f00000000) MASK (ffffffff00000000);
+SDR 64 TDI (00000000203900c0) TDO (001fffff00000000) MASK (ffffffff00000000);
+SDR 64 TDI (00000000103900c0) TDO (0000000000000000) MASK (ffffffff00000000);
+SDR 64 TDI (00000000303900c0) TDO (0000000000000000) MASK (ffffffff00000000);
+SDR 64 TDI (00000000083900c0) TDO (0000000000000000) MASK (ffffffff00000000);
+SDR 64 TDI (00000000283900c0) TDO (e000000000000000) MASK (ffffffff00000000);
+SDR 64 TDI (00000000183900c0) TDO (ffffffff00000000) MASK (ffffffff00000000);
+SDR 64 TDI (00000000383900c0) TDO (ffffffff00000000) MASK (ffffffff00000000);
+SDR 64 TDI (00000000043900c0) TDO (0000007f00000000) MASK (ffffffff00000000);
+SDR 64 TDI (00000000243900c0) TDO (403f005400000000) MASK (ffffffff00000000);
+SDR 64 TDI (00000000143900c0) TDO (f1f0000000000000) MASK (ffffffff00000000);
+SIR 10 TDI (3f7);
+RUNTEST 100 TCK;
diff --git a/hardware/portapack_h4m/CPLD/Supra/portapack_h4m_cpld_routed.v b/hardware/portapack_h4m/CPLD/Supra/portapack_h4m_cpld_routed.v
new file mode 100644
index 00000000..0e6ee1d6
--- /dev/null
+++ b/hardware/portapack_h4m/CPLD/Supra/portapack_h4m_cpld_routed.v
@@ -0,0 +1,2342 @@
+`timescale 1 ps/ 1 ps
+
+module top(
+	MCU_D,
+	MCU_DIR,
+	MCU_IO_STBX,
+	MCU_LCD_WRX,
+	MCU_ADDR,
+	MCU_LCD_TE,
+	MCU_P2_8,
+	MCU_LCD_RDX,
+	TP_U,
+	TP_D,
+	TP_L,
+	TP_R,
+	SW_SEL,
+	SW_ROT_A,
+	SW_ROT_B,
+	SW_U,
+	SW_D,
+	SW_L,
+	SW_R,
+	LCD_RESETX,
+	LCD_RS,
+	LCD_WRX,
+	LCD_RDX,
+	LCD_DB,
+	LCD_TE,
+	LCD_BACKLIGHT,
+	SYSOFF,
+	AUDIO_RESETX,
+	REF_EN,
+	GPS_RESETX,
+	GPS_TX_READY,
+	GPS_TIMEPULSE,
+	DEVICE_RESET,
+	DEVICE_RESET_V);
+output	[7:0] MCU_D;
+input	MCU_DIR;
+input	MCU_IO_STBX;
+input	MCU_LCD_WRX;
+input	MCU_ADDR;
+output	MCU_LCD_TE;
+input	MCU_P2_8;
+input	MCU_LCD_RDX;
+output	TP_U;
+output	TP_D;
+output	TP_L;
+output	TP_R;
+input	SW_SEL;
+input	SW_ROT_A;
+input	SW_ROT_B;
+input	SW_U;
+input	SW_D;
+input	SW_L;
+input	SW_R;
+output	LCD_RESETX;
+output	LCD_RS;
+output	LCD_WRX;
+output	LCD_RDX;
+output	[15:0] LCD_DB;
+input	LCD_TE;
+output	LCD_BACKLIGHT;
+output	SYSOFF;
+output	AUDIO_RESETX;
+output	REF_EN;
+output	GPS_RESETX;
+input	GPS_TX_READY;
+input	GPS_TIMEPULSE;
+input	DEVICE_RESET;
+input	DEVICE_RESET_V;
+
+//wire	gnd;
+//wire	vcc;
+wire	AsyncReset_X1_Y15_GND;
+wire	AsyncReset_X1_Y19_GND;
+wire	AsyncReset_X1_Y20_GND;
+wire	AsyncReset_X1_Y21_GND;
+wire	AsyncReset_X1_Y24_GND;
+wire	AsyncReset_X1_Y26_GND;
+wire	\DEVICE_RESET_V~input_o ;
+wire	\DEVICE_RESET~input_o ;
+wire	\GPS_TIMEPULSE~input_o ;
+wire	\GPS_TX_READY~input_o ;
+wire	\LCD_DB[0]~input_o ;
+wire	\LCD_DB[10]~input_o ;
+wire	\LCD_DB[11]~input_o ;
+wire	\LCD_DB[12]~input_o ;
+wire	\LCD_DB[13]~input_o ;
+wire	\LCD_DB[14]~input_o ;
+wire	\LCD_DB[15]~input_o ;
+wire	\LCD_DB[1]~input_o ;
+wire	\LCD_DB[2]~input_o ;
+wire	\LCD_DB[3]~input_o ;
+wire	\LCD_DB[4]~input_o ;
+wire	\LCD_DB[5]~input_o ;
+wire	\LCD_DB[6]~input_o ;
+wire	\LCD_DB[7]~input_o ;
+wire	\LCD_DB[8]~input_o ;
+wire	\LCD_DB[9]~input_o ;
+wire	\LCD_TE~input_o ;
+wire	\MCU_ADDR~input_o ;
+wire	\MCU_DIR~input_o ;
+wire	\MCU_D[0]~input_o ;
+wire	\MCU_D[1]~input_o ;
+wire	\MCU_D[2]~input_o ;
+wire	\MCU_D[3]~input_o ;
+wire	\MCU_D[4]~input_o ;
+wire	\MCU_D[5]~input_o ;
+wire	\MCU_D[6]~input_o ;
+wire	\MCU_D[7]~input_o ;
+wire	\MCU_IO_STBX~input_o ;
+wire	\MCU_IO_STBX~inputclkctrl_outclk ;
+wire	\MCU_IO_STBX~inputclkctrl_outclk__lcd_reset_q~0_combout_X1_Y15_SIG_SIG ;
+wire	\MCU_IO_STBX~inputclkctrl_outclk__tp_q[3]~0_combout_X1_Y15_SIG_SIG ;
+wire	\MCU_LCD_RDX~input_o ;
+wire	\MCU_LCD_RDX~inputclkctrl_outclk ;
+wire	\MCU_LCD_RDX~inputclkctrl_outclk_X1_Y19_SIG_VCC ;
+wire	\MCU_LCD_RDX~inputclkctrl_outclk_X1_Y21_SIG_VCC ;
+wire	\MCU_LCD_RDX~inputclkctrl_outclk_X1_Y24_SIG_VCC ;
+wire	\MCU_LCD_RDX~inputclkctrl_outclk_X1_Y26_SIG_VCC ;
+wire	\MCU_LCD_WRX~input_o ;
+wire	\MCU_LCD_WRX~inputclkctrl_outclk ;
+wire	\MCU_LCD_WRX~inputclkctrl_outclk_X1_Y20_INV_VCC ;
+wire	\MCU_LCD_WRX~inputclkctrl_outclk_X1_Y26_INV_VCC ;
+wire	\MCU_P2_8~input_o ;
+wire	\SW_D~input_o ;
+wire	\SW_L~input_o ;
+wire	\SW_ROT_A~input_o ;
+wire	\SW_ROT_B~input_o ;
+wire	\SW_R~input_o ;
+wire	\SW_SEL~input_o ;
+wire	\SW_U~input_o ;
+wire	SyncLoad_X1_Y15_VCC;
+wire	SyncLoad_X1_Y19_VCC;
+wire	SyncLoad_X1_Y20_VCC;
+wire	SyncLoad_X1_Y21_VCC;
+wire	SyncLoad_X1_Y24_VCC;
+wire	SyncLoad_X1_Y26_VCC;
+wire	SyncReset_X1_Y15_GND;
+wire	SyncReset_X1_Y19_GND;
+wire	SyncReset_X1_Y20_GND;
+wire	SyncReset_X1_Y21_GND;
+wire	SyncReset_X1_Y24_GND;
+wire	SyncReset_X1_Y26_GND;
+wire	\audio_reset_q~0_combout ;
+wire	\audio_reset_q~q ;
+tri1	devclrn;
+tri1	devoe;
+tri1	devpor;
+wire	\lcd_backlight_q~feeder_combout ;
+wire	\lcd_backlight_q~q ;
+wire	[7:0] lcd_data_in_q;
+//wire	lcd_data_in_q[0];
+//wire	lcd_data_in_q[1];
+//wire	lcd_data_in_q[2];
+//wire	lcd_data_in_q[3];
+//wire	lcd_data_in_q[4];
+//wire	lcd_data_in_q[5];
+//wire	lcd_data_in_q[6];
+//wire	lcd_data_in_q[7];
+wire	[7:0] lcd_data_out_q;
+//wire	lcd_data_out_q[0];
+wire	\lcd_data_out_q[0]~feeder_combout ;
+//wire	lcd_data_out_q[1];
+wire	\lcd_data_out_q[1]~feeder_combout ;
+//wire	lcd_data_out_q[2];
+wire	\lcd_data_out_q[2]~feeder_combout ;
+//wire	lcd_data_out_q[3];
+//wire	lcd_data_out_q[4];
+wire	\lcd_data_out_q[4]~feeder_combout ;
+//wire	lcd_data_out_q[5];
+//wire	lcd_data_out_q[6];
+//wire	lcd_data_out_q[7];
+wire	\lcd_data_out_q[7]~feeder_combout ;
+wire	\lcd_reset_q~0_combout ;
+wire	\lcd_reset_q~1_combout ;
+wire	\lcd_reset_q~q ;
+wire	\mcu_data_out[0]~0_combout ;
+wire	\mcu_data_out[0]~1_combout ;
+wire	\mcu_data_out[1]~2_combout ;
+wire	\mcu_data_out[1]~3_combout ;
+wire	\mcu_data_out[2]~4_combout ;
+wire	\mcu_data_out[2]~5_combout ;
+wire	\mcu_data_out[3]~6_combout ;
+wire	\mcu_data_out[3]~7_combout ;
+wire	\mcu_data_out[4]~8_combout ;
+wire	\mcu_data_out[4]~9_combout ;
+wire	\mcu_data_out[5]~10_combout ;
+wire	\mcu_data_out[5]~11_combout ;
+wire	\mcu_data_out[6]~12_combout ;
+wire	\mcu_data_out[6]~13_combout ;
+wire	\mcu_data_out[7]~14_combout ;
+wire	\mcu_data_out[7]~15_combout ;
+wire	\ref_en_q~feeder_combout ;
+wire	\ref_en_q~q ;
+wire	\sysoff_q~feeder_combout ;
+wire	\sysoff_q~q ;
+wire	[7:0] tp_q;
+//wire	tp_q[0];
+//wire	tp_q[1];
+//wire	tp_q[2];
+wire	\tp_q[2]~feeder_combout ;
+//wire	tp_q[3];
+wire	\tp_q[3]~0_combout ;
+//wire	tp_q[4];
+wire	\tp_q[4]~feeder_combout ;
+//wire	tp_q[5];
+//wire	tp_q[6];
+wire	\tp_q[6]~feeder_combout ;
+//wire	tp_q[7];
+wire	\tp_q[7]~feeder_combout ;
+wire	unknown;
+wire	\~ALTERA_ASDO_DATA1~~ibuf_o ;
+wire	\~ALTERA_ASDO_DATA1~~padout ;
+wire	\~ALTERA_DATA0~~ibuf_o ;
+wire	\~ALTERA_DATA0~~padout ;
+wire	\~ALTERA_FLASH_nCE_nCSO~~ibuf_o ;
+wire	\~ALTERA_FLASH_nCE_nCSO~~padout ;
+
+wire vcc;
+wire gnd;
+assign vcc = 1'b1;
+assign gnd = 1'b0;
+
+alta_io \AUDIO_RESETX~output (
+	.datain(\audio_reset_q~q ),
+	.oe(vcc),
+	.padio(AUDIO_RESETX),
+	.combout());
+defparam \AUDIO_RESETX~output .coord_x = 7;
+defparam \AUDIO_RESETX~output .coord_y = 2;
+defparam \AUDIO_RESETX~output .coord_z = 4;
+defparam \AUDIO_RESETX~output .PRG_DELAYB = 1'b1;
+defparam \AUDIO_RESETX~output .RX_SEL = 1'b0;
+defparam \AUDIO_RESETX~output .PDCNTL = 2'b01;
+defparam \AUDIO_RESETX~output .NDCNTL = 2'b01;
+defparam \AUDIO_RESETX~output .PRG_SLR = 1'b1;
+defparam \AUDIO_RESETX~output .CFG_KEEP = 2'b00;
+defparam \AUDIO_RESETX~output .PU = 4'b0000;
+
+alta_io \DEVICE_RESET_V~input (
+	.datain(gnd),
+	.oe(gnd),
+	.padio(DEVICE_RESET_V),
+	.combout(\DEVICE_RESET_V~input_o ));
+defparam \DEVICE_RESET_V~input .coord_x = 4;
+defparam \DEVICE_RESET_V~input .coord_y = 0;
+defparam \DEVICE_RESET_V~input .coord_z = 5;
+defparam \DEVICE_RESET_V~input .PRG_DELAYB = 1'b1;
+defparam \DEVICE_RESET_V~input .RX_SEL = 1'b0;
+defparam \DEVICE_RESET_V~input .PDCNTL = 2'b11;
+defparam \DEVICE_RESET_V~input .NDCNTL = 2'b11;
+defparam \DEVICE_RESET_V~input .PRG_SLR = 1'b0;
+defparam \DEVICE_RESET_V~input .CFG_KEEP = 2'b00;
+defparam \DEVICE_RESET_V~input .PU = 4'b0000;
+
+alta_io \DEVICE_RESET~input (
+	.datain(gnd),
+	.oe(gnd),
+	.padio(DEVICE_RESET),
+	.combout(\DEVICE_RESET~input_o ));
+defparam \DEVICE_RESET~input .coord_x = 6;
+defparam \DEVICE_RESET~input .coord_y = 0;
+defparam \DEVICE_RESET~input .coord_z = 0;
+defparam \DEVICE_RESET~input .PRG_DELAYB = 1'b1;
+defparam \DEVICE_RESET~input .RX_SEL = 1'b0;
+defparam \DEVICE_RESET~input .PDCNTL = 2'b11;
+defparam \DEVICE_RESET~input .NDCNTL = 2'b11;
+defparam \DEVICE_RESET~input .PRG_SLR = 1'b0;
+defparam \DEVICE_RESET~input .CFG_KEEP = 2'b00;
+defparam \DEVICE_RESET~input .PU = 4'b0000;
+
+alta_io \GPS_RESETX~output (
+	.datain(vcc),
+	.oe(vcc),
+	.padio(GPS_RESETX),
+	.combout());
+defparam \GPS_RESETX~output .coord_x = 7;
+defparam \GPS_RESETX~output .coord_y = 3;
+defparam \GPS_RESETX~output .coord_z = 0;
+defparam \GPS_RESETX~output .PRG_DELAYB = 1'b1;
+defparam \GPS_RESETX~output .RX_SEL = 1'b0;
+defparam \GPS_RESETX~output .PDCNTL = 2'b01;
+defparam \GPS_RESETX~output .NDCNTL = 2'b01;
+defparam \GPS_RESETX~output .PRG_SLR = 1'b1;
+defparam \GPS_RESETX~output .CFG_KEEP = 2'b00;
+defparam \GPS_RESETX~output .PU = 4'b0000;
+
+alta_io \GPS_TIMEPULSE~input (
+	.datain(gnd),
+	.oe(gnd),
+	.padio(GPS_TIMEPULSE),
+	.combout(\GPS_TIMEPULSE~input_o ));
+defparam \GPS_TIMEPULSE~input .coord_x = 6;
+defparam \GPS_TIMEPULSE~input .coord_y = 4;
+defparam \GPS_TIMEPULSE~input .coord_z = 5;
+defparam \GPS_TIMEPULSE~input .PRG_DELAYB = 1'b1;
+defparam \GPS_TIMEPULSE~input .RX_SEL = 1'b0;
+defparam \GPS_TIMEPULSE~input .PDCNTL = 2'b01;
+defparam \GPS_TIMEPULSE~input .NDCNTL = 2'b01;
+defparam \GPS_TIMEPULSE~input .PRG_SLR = 1'b1;
+defparam \GPS_TIMEPULSE~input .CFG_KEEP = 2'b00;
+defparam \GPS_TIMEPULSE~input .PU = 4'b1000;
+
+alta_io \GPS_TX_READY~input (
+	.datain(gnd),
+	.oe(gnd),
+	.padio(GPS_TX_READY),
+	.combout(\GPS_TX_READY~input_o ));
+defparam \GPS_TX_READY~input .coord_x = 6;
+defparam \GPS_TX_READY~input .coord_y = 4;
+defparam \GPS_TX_READY~input .coord_z = 4;
+defparam \GPS_TX_READY~input .PRG_DELAYB = 1'b1;
+defparam \GPS_TX_READY~input .RX_SEL = 1'b0;
+defparam \GPS_TX_READY~input .PDCNTL = 2'b01;
+defparam \GPS_TX_READY~input .NDCNTL = 2'b01;
+defparam \GPS_TX_READY~input .PRG_SLR = 1'b1;
+defparam \GPS_TX_READY~input .CFG_KEEP = 2'b00;
+defparam \GPS_TX_READY~input .PU = 4'b1000;
+
+alta_io \LCD_BACKLIGHT~output (
+	.datain(\lcd_backlight_q~q ),
+	.oe(vcc),
+	.padio(LCD_BACKLIGHT),
+	.combout());
+defparam \LCD_BACKLIGHT~output .coord_x = 5;
+defparam \LCD_BACKLIGHT~output .coord_y = 4;
+defparam \LCD_BACKLIGHT~output .coord_z = 4;
+defparam \LCD_BACKLIGHT~output .PRG_DELAYB = 1'b1;
+defparam \LCD_BACKLIGHT~output .RX_SEL = 1'b0;
+defparam \LCD_BACKLIGHT~output .PDCNTL = 2'b01;
+defparam \LCD_BACKLIGHT~output .NDCNTL = 2'b01;
+defparam \LCD_BACKLIGHT~output .PRG_SLR = 1'b1;
+defparam \LCD_BACKLIGHT~output .CFG_KEEP = 2'b00;
+defparam \LCD_BACKLIGHT~output .PU = 4'b0000;
+
+alta_io \LCD_DB[0]~output (
+	.datain(\MCU_D[0]~input_o ),
+	.oe(\MCU_LCD_RDX~input_o ),
+	.padio(LCD_DB[0]),
+	.combout(\LCD_DB[0]~input_o ));
+defparam \LCD_DB[0]~output .coord_x = 2;
+defparam \LCD_DB[0]~output .coord_y = 4;
+defparam \LCD_DB[0]~output .coord_z = 1;
+defparam \LCD_DB[0]~output .PRG_DELAYB = 1'b1;
+defparam \LCD_DB[0]~output .RX_SEL = 1'b0;
+defparam \LCD_DB[0]~output .PDCNTL = 2'b01;
+defparam \LCD_DB[0]~output .NDCNTL = 2'b01;
+defparam \LCD_DB[0]~output .PRG_SLR = 1'b1;
+defparam \LCD_DB[0]~output .CFG_KEEP = 2'b00;
+defparam \LCD_DB[0]~output .PU = 4'b1000;
+
+alta_io \LCD_DB[10]~output (
+	.datain(lcd_data_out_q[2]),
+	.oe(\MCU_LCD_RDX~input_o ),
+	.padio(LCD_DB[10]),
+	.combout(\LCD_DB[10]~input_o ));
+defparam \LCD_DB[10]~output .coord_x = 4;
+defparam \LCD_DB[10]~output .coord_y = 4;
+defparam \LCD_DB[10]~output .coord_z = 0;
+defparam \LCD_DB[10]~output .PRG_DELAYB = 1'b1;
+defparam \LCD_DB[10]~output .RX_SEL = 1'b0;
+defparam \LCD_DB[10]~output .PDCNTL = 2'b01;
+defparam \LCD_DB[10]~output .NDCNTL = 2'b01;
+defparam \LCD_DB[10]~output .PRG_SLR = 1'b1;
+defparam \LCD_DB[10]~output .CFG_KEEP = 2'b00;
+defparam \LCD_DB[10]~output .PU = 4'b1000;
+
+alta_io \LCD_DB[11]~output (
+	.datain(lcd_data_out_q[3]),
+	.oe(\MCU_LCD_RDX~input_o ),
+	.padio(LCD_DB[11]),
+	.combout(\LCD_DB[11]~input_o ));
+defparam \LCD_DB[11]~output .coord_x = 4;
+defparam \LCD_DB[11]~output .coord_y = 4;
+defparam \LCD_DB[11]~output .coord_z = 1;
+defparam \LCD_DB[11]~output .PRG_DELAYB = 1'b1;
+defparam \LCD_DB[11]~output .RX_SEL = 1'b0;
+defparam \LCD_DB[11]~output .PDCNTL = 2'b01;
+defparam \LCD_DB[11]~output .NDCNTL = 2'b01;
+defparam \LCD_DB[11]~output .PRG_SLR = 1'b1;
+defparam \LCD_DB[11]~output .CFG_KEEP = 2'b00;
+defparam \LCD_DB[11]~output .PU = 4'b1000;
+
+alta_io \LCD_DB[12]~output (
+	.datain(lcd_data_out_q[4]),
+	.oe(\MCU_LCD_RDX~input_o ),
+	.padio(LCD_DB[12]),
+	.combout(\LCD_DB[12]~input_o ));
+defparam \LCD_DB[12]~output .coord_x = 4;
+defparam \LCD_DB[12]~output .coord_y = 4;
+defparam \LCD_DB[12]~output .coord_z = 2;
+defparam \LCD_DB[12]~output .PRG_DELAYB = 1'b1;
+defparam \LCD_DB[12]~output .RX_SEL = 1'b0;
+defparam \LCD_DB[12]~output .PDCNTL = 2'b01;
+defparam \LCD_DB[12]~output .NDCNTL = 2'b01;
+defparam \LCD_DB[12]~output .PRG_SLR = 1'b1;
+defparam \LCD_DB[12]~output .CFG_KEEP = 2'b00;
+defparam \LCD_DB[12]~output .PU = 4'b1000;
+
+alta_io \LCD_DB[13]~output (
+	.datain(lcd_data_out_q[5]),
+	.oe(\MCU_LCD_RDX~input_o ),
+	.padio(LCD_DB[13]),
+	.combout(\LCD_DB[13]~input_o ));
+defparam \LCD_DB[13]~output .coord_x = 4;
+defparam \LCD_DB[13]~output .coord_y = 4;
+defparam \LCD_DB[13]~output .coord_z = 3;
+defparam \LCD_DB[13]~output .PRG_DELAYB = 1'b1;
+defparam \LCD_DB[13]~output .RX_SEL = 1'b0;
+defparam \LCD_DB[13]~output .PDCNTL = 2'b01;
+defparam \LCD_DB[13]~output .NDCNTL = 2'b01;
+defparam \LCD_DB[13]~output .PRG_SLR = 1'b1;
+defparam \LCD_DB[13]~output .CFG_KEEP = 2'b00;
+defparam \LCD_DB[13]~output .PU = 4'b1000;
+
+alta_io \LCD_DB[14]~output (
+	.datain(lcd_data_out_q[6]),
+	.oe(\MCU_LCD_RDX~input_o ),
+	.padio(LCD_DB[14]),
+	.combout(\LCD_DB[14]~input_o ));
+defparam \LCD_DB[14]~output .coord_x = 4;
+defparam \LCD_DB[14]~output .coord_y = 4;
+defparam \LCD_DB[14]~output .coord_z = 4;
+defparam \LCD_DB[14]~output .PRG_DELAYB = 1'b1;
+defparam \LCD_DB[14]~output .RX_SEL = 1'b0;
+defparam \LCD_DB[14]~output .PDCNTL = 2'b01;
+defparam \LCD_DB[14]~output .NDCNTL = 2'b01;
+defparam \LCD_DB[14]~output .PRG_SLR = 1'b1;
+defparam \LCD_DB[14]~output .CFG_KEEP = 2'b00;
+defparam \LCD_DB[14]~output .PU = 4'b1000;
+
+alta_io \LCD_DB[15]~output (
+	.datain(lcd_data_out_q[7]),
+	.oe(\MCU_LCD_RDX~input_o ),
+	.padio(LCD_DB[15]),
+	.combout(\LCD_DB[15]~input_o ));
+defparam \LCD_DB[15]~output .coord_x = 5;
+defparam \LCD_DB[15]~output .coord_y = 4;
+defparam \LCD_DB[15]~output .coord_z = 0;
+defparam \LCD_DB[15]~output .PRG_DELAYB = 1'b1;
+defparam \LCD_DB[15]~output .RX_SEL = 1'b0;
+defparam \LCD_DB[15]~output .PDCNTL = 2'b01;
+defparam \LCD_DB[15]~output .NDCNTL = 2'b01;
+defparam \LCD_DB[15]~output .PRG_SLR = 1'b1;
+defparam \LCD_DB[15]~output .CFG_KEEP = 2'b00;
+defparam \LCD_DB[15]~output .PU = 4'b1000;
+
+alta_io \LCD_DB[1]~output (
+	.datain(\MCU_D[1]~input_o ),
+	.oe(\MCU_LCD_RDX~input_o ),
+	.padio(LCD_DB[1]),
+	.combout(\LCD_DB[1]~input_o ));
+defparam \LCD_DB[1]~output .coord_x = 2;
+defparam \LCD_DB[1]~output .coord_y = 4;
+defparam \LCD_DB[1]~output .coord_z = 2;
+defparam \LCD_DB[1]~output .PRG_DELAYB = 1'b1;
+defparam \LCD_DB[1]~output .RX_SEL = 1'b0;
+defparam \LCD_DB[1]~output .PDCNTL = 2'b01;
+defparam \LCD_DB[1]~output .NDCNTL = 2'b01;
+defparam \LCD_DB[1]~output .PRG_SLR = 1'b1;
+defparam \LCD_DB[1]~output .CFG_KEEP = 2'b00;
+defparam \LCD_DB[1]~output .PU = 4'b1000;
+
+alta_io \LCD_DB[2]~output (
+	.datain(\MCU_D[2]~input_o ),
+	.oe(\MCU_LCD_RDX~input_o ),
+	.padio(LCD_DB[2]),
+	.combout(\LCD_DB[2]~input_o ));
+defparam \LCD_DB[2]~output .coord_x = 2;
+defparam \LCD_DB[2]~output .coord_y = 4;
+defparam \LCD_DB[2]~output .coord_z = 3;
+defparam \LCD_DB[2]~output .PRG_DELAYB = 1'b1;
+defparam \LCD_DB[2]~output .RX_SEL = 1'b0;
+defparam \LCD_DB[2]~output .PDCNTL = 2'b01;
+defparam \LCD_DB[2]~output .NDCNTL = 2'b01;
+defparam \LCD_DB[2]~output .PRG_SLR = 1'b1;
+defparam \LCD_DB[2]~output .CFG_KEEP = 2'b00;
+defparam \LCD_DB[2]~output .PU = 4'b1000;
+
+alta_io \LCD_DB[3]~output (
+	.datain(\MCU_D[3]~input_o ),
+	.oe(\MCU_LCD_RDX~input_o ),
+	.padio(LCD_DB[3]),
+	.combout(\LCD_DB[3]~input_o ));
+defparam \LCD_DB[3]~output .coord_x = 2;
+defparam \LCD_DB[3]~output .coord_y = 4;
+defparam \LCD_DB[3]~output .coord_z = 4;
+defparam \LCD_DB[3]~output .PRG_DELAYB = 1'b1;
+defparam \LCD_DB[3]~output .RX_SEL = 1'b0;
+defparam \LCD_DB[3]~output .PDCNTL = 2'b01;
+defparam \LCD_DB[3]~output .NDCNTL = 2'b01;
+defparam \LCD_DB[3]~output .PRG_SLR = 1'b1;
+defparam \LCD_DB[3]~output .CFG_KEEP = 2'b00;
+defparam \LCD_DB[3]~output .PU = 4'b1000;
+
+alta_io \LCD_DB[4]~output (
+	.datain(\MCU_D[4]~input_o ),
+	.oe(\MCU_LCD_RDX~input_o ),
+	.padio(LCD_DB[4]),
+	.combout(\LCD_DB[4]~input_o ));
+defparam \LCD_DB[4]~output .coord_x = 2;
+defparam \LCD_DB[4]~output .coord_y = 4;
+defparam \LCD_DB[4]~output .coord_z = 5;
+defparam \LCD_DB[4]~output .PRG_DELAYB = 1'b1;
+defparam \LCD_DB[4]~output .RX_SEL = 1'b0;
+defparam \LCD_DB[4]~output .PDCNTL = 2'b01;
+defparam \LCD_DB[4]~output .NDCNTL = 2'b01;
+defparam \LCD_DB[4]~output .PRG_SLR = 1'b1;
+defparam \LCD_DB[4]~output .CFG_KEEP = 2'b00;
+defparam \LCD_DB[4]~output .PU = 4'b1000;
+
+alta_io \LCD_DB[5]~output (
+	.datain(\MCU_D[5]~input_o ),
+	.oe(\MCU_LCD_RDX~input_o ),
+	.padio(LCD_DB[5]),
+	.combout(\LCD_DB[5]~input_o ));
+defparam \LCD_DB[5]~output .coord_x = 3;
+defparam \LCD_DB[5]~output .coord_y = 4;
+defparam \LCD_DB[5]~output .coord_z = 0;
+defparam \LCD_DB[5]~output .PRG_DELAYB = 1'b1;
+defparam \LCD_DB[5]~output .RX_SEL = 1'b0;
+defparam \LCD_DB[5]~output .PDCNTL = 2'b01;
+defparam \LCD_DB[5]~output .NDCNTL = 2'b01;
+defparam \LCD_DB[5]~output .PRG_SLR = 1'b1;
+defparam \LCD_DB[5]~output .CFG_KEEP = 2'b00;
+defparam \LCD_DB[5]~output .PU = 4'b1000;
+
+alta_io \LCD_DB[6]~output (
+	.datain(\MCU_D[6]~input_o ),
+	.oe(\MCU_LCD_RDX~input_o ),
+	.padio(LCD_DB[6]),
+	.combout(\LCD_DB[6]~input_o ));
+defparam \LCD_DB[6]~output .coord_x = 3;
+defparam \LCD_DB[6]~output .coord_y = 4;
+defparam \LCD_DB[6]~output .coord_z = 1;
+defparam \LCD_DB[6]~output .PRG_DELAYB = 1'b1;
+defparam \LCD_DB[6]~output .RX_SEL = 1'b0;
+defparam \LCD_DB[6]~output .PDCNTL = 2'b01;
+defparam \LCD_DB[6]~output .NDCNTL = 2'b01;
+defparam \LCD_DB[6]~output .PRG_SLR = 1'b1;
+defparam \LCD_DB[6]~output .CFG_KEEP = 2'b00;
+defparam \LCD_DB[6]~output .PU = 4'b1000;
+
+alta_io \LCD_DB[7]~output (
+	.datain(\MCU_D[7]~input_o ),
+	.oe(\MCU_LCD_RDX~input_o ),
+	.padio(LCD_DB[7]),
+	.combout(\LCD_DB[7]~input_o ));
+defparam \LCD_DB[7]~output .coord_x = 3;
+defparam \LCD_DB[7]~output .coord_y = 4;
+defparam \LCD_DB[7]~output .coord_z = 2;
+defparam \LCD_DB[7]~output .PRG_DELAYB = 1'b1;
+defparam \LCD_DB[7]~output .RX_SEL = 1'b0;
+defparam \LCD_DB[7]~output .PDCNTL = 2'b01;
+defparam \LCD_DB[7]~output .NDCNTL = 2'b01;
+defparam \LCD_DB[7]~output .PRG_SLR = 1'b1;
+defparam \LCD_DB[7]~output .CFG_KEEP = 2'b00;
+defparam \LCD_DB[7]~output .PU = 4'b1000;
+
+alta_io \LCD_DB[8]~output (
+	.datain(lcd_data_out_q[0]),
+	.oe(\MCU_LCD_RDX~input_o ),
+	.padio(LCD_DB[8]),
+	.combout(\LCD_DB[8]~input_o ));
+defparam \LCD_DB[8]~output .coord_x = 3;
+defparam \LCD_DB[8]~output .coord_y = 4;
+defparam \LCD_DB[8]~output .coord_z = 3;
+defparam \LCD_DB[8]~output .PRG_DELAYB = 1'b1;
+defparam \LCD_DB[8]~output .RX_SEL = 1'b0;
+defparam \LCD_DB[8]~output .PDCNTL = 2'b01;
+defparam \LCD_DB[8]~output .NDCNTL = 2'b01;
+defparam \LCD_DB[8]~output .PRG_SLR = 1'b1;
+defparam \LCD_DB[8]~output .CFG_KEEP = 2'b00;
+defparam \LCD_DB[8]~output .PU = 4'b1000;
+
+alta_io \LCD_DB[9]~output (
+	.datain(lcd_data_out_q[1]),
+	.oe(\MCU_LCD_RDX~input_o ),
+	.padio(LCD_DB[9]),
+	.combout(\LCD_DB[9]~input_o ));
+defparam \LCD_DB[9]~output .coord_x = 3;
+defparam \LCD_DB[9]~output .coord_y = 4;
+defparam \LCD_DB[9]~output .coord_z = 4;
+defparam \LCD_DB[9]~output .PRG_DELAYB = 1'b1;
+defparam \LCD_DB[9]~output .RX_SEL = 1'b0;
+defparam \LCD_DB[9]~output .PDCNTL = 2'b01;
+defparam \LCD_DB[9]~output .NDCNTL = 2'b01;
+defparam \LCD_DB[9]~output .PRG_SLR = 1'b1;
+defparam \LCD_DB[9]~output .CFG_KEEP = 2'b00;
+defparam \LCD_DB[9]~output .PU = 4'b1000;
+
+alta_io \LCD_RDX~output (
+	.datain(\MCU_LCD_RDX~input_o ),
+	.oe(vcc),
+	.padio(LCD_RDX),
+	.combout());
+defparam \LCD_RDX~output .coord_x = 1;
+defparam \LCD_RDX~output .coord_y = 4;
+defparam \LCD_RDX~output .coord_z = 1;
+defparam \LCD_RDX~output .PRG_DELAYB = 1'b1;
+defparam \LCD_RDX~output .RX_SEL = 1'b0;
+defparam \LCD_RDX~output .PDCNTL = 2'b01;
+defparam \LCD_RDX~output .NDCNTL = 2'b01;
+defparam \LCD_RDX~output .PRG_SLR = 1'b1;
+defparam \LCD_RDX~output .CFG_KEEP = 2'b00;
+defparam \LCD_RDX~output .PU = 4'b0000;
+
+alta_io \LCD_RESETX~output (
+	.datain(\lcd_reset_q~q ),
+	.oe(vcc),
+	.padio(LCD_RESETX),
+	.combout());
+defparam \LCD_RESETX~output .coord_x = 2;
+defparam \LCD_RESETX~output .coord_y = 4;
+defparam \LCD_RESETX~output .coord_z = 0;
+defparam \LCD_RESETX~output .PRG_DELAYB = 1'b1;
+defparam \LCD_RESETX~output .RX_SEL = 1'b0;
+defparam \LCD_RESETX~output .PDCNTL = 2'b01;
+defparam \LCD_RESETX~output .NDCNTL = 2'b01;
+defparam \LCD_RESETX~output .PRG_SLR = 1'b1;
+defparam \LCD_RESETX~output .CFG_KEEP = 2'b00;
+defparam \LCD_RESETX~output .PU = 4'b0000;
+
+alta_io \LCD_RS~output (
+	.datain(\MCU_ADDR~input_o ),
+	.oe(vcc),
+	.padio(LCD_RS),
+	.combout());
+defparam \LCD_RS~output .coord_x = 0;
+defparam \LCD_RS~output .coord_y = 3;
+defparam \LCD_RS~output .coord_z = 0;
+defparam \LCD_RS~output .PRG_DELAYB = 1'b1;
+defparam \LCD_RS~output .RX_SEL = 1'b0;
+defparam \LCD_RS~output .PDCNTL = 2'b01;
+defparam \LCD_RS~output .NDCNTL = 2'b01;
+defparam \LCD_RS~output .PRG_SLR = 1'b1;
+defparam \LCD_RS~output .CFG_KEEP = 2'b00;
+defparam \LCD_RS~output .PU = 4'b0000;
+
+alta_io \LCD_TE~input (
+	.datain(gnd),
+	.oe(gnd),
+	.padio(LCD_TE),
+	.combout(\LCD_TE~input_o ));
+defparam \LCD_TE~input .coord_x = 0;
+defparam \LCD_TE~input .coord_y = 3;
+defparam \LCD_TE~input .coord_z = 1;
+defparam \LCD_TE~input .PRG_DELAYB = 1'b1;
+defparam \LCD_TE~input .RX_SEL = 1'b0;
+defparam \LCD_TE~input .PDCNTL = 2'b01;
+defparam \LCD_TE~input .NDCNTL = 2'b01;
+defparam \LCD_TE~input .PRG_SLR = 1'b1;
+defparam \LCD_TE~input .CFG_KEEP = 2'b00;
+defparam \LCD_TE~input .PU = 4'b0000;
+
+alta_io \LCD_WRX~output (
+	.datain(\MCU_LCD_WRX~input_o ),
+	.oe(vcc),
+	.padio(LCD_WRX),
+	.combout());
+defparam \LCD_WRX~output .coord_x = 1;
+defparam \LCD_WRX~output .coord_y = 4;
+defparam \LCD_WRX~output .coord_z = 0;
+defparam \LCD_WRX~output .PRG_DELAYB = 1'b1;
+defparam \LCD_WRX~output .RX_SEL = 1'b0;
+defparam \LCD_WRX~output .PDCNTL = 2'b01;
+defparam \LCD_WRX~output .NDCNTL = 2'b01;
+defparam \LCD_WRX~output .PRG_SLR = 1'b1;
+defparam \LCD_WRX~output .CFG_KEEP = 2'b00;
+defparam \LCD_WRX~output .PU = 4'b0000;
+
+alta_io \MCU_ADDR~input (
+	.datain(gnd),
+	.oe(gnd),
+	.padio(MCU_ADDR),
+	.combout(\MCU_ADDR~input_o ));
+defparam \MCU_ADDR~input .coord_x = 5;
+defparam \MCU_ADDR~input .coord_y = 0;
+defparam \MCU_ADDR~input .coord_z = 3;
+defparam \MCU_ADDR~input .PRG_DELAYB = 1'b1;
+defparam \MCU_ADDR~input .RX_SEL = 1'b0;
+defparam \MCU_ADDR~input .PDCNTL = 2'b01;
+defparam \MCU_ADDR~input .NDCNTL = 2'b01;
+defparam \MCU_ADDR~input .PRG_SLR = 1'b1;
+defparam \MCU_ADDR~input .CFG_KEEP = 2'b00;
+defparam \MCU_ADDR~input .PU = 4'b1000;
+
+alta_io \MCU_DIR~input (
+	.datain(gnd),
+	.oe(gnd),
+	.padio(MCU_DIR),
+	.combout(\MCU_DIR~input_o ));
+defparam \MCU_DIR~input .coord_x = 7;
+defparam \MCU_DIR~input .coord_y = 3;
+defparam \MCU_DIR~input .coord_z = 1;
+defparam \MCU_DIR~input .PRG_DELAYB = 1'b1;
+defparam \MCU_DIR~input .RX_SEL = 1'b0;
+defparam \MCU_DIR~input .PDCNTL = 2'b01;
+defparam \MCU_DIR~input .NDCNTL = 2'b01;
+defparam \MCU_DIR~input .PRG_SLR = 1'b1;
+defparam \MCU_DIR~input .CFG_KEEP = 2'b00;
+defparam \MCU_DIR~input .PU = 4'b1000;
+
+alta_io \MCU_D[0]~output (
+	.datain(\mcu_data_out[0]~1_combout ),
+	.oe(\MCU_DIR~input_o ),
+	.padio(MCU_D[0]),
+	.combout(\MCU_D[0]~input_o ));
+defparam \MCU_D[0]~output .coord_x = 4;
+defparam \MCU_D[0]~output .coord_y = 0;
+defparam \MCU_D[0]~output .coord_z = 2;
+defparam \MCU_D[0]~output .PRG_DELAYB = 1'b1;
+defparam \MCU_D[0]~output .RX_SEL = 1'b0;
+defparam \MCU_D[0]~output .PDCNTL = 2'b01;
+defparam \MCU_D[0]~output .NDCNTL = 2'b01;
+defparam \MCU_D[0]~output .PRG_SLR = 1'b1;
+defparam \MCU_D[0]~output .CFG_KEEP = 2'b00;
+defparam \MCU_D[0]~output .PU = 4'b1000;
+
+alta_io \MCU_D[1]~output (
+	.datain(\mcu_data_out[1]~3_combout ),
+	.oe(\MCU_DIR~input_o ),
+	.padio(MCU_D[1]),
+	.combout(\MCU_D[1]~input_o ));
+defparam \MCU_D[1]~output .coord_x = 4;
+defparam \MCU_D[1]~output .coord_y = 0;
+defparam \MCU_D[1]~output .coord_z = 3;
+defparam \MCU_D[1]~output .PRG_DELAYB = 1'b1;
+defparam \MCU_D[1]~output .RX_SEL = 1'b0;
+defparam \MCU_D[1]~output .PDCNTL = 2'b01;
+defparam \MCU_D[1]~output .NDCNTL = 2'b01;
+defparam \MCU_D[1]~output .PRG_SLR = 1'b1;
+defparam \MCU_D[1]~output .CFG_KEEP = 2'b00;
+defparam \MCU_D[1]~output .PU = 4'b1000;
+
+alta_io \MCU_D[2]~output (
+	.datain(\mcu_data_out[2]~5_combout ),
+	.oe(\MCU_DIR~input_o ),
+	.padio(MCU_D[2]),
+	.combout(\MCU_D[2]~input_o ));
+defparam \MCU_D[2]~output .coord_x = 4;
+defparam \MCU_D[2]~output .coord_y = 0;
+defparam \MCU_D[2]~output .coord_z = 0;
+defparam \MCU_D[2]~output .PRG_DELAYB = 1'b1;
+defparam \MCU_D[2]~output .RX_SEL = 1'b0;
+defparam \MCU_D[2]~output .PDCNTL = 2'b01;
+defparam \MCU_D[2]~output .NDCNTL = 2'b01;
+defparam \MCU_D[2]~output .PRG_SLR = 1'b1;
+defparam \MCU_D[2]~output .CFG_KEEP = 2'b00;
+defparam \MCU_D[2]~output .PU = 4'b1000;
+
+alta_io \MCU_D[3]~output (
+	.datain(\mcu_data_out[3]~7_combout ),
+	.oe(\MCU_DIR~input_o ),
+	.padio(MCU_D[3]),
+	.combout(\MCU_D[3]~input_o ));
+defparam \MCU_D[3]~output .coord_x = 3;
+defparam \MCU_D[3]~output .coord_y = 0;
+defparam \MCU_D[3]~output .coord_z = 4;
+defparam \MCU_D[3]~output .PRG_DELAYB = 1'b1;
+defparam \MCU_D[3]~output .RX_SEL = 1'b0;
+defparam \MCU_D[3]~output .PDCNTL = 2'b01;
+defparam \MCU_D[3]~output .NDCNTL = 2'b01;
+defparam \MCU_D[3]~output .PRG_SLR = 1'b1;
+defparam \MCU_D[3]~output .CFG_KEEP = 2'b00;
+defparam \MCU_D[3]~output .PU = 4'b1000;
+
+alta_io \MCU_D[4]~output (
+	.datain(\mcu_data_out[4]~9_combout ),
+	.oe(\MCU_DIR~input_o ),
+	.padio(MCU_D[4]),
+	.combout(\MCU_D[4]~input_o ));
+defparam \MCU_D[4]~output .coord_x = 3;
+defparam \MCU_D[4]~output .coord_y = 0;
+defparam \MCU_D[4]~output .coord_z = 2;
+defparam \MCU_D[4]~output .PRG_DELAYB = 1'b1;
+defparam \MCU_D[4]~output .RX_SEL = 1'b0;
+defparam \MCU_D[4]~output .PDCNTL = 2'b01;
+defparam \MCU_D[4]~output .NDCNTL = 2'b01;
+defparam \MCU_D[4]~output .PRG_SLR = 1'b1;
+defparam \MCU_D[4]~output .CFG_KEEP = 2'b00;
+defparam \MCU_D[4]~output .PU = 4'b1000;
+
+alta_io \MCU_D[5]~output (
+	.datain(\mcu_data_out[5]~11_combout ),
+	.oe(\MCU_DIR~input_o ),
+	.padio(MCU_D[5]),
+	.combout(\MCU_D[5]~input_o ));
+defparam \MCU_D[5]~output .coord_x = 3;
+defparam \MCU_D[5]~output .coord_y = 0;
+defparam \MCU_D[5]~output .coord_z = 3;
+defparam \MCU_D[5]~output .PRG_DELAYB = 1'b1;
+defparam \MCU_D[5]~output .RX_SEL = 1'b0;
+defparam \MCU_D[5]~output .PDCNTL = 2'b01;
+defparam \MCU_D[5]~output .NDCNTL = 2'b01;
+defparam \MCU_D[5]~output .PRG_SLR = 1'b1;
+defparam \MCU_D[5]~output .CFG_KEEP = 2'b00;
+defparam \MCU_D[5]~output .PU = 4'b1000;
+
+alta_io \MCU_D[6]~output (
+	.datain(\mcu_data_out[6]~13_combout ),
+	.oe(\MCU_DIR~input_o ),
+	.padio(MCU_D[6]),
+	.combout(\MCU_D[6]~input_o ));
+defparam \MCU_D[6]~output .coord_x = 3;
+defparam \MCU_D[6]~output .coord_y = 0;
+defparam \MCU_D[6]~output .coord_z = 1;
+defparam \MCU_D[6]~output .PRG_DELAYB = 1'b1;
+defparam \MCU_D[6]~output .RX_SEL = 1'b0;
+defparam \MCU_D[6]~output .PDCNTL = 2'b01;
+defparam \MCU_D[6]~output .NDCNTL = 2'b01;
+defparam \MCU_D[6]~output .PRG_SLR = 1'b1;
+defparam \MCU_D[6]~output .CFG_KEEP = 2'b00;
+defparam \MCU_D[6]~output .PU = 4'b1000;
+
+alta_io \MCU_D[7]~output (
+	.datain(\mcu_data_out[7]~15_combout ),
+	.oe(\MCU_DIR~input_o ),
+	.padio(MCU_D[7]),
+	.combout(\MCU_D[7]~input_o ));
+defparam \MCU_D[7]~output .coord_x = 3;
+defparam \MCU_D[7]~output .coord_y = 0;
+defparam \MCU_D[7]~output .coord_z = 0;
+defparam \MCU_D[7]~output .PRG_DELAYB = 1'b1;
+defparam \MCU_D[7]~output .RX_SEL = 1'b0;
+defparam \MCU_D[7]~output .PDCNTL = 2'b01;
+defparam \MCU_D[7]~output .NDCNTL = 2'b01;
+defparam \MCU_D[7]~output .PRG_SLR = 1'b1;
+defparam \MCU_D[7]~output .CFG_KEEP = 2'b00;
+defparam \MCU_D[7]~output .PU = 4'b1000;
+
+alta_io \MCU_IO_STBX~input (
+	.datain(gnd),
+	.oe(gnd),
+	.padio(MCU_IO_STBX),
+	.combout(\MCU_IO_STBX~input_o ));
+defparam \MCU_IO_STBX~input .coord_x = 5;
+defparam \MCU_IO_STBX~input .coord_y = 0;
+defparam \MCU_IO_STBX~input .coord_z = 2;
+defparam \MCU_IO_STBX~input .PRG_DELAYB = 1'b1;
+defparam \MCU_IO_STBX~input .RX_SEL = 1'b0;
+defparam \MCU_IO_STBX~input .PDCNTL = 2'b01;
+defparam \MCU_IO_STBX~input .NDCNTL = 2'b01;
+defparam \MCU_IO_STBX~input .PRG_SLR = 1'b1;
+defparam \MCU_IO_STBX~input .CFG_KEEP = 2'b00;
+defparam \MCU_IO_STBX~input .PU = 4'b1000;
+
+alta_io_gclk \MCU_IO_STBX~inputclkctrl (
+	.inclk(\MCU_IO_STBX~input_o ),
+	.outclk(\MCU_IO_STBX~inputclkctrl_outclk ));
+defparam \MCU_IO_STBX~inputclkctrl .coord_x = 0;
+defparam \MCU_IO_STBX~inputclkctrl .coord_y = 2;
+defparam \MCU_IO_STBX~inputclkctrl .coord_z = 1;
+
+alta_io \MCU_LCD_RDX~input (
+	.datain(gnd),
+	.oe(gnd),
+	.padio(MCU_LCD_RDX),
+	.combout(\MCU_LCD_RDX~input_o ));
+defparam \MCU_LCD_RDX~input .coord_x = 5;
+defparam \MCU_LCD_RDX~input .coord_y = 0;
+defparam \MCU_LCD_RDX~input .coord_z = 0;
+defparam \MCU_LCD_RDX~input .PRG_DELAYB = 1'b1;
+defparam \MCU_LCD_RDX~input .RX_SEL = 1'b0;
+defparam \MCU_LCD_RDX~input .PDCNTL = 2'b01;
+defparam \MCU_LCD_RDX~input .NDCNTL = 2'b01;
+defparam \MCU_LCD_RDX~input .PRG_SLR = 1'b1;
+defparam \MCU_LCD_RDX~input .CFG_KEEP = 2'b00;
+defparam \MCU_LCD_RDX~input .PU = 4'b1000;
+
+alta_io_gclk \MCU_LCD_RDX~inputclkctrl (
+	.inclk(\MCU_LCD_RDX~input_o ),
+	.outclk(\MCU_LCD_RDX~inputclkctrl_outclk ));
+defparam \MCU_LCD_RDX~inputclkctrl .coord_x = 7;
+defparam \MCU_LCD_RDX~inputclkctrl .coord_y = 2;
+defparam \MCU_LCD_RDX~inputclkctrl .coord_z = 0;
+
+alta_io \MCU_LCD_TE~output (
+	.datain(\LCD_TE~input_o ),
+	.oe(vcc),
+	.padio(MCU_LCD_TE),
+	.combout());
+defparam \MCU_LCD_TE~output .coord_x = 5;
+defparam \MCU_LCD_TE~output .coord_y = 0;
+defparam \MCU_LCD_TE~output .coord_z = 1;
+defparam \MCU_LCD_TE~output .PRG_DELAYB = 1'b1;
+defparam \MCU_LCD_TE~output .RX_SEL = 1'b0;
+defparam \MCU_LCD_TE~output .PDCNTL = 2'b01;
+defparam \MCU_LCD_TE~output .NDCNTL = 2'b01;
+defparam \MCU_LCD_TE~output .PRG_SLR = 1'b1;
+defparam \MCU_LCD_TE~output .CFG_KEEP = 2'b00;
+defparam \MCU_LCD_TE~output .PU = 4'b0000;
+
+alta_io \MCU_LCD_WRX~input (
+	.datain(gnd),
+	.oe(gnd),
+	.padio(MCU_LCD_WRX),
+	.combout(\MCU_LCD_WRX~input_o ));
+defparam \MCU_LCD_WRX~input .coord_x = 7;
+defparam \MCU_LCD_WRX~input .coord_y = 3;
+defparam \MCU_LCD_WRX~input .coord_z = 2;
+defparam \MCU_LCD_WRX~input .PRG_DELAYB = 1'b1;
+defparam \MCU_LCD_WRX~input .RX_SEL = 1'b0;
+defparam \MCU_LCD_WRX~input .PDCNTL = 2'b01;
+defparam \MCU_LCD_WRX~input .NDCNTL = 2'b01;
+defparam \MCU_LCD_WRX~input .PRG_SLR = 1'b1;
+defparam \MCU_LCD_WRX~input .CFG_KEEP = 2'b00;
+defparam \MCU_LCD_WRX~input .PU = 4'b0000;
+
+alta_io_gclk \MCU_LCD_WRX~inputclkctrl (
+	.inclk(\MCU_LCD_WRX~input_o ),
+	.outclk(\MCU_LCD_WRX~inputclkctrl_outclk ));
+defparam \MCU_LCD_WRX~inputclkctrl .coord_x = 7;
+defparam \MCU_LCD_WRX~inputclkctrl .coord_y = 2;
+defparam \MCU_LCD_WRX~inputclkctrl .coord_z = 1;
+
+alta_io \MCU_P2_8~input (
+	.datain(gnd),
+	.oe(gnd),
+	.padio(MCU_P2_8),
+	.combout(\MCU_P2_8~input_o ));
+defparam \MCU_P2_8~input .coord_x = 5;
+defparam \MCU_P2_8~input .coord_y = 0;
+defparam \MCU_P2_8~input .coord_z = 4;
+defparam \MCU_P2_8~input .PRG_DELAYB = 1'b1;
+defparam \MCU_P2_8~input .RX_SEL = 1'b0;
+defparam \MCU_P2_8~input .PDCNTL = 2'b01;
+defparam \MCU_P2_8~input .NDCNTL = 2'b01;
+defparam \MCU_P2_8~input .PRG_SLR = 1'b1;
+defparam \MCU_P2_8~input .CFG_KEEP = 2'b00;
+defparam \MCU_P2_8~input .PU = 4'b0000;
+
+alta_io \REF_EN~output (
+	.datain(\ref_en_q~q ),
+	.oe(vcc),
+	.padio(REF_EN),
+	.combout());
+defparam \REF_EN~output .coord_x = 7;
+defparam \REF_EN~output .coord_y = 2;
+defparam \REF_EN~output .coord_z = 3;
+defparam \REF_EN~output .PRG_DELAYB = 1'b1;
+defparam \REF_EN~output .RX_SEL = 1'b0;
+defparam \REF_EN~output .PDCNTL = 2'b01;
+defparam \REF_EN~output .NDCNTL = 2'b01;
+defparam \REF_EN~output .PRG_SLR = 1'b1;
+defparam \REF_EN~output .CFG_KEEP = 2'b00;
+defparam \REF_EN~output .PU = 4'b0000;
+
+alta_io \SW_D~input (
+	.datain(gnd),
+	.oe(gnd),
+	.padio(SW_D),
+	.combout(\SW_D~input_o ));
+defparam \SW_D~input .coord_x = 0;
+defparam \SW_D~input .coord_y = 2;
+defparam \SW_D~input .coord_z = 1;
+defparam \SW_D~input .PRG_DELAYB = 1'b1;
+defparam \SW_D~input .RX_SEL = 1'b1;
+defparam \SW_D~input .PDCNTL = 2'b01;
+defparam \SW_D~input .NDCNTL = 2'b01;
+defparam \SW_D~input .PRG_SLR = 1'b1;
+defparam \SW_D~input .CFG_KEEP = 2'b00;
+defparam \SW_D~input .PU = 4'b1000;
+
+alta_io \SW_L~input (
+	.datain(gnd),
+	.oe(gnd),
+	.padio(SW_L),
+	.combout(\SW_L~input_o ));
+defparam \SW_L~input .coord_x = 4;
+defparam \SW_L~input .coord_y = 0;
+defparam \SW_L~input .coord_z = 4;
+defparam \SW_L~input .PRG_DELAYB = 1'b1;
+defparam \SW_L~input .RX_SEL = 1'b1;
+defparam \SW_L~input .PDCNTL = 2'b01;
+defparam \SW_L~input .NDCNTL = 2'b01;
+defparam \SW_L~input .PRG_SLR = 1'b1;
+defparam \SW_L~input .CFG_KEEP = 2'b00;
+defparam \SW_L~input .PU = 4'b1000;
+
+alta_io \SW_ROT_A~input (
+	.datain(gnd),
+	.oe(gnd),
+	.padio(SW_ROT_A),
+	.combout(\SW_ROT_A~input_o ));
+defparam \SW_ROT_A~input .coord_x = 0;
+defparam \SW_ROT_A~input .coord_y = 2;
+defparam \SW_ROT_A~input .coord_z = 2;
+defparam \SW_ROT_A~input .PRG_DELAYB = 1'b1;
+defparam \SW_ROT_A~input .RX_SEL = 1'b1;
+defparam \SW_ROT_A~input .PDCNTL = 2'b01;
+defparam \SW_ROT_A~input .NDCNTL = 2'b01;
+defparam \SW_ROT_A~input .PRG_SLR = 1'b1;
+defparam \SW_ROT_A~input .CFG_KEEP = 2'b00;
+defparam \SW_ROT_A~input .PU = 4'b1000;
+
+alta_io \SW_ROT_B~input (
+	.datain(gnd),
+	.oe(gnd),
+	.padio(SW_ROT_B),
+	.combout(\SW_ROT_B~input_o ));
+defparam \SW_ROT_B~input .coord_x = 0;
+defparam \SW_ROT_B~input .coord_y = 2;
+defparam \SW_ROT_B~input .coord_z = 3;
+defparam \SW_ROT_B~input .PRG_DELAYB = 1'b1;
+defparam \SW_ROT_B~input .RX_SEL = 1'b1;
+defparam \SW_ROT_B~input .PDCNTL = 2'b01;
+defparam \SW_ROT_B~input .NDCNTL = 2'b01;
+defparam \SW_ROT_B~input .PRG_SLR = 1'b1;
+defparam \SW_ROT_B~input .CFG_KEEP = 2'b00;
+defparam \SW_ROT_B~input .PU = 4'b1000;
+
+alta_io \SW_R~input (
+	.datain(gnd),
+	.oe(gnd),
+	.padio(SW_R),
+	.combout(\SW_R~input_o ));
+defparam \SW_R~input .coord_x = 0;
+defparam \SW_R~input .coord_y = 2;
+defparam \SW_R~input .coord_z = 0;
+defparam \SW_R~input .PRG_DELAYB = 1'b1;
+defparam \SW_R~input .RX_SEL = 1'b1;
+defparam \SW_R~input .PDCNTL = 2'b01;
+defparam \SW_R~input .NDCNTL = 2'b01;
+defparam \SW_R~input .PRG_SLR = 1'b1;
+defparam \SW_R~input .CFG_KEEP = 2'b00;
+defparam \SW_R~input .PU = 4'b1000;
+
+alta_io \SW_SEL~input (
+	.datain(gnd),
+	.oe(gnd),
+	.padio(SW_SEL),
+	.combout(\SW_SEL~input_o ));
+defparam \SW_SEL~input .coord_x = 0;
+defparam \SW_SEL~input .coord_y = 2;
+defparam \SW_SEL~input .coord_z = 4;
+defparam \SW_SEL~input .PRG_DELAYB = 1'b1;
+defparam \SW_SEL~input .RX_SEL = 1'b1;
+defparam \SW_SEL~input .PDCNTL = 2'b01;
+defparam \SW_SEL~input .NDCNTL = 2'b01;
+defparam \SW_SEL~input .PRG_SLR = 1'b1;
+defparam \SW_SEL~input .CFG_KEEP = 2'b00;
+defparam \SW_SEL~input .PU = 4'b1000;
+
+alta_io \SW_U~input (
+	.datain(gnd),
+	.oe(gnd),
+	.padio(SW_U),
+	.combout(\SW_U~input_o ));
+defparam \SW_U~input .coord_x = 4;
+defparam \SW_U~input .coord_y = 0;
+defparam \SW_U~input .coord_z = 1;
+defparam \SW_U~input .PRG_DELAYB = 1'b1;
+defparam \SW_U~input .RX_SEL = 1'b1;
+defparam \SW_U~input .PDCNTL = 2'b01;
+defparam \SW_U~input .NDCNTL = 2'b01;
+defparam \SW_U~input .PRG_SLR = 1'b1;
+defparam \SW_U~input .CFG_KEEP = 2'b00;
+defparam \SW_U~input .PU = 4'b1000;
+
+alta_io \SYSOFF~output (
+	.datain(\sysoff_q~q ),
+	.oe(vcc),
+	.padio(SYSOFF),
+	.combout());
+defparam \SYSOFF~output .coord_x = 6;
+defparam \SYSOFF~output .coord_y = 0;
+defparam \SYSOFF~output .coord_z = 1;
+defparam \SYSOFF~output .PRG_DELAYB = 1'b1;
+defparam \SYSOFF~output .RX_SEL = 1'b0;
+defparam \SYSOFF~output .PDCNTL = 2'b11;
+defparam \SYSOFF~output .NDCNTL = 2'b11;
+defparam \SYSOFF~output .PRG_SLR = 1'b0;
+defparam \SYSOFF~output .CFG_KEEP = 2'b00;
+defparam \SYSOFF~output .PU = 4'b0000;
+
+alta_io \TP_D~output (
+	.datain(tp_q[2]),
+	.oe(tp_q[6]),
+	.padio(TP_D),
+	.combout());
+defparam \TP_D~output .coord_x = 0;
+defparam \TP_D~output .coord_y = 3;
+defparam \TP_D~output .coord_z = 4;
+defparam \TP_D~output .PRG_DELAYB = 1'b1;
+defparam \TP_D~output .RX_SEL = 1'b0;
+defparam \TP_D~output .PDCNTL = 2'b11;
+defparam \TP_D~output .NDCNTL = 2'b11;
+defparam \TP_D~output .PRG_SLR = 1'b1;
+defparam \TP_D~output .CFG_KEEP = 2'b00;
+defparam \TP_D~output .PU = 4'b1000;
+
+alta_io \TP_L~output (
+	.datain(tp_q[1]),
+	.oe(tp_q[5]),
+	.padio(TP_L),
+	.combout());
+defparam \TP_L~output .coord_x = 0;
+defparam \TP_L~output .coord_y = 3;
+defparam \TP_L~output .coord_z = 5;
+defparam \TP_L~output .PRG_DELAYB = 1'b1;
+defparam \TP_L~output .RX_SEL = 1'b0;
+defparam \TP_L~output .PDCNTL = 2'b11;
+defparam \TP_L~output .NDCNTL = 2'b11;
+defparam \TP_L~output .PRG_SLR = 1'b1;
+defparam \TP_L~output .CFG_KEEP = 2'b00;
+defparam \TP_L~output .PU = 4'b1000;
+
+alta_io \TP_R~output (
+	.datain(tp_q[0]),
+	.oe(tp_q[4]),
+	.padio(TP_R),
+	.combout());
+defparam \TP_R~output .coord_x = 0;
+defparam \TP_R~output .coord_y = 3;
+defparam \TP_R~output .coord_z = 2;
+defparam \TP_R~output .PRG_DELAYB = 1'b1;
+defparam \TP_R~output .RX_SEL = 1'b0;
+defparam \TP_R~output .PDCNTL = 2'b11;
+defparam \TP_R~output .NDCNTL = 2'b11;
+defparam \TP_R~output .PRG_SLR = 1'b1;
+defparam \TP_R~output .CFG_KEEP = 2'b00;
+defparam \TP_R~output .PU = 4'b1000;
+
+alta_io \TP_U~output (
+	.datain(tp_q[3]),
+	.oe(tp_q[7]),
+	.padio(TP_U),
+	.combout());
+defparam \TP_U~output .coord_x = 0;
+defparam \TP_U~output .coord_y = 3;
+defparam \TP_U~output .coord_z = 6;
+defparam \TP_U~output .PRG_DELAYB = 1'b1;
+defparam \TP_U~output .RX_SEL = 1'b0;
+defparam \TP_U~output .PDCNTL = 2'b11;
+defparam \TP_U~output .NDCNTL = 2'b11;
+defparam \TP_U~output .PRG_SLR = 1'b1;
+defparam \TP_U~output .CFG_KEEP = 2'b00;
+defparam \TP_U~output .PU = 4'b1000;
+
+alta_asyncctrl asyncreset_ctrl_X1_Y15_N0(
+	.Din(),
+	.Dout(AsyncReset_X1_Y15_GND));
+defparam asyncreset_ctrl_X1_Y15_N0.coord_x = 3;
+defparam asyncreset_ctrl_X1_Y15_N0.coord_y = 3;
+defparam asyncreset_ctrl_X1_Y15_N0.coord_z = 0;
+defparam asyncreset_ctrl_X1_Y15_N0.AsyncCtrlMux = 2'b00;
+
+alta_asyncctrl asyncreset_ctrl_X1_Y19_N0(
+	.Din(),
+	.Dout(AsyncReset_X1_Y19_GND));
+defparam asyncreset_ctrl_X1_Y19_N0.coord_x = 3;
+defparam asyncreset_ctrl_X1_Y19_N0.coord_y = 1;
+defparam asyncreset_ctrl_X1_Y19_N0.coord_z = 0;
+defparam asyncreset_ctrl_X1_Y19_N0.AsyncCtrlMux = 2'b00;
+
+alta_asyncctrl asyncreset_ctrl_X1_Y20_N0(
+	.Din(),
+	.Dout(AsyncReset_X1_Y20_GND));
+defparam asyncreset_ctrl_X1_Y20_N0.coord_x = 4;
+defparam asyncreset_ctrl_X1_Y20_N0.coord_y = 3;
+defparam asyncreset_ctrl_X1_Y20_N0.coord_z = 0;
+defparam asyncreset_ctrl_X1_Y20_N0.AsyncCtrlMux = 2'b00;
+
+alta_asyncctrl asyncreset_ctrl_X1_Y21_N0(
+	.Din(),
+	.Dout(AsyncReset_X1_Y21_GND));
+defparam asyncreset_ctrl_X1_Y21_N0.coord_x = 5;
+defparam asyncreset_ctrl_X1_Y21_N0.coord_y = 3;
+defparam asyncreset_ctrl_X1_Y21_N0.coord_z = 0;
+defparam asyncreset_ctrl_X1_Y21_N0.AsyncCtrlMux = 2'b00;
+
+alta_asyncctrl asyncreset_ctrl_X1_Y24_N0(
+	.Din(),
+	.Dout(AsyncReset_X1_Y24_GND));
+defparam asyncreset_ctrl_X1_Y24_N0.coord_x = 5;
+defparam asyncreset_ctrl_X1_Y24_N0.coord_y = 2;
+defparam asyncreset_ctrl_X1_Y24_N0.coord_z = 0;
+defparam asyncreset_ctrl_X1_Y24_N0.AsyncCtrlMux = 2'b00;
+
+alta_asyncctrl asyncreset_ctrl_X1_Y26_N0(
+	.Din(),
+	.Dout(AsyncReset_X1_Y26_GND));
+defparam asyncreset_ctrl_X1_Y26_N0.coord_x = 3;
+defparam asyncreset_ctrl_X1_Y26_N0.coord_y = 2;
+defparam asyncreset_ctrl_X1_Y26_N0.coord_z = 0;
+defparam asyncreset_ctrl_X1_Y26_N0.AsyncCtrlMux = 2'b00;
+
+alta_slice audio_reset_q(
+	.A(\MCU_D[1]~input_o ),
+	.B(vcc),
+	.C(vcc),
+	.D(vcc),
+	.Cin(),
+	.Qin(\audio_reset_q~q ),
+	.Clk(\MCU_IO_STBX~inputclkctrl_outclk__lcd_reset_q~0_combout_X1_Y15_SIG_SIG ),
+	.AsyncReset(AsyncReset_X1_Y15_GND),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\audio_reset_q~0_combout ),
+	.Cout(),
+	.Q(\audio_reset_q~q ));
+defparam audio_reset_q.coord_x = 3;
+defparam audio_reset_q.coord_y = 3;
+defparam audio_reset_q.coord_z = 12;
+defparam audio_reset_q.mask = 16'h5555;
+defparam audio_reset_q.modeMux = 1'b0;
+defparam audio_reset_q.FeedbackMux = 1'b0;
+defparam audio_reset_q.ShiftMux = 1'b0;
+defparam audio_reset_q.BypassEn = 1'b0;
+defparam audio_reset_q.CarryEnb = 1'b1;
+
+alta_clkenctrl clken_ctrl_X1_Y15_N0(
+	.ClkIn(\MCU_IO_STBX~inputclkctrl_outclk ),
+	.ClkEn(\tp_q[3]~0_combout ),
+	.ClkOut(\MCU_IO_STBX~inputclkctrl_outclk__tp_q[3]~0_combout_X1_Y15_SIG_SIG ));
+defparam clken_ctrl_X1_Y15_N0.coord_x = 3;
+defparam clken_ctrl_X1_Y15_N0.coord_y = 3;
+defparam clken_ctrl_X1_Y15_N0.coord_z = 0;
+defparam clken_ctrl_X1_Y15_N0.ClkMux = 2'b10;
+defparam clken_ctrl_X1_Y15_N0.ClkEnMux = 2'b10;
+
+alta_clkenctrl clken_ctrl_X1_Y15_N1(
+	.ClkIn(\MCU_IO_STBX~inputclkctrl_outclk ),
+	.ClkEn(\lcd_reset_q~0_combout ),
+	.ClkOut(\MCU_IO_STBX~inputclkctrl_outclk__lcd_reset_q~0_combout_X1_Y15_SIG_SIG ));
+defparam clken_ctrl_X1_Y15_N1.coord_x = 3;
+defparam clken_ctrl_X1_Y15_N1.coord_y = 3;
+defparam clken_ctrl_X1_Y15_N1.coord_z = 1;
+defparam clken_ctrl_X1_Y15_N1.ClkMux = 2'b10;
+defparam clken_ctrl_X1_Y15_N1.ClkEnMux = 2'b10;
+
+alta_clkenctrl clken_ctrl_X1_Y19_N0(
+	.ClkIn(\MCU_LCD_RDX~inputclkctrl_outclk ),
+	.ClkEn(),
+	.ClkOut(\MCU_LCD_RDX~inputclkctrl_outclk_X1_Y19_SIG_VCC ));
+defparam clken_ctrl_X1_Y19_N0.coord_x = 3;
+defparam clken_ctrl_X1_Y19_N0.coord_y = 1;
+defparam clken_ctrl_X1_Y19_N0.coord_z = 0;
+defparam clken_ctrl_X1_Y19_N0.ClkMux = 2'b10;
+defparam clken_ctrl_X1_Y19_N0.ClkEnMux = 2'b01;
+
+alta_clkenctrl clken_ctrl_X1_Y20_N0(
+	.ClkIn(\MCU_LCD_WRX~inputclkctrl_outclk ),
+	.ClkEn(),
+	.ClkOut(\MCU_LCD_WRX~inputclkctrl_outclk_X1_Y20_INV_VCC ));
+defparam clken_ctrl_X1_Y20_N0.coord_x = 4;
+defparam clken_ctrl_X1_Y20_N0.coord_y = 3;
+defparam clken_ctrl_X1_Y20_N0.coord_z = 0;
+defparam clken_ctrl_X1_Y20_N0.ClkMux = 2'b11;
+defparam clken_ctrl_X1_Y20_N0.ClkEnMux = 2'b01;
+
+alta_clkenctrl clken_ctrl_X1_Y21_N0(
+	.ClkIn(\MCU_LCD_RDX~inputclkctrl_outclk ),
+	.ClkEn(),
+	.ClkOut(\MCU_LCD_RDX~inputclkctrl_outclk_X1_Y21_SIG_VCC ));
+defparam clken_ctrl_X1_Y21_N0.coord_x = 5;
+defparam clken_ctrl_X1_Y21_N0.coord_y = 3;
+defparam clken_ctrl_X1_Y21_N0.coord_z = 0;
+defparam clken_ctrl_X1_Y21_N0.ClkMux = 2'b10;
+defparam clken_ctrl_X1_Y21_N0.ClkEnMux = 2'b01;
+
+alta_clkenctrl clken_ctrl_X1_Y24_N0(
+	.ClkIn(\MCU_LCD_RDX~inputclkctrl_outclk ),
+	.ClkEn(),
+	.ClkOut(\MCU_LCD_RDX~inputclkctrl_outclk_X1_Y24_SIG_VCC ));
+defparam clken_ctrl_X1_Y24_N0.coord_x = 5;
+defparam clken_ctrl_X1_Y24_N0.coord_y = 2;
+defparam clken_ctrl_X1_Y24_N0.coord_z = 0;
+defparam clken_ctrl_X1_Y24_N0.ClkMux = 2'b10;
+defparam clken_ctrl_X1_Y24_N0.ClkEnMux = 2'b01;
+
+alta_clkenctrl clken_ctrl_X1_Y26_N0(
+	.ClkIn(\MCU_LCD_RDX~inputclkctrl_outclk ),
+	.ClkEn(),
+	.ClkOut(\MCU_LCD_RDX~inputclkctrl_outclk_X1_Y26_SIG_VCC ));
+defparam clken_ctrl_X1_Y26_N0.coord_x = 3;
+defparam clken_ctrl_X1_Y26_N0.coord_y = 2;
+defparam clken_ctrl_X1_Y26_N0.coord_z = 0;
+defparam clken_ctrl_X1_Y26_N0.ClkMux = 2'b10;
+defparam clken_ctrl_X1_Y26_N0.ClkEnMux = 2'b01;
+
+alta_clkenctrl clken_ctrl_X1_Y26_N1(
+	.ClkIn(\MCU_LCD_WRX~inputclkctrl_outclk ),
+	.ClkEn(),
+	.ClkOut(\MCU_LCD_WRX~inputclkctrl_outclk_X1_Y26_INV_VCC ));
+defparam clken_ctrl_X1_Y26_N1.coord_x = 3;
+defparam clken_ctrl_X1_Y26_N1.coord_y = 2;
+defparam clken_ctrl_X1_Y26_N1.coord_z = 1;
+defparam clken_ctrl_X1_Y26_N1.ClkMux = 2'b11;
+defparam clken_ctrl_X1_Y26_N1.ClkEnMux = 2'b01;
+
+alta_slice lcd_backlight_q(
+	.A(vcc),
+	.B(vcc),
+	.C(vcc),
+	.D(\MCU_D[7]~input_o ),
+	.Cin(),
+	.Qin(\lcd_backlight_q~q ),
+	.Clk(\MCU_IO_STBX~inputclkctrl_outclk__lcd_reset_q~0_combout_X1_Y15_SIG_SIG ),
+	.AsyncReset(AsyncReset_X1_Y15_GND),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\lcd_backlight_q~feeder_combout ),
+	.Cout(),
+	.Q(\lcd_backlight_q~q ));
+defparam lcd_backlight_q.coord_x = 3;
+defparam lcd_backlight_q.coord_y = 3;
+defparam lcd_backlight_q.coord_z = 8;
+defparam lcd_backlight_q.mask = 16'hFF00;
+defparam lcd_backlight_q.modeMux = 1'b0;
+defparam lcd_backlight_q.FeedbackMux = 1'b0;
+defparam lcd_backlight_q.ShiftMux = 1'b0;
+defparam lcd_backlight_q.BypassEn = 1'b0;
+defparam lcd_backlight_q.CarryEnb = 1'b1;
+
+alta_slice \lcd_data_in_q[0] (
+	.A(vcc),
+	.B(\LCD_DB[8]~input_o ),
+	.C(\LCD_DB[0]~input_o ),
+	.D(\MCU_LCD_RDX~input_o ),
+	.Cin(),
+	.Qin(lcd_data_in_q[0]),
+	.Clk(\MCU_LCD_RDX~inputclkctrl_outclk_X1_Y19_SIG_VCC ),
+	.AsyncReset(AsyncReset_X1_Y19_GND),
+	.SyncReset(SyncReset_X1_Y19_GND),
+	.ShiftData(),
+	.SyncLoad(SyncLoad_X1_Y19_VCC),
+	.LutOut(\mcu_data_out[0]~0_combout ),
+	.Cout(),
+	.Q(lcd_data_in_q[0]));
+defparam \lcd_data_in_q[0] .coord_x = 3;
+defparam \lcd_data_in_q[0] .coord_y = 1;
+defparam \lcd_data_in_q[0] .coord_z = 15;
+defparam \lcd_data_in_q[0] .mask = 16'hF0CC;
+defparam \lcd_data_in_q[0] .modeMux = 1'b0;
+defparam \lcd_data_in_q[0] .FeedbackMux = 1'b1;
+defparam \lcd_data_in_q[0] .ShiftMux = 1'b0;
+defparam \lcd_data_in_q[0] .BypassEn = 1'b1;
+defparam \lcd_data_in_q[0] .CarryEnb = 1'b1;
+
+alta_slice \lcd_data_in_q[1] (
+	.A(vcc),
+	.B(\MCU_LCD_RDX~input_o ),
+	.C(\LCD_DB[1]~input_o ),
+	.D(\LCD_DB[9]~input_o ),
+	.Cin(),
+	.Qin(lcd_data_in_q[1]),
+	.Clk(\MCU_LCD_RDX~inputclkctrl_outclk_X1_Y21_SIG_VCC ),
+	.AsyncReset(AsyncReset_X1_Y21_GND),
+	.SyncReset(SyncReset_X1_Y21_GND),
+	.ShiftData(),
+	.SyncLoad(SyncLoad_X1_Y21_VCC),
+	.LutOut(\mcu_data_out[1]~2_combout ),
+	.Cout(),
+	.Q(lcd_data_in_q[1]));
+defparam \lcd_data_in_q[1] .coord_x = 5;
+defparam \lcd_data_in_q[1] .coord_y = 3;
+defparam \lcd_data_in_q[1] .coord_z = 5;
+defparam \lcd_data_in_q[1] .mask = 16'hF3C0;
+defparam \lcd_data_in_q[1] .modeMux = 1'b0;
+defparam \lcd_data_in_q[1] .FeedbackMux = 1'b1;
+defparam \lcd_data_in_q[1] .ShiftMux = 1'b0;
+defparam \lcd_data_in_q[1] .BypassEn = 1'b1;
+defparam \lcd_data_in_q[1] .CarryEnb = 1'b1;
+
+alta_slice \lcd_data_in_q[2] (
+	.A(vcc),
+	.B(\LCD_DB[10]~input_o ),
+	.C(\LCD_DB[2]~input_o ),
+	.D(\MCU_LCD_RDX~input_o ),
+	.Cin(),
+	.Qin(lcd_data_in_q[2]),
+	.Clk(\MCU_LCD_RDX~inputclkctrl_outclk_X1_Y24_SIG_VCC ),
+	.AsyncReset(AsyncReset_X1_Y24_GND),
+	.SyncReset(SyncReset_X1_Y24_GND),
+	.ShiftData(),
+	.SyncLoad(SyncLoad_X1_Y24_VCC),
+	.LutOut(\mcu_data_out[2]~4_combout ),
+	.Cout(),
+	.Q(lcd_data_in_q[2]));
+defparam \lcd_data_in_q[2] .coord_x = 5;
+defparam \lcd_data_in_q[2] .coord_y = 2;
+defparam \lcd_data_in_q[2] .coord_z = 15;
+defparam \lcd_data_in_q[2] .mask = 16'hF0CC;
+defparam \lcd_data_in_q[2] .modeMux = 1'b0;
+defparam \lcd_data_in_q[2] .FeedbackMux = 1'b1;
+defparam \lcd_data_in_q[2] .ShiftMux = 1'b0;
+defparam \lcd_data_in_q[2] .BypassEn = 1'b1;
+defparam \lcd_data_in_q[2] .CarryEnb = 1'b1;
+
+alta_slice \lcd_data_in_q[3] (
+	.A(\LCD_DB[11]~input_o ),
+	.B(vcc),
+	.C(\LCD_DB[3]~input_o ),
+	.D(\MCU_LCD_RDX~input_o ),
+	.Cin(),
+	.Qin(lcd_data_in_q[3]),
+	.Clk(\MCU_LCD_RDX~inputclkctrl_outclk_X1_Y26_SIG_VCC ),
+	.AsyncReset(AsyncReset_X1_Y26_GND),
+	.SyncReset(SyncReset_X1_Y26_GND),
+	.ShiftData(),
+	.SyncLoad(SyncLoad_X1_Y26_VCC),
+	.LutOut(\mcu_data_out[3]~6_combout ),
+	.Cout(),
+	.Q(lcd_data_in_q[3]));
+defparam \lcd_data_in_q[3] .coord_x = 3;
+defparam \lcd_data_in_q[3] .coord_y = 2;
+defparam \lcd_data_in_q[3] .coord_z = 3;
+defparam \lcd_data_in_q[3] .mask = 16'hF0AA;
+defparam \lcd_data_in_q[3] .modeMux = 1'b0;
+defparam \lcd_data_in_q[3] .FeedbackMux = 1'b1;
+defparam \lcd_data_in_q[3] .ShiftMux = 1'b0;
+defparam \lcd_data_in_q[3] .BypassEn = 1'b1;
+defparam \lcd_data_in_q[3] .CarryEnb = 1'b1;
+
+alta_slice \lcd_data_in_q[4] (
+	.A(vcc),
+	.B(\MCU_LCD_RDX~input_o ),
+	.C(\LCD_DB[4]~input_o ),
+	.D(\LCD_DB[12]~input_o ),
+	.Cin(),
+	.Qin(lcd_data_in_q[4]),
+	.Clk(\MCU_LCD_RDX~inputclkctrl_outclk_X1_Y26_SIG_VCC ),
+	.AsyncReset(AsyncReset_X1_Y26_GND),
+	.SyncReset(SyncReset_X1_Y26_GND),
+	.ShiftData(),
+	.SyncLoad(SyncLoad_X1_Y26_VCC),
+	.LutOut(\mcu_data_out[4]~8_combout ),
+	.Cout(),
+	.Q(lcd_data_in_q[4]));
+defparam \lcd_data_in_q[4] .coord_x = 3;
+defparam \lcd_data_in_q[4] .coord_y = 2;
+defparam \lcd_data_in_q[4] .coord_z = 5;
+defparam \lcd_data_in_q[4] .mask = 16'hF3C0;
+defparam \lcd_data_in_q[4] .modeMux = 1'b0;
+defparam \lcd_data_in_q[4] .FeedbackMux = 1'b1;
+defparam \lcd_data_in_q[4] .ShiftMux = 1'b0;
+defparam \lcd_data_in_q[4] .BypassEn = 1'b1;
+defparam \lcd_data_in_q[4] .CarryEnb = 1'b1;
+
+alta_slice \lcd_data_in_q[5] (
+	.A(\LCD_DB[13]~input_o ),
+	.B(vcc),
+	.C(\LCD_DB[5]~input_o ),
+	.D(\MCU_LCD_RDX~input_o ),
+	.Cin(),
+	.Qin(lcd_data_in_q[5]),
+	.Clk(\MCU_LCD_RDX~inputclkctrl_outclk_X1_Y26_SIG_VCC ),
+	.AsyncReset(AsyncReset_X1_Y26_GND),
+	.SyncReset(SyncReset_X1_Y26_GND),
+	.ShiftData(),
+	.SyncLoad(SyncLoad_X1_Y26_VCC),
+	.LutOut(\mcu_data_out[5]~10_combout ),
+	.Cout(),
+	.Q(lcd_data_in_q[5]));
+defparam \lcd_data_in_q[5] .coord_x = 3;
+defparam \lcd_data_in_q[5] .coord_y = 2;
+defparam \lcd_data_in_q[5] .coord_z = 4;
+defparam \lcd_data_in_q[5] .mask = 16'hF0AA;
+defparam \lcd_data_in_q[5] .modeMux = 1'b0;
+defparam \lcd_data_in_q[5] .FeedbackMux = 1'b1;
+defparam \lcd_data_in_q[5] .ShiftMux = 1'b0;
+defparam \lcd_data_in_q[5] .BypassEn = 1'b1;
+defparam \lcd_data_in_q[5] .CarryEnb = 1'b1;
+
+alta_slice \lcd_data_in_q[6] (
+	.A(vcc),
+	.B(\LCD_DB[14]~input_o ),
+	.C(\LCD_DB[6]~input_o ),
+	.D(\MCU_LCD_RDX~input_o ),
+	.Cin(),
+	.Qin(lcd_data_in_q[6]),
+	.Clk(\MCU_LCD_RDX~inputclkctrl_outclk_X1_Y19_SIG_VCC ),
+	.AsyncReset(AsyncReset_X1_Y19_GND),
+	.SyncReset(SyncReset_X1_Y19_GND),
+	.ShiftData(),
+	.SyncLoad(SyncLoad_X1_Y19_VCC),
+	.LutOut(\mcu_data_out[6]~12_combout ),
+	.Cout(),
+	.Q(lcd_data_in_q[6]));
+defparam \lcd_data_in_q[6] .coord_x = 3;
+defparam \lcd_data_in_q[6] .coord_y = 1;
+defparam \lcd_data_in_q[6] .coord_z = 2;
+defparam \lcd_data_in_q[6] .mask = 16'hF0CC;
+defparam \lcd_data_in_q[6] .modeMux = 1'b0;
+defparam \lcd_data_in_q[6] .FeedbackMux = 1'b1;
+defparam \lcd_data_in_q[6] .ShiftMux = 1'b0;
+defparam \lcd_data_in_q[6] .BypassEn = 1'b1;
+defparam \lcd_data_in_q[6] .CarryEnb = 1'b1;
+
+alta_slice \lcd_data_in_q[7] (
+	.A(vcc),
+	.B(\LCD_DB[15]~input_o ),
+	.C(\LCD_DB[7]~input_o ),
+	.D(\MCU_LCD_RDX~input_o ),
+	.Cin(),
+	.Qin(lcd_data_in_q[7]),
+	.Clk(\MCU_LCD_RDX~inputclkctrl_outclk_X1_Y21_SIG_VCC ),
+	.AsyncReset(AsyncReset_X1_Y21_GND),
+	.SyncReset(SyncReset_X1_Y21_GND),
+	.ShiftData(),
+	.SyncLoad(SyncLoad_X1_Y21_VCC),
+	.LutOut(\mcu_data_out[7]~14_combout ),
+	.Cout(),
+	.Q(lcd_data_in_q[7]));
+defparam \lcd_data_in_q[7] .coord_x = 5;
+defparam \lcd_data_in_q[7] .coord_y = 3;
+defparam \lcd_data_in_q[7] .coord_z = 9;
+defparam \lcd_data_in_q[7] .mask = 16'hF0CC;
+defparam \lcd_data_in_q[7] .modeMux = 1'b0;
+defparam \lcd_data_in_q[7] .FeedbackMux = 1'b1;
+defparam \lcd_data_in_q[7] .ShiftMux = 1'b0;
+defparam \lcd_data_in_q[7] .BypassEn = 1'b1;
+defparam \lcd_data_in_q[7] .CarryEnb = 1'b1;
+
+alta_slice \lcd_data_out_q[0] (
+	.A(vcc),
+	.B(vcc),
+	.C(vcc),
+	.D(\MCU_D[0]~input_o ),
+	.Cin(),
+	.Qin(lcd_data_out_q[0]),
+	.Clk(\MCU_LCD_WRX~inputclkctrl_outclk_X1_Y20_INV_VCC ),
+	.AsyncReset(AsyncReset_X1_Y20_GND),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\lcd_data_out_q[0]~feeder_combout ),
+	.Cout(),
+	.Q(lcd_data_out_q[0]));
+defparam \lcd_data_out_q[0] .coord_x = 4;
+defparam \lcd_data_out_q[0] .coord_y = 3;
+defparam \lcd_data_out_q[0] .coord_z = 15;
+defparam \lcd_data_out_q[0] .mask = 16'hFF00;
+defparam \lcd_data_out_q[0] .modeMux = 1'b0;
+defparam \lcd_data_out_q[0] .FeedbackMux = 1'b0;
+defparam \lcd_data_out_q[0] .ShiftMux = 1'b0;
+defparam \lcd_data_out_q[0] .BypassEn = 1'b0;
+defparam \lcd_data_out_q[0] .CarryEnb = 1'b1;
+
+alta_slice \lcd_data_out_q[1] (
+	.A(vcc),
+	.B(vcc),
+	.C(vcc),
+	.D(\MCU_D[1]~input_o ),
+	.Cin(),
+	.Qin(lcd_data_out_q[1]),
+	.Clk(\MCU_LCD_WRX~inputclkctrl_outclk_X1_Y20_INV_VCC ),
+	.AsyncReset(AsyncReset_X1_Y20_GND),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\lcd_data_out_q[1]~feeder_combout ),
+	.Cout(),
+	.Q(lcd_data_out_q[1]));
+defparam \lcd_data_out_q[1] .coord_x = 4;
+defparam \lcd_data_out_q[1] .coord_y = 3;
+defparam \lcd_data_out_q[1] .coord_z = 0;
+defparam \lcd_data_out_q[1] .mask = 16'hFF00;
+defparam \lcd_data_out_q[1] .modeMux = 1'b0;
+defparam \lcd_data_out_q[1] .FeedbackMux = 1'b0;
+defparam \lcd_data_out_q[1] .ShiftMux = 1'b0;
+defparam \lcd_data_out_q[1] .BypassEn = 1'b0;
+defparam \lcd_data_out_q[1] .CarryEnb = 1'b1;
+
+alta_slice \lcd_data_out_q[2] (
+	.A(vcc),
+	.B(vcc),
+	.C(vcc),
+	.D(\MCU_D[2]~input_o ),
+	.Cin(),
+	.Qin(lcd_data_out_q[2]),
+	.Clk(\MCU_LCD_WRX~inputclkctrl_outclk_X1_Y20_INV_VCC ),
+	.AsyncReset(AsyncReset_X1_Y20_GND),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\lcd_data_out_q[2]~feeder_combout ),
+	.Cout(),
+	.Q(lcd_data_out_q[2]));
+defparam \lcd_data_out_q[2] .coord_x = 4;
+defparam \lcd_data_out_q[2] .coord_y = 3;
+defparam \lcd_data_out_q[2] .coord_z = 5;
+defparam \lcd_data_out_q[2] .mask = 16'hFF00;
+defparam \lcd_data_out_q[2] .modeMux = 1'b0;
+defparam \lcd_data_out_q[2] .FeedbackMux = 1'b0;
+defparam \lcd_data_out_q[2] .ShiftMux = 1'b0;
+defparam \lcd_data_out_q[2] .BypassEn = 1'b0;
+defparam \lcd_data_out_q[2] .CarryEnb = 1'b1;
+
+alta_slice \lcd_data_out_q[3] (
+	.A(),
+	.B(),
+	.C(\MCU_D[3]~input_o ),
+	.D(),
+	.Cin(),
+	.Qin(lcd_data_out_q[3]),
+	.Clk(\MCU_LCD_WRX~inputclkctrl_outclk_X1_Y26_INV_VCC ),
+	.AsyncReset(AsyncReset_X1_Y26_GND),
+	.SyncReset(SyncReset_X1_Y26_GND),
+	.ShiftData(),
+	.SyncLoad(SyncLoad_X1_Y26_VCC),
+	.LutOut(),
+	.Cout(),
+	.Q(lcd_data_out_q[3]));
+defparam \lcd_data_out_q[3] .coord_x = 3;
+defparam \lcd_data_out_q[3] .coord_y = 2;
+defparam \lcd_data_out_q[3] .coord_z = 7;
+defparam \lcd_data_out_q[3] .mask = 16'hFFFF;
+defparam \lcd_data_out_q[3] .modeMux = 1'b1;
+defparam \lcd_data_out_q[3] .FeedbackMux = 1'b0;
+defparam \lcd_data_out_q[3] .ShiftMux = 1'b0;
+defparam \lcd_data_out_q[3] .BypassEn = 1'b1;
+defparam \lcd_data_out_q[3] .CarryEnb = 1'b1;
+
+alta_slice \lcd_data_out_q[4] (
+	.A(vcc),
+	.B(vcc),
+	.C(vcc),
+	.D(\MCU_D[4]~input_o ),
+	.Cin(),
+	.Qin(lcd_data_out_q[4]),
+	.Clk(\MCU_LCD_WRX~inputclkctrl_outclk_X1_Y26_INV_VCC ),
+	.AsyncReset(AsyncReset_X1_Y26_GND),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\lcd_data_out_q[4]~feeder_combout ),
+	.Cout(),
+	.Q(lcd_data_out_q[4]));
+defparam \lcd_data_out_q[4] .coord_x = 3;
+defparam \lcd_data_out_q[4] .coord_y = 2;
+defparam \lcd_data_out_q[4] .coord_z = 6;
+defparam \lcd_data_out_q[4] .mask = 16'hFF00;
+defparam \lcd_data_out_q[4] .modeMux = 1'b0;
+defparam \lcd_data_out_q[4] .FeedbackMux = 1'b0;
+defparam \lcd_data_out_q[4] .ShiftMux = 1'b0;
+defparam \lcd_data_out_q[4] .BypassEn = 1'b0;
+defparam \lcd_data_out_q[4] .CarryEnb = 1'b1;
+
+alta_slice \lcd_data_out_q[5] (
+	.A(),
+	.B(),
+	.C(\MCU_D[5]~input_o ),
+	.D(),
+	.Cin(),
+	.Qin(lcd_data_out_q[5]),
+	.Clk(\MCU_LCD_WRX~inputclkctrl_outclk_X1_Y26_INV_VCC ),
+	.AsyncReset(AsyncReset_X1_Y26_GND),
+	.SyncReset(SyncReset_X1_Y26_GND),
+	.ShiftData(),
+	.SyncLoad(SyncLoad_X1_Y26_VCC),
+	.LutOut(),
+	.Cout(),
+	.Q(lcd_data_out_q[5]));
+defparam \lcd_data_out_q[5] .coord_x = 3;
+defparam \lcd_data_out_q[5] .coord_y = 2;
+defparam \lcd_data_out_q[5] .coord_z = 2;
+defparam \lcd_data_out_q[5] .mask = 16'hFFFF;
+defparam \lcd_data_out_q[5] .modeMux = 1'b1;
+defparam \lcd_data_out_q[5] .FeedbackMux = 1'b0;
+defparam \lcd_data_out_q[5] .ShiftMux = 1'b0;
+defparam \lcd_data_out_q[5] .BypassEn = 1'b1;
+defparam \lcd_data_out_q[5] .CarryEnb = 1'b1;
+
+alta_slice \lcd_data_out_q[6] (
+	.A(),
+	.B(),
+	.C(\MCU_D[6]~input_o ),
+	.D(),
+	.Cin(),
+	.Qin(lcd_data_out_q[6]),
+	.Clk(\MCU_LCD_WRX~inputclkctrl_outclk_X1_Y20_INV_VCC ),
+	.AsyncReset(AsyncReset_X1_Y20_GND),
+	.SyncReset(SyncReset_X1_Y20_GND),
+	.ShiftData(),
+	.SyncLoad(SyncLoad_X1_Y20_VCC),
+	.LutOut(),
+	.Cout(),
+	.Q(lcd_data_out_q[6]));
+defparam \lcd_data_out_q[6] .coord_x = 4;
+defparam \lcd_data_out_q[6] .coord_y = 3;
+defparam \lcd_data_out_q[6] .coord_z = 6;
+defparam \lcd_data_out_q[6] .mask = 16'hFFFF;
+defparam \lcd_data_out_q[6] .modeMux = 1'b1;
+defparam \lcd_data_out_q[6] .FeedbackMux = 1'b0;
+defparam \lcd_data_out_q[6] .ShiftMux = 1'b0;
+defparam \lcd_data_out_q[6] .BypassEn = 1'b1;
+defparam \lcd_data_out_q[6] .CarryEnb = 1'b1;
+
+alta_slice \lcd_data_out_q[7] (
+	.A(vcc),
+	.B(vcc),
+	.C(vcc),
+	.D(\MCU_D[7]~input_o ),
+	.Cin(),
+	.Qin(lcd_data_out_q[7]),
+	.Clk(\MCU_LCD_WRX~inputclkctrl_outclk_X1_Y20_INV_VCC ),
+	.AsyncReset(AsyncReset_X1_Y20_GND),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\lcd_data_out_q[7]~feeder_combout ),
+	.Cout(),
+	.Q(lcd_data_out_q[7]));
+defparam \lcd_data_out_q[7] .coord_x = 4;
+defparam \lcd_data_out_q[7] .coord_y = 3;
+defparam \lcd_data_out_q[7] .coord_z = 10;
+defparam \lcd_data_out_q[7] .mask = 16'hFF00;
+defparam \lcd_data_out_q[7] .modeMux = 1'b0;
+defparam \lcd_data_out_q[7] .FeedbackMux = 1'b0;
+defparam \lcd_data_out_q[7] .ShiftMux = 1'b0;
+defparam \lcd_data_out_q[7] .BypassEn = 1'b0;
+defparam \lcd_data_out_q[7] .CarryEnb = 1'b1;
+
+alta_slice lcd_reset_q(
+	.A(vcc),
+	.B(vcc),
+	.C(vcc),
+	.D(\MCU_D[0]~input_o ),
+	.Cin(),
+	.Qin(\lcd_reset_q~q ),
+	.Clk(\MCU_IO_STBX~inputclkctrl_outclk__lcd_reset_q~0_combout_X1_Y15_SIG_SIG ),
+	.AsyncReset(AsyncReset_X1_Y15_GND),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\lcd_reset_q~1_combout ),
+	.Cout(),
+	.Q(\lcd_reset_q~q ));
+defparam lcd_reset_q.coord_x = 3;
+defparam lcd_reset_q.coord_y = 3;
+defparam lcd_reset_q.coord_z = 1;
+defparam lcd_reset_q.mask = 16'h00FF;
+defparam lcd_reset_q.modeMux = 1'b0;
+defparam lcd_reset_q.FeedbackMux = 1'b0;
+defparam lcd_reset_q.ShiftMux = 1'b0;
+defparam lcd_reset_q.BypassEn = 1'b0;
+defparam lcd_reset_q.CarryEnb = 1'b1;
+
+alta_slice \lcd_reset_q~0 (
+	.A(vcc),
+	.B(vcc),
+	.C(\MCU_ADDR~input_o ),
+	.D(\MCU_DIR~input_o ),
+	.Cin(),
+	.Qin(),
+	.Clk(),
+	.AsyncReset(),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\lcd_reset_q~0_combout ),
+	.Cout(),
+	.Q());
+defparam \lcd_reset_q~0 .coord_x = 3;
+defparam \lcd_reset_q~0 .coord_y = 3;
+defparam \lcd_reset_q~0 .coord_z = 7;
+defparam \lcd_reset_q~0 .mask = 16'h00F0;
+defparam \lcd_reset_q~0 .modeMux = 1'b0;
+defparam \lcd_reset_q~0 .FeedbackMux = 1'b0;
+defparam \lcd_reset_q~0 .ShiftMux = 1'b0;
+defparam \lcd_reset_q~0 .BypassEn = 1'b0;
+defparam \lcd_reset_q~0 .CarryEnb = 1'b1;
+
+alta_slice \mcu_data_out[0]~1 (
+	.A(\mcu_data_out[0]~0_combout ),
+	.B(\SW_R~input_o ),
+	.C(\MCU_DIR~input_o ),
+	.D(\MCU_IO_STBX~input_o ),
+	.Cin(),
+	.Qin(),
+	.Clk(),
+	.AsyncReset(),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\mcu_data_out[0]~1_combout ),
+	.Cout(),
+	.Q());
+defparam \mcu_data_out[0]~1 .coord_x = 4;
+defparam \mcu_data_out[0]~1 .coord_y = 1;
+defparam \mcu_data_out[0]~1 .coord_z = 15;
+defparam \mcu_data_out[0]~1 .mask = 16'hAA3A;
+defparam \mcu_data_out[0]~1 .modeMux = 1'b0;
+defparam \mcu_data_out[0]~1 .FeedbackMux = 1'b0;
+defparam \mcu_data_out[0]~1 .ShiftMux = 1'b0;
+defparam \mcu_data_out[0]~1 .BypassEn = 1'b0;
+defparam \mcu_data_out[0]~1 .CarryEnb = 1'b1;
+
+alta_slice \mcu_data_out[1]~3 (
+	.A(\SW_L~input_o ),
+	.B(\mcu_data_out[1]~2_combout ),
+	.C(\MCU_DIR~input_o ),
+	.D(\MCU_IO_STBX~input_o ),
+	.Cin(),
+	.Qin(),
+	.Clk(),
+	.AsyncReset(),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\mcu_data_out[1]~3_combout ),
+	.Cout(),
+	.Q());
+defparam \mcu_data_out[1]~3 .coord_x = 4;
+defparam \mcu_data_out[1]~3 .coord_y = 1;
+defparam \mcu_data_out[1]~3 .coord_z = 14;
+defparam \mcu_data_out[1]~3 .mask = 16'hCC5C;
+defparam \mcu_data_out[1]~3 .modeMux = 1'b0;
+defparam \mcu_data_out[1]~3 .FeedbackMux = 1'b0;
+defparam \mcu_data_out[1]~3 .ShiftMux = 1'b0;
+defparam \mcu_data_out[1]~3 .BypassEn = 1'b0;
+defparam \mcu_data_out[1]~3 .CarryEnb = 1'b1;
+
+alta_slice \mcu_data_out[2]~5 (
+	.A(\MCU_DIR~input_o ),
+	.B(\SW_D~input_o ),
+	.C(\MCU_IO_STBX~input_o ),
+	.D(\mcu_data_out[2]~4_combout ),
+	.Cin(),
+	.Qin(),
+	.Clk(),
+	.AsyncReset(),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\mcu_data_out[2]~5_combout ),
+	.Cout(),
+	.Q());
+defparam \mcu_data_out[2]~5 .coord_x = 4;
+defparam \mcu_data_out[2]~5 .coord_y = 2;
+defparam \mcu_data_out[2]~5 .coord_z = 7;
+defparam \mcu_data_out[2]~5 .mask = 16'hF702;
+defparam \mcu_data_out[2]~5 .modeMux = 1'b0;
+defparam \mcu_data_out[2]~5 .FeedbackMux = 1'b0;
+defparam \mcu_data_out[2]~5 .ShiftMux = 1'b0;
+defparam \mcu_data_out[2]~5 .BypassEn = 1'b0;
+defparam \mcu_data_out[2]~5 .CarryEnb = 1'b1;
+
+alta_slice \mcu_data_out[3]~7 (
+	.A(\SW_U~input_o ),
+	.B(\mcu_data_out[3]~6_combout ),
+	.C(\MCU_DIR~input_o ),
+	.D(\MCU_IO_STBX~input_o ),
+	.Cin(),
+	.Qin(),
+	.Clk(),
+	.AsyncReset(),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\mcu_data_out[3]~7_combout ),
+	.Cout(),
+	.Q());
+defparam \mcu_data_out[3]~7 .coord_x = 4;
+defparam \mcu_data_out[3]~7 .coord_y = 2;
+defparam \mcu_data_out[3]~7 .coord_z = 6;
+defparam \mcu_data_out[3]~7 .mask = 16'hCC5C;
+defparam \mcu_data_out[3]~7 .modeMux = 1'b0;
+defparam \mcu_data_out[3]~7 .FeedbackMux = 1'b0;
+defparam \mcu_data_out[3]~7 .ShiftMux = 1'b0;
+defparam \mcu_data_out[3]~7 .BypassEn = 1'b0;
+defparam \mcu_data_out[3]~7 .CarryEnb = 1'b1;
+
+alta_slice \mcu_data_out[4]~9 (
+	.A(\MCU_DIR~input_o ),
+	.B(\mcu_data_out[4]~8_combout ),
+	.C(\SW_SEL~input_o ),
+	.D(\MCU_IO_STBX~input_o ),
+	.Cin(),
+	.Qin(),
+	.Clk(),
+	.AsyncReset(),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\mcu_data_out[4]~9_combout ),
+	.Cout(),
+	.Q());
+defparam \mcu_data_out[4]~9 .coord_x = 4;
+defparam \mcu_data_out[4]~9 .coord_y = 2;
+defparam \mcu_data_out[4]~9 .coord_z = 14;
+defparam \mcu_data_out[4]~9 .mask = 16'hCC4E;
+defparam \mcu_data_out[4]~9 .modeMux = 1'b0;
+defparam \mcu_data_out[4]~9 .FeedbackMux = 1'b0;
+defparam \mcu_data_out[4]~9 .ShiftMux = 1'b0;
+defparam \mcu_data_out[4]~9 .BypassEn = 1'b0;
+defparam \mcu_data_out[4]~9 .CarryEnb = 1'b1;
+
+alta_slice \mcu_data_out[5]~11 (
+	.A(\mcu_data_out[5]~10_combout ),
+	.B(\SW_ROT_A~input_o ),
+	.C(\MCU_DIR~input_o ),
+	.D(\MCU_IO_STBX~input_o ),
+	.Cin(),
+	.Qin(),
+	.Clk(),
+	.AsyncReset(),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\mcu_data_out[5]~11_combout ),
+	.Cout(),
+	.Q());
+defparam \mcu_data_out[5]~11 .coord_x = 4;
+defparam \mcu_data_out[5]~11 .coord_y = 2;
+defparam \mcu_data_out[5]~11 .coord_z = 15;
+defparam \mcu_data_out[5]~11 .mask = 16'hAA3A;
+defparam \mcu_data_out[5]~11 .modeMux = 1'b0;
+defparam \mcu_data_out[5]~11 .FeedbackMux = 1'b0;
+defparam \mcu_data_out[5]~11 .ShiftMux = 1'b0;
+defparam \mcu_data_out[5]~11 .BypassEn = 1'b0;
+defparam \mcu_data_out[5]~11 .CarryEnb = 1'b1;
+
+alta_slice \mcu_data_out[6]~13 (
+	.A(\mcu_data_out[6]~12_combout ),
+	.B(\SW_ROT_B~input_o ),
+	.C(\MCU_DIR~input_o ),
+	.D(\MCU_IO_STBX~input_o ),
+	.Cin(),
+	.Qin(),
+	.Clk(),
+	.AsyncReset(),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\mcu_data_out[6]~13_combout ),
+	.Cout(),
+	.Q());
+defparam \mcu_data_out[6]~13 .coord_x = 4;
+defparam \mcu_data_out[6]~13 .coord_y = 1;
+defparam \mcu_data_out[6]~13 .coord_z = 8;
+defparam \mcu_data_out[6]~13 .mask = 16'hAA3A;
+defparam \mcu_data_out[6]~13 .modeMux = 1'b0;
+defparam \mcu_data_out[6]~13 .FeedbackMux = 1'b0;
+defparam \mcu_data_out[6]~13 .ShiftMux = 1'b0;
+defparam \mcu_data_out[6]~13 .BypassEn = 1'b0;
+defparam \mcu_data_out[6]~13 .CarryEnb = 1'b1;
+
+alta_slice \mcu_data_out[7]~15 (
+	.A(\mcu_data_out[7]~14_combout ),
+	.B(\LCD_TE~input_o ),
+	.C(\MCU_DIR~input_o ),
+	.D(\MCU_IO_STBX~input_o ),
+	.Cin(),
+	.Qin(),
+	.Clk(),
+	.AsyncReset(),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\mcu_data_out[7]~15_combout ),
+	.Cout(),
+	.Q());
+defparam \mcu_data_out[7]~15 .coord_x = 4;
+defparam \mcu_data_out[7]~15 .coord_y = 1;
+defparam \mcu_data_out[7]~15 .coord_z = 7;
+defparam \mcu_data_out[7]~15 .mask = 16'hAACA;
+defparam \mcu_data_out[7]~15 .modeMux = 1'b0;
+defparam \mcu_data_out[7]~15 .FeedbackMux = 1'b0;
+defparam \mcu_data_out[7]~15 .ShiftMux = 1'b0;
+defparam \mcu_data_out[7]~15 .BypassEn = 1'b0;
+defparam \mcu_data_out[7]~15 .CarryEnb = 1'b1;
+
+alta_slice ref_en_q(
+	.A(vcc),
+	.B(vcc),
+	.C(vcc),
+	.D(\MCU_D[6]~input_o ),
+	.Cin(),
+	.Qin(\ref_en_q~q ),
+	.Clk(\MCU_IO_STBX~inputclkctrl_outclk__lcd_reset_q~0_combout_X1_Y15_SIG_SIG ),
+	.AsyncReset(AsyncReset_X1_Y15_GND),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\ref_en_q~feeder_combout ),
+	.Cout(),
+	.Q(\ref_en_q~q ));
+defparam ref_en_q.coord_x = 3;
+defparam ref_en_q.coord_y = 3;
+defparam ref_en_q.coord_z = 13;
+defparam ref_en_q.mask = 16'hFF00;
+defparam ref_en_q.modeMux = 1'b0;
+defparam ref_en_q.FeedbackMux = 1'b0;
+defparam ref_en_q.ShiftMux = 1'b0;
+defparam ref_en_q.BypassEn = 1'b0;
+defparam ref_en_q.CarryEnb = 1'b1;
+
+alta_syncctrl syncload_ctrl_X1_Y15(
+	.Din(),
+	.Dout(SyncLoad_X1_Y15_VCC));
+defparam syncload_ctrl_X1_Y15.coord_x = 3;
+defparam syncload_ctrl_X1_Y15.coord_y = 3;
+defparam syncload_ctrl_X1_Y15.coord_z = 1;
+defparam syncload_ctrl_X1_Y15.SyncCtrlMux = 2'b01;
+
+alta_syncctrl syncload_ctrl_X1_Y19(
+	.Din(),
+	.Dout(SyncLoad_X1_Y19_VCC));
+defparam syncload_ctrl_X1_Y19.coord_x = 3;
+defparam syncload_ctrl_X1_Y19.coord_y = 1;
+defparam syncload_ctrl_X1_Y19.coord_z = 1;
+defparam syncload_ctrl_X1_Y19.SyncCtrlMux = 2'b01;
+
+alta_syncctrl syncload_ctrl_X1_Y20(
+	.Din(),
+	.Dout(SyncLoad_X1_Y20_VCC));
+defparam syncload_ctrl_X1_Y20.coord_x = 4;
+defparam syncload_ctrl_X1_Y20.coord_y = 3;
+defparam syncload_ctrl_X1_Y20.coord_z = 1;
+defparam syncload_ctrl_X1_Y20.SyncCtrlMux = 2'b01;
+
+alta_syncctrl syncload_ctrl_X1_Y21(
+	.Din(),
+	.Dout(SyncLoad_X1_Y21_VCC));
+defparam syncload_ctrl_X1_Y21.coord_x = 5;
+defparam syncload_ctrl_X1_Y21.coord_y = 3;
+defparam syncload_ctrl_X1_Y21.coord_z = 1;
+defparam syncload_ctrl_X1_Y21.SyncCtrlMux = 2'b01;
+
+alta_syncctrl syncload_ctrl_X1_Y24(
+	.Din(),
+	.Dout(SyncLoad_X1_Y24_VCC));
+defparam syncload_ctrl_X1_Y24.coord_x = 5;
+defparam syncload_ctrl_X1_Y24.coord_y = 2;
+defparam syncload_ctrl_X1_Y24.coord_z = 1;
+defparam syncload_ctrl_X1_Y24.SyncCtrlMux = 2'b01;
+
+alta_syncctrl syncload_ctrl_X1_Y26(
+	.Din(),
+	.Dout(SyncLoad_X1_Y26_VCC));
+defparam syncload_ctrl_X1_Y26.coord_x = 3;
+defparam syncload_ctrl_X1_Y26.coord_y = 2;
+defparam syncload_ctrl_X1_Y26.coord_z = 1;
+defparam syncload_ctrl_X1_Y26.SyncCtrlMux = 2'b01;
+
+alta_syncctrl syncreset_ctrl_X1_Y15(
+	.Din(),
+	.Dout(SyncReset_X1_Y15_GND));
+defparam syncreset_ctrl_X1_Y15.coord_x = 3;
+defparam syncreset_ctrl_X1_Y15.coord_y = 3;
+defparam syncreset_ctrl_X1_Y15.coord_z = 0;
+defparam syncreset_ctrl_X1_Y15.SyncCtrlMux = 2'b00;
+
+alta_syncctrl syncreset_ctrl_X1_Y19(
+	.Din(),
+	.Dout(SyncReset_X1_Y19_GND));
+defparam syncreset_ctrl_X1_Y19.coord_x = 3;
+defparam syncreset_ctrl_X1_Y19.coord_y = 1;
+defparam syncreset_ctrl_X1_Y19.coord_z = 0;
+defparam syncreset_ctrl_X1_Y19.SyncCtrlMux = 2'b00;
+
+alta_syncctrl syncreset_ctrl_X1_Y20(
+	.Din(),
+	.Dout(SyncReset_X1_Y20_GND));
+defparam syncreset_ctrl_X1_Y20.coord_x = 4;
+defparam syncreset_ctrl_X1_Y20.coord_y = 3;
+defparam syncreset_ctrl_X1_Y20.coord_z = 0;
+defparam syncreset_ctrl_X1_Y20.SyncCtrlMux = 2'b00;
+
+alta_syncctrl syncreset_ctrl_X1_Y21(
+	.Din(),
+	.Dout(SyncReset_X1_Y21_GND));
+defparam syncreset_ctrl_X1_Y21.coord_x = 5;
+defparam syncreset_ctrl_X1_Y21.coord_y = 3;
+defparam syncreset_ctrl_X1_Y21.coord_z = 0;
+defparam syncreset_ctrl_X1_Y21.SyncCtrlMux = 2'b00;
+
+alta_syncctrl syncreset_ctrl_X1_Y24(
+	.Din(),
+	.Dout(SyncReset_X1_Y24_GND));
+defparam syncreset_ctrl_X1_Y24.coord_x = 5;
+defparam syncreset_ctrl_X1_Y24.coord_y = 2;
+defparam syncreset_ctrl_X1_Y24.coord_z = 0;
+defparam syncreset_ctrl_X1_Y24.SyncCtrlMux = 2'b00;
+
+alta_syncctrl syncreset_ctrl_X1_Y26(
+	.Din(),
+	.Dout(SyncReset_X1_Y26_GND));
+defparam syncreset_ctrl_X1_Y26.coord_x = 3;
+defparam syncreset_ctrl_X1_Y26.coord_y = 2;
+defparam syncreset_ctrl_X1_Y26.coord_z = 0;
+defparam syncreset_ctrl_X1_Y26.SyncCtrlMux = 2'b00;
+
+alta_slice sysoff_q(
+	.A(\MCU_D[2]~input_o ),
+	.B(vcc),
+	.C(vcc),
+	.D(vcc),
+	.Cin(),
+	.Qin(\sysoff_q~q ),
+	.Clk(\MCU_IO_STBX~inputclkctrl_outclk__lcd_reset_q~0_combout_X1_Y15_SIG_SIG ),
+	.AsyncReset(AsyncReset_X1_Y15_GND),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\sysoff_q~feeder_combout ),
+	.Cout(),
+	.Q(\sysoff_q~q ));
+defparam sysoff_q.coord_x = 3;
+defparam sysoff_q.coord_y = 3;
+defparam sysoff_q.coord_z = 2;
+defparam sysoff_q.mask = 16'hAAAA;
+defparam sysoff_q.modeMux = 1'b0;
+defparam sysoff_q.FeedbackMux = 1'b0;
+defparam sysoff_q.ShiftMux = 1'b0;
+defparam sysoff_q.BypassEn = 1'b0;
+defparam sysoff_q.CarryEnb = 1'b1;
+
+alta_slice \tp_q[0] (
+	.A(),
+	.B(),
+	.C(\MCU_D[0]~input_o ),
+	.D(),
+	.Cin(),
+	.Qin(tp_q[0]),
+	.Clk(\MCU_IO_STBX~inputclkctrl_outclk__tp_q[3]~0_combout_X1_Y15_SIG_SIG ),
+	.AsyncReset(AsyncReset_X1_Y15_GND),
+	.SyncReset(SyncReset_X1_Y15_GND),
+	.ShiftData(),
+	.SyncLoad(SyncLoad_X1_Y15_VCC),
+	.LutOut(),
+	.Cout(),
+	.Q(tp_q[0]));
+defparam \tp_q[0] .coord_x = 3;
+defparam \tp_q[0] .coord_y = 3;
+defparam \tp_q[0] .coord_z = 9;
+defparam \tp_q[0] .mask = 16'hFFFF;
+defparam \tp_q[0] .modeMux = 1'b1;
+defparam \tp_q[0] .FeedbackMux = 1'b0;
+defparam \tp_q[0] .ShiftMux = 1'b0;
+defparam \tp_q[0] .BypassEn = 1'b1;
+defparam \tp_q[0] .CarryEnb = 1'b1;
+
+alta_slice \tp_q[1] (
+	.A(),
+	.B(),
+	.C(\MCU_D[1]~input_o ),
+	.D(),
+	.Cin(),
+	.Qin(tp_q[1]),
+	.Clk(\MCU_IO_STBX~inputclkctrl_outclk__tp_q[3]~0_combout_X1_Y15_SIG_SIG ),
+	.AsyncReset(AsyncReset_X1_Y15_GND),
+	.SyncReset(SyncReset_X1_Y15_GND),
+	.ShiftData(),
+	.SyncLoad(SyncLoad_X1_Y15_VCC),
+	.LutOut(),
+	.Cout(),
+	.Q(tp_q[1]));
+defparam \tp_q[1] .coord_x = 3;
+defparam \tp_q[1] .coord_y = 3;
+defparam \tp_q[1] .coord_z = 10;
+defparam \tp_q[1] .mask = 16'hFFFF;
+defparam \tp_q[1] .modeMux = 1'b1;
+defparam \tp_q[1] .FeedbackMux = 1'b0;
+defparam \tp_q[1] .ShiftMux = 1'b0;
+defparam \tp_q[1] .BypassEn = 1'b1;
+defparam \tp_q[1] .CarryEnb = 1'b1;
+
+alta_slice \tp_q[2] (
+	.A(\MCU_D[2]~input_o ),
+	.B(vcc),
+	.C(vcc),
+	.D(vcc),
+	.Cin(),
+	.Qin(tp_q[2]),
+	.Clk(\MCU_IO_STBX~inputclkctrl_outclk__tp_q[3]~0_combout_X1_Y15_SIG_SIG ),
+	.AsyncReset(AsyncReset_X1_Y15_GND),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\tp_q[2]~feeder_combout ),
+	.Cout(),
+	.Q(tp_q[2]));
+defparam \tp_q[2] .coord_x = 3;
+defparam \tp_q[2] .coord_y = 3;
+defparam \tp_q[2] .coord_z = 4;
+defparam \tp_q[2] .mask = 16'hAAAA;
+defparam \tp_q[2] .modeMux = 1'b0;
+defparam \tp_q[2] .FeedbackMux = 1'b0;
+defparam \tp_q[2] .ShiftMux = 1'b0;
+defparam \tp_q[2] .BypassEn = 1'b0;
+defparam \tp_q[2] .CarryEnb = 1'b1;
+
+alta_slice \tp_q[3] (
+	.A(),
+	.B(),
+	.C(\MCU_D[3]~input_o ),
+	.D(),
+	.Cin(),
+	.Qin(tp_q[3]),
+	.Clk(\MCU_IO_STBX~inputclkctrl_outclk__tp_q[3]~0_combout_X1_Y15_SIG_SIG ),
+	.AsyncReset(AsyncReset_X1_Y15_GND),
+	.SyncReset(SyncReset_X1_Y15_GND),
+	.ShiftData(),
+	.SyncLoad(SyncLoad_X1_Y15_VCC),
+	.LutOut(),
+	.Cout(),
+	.Q(tp_q[3]));
+defparam \tp_q[3] .coord_x = 3;
+defparam \tp_q[3] .coord_y = 3;
+defparam \tp_q[3] .coord_z = 14;
+defparam \tp_q[3] .mask = 16'hFFFF;
+defparam \tp_q[3] .modeMux = 1'b1;
+defparam \tp_q[3] .FeedbackMux = 1'b0;
+defparam \tp_q[3] .ShiftMux = 1'b0;
+defparam \tp_q[3] .BypassEn = 1'b1;
+defparam \tp_q[3] .CarryEnb = 1'b1;
+
+alta_slice \tp_q[3]~0 (
+	.A(vcc),
+	.B(vcc),
+	.C(\MCU_ADDR~input_o ),
+	.D(\MCU_DIR~input_o ),
+	.Cin(),
+	.Qin(),
+	.Clk(),
+	.AsyncReset(),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\tp_q[3]~0_combout ),
+	.Cout(),
+	.Q());
+defparam \tp_q[3]~0 .coord_x = 3;
+defparam \tp_q[3]~0 .coord_y = 3;
+defparam \tp_q[3]~0 .coord_z = 3;
+defparam \tp_q[3]~0 .mask = 16'h000F;
+defparam \tp_q[3]~0 .modeMux = 1'b0;
+defparam \tp_q[3]~0 .FeedbackMux = 1'b0;
+defparam \tp_q[3]~0 .ShiftMux = 1'b0;
+defparam \tp_q[3]~0 .BypassEn = 1'b0;
+defparam \tp_q[3]~0 .CarryEnb = 1'b1;
+
+alta_slice \tp_q[4] (
+	.A(vcc),
+	.B(vcc),
+	.C(vcc),
+	.D(\MCU_D[4]~input_o ),
+	.Cin(),
+	.Qin(tp_q[4]),
+	.Clk(\MCU_IO_STBX~inputclkctrl_outclk__tp_q[3]~0_combout_X1_Y15_SIG_SIG ),
+	.AsyncReset(AsyncReset_X1_Y15_GND),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\tp_q[4]~feeder_combout ),
+	.Cout(),
+	.Q(tp_q[4]));
+defparam \tp_q[4] .coord_x = 3;
+defparam \tp_q[4] .coord_y = 3;
+defparam \tp_q[4] .coord_z = 5;
+defparam \tp_q[4] .mask = 16'hFF00;
+defparam \tp_q[4] .modeMux = 1'b0;
+defparam \tp_q[4] .FeedbackMux = 1'b0;
+defparam \tp_q[4] .ShiftMux = 1'b0;
+defparam \tp_q[4] .BypassEn = 1'b0;
+defparam \tp_q[4] .CarryEnb = 1'b1;
+
+alta_slice \tp_q[5] (
+	.A(),
+	.B(),
+	.C(\MCU_D[5]~input_o ),
+	.D(),
+	.Cin(),
+	.Qin(tp_q[5]),
+	.Clk(\MCU_IO_STBX~inputclkctrl_outclk__tp_q[3]~0_combout_X1_Y15_SIG_SIG ),
+	.AsyncReset(AsyncReset_X1_Y15_GND),
+	.SyncReset(SyncReset_X1_Y15_GND),
+	.ShiftData(),
+	.SyncLoad(SyncLoad_X1_Y15_VCC),
+	.LutOut(),
+	.Cout(),
+	.Q(tp_q[5]));
+defparam \tp_q[5] .coord_x = 3;
+defparam \tp_q[5] .coord_y = 3;
+defparam \tp_q[5] .coord_z = 6;
+defparam \tp_q[5] .mask = 16'hFFFF;
+defparam \tp_q[5] .modeMux = 1'b1;
+defparam \tp_q[5] .FeedbackMux = 1'b0;
+defparam \tp_q[5] .ShiftMux = 1'b0;
+defparam \tp_q[5] .BypassEn = 1'b1;
+defparam \tp_q[5] .CarryEnb = 1'b1;
+
+alta_slice \tp_q[6] (
+	.A(vcc),
+	.B(vcc),
+	.C(vcc),
+	.D(\MCU_D[6]~input_o ),
+	.Cin(),
+	.Qin(tp_q[6]),
+	.Clk(\MCU_IO_STBX~inputclkctrl_outclk__tp_q[3]~0_combout_X1_Y15_SIG_SIG ),
+	.AsyncReset(AsyncReset_X1_Y15_GND),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\tp_q[6]~feeder_combout ),
+	.Cout(),
+	.Q(tp_q[6]));
+defparam \tp_q[6] .coord_x = 3;
+defparam \tp_q[6] .coord_y = 3;
+defparam \tp_q[6] .coord_z = 15;
+defparam \tp_q[6] .mask = 16'hFF00;
+defparam \tp_q[6] .modeMux = 1'b0;
+defparam \tp_q[6] .FeedbackMux = 1'b0;
+defparam \tp_q[6] .ShiftMux = 1'b0;
+defparam \tp_q[6] .BypassEn = 1'b0;
+defparam \tp_q[6] .CarryEnb = 1'b1;
+
+alta_slice \tp_q[7] (
+	.A(vcc),
+	.B(vcc),
+	.C(vcc),
+	.D(\MCU_D[7]~input_o ),
+	.Cin(),
+	.Qin(tp_q[7]),
+	.Clk(\MCU_IO_STBX~inputclkctrl_outclk__tp_q[3]~0_combout_X1_Y15_SIG_SIG ),
+	.AsyncReset(AsyncReset_X1_Y15_GND),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\tp_q[7]~feeder_combout ),
+	.Cout(),
+	.Q(tp_q[7]));
+defparam \tp_q[7] .coord_x = 3;
+defparam \tp_q[7] .coord_y = 3;
+defparam \tp_q[7] .coord_z = 11;
+defparam \tp_q[7] .mask = 16'hFF00;
+defparam \tp_q[7] .modeMux = 1'b0;
+defparam \tp_q[7] .FeedbackMux = 1'b0;
+defparam \tp_q[7] .ShiftMux = 1'b0;
+defparam \tp_q[7] .BypassEn = 1'b0;
+defparam \tp_q[7] .CarryEnb = 1'b1;
+
+endmodule
diff --git a/hardware/portapack_h4m/CPLD/Supra/portapack_h4m_cpld_sram.prg b/hardware/portapack_h4m/CPLD/Supra/portapack_h4m_cpld_sram.prg
new file mode 100644
index 00000000..6f2e9295
--- /dev/null
+++ b/hardware/portapack_h4m/CPLD/Supra/portapack_h4m_cpld_sram.prg
@@ -0,0 +1,58 @@
+set sh_continue_on_error false
+usb_connect
+if { ! [jtag_device_id] } {
+  exit
+}
+runtest -tck 1
+sir 10 -tdi 3e3
+runtest -tck 5000
+sir 10 -tdi 3f8
+runtest -tck 100
+sir 10 -tdi 3f9
+runtest -tck 100
+sir 10 -tdi 3f8
+runtest -tck 100
+sir 10 -tdi 6
+runtest -tck 100
+sdr 32 -tdi 00000000 -tdo 00025610 -mask ffffffff
+sir 10 -tdi 3fc
+runtest -tck 100
+sdr 8 -tdi 00
+sir 10 -tdi 3fa
+runtest -tck 100
+sdr 57568 \
+  -tdi  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\
+  -tdo  0 \
+  -mask 0
+sir 10 -tdi 3e5
+runtest -tck 100
+sir 10 -tdi 3fc
+runtest -tck 100
+sdr 8 -tdi 00
+sir 10 -tdi 3fa
+runtest -tck 100
+sdr 64 \
+  -tdi  04f0200004000005 \
+  -tdo  0 \
+  -mask 0
+sir 10 -tdi 3fd
+runtest -tck 100
+sdr 1044 \
+  -tdi  0 \
+  -tdo  142CA1650B285942C83DC1EE0F707BE1670B3859C2CE1651F28F947CA3E40B205902C81640B285942CA1650B285942CA1650B285942CA1650B285942CA1650B20F707B83DC0B285942C81650B205907B83DC1EE0F707B83DC1EE0F702C81641EE0F707B83DC1EE0F707B83DC1EE0F107881650B285902CA1641E385942CA1670B2858 \
+  -mask 1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE
+sir 10 -tdi 3fa
+runtest -tck 100
+sdr 64 \
+  -tdi  0402130000000005 \
+  -tdo  0 \
+  -mask 0
+sir 10 -tdi 3fd
+runtest -tck 100
+sdr 51268 \
+  -tdi  0 \
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