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Activating TX Low Pass Filter in Second IF IC (#1470)

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* Activating TX Low Pass Filter in Second IF IC
* solving PR conversation revisions
* Final TX LPF decision for ADSB_TX
* Small comments correction.
* Added set TX LPF also  in APRS, BurgerPgr,Jammer
This commit is contained in:
Brumi-2021
2023-10-08 17:50:31 +02:00
committed by GitHub
parent 5a850984b9
commit defb934c3f
19 changed files with 81 additions and 18 deletions
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26
firmware/application/hw/max2837.cpp
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@@ -122,7 +122,7 @@ void MAX2837::init() {
_map.r.lpf_1.LPF_EN = 1; /* Enable low-pass filter */
_map.r.lpf_1.ModeCtrl = 0b01; /* Rx LPF */
_map.r.lpf_1.FT = 0b0000; /* 5MHz LPF */
_map.r.lpf_1.FT = 0b0000; /* 1,75MHz LPF */
_map.r.spi_en.EN_SPI = 1; /* enable chip functions when ENABLE pin set */
@@ -233,10 +233,28 @@ void MAX2837::set_vga_gain(const int_fast8_t db) {
flush();
}
void MAX2837::set_lpf_rf_bandwidth(const uint32_t bandwidth_minimum) {
void MAX2837::set_lpf_rf_bandwidth_rx(const uint32_t bandwidth_minimum) {
_map.r.lpf_1.ModeCtrl = 0b01; /* Address reg 2, D3-D2, Set mode lowpass filter block to Rx LPF . Active when Address 6 D<9> = 1 */
_map.r.lpf_1.FT = filter::bandwidth_ordinal(bandwidth_minimum);
_dirty[Register::LPF_1] = 1;
flush();
flush_one(Register::LPF_1);
_map.r.vga_3_rx_top.LPF_MODE_SEL = 1; /* Address 6 reg, D9 bit:LPF mode mux, LPF_MODE_SEL 0 = Normal operation, 1 = Operating mode is programmed Address 2 D3:D2*/
flush_one(Register::VGA_3_RX_TOP);
_map.r.vga_3_rx_top.LPF_MODE_SEL = 0; /* Leave LPF_MODE_SEL 0 = Normal operation */
flush_one(Register::VGA_3_RX_TOP);
}
void MAX2837::set_lpf_rf_bandwidth_tx(const uint32_t bandwidth_minimum) {
_map.r.lpf_1.ModeCtrl = 0b10; /* Address 2 reg, D3-D2, Set mode lowpass filter block to Tx LPF . Active when Address 6 D<9> = 1 */
_map.r.lpf_1.FT = filter::bandwidth_ordinal(bandwidth_minimum);
flush_one(Register::LPF_1);
_map.r.vga_3_rx_top.LPF_MODE_SEL = 1; /* Address 6 reg, D9 bit:LPF mode mux, LPF_MODE_SEL 0 = Normal operation, 1 = Operating mode is programmed Address 2 D3:D2*/
flush_one(Register::VGA_3_RX_TOP);
_map.r.vga_3_rx_top.LPF_MODE_SEL = 0; /* Leave LPF_MODE_SEL 0 = Normal operation */
flush_one(Register::VGA_3_RX_TOP);
}
bool MAX2837::set_frequency(const rf::Frequency lo_frequency) {

3
firmware/application/hw/max2837.hpp
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@@ -783,7 +783,8 @@ class MAX2837 : public MAX283x {
void set_tx_vga_gain(const int_fast8_t db) override;
void set_lna_gain(const int_fast8_t db) override;
void set_vga_gain(const int_fast8_t db) override;
void set_lpf_rf_bandwidth(const uint32_t bandwidth_minimum) override;
void set_lpf_rf_bandwidth_rx(const uint32_t bandwidth_minimum) override;
void set_lpf_rf_bandwidth_tx(const uint32_t bandwidth_minimum) override;
#if 0
void rx_cal() {
_map.r.spi_en.EN_SPI = 1;

28
firmware/application/hw/max2839.cpp
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@@ -278,10 +278,32 @@ void MAX2839::set_vga_gain(const int_fast8_t db) {
configure_rx_gain();
}
void MAX2839::set_lpf_rf_bandwidth(const uint32_t bandwidth_minimum) {
void MAX2839::set_lpf_rf_bandwidth_rx(const uint32_t bandwidth_minimum) {
_map.r.lpf_vga_1.ModeCtrl = 0b01; /* Address reg 5, D9-D8, Set mode lowpass filter block to Rx LPF . Active when Address 8 D<2> = 1 */
flush_one(Register::LPF_VGA_1);
_map.r.rx_top_1.LPF_MODE_SEL = 1; /* Address 8 reg, D2 bit:LPF mode mux, LPF_MODE_SEL 0 = Normal operation, 1 = Operating mode is programmed Address 5 D<9:8> */
flush_one(Register::RX_TOP_1);
_map.r.lpf.FT = filter::bandwidth_ordinal(bandwidth_minimum);
_dirty[Register::LPF] = 1;
flush();
flush_one(Register::LPF);
_map.r.rx_top_1.LPF_MODE_SEL = 0; /* Address 8 reg, D2 bit:LPF mode mux, LPF_MODE_SEL 0 = Normal operation, 1 = Operating mode is programmed Address 5 D<9:8> */
flush_one(Register::RX_TOP_1); /* Leave LPF_MODE_SEL 0 = Normal operation */
}
void MAX2839::set_lpf_rf_bandwidth_tx(const uint32_t bandwidth_minimum) {
_map.r.lpf_vga_1.ModeCtrl = 0b10; /* Address reg 5, D9-D8, Set mode lowpass filter block to Tx LPF . Active when Address 8 D<2> = 1 */
flush_one(Register::LPF_VGA_1);
_map.r.rx_top_1.LPF_MODE_SEL = 1; /* Address 8 reg, D2 bit:LPF mode mux, LPF_MODE_SEL 0 = Normal operation, 1 = Operating mode is programmed Address 5 D<9:8> */
flush_one(Register::RX_TOP_1);
_map.r.lpf.FT = filter::bandwidth_ordinal(bandwidth_minimum);
flush_one(Register::LPF);
_map.r.rx_top_1.LPF_MODE_SEL = 0; /* Address 8 reg, D2 bit:LPF mode mux, LPF_MODE_SEL 0 = Normal operation, 1 = Operating mode is programmed Address 5 D<9:8> */
flush_one(Register::RX_TOP_1); /* Leave LPF_MODE_SEL 0 = Normal operation */
}
bool MAX2839::set_frequency(const rf::Frequency lo_frequency) {

3
firmware/application/hw/max2839.hpp
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@@ -686,7 +686,8 @@ class MAX2839 : public MAX283x {
void set_tx_vga_gain(const int_fast8_t db) override;
void set_lna_gain(const int_fast8_t db) override;
void set_vga_gain(const int_fast8_t db) override;
void set_lpf_rf_bandwidth(const uint32_t bandwidth_minimum) override;
void set_lpf_rf_bandwidth_rx(const uint32_t bandwidth_minimum) override;
void set_lpf_rf_bandwidth_tx(const uint32_t bandwidth_minimum) override;
bool set_frequency(const rf::Frequency lo_frequency) override;
void set_rx_lo_iq_calibration(const size_t v) override;
void set_rx_buff_vcm(const size_t v) override;

3
firmware/application/hw/max283x.hpp
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@@ -123,7 +123,8 @@ class MAX283x {
virtual void set_tx_vga_gain(const int_fast8_t db);
virtual void set_lna_gain(const int_fast8_t db);
virtual void set_vga_gain(const int_fast8_t db);
virtual void set_lpf_rf_bandwidth(const uint32_t bandwidth_minimum);
virtual void set_lpf_rf_bandwidth_rx(const uint32_t bandwidth_minimum);
virtual void set_lpf_rf_bandwidth_tx(const uint32_t bandwidth_minimum);
virtual bool set_frequency(const rf::Frequency lo_frequency);