mirror of
https://github.com/portapack-mayhem/mayhem-firmware.git
synced 2025-12-11 02:02:31 +00:00
ChibiOS 2.6.8, until I can figure out where to get it from git.
This commit is contained in:
Jared Boone
269
firmware/chibios/os/hal/platforms/LPC8xx/serial_lld.h
Executable file
269
firmware/chibios/os/hal/platforms/LPC8xx/serial_lld.h
Executable file
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/*
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ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file LPC8xx/serial_lld.h
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* @brief LPC8xx low level serial driver header.
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*
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* @addtogroup SERIAL
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* @{
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*/
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#ifndef _SERIAL_LLD_H_
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#define _SERIAL_LLD_H_
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#if HAL_USE_SERIAL || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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#define CFG_ENA 0x0001
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#define CFG_DL7 0x0000
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#define CFG_DL8 0x0004
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#define CFG_DL9 0x0008
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#define CFG_NOPARITY 0x0000
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#define CFG_PARITYEVEN 0x0020
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#define CFG_PARITYODD 0x0030
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#define CFG_STOP1 0x0000
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#define CFG_STOP2 0x0040
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#define CFG_CTSEN 0x0200
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#define CFG_SYNCEN 0x0800
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#define CFG_CLKPOL_FALL 0x0000
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#define CFG_CLKPOL_RISE 0x1000
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#define CFG_SYNC_SLV 0x0000
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#define CFG_SYNC_MAST 0x4000
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#define CFG_LOOP_EN 0x8000
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#define CTRL_TXBRKEN 0x0002
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#define CTRL_ADDRDET 0x0004
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#define CTRL_TXDIS 0x0040
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#define CTRL_CC 0x0100
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#define CTRL_CLRCC 0x0200
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#define STAT_RXRDY 0x0001
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#define STAT_RXIDLE 0x0002
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#define STAT_TXRDY 0x0004
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#define STAT_TXIDLE 0x0008
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#define STAT_CTS 0x0010
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#define STAT_DELTACTS 0x0020
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#define STAT_TXDIS 0x0040
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#define STAT_OVERRUN 0x0100
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#define STAT_RXBRK 0x0400
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#define STAT_DELTARXBRK 0x0800
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#define STAT_START 0x1000
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#define STAT_FRAMERR 0x2000
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#define STAT_PARITYERR 0x4000
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#define STAT_RXNOISE 0x8000
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/**
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* @brief UART0 driver enable switch.
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* @details If set to @p TRUE the support for UART0 is included.
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* @note The default is @p TRUE .
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*/
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#if !defined(LPC8xx_SERIAL_USE_UART0) || defined(__DOXYGEN__)
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#define LPC8xx_SERIAL_USE_UART0 TRUE
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#endif
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/**
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* @brief UART1 driver enable switch.
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* @details If set to @p TRUE the support for UART1 is included.
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* @note The default is @p FALSE .
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*/
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#if !defined(LPC8xx_SERIAL_USE_UART1) || defined(__DOXYGEN__)
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#define LPC8xx_SERIAL_USE_UART1 FALSE
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#endif
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/**
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* @brief UART2 driver enable switch.
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* @details If set to @p TRUE the support for UART2 is included.
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* @note The default is @p FALSE .
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*/
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#if !defined(LPC8xx_SERIAL_USE_UART2) || defined(__DOXYGEN__)
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#define LPC8xx_SERIAL_USE_UART2 FALSE
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#endif
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/**
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* @brief UART0 interrupt priority level setting.
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*/
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#if !defined(LPC8xx_SERIAL_UART0_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define LPC8xx_SERIAL_UART0_IRQ_PRIORITY 3
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#endif
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/**
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* @brief UART1 interrupt priority level setting.
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*/
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#if !defined(LPC8xx_SERIAL_UART1_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define LPC8xx_SERIAL_UART1_IRQ_PRIORITY 3
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#endif
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/**
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* @brief UART2 interrupt priority level setting.
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*/
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#if !defined(LPC8xx_SERIAL_UART2_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define LPC8xx_SERIAL_UART2_IRQ_PRIORITY 3
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#endif
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/**
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* @brief Uart Baud Clock (U_PCLK).
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* @details The Baud clock rate we would like to achieve.
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* @note The default is @p 11.0592MHz.
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* A multiple of 1.8432MHz will give accurate
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* results at all standard baud rates .
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*/
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#if !defined(LPC8xx_SERIAL_U_PCLK) || defined(__DOXYGEN__)
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#define LPC8xx_SERIAL_U_PCLK 11059200
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#endif
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/**
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* @brief UARTCLKDIV divider.
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*/
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#if !defined(LPC8xx_SERIAL_UARTCLKDIV) || defined(__DOXYGEN__)
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#define LPC8xx_SERIAL_UARTCLKDIV (LPC8xx_MAINCLK/LPC8xx_SERIAL_U_PCLK)
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#endif
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// Output from uart clock divider
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#define LPC8xx_UARTDIVCLK (LPC8xx_MAINCLK/LPC8xx_SERIAL_UARTCLKDIV)
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/**
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* @brief UARTFRGDIV
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* @details Fractional Baud rate generator denominator.
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* @note If used, *must* be set to 256, otherwise set to 0
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*/
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#if !defined(LPC8xx_SERIAL_UARTFRGDIV) || defined(__DOXYGEN__)
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#if (LPC8xx_SERIAL_UARTCLKDIV != LPC8xx_SERIAL_U_PCLK)
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#define LPC8xx_SERIAL_UARTFRGDIV 0xFF
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#else
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#define LPC8xx_SERIAL_UARTFRGDIV 0x00
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#endif
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#endif
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/**
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* @brief UARTFRGMUL
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* @details Fractional Baud rate generator numerator.
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* Refer to LPC8xx User Manual 4.6.19 for calculation
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* @note the *2, +1 and /2 are included to round to the nearest integer.
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*/
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#if !defined(LPC8xx_SERIAL_UARTFRGMUL) || defined(__DOXYGEN__)
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#if (LPC8xx_SERIAL_UARTCLKDIV != LPC8xx_SERIAL_U_PCLK)
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#define LPC8xx_SERIAL_UARTFRGMULT ( ( ( ( (LPC8xx_UARTDIVCLK- \
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LPC8xx_SERIAL_U_PCLK) \
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*256*2 ) \
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/LPC8xx_SERIAL_U_PCLK ) \
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+1 ) \
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/2 )
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#else
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#define LPC8xx_SERIAL_UARTFRGMULT 0x00
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#endif
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#endif
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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#if (LPC8xx_SERIAL_UARTCLKDIV < 1) || (LPC8xx_SERIAL_UARTCLKDIV > 255)
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#error "invalid LPC8xx_SERIAL_UARTCLKDIV setting"
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#endif
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#if (LPC8xx_SERIAL_UARTFRGDIV != 0) && (LPC8xx_SERIAL_UARTFRGDIV != 255)
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#error "invalid LPC8xx_SERIAL_UARTFRGDIV setting"
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#endif
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#if (LPC8xx_SERIAL_UARTFRGMUL != 0) && (LPC8xx_SERIAL_UARTFRGMUL > 255)
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#error "invalid LPC8xx_SERIAL_UARTFRGMUL setting"
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#endif
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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/**
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* @brief LPC8xx Serial Driver configuration structure.
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* @details An instance of this structure must be passed to @p sdStart()
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* in order to configure and start a serial driver operations.
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*/
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typedef struct {
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/**
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* @brief Bit rate.
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*/
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uint32_t sc_speed;
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/**
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* @brief Initialization value for the CFG register.
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*/
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uint32_t sc_cfg;
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} SerialConfig;
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/**
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* @brief @p SerialDriver specific data.
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*/
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#define _serial_driver_data \
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_base_asynchronous_channel_data \
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/* Driver state.*/ \
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sdstate_t state; \
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/* Input queue.*/ \
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InputQueue iqueue; \
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/* Output queue.*/ \
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OutputQueue oqueue; \
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/* Input circular buffer.*/ \
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uint8_t ib[SERIAL_BUFFERS_SIZE]; \
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/* Output circular buffer.*/ \
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uint8_t ob[SERIAL_BUFFERS_SIZE]; \
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/* End of the mandatory fields.*/ \
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/* Pointer to the USART registers block.*/ \
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LPC_USART_TypeDef *uart;
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/*===========================================================================*/
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/* Driver macros. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* External declarations. */
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/*===========================================================================*/
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#if LPC8xx_SERIAL_USE_UART0 && !defined(__DOXYGEN__)
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extern SerialDriver SD1;
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#endif
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#if LPC8xx_SERIAL_USE_UART1 && !defined(__DOXYGEN__)
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extern SerialDriver SD2;
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#endif
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#if LPC8xx_SERIAL_USE_UART2 && !defined(__DOXYGEN__)
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extern SerialDriver SD3;
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#endif
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#ifdef __cplusplus
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extern "C" {
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#endif
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void sd_lld_init(void);
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void sd_lld_start(SerialDriver *sdp, const SerialConfig *config);
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void sd_lld_stop(SerialDriver *sdp);
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#ifdef __cplusplus
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}
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#endif
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#endif /* HAL_USE_SERIAL */
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#endif /* _SERIAL_LLD_H_ */
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/** @} */
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