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ChibiOS 2.6.8, until I can figure out where to get it from git.

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Jared Boone
2015-07-08 08:40:23 -07:00
parent dc6fee8370
commit e1eea8e08a
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281
firmware/chibios/os/hal/platforms/SPC560BCxx/hal_lld.c Executable file
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/*
SPC5 HAL - Copyright (C) 2013 STMicroelectronics
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file SPC560BCxx/hal_lld.c
* @brief SPC560B/Cxx HAL subsystem low level driver source.
*
* @addtogroup HAL
* @{
*/
#include "ch.h"
#include "hal.h"
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
/**
* @brief PIT channel 3 interrupt handler.
*
* @isr
*/
CH_IRQ_HANDLER(vector59) {
CH_IRQ_PROLOGUE();
chSysLockFromIsr();
chSysTimerHandlerI();
chSysUnlockFromIsr();
/* Resets the PIT channel 3 IRQ flag.*/
PIT.CH[0].TFLG.R = 1;
CH_IRQ_EPILOGUE();
}
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/**
* @brief Low level HAL driver initialization.
*
* @notapi
*/
void hal_lld_init(void) {
uint32_t reg;
/* The system is switched to the RUN0 mode, the default for normal
operations.*/
if (halSPCSetRunMode(SPC5_RUNMODE_RUN0) == CH_FAILED) {
SPC5_CLOCK_FAILURE_HOOK();
}
/* INTC initialization, software vector mode, 4 bytes vectors, starting
at priority 0.*/
INTC.MCR.R = 0;
INTC.CPR.R = 0;
INTC.IACKR.R = (uint32_t)_vectors;
/* PIT channel 0 initialization for Kernel ticks, the PIT is configured
to run in DRUN,RUN0...RUN3 and HALT0 modes, the clock is gated in other
modes.*/
INTC.PSR[59].R = SPC5_PIT0_IRQ_PRIORITY;
halSPCSetPeripheralClockMode(92,
SPC5_ME_PCTL_RUN(2) | SPC5_ME_PCTL_LP(2));
reg = halSPCGetSystemClock() / CH_FREQUENCY - 1;
PIT.PITMCR.R = 1; /* PIT clock enabled, stop while debugging. */
PIT.CH[0].LDVAL.R = reg;
PIT.CH[0].CVAL.R = reg;
PIT.CH[0].TFLG.R = 1; /* Interrupt flag cleared. */
PIT.CH[0].TCTRL.R = 3; /* Timer active, interrupt enabled. */
}
/**
* @brief SPC560B/Cxx clocks and PLL initialization.
* @note All the involved constants come from the file @p board.h and
* @p hal_lld.h
* @note This function must be invoked only after the system reset.
*
* @special
*/
void spc_clock_init(void) {
/* Waiting for IRC stabilization before attempting anything else.*/
while (!ME.GS.B.S_FIRC)
;
#if !SPC5_NO_INIT
#if SPC5_DISABLE_WATCHDOG
/* SWT disabled.*/
SWT.SR.R = 0xC520;
SWT.SR.R = 0xD928;
SWT.CR.R = 0xFF00000A;
#endif
/* SSCM initialization. Setting up the most restrictive handling of
invalid accesses to peripherals.*/
SSCM.ERROR.R = 3; /* PAE and RAE bits. */
/* RGM errors clearing.*/
RGM.FES.R = 0xFFFF;
RGM.DES.R = 0xFFFF;
/* Oscillators dividers setup.*/
CGM.FIRC_CTL.B.RCDIV = SPC5_IRCDIV_VALUE - 1;
CGM.FXOSC_CTL.B.OSCDIV = SPC5_XOSCDIV_VALUE - 1;
/* The system must be in DRUN mode on entry, if this is not the case then
it is considered a serious anomaly.*/
if (ME.GS.B.S_CURRENTMODE != SPC5_RUNMODE_DRUN) {
SPC5_CLOCK_FAILURE_HOOK();
}
#if defined(SPC5_OSC_BYPASS)
/* If the board is equipped with an oscillator instead of a xtal then the
bypass must be activated.*/
CGM.OSC_CTL.B.OSCBYP = TRUE;
#endif /* SPC5_OSC_BYPASS */
/* Setting the various dividers and source selectors.*/
CGM.SC_DC[0].R = SPC5_CGM_SC_DC0;
CGM.SC_DC[1].R = SPC5_CGM_SC_DC1;
CGM.SC_DC[2].R = SPC5_CGM_SC_DC2;
/* Initialization of the FMPLLs settings.*/
CGM.FMPLL_CR.R = SPC5_FMPLL0_ODF |
((SPC5_FMPLL0_IDF_VALUE - 1) << 26) |
(SPC5_FMPLL0_NDIV_VALUE << 16);
CGM.FMPLL_MR.R = 0; /* TODO: Add a setting. */
/* Run modes initialization.*/
ME.IS.R = 8; /* Resetting I_ICONF status.*/
ME.MER.R = SPC5_ME_ME_BITS; /* Enabled run modes. */
ME.TEST.R = SPC5_ME_TEST_MC_BITS; /* TEST run mode. */
ME.SAFE.R = SPC5_ME_SAFE_MC_BITS; /* SAFE run mode. */
ME.DRUN.R = SPC5_ME_DRUN_MC_BITS; /* DRUN run mode. */
ME.RUN[0].R = SPC5_ME_RUN0_MC_BITS; /* RUN0 run mode. */
ME.RUN[1].R = SPC5_ME_RUN1_MC_BITS; /* RUN1 run mode. */
ME.RUN[2].R = SPC5_ME_RUN2_MC_BITS; /* RUN2 run mode. */
ME.RUN[3].R = SPC5_ME_RUN3_MC_BITS; /* RUN0 run mode. */
ME.HALT0.R = SPC5_ME_HALT0_MC_BITS; /* HALT0 run mode. */
ME.STOP0.R = SPC5_ME_STOP0_MC_BITS; /* STOP0 run mode. */
ME.STANDBY0.R = SPC5_ME_STANDBY0_MC_BITS; /* STANDBY0 run mode. */
if (ME.IS.B.I_CONF) {
/* Configuration rejected.*/
SPC5_CLOCK_FAILURE_HOOK();
}
/* Peripherals run and low power modes initialization.*/
ME.RUNPC[0].R = SPC5_ME_RUN_PC0_BITS;
ME.RUNPC[1].R = SPC5_ME_RUN_PC1_BITS;
ME.RUNPC[2].R = SPC5_ME_RUN_PC2_BITS;
ME.RUNPC[3].R = SPC5_ME_RUN_PC3_BITS;
ME.RUNPC[4].R = SPC5_ME_RUN_PC4_BITS;
ME.RUNPC[5].R = SPC5_ME_RUN_PC5_BITS;
ME.RUNPC[6].R = SPC5_ME_RUN_PC6_BITS;
ME.RUNPC[7].R = SPC5_ME_RUN_PC7_BITS;
ME.LPPC[0].R = SPC5_ME_LP_PC0_BITS;
ME.LPPC[1].R = SPC5_ME_LP_PC1_BITS;
ME.LPPC[2].R = SPC5_ME_LP_PC2_BITS;
ME.LPPC[3].R = SPC5_ME_LP_PC3_BITS;
ME.LPPC[4].R = SPC5_ME_LP_PC4_BITS;
ME.LPPC[5].R = SPC5_ME_LP_PC5_BITS;
ME.LPPC[6].R = SPC5_ME_LP_PC6_BITS;
ME.LPPC[7].R = SPC5_ME_LP_PC7_BITS;
/* CFLASH settings calculated for a maximum clock of 64MHz.*/
CFLASH.PFCR0.B.BK0_APC = 2;
CFLASH.PFCR0.B.BK0_RWSC = 2;
CFLASH.PFCR1.B.BK1_APC = 2;
CFLASH.PFCR1.B.BK1_RWSC = 2;
/* Switches again to DRUN mode (current mode) in order to update the
settings.*/
if (halSPCSetRunMode(SPC5_RUNMODE_DRUN) == CH_FAILED) {
SPC5_CLOCK_FAILURE_HOOK();
}
#endif /* !SPC5_NO_INIT */
}
/**
* @brief Switches the system to the specified run mode.
*
* @param[in] mode one of the possible run modes
*
* @return The operation status.
* @retval CH_SUCCESS if the switch operation has been completed.
* @retval CH_FAILED if the switch operation failed.
*/
bool_t halSPCSetRunMode(spc5_runmode_t mode) {
/* Clearing status register bits I_IMODE(4) and I_IMTC(1).*/
ME.IS.R = 5;
/* Starts a transition process.*/
ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY;
ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY_INV;
/* Waits for the mode switch or an error condition.*/
while (TRUE) {
uint32_t r = ME.IS.R;
if (r & 1)
return CH_SUCCESS;
if (r & 4)
return CH_FAILED;
}
}
/**
* @brief Changes the clock mode of a peripheral.
*
* @param[in] n index of the @p PCTL register
* @param[in] pctl new value for the @p PCTL register
*
* @notapi
*/
void halSPCSetPeripheralClockMode(uint32_t n, uint32_t pctl) {
uint32_t mode;
ME.PCTL[n].R = pctl;
mode = ME.MCTL.B.TARGET_MODE;
ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY;
ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY_INV;
}
#if !SPC5_NO_INIT || defined(__DOXYGEN__)
/**
* @brief Returns the system clock under the current run mode.
*
* @return The system clock in Hertz.
*/
uint32_t halSPCGetSystemClock(void) {
uint32_t sysclk;
sysclk = ME.GS.B.S_SYSCLK;
switch (sysclk) {
case SPC5_ME_GS_SYSCLK_IRC:
return SPC5_IRC_CLK;
case SPC5_ME_GS_SYSCLK_DIVIRC:
return SPC5_IRC_CLK / SPC5_IRCDIV_VALUE;
case SPC5_ME_GS_SYSCLK_XOSC:
return SPC5_XOSC_CLK / SPC5_XOSCDIV_VALUE;
case SPC5_ME_GS_SYSCLK_DIVXOSC:
return SPC5_XOSC_CLK;
case SPC5_ME_GS_SYSCLK_FMPLL0:
return SPC5_FMPLL0_CLK;
default:
return 0;
}
}
#endif /* !SPC5_NO_INIT */
/** @} */

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firmware/chibios/os/hal/platforms/SPC560BCxx/hal_lld.h Executable file
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/*
SPC5 HAL - Copyright (C) 2013 STMicroelectronics
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file SPC560BCxx/hal_lld.h
* @brief SPC560B/Cxx HAL subsystem low level driver header.
* @pre This module requires the following macros to be defined in the
* @p board.h file:
* - SPC5_XOSC_CLK.
* - SPC5_OSC_BYPASS (optionally).
* .
*
* @addtogroup HAL
* @{
*/
#ifndef _HAL_LLD_H_
#define _HAL_LLD_H_
#include "xpc560bc.h"
#include "spc560bc_registry.h"
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/**
* @brief Defines the support for realtime counters in the HAL.
*/
#define HAL_IMPLEMENTS_COUNTERS FALSE
/**
* @name Platform identification
* @{
*/
#define PLATFORM_NAME "SPC560B/Cxx Car Body and Convenience"
/** @} */
/**
* @name Absolute Maximum Ratings
* @{
*/
/**
* @brief Maximum XOSC clock frequency.
*/
#define SPC5_XOSC_CLK_MAX 16000000
/**
* @brief Minimum XOSC clock frequency.
*/
#define SPC5_XOSC_CLK_MIN 4000000
/**
* @brief Maximum SXOSC clock frequency.
*/
#define SPC5_SXOSC_CLK_MAX 40000
/**
* @brief Minimum SXOSC clock frequency.
*/
#define SPC5_SXOSC_CLK_MIN 32000
/**
* @brief Maximum FMPLLs input clock frequency.
*/
#define SPC5_FMPLLIN_MIN 4000000
/**
* @brief Maximum FMPLLs input clock frequency.
*/
#define SPC5_FMPLLIN_MAX 64000000
/**
* @brief Maximum FMPLLs VCO clock frequency.
*/
#define SPC5_FMPLLVCO_MAX 512000000
/**
* @brief Maximum FMPLLs VCO clock frequency.
*/
#define SPC5_FMPLLVCO_MIN 256000000
/**
* @brief Maximum FMPLL0 output clock frequency.
*/
#define SPC5_FMPLL0_CLK_MAX 64000000
/** @} */
/**
* @name Internal clock sources
* @{
*/
#define SPC5_IRC_CLK 16000000 /**< Internal fast RC
oscillator. */
#define SPC5_SIRC_CLK 128000 /**< Internal RC slow
oscillator. */
/** @} */
/**
* @name FMPLL_CR register bits definitions
* @{
*/
#define SPC5_FMPLL_ODF_DIV2 (0U << 24)
#define SPC5_FMPLL_ODF_DIV4 (1U << 24)
#define SPC5_FMPLL_ODF_DIV8 (2U << 24)
#define SPC5_FMPLL_ODF_DIV16 (3U << 24)
/** @} */
/**
* @name ME_GS register bits definitions
* @{
*/
#define SPC5_ME_GS_SYSCLK_MASK (15U << 0)
#define SPC5_ME_GS_SYSCLK_IRC (0U << 0)
#define SPC5_ME_GS_SYSCLK_DIVIRC (1U << 0)
#define SPC5_ME_GS_SYSCLK_XOSC (2U << 0)
#define SPC5_ME_GS_SYSCLK_DIVXOSC (3U << 0)
#define SPC5_ME_GS_SYSCLK_FMPLL0 (4U << 0)
/** @} */
/**
* @name ME_ME register bits definitions
* @{
*/
#define SPC5_ME_ME_RESET (1U << 0)
#define SPC5_ME_ME_TEST (1U << 1)
#define SPC5_ME_ME_SAFE (1U << 2)
#define SPC5_ME_ME_DRUN (1U << 3)
#define SPC5_ME_ME_RUN0 (1U << 4)
#define SPC5_ME_ME_RUN1 (1U << 5)
#define SPC5_ME_ME_RUN2 (1U << 6)
#define SPC5_ME_ME_RUN3 (1U << 7)
#define SPC5_ME_ME_HALT0 (1U << 8)
#define SPC5_ME_ME_STOP0 (1U << 10)
#define SPC5_ME_ME_STANDBY0 (1U << 13)
/** @} */
/**
* @name ME_xxx_MC registers bits definitions
* @{
*/
#define SPC5_ME_MC_SYSCLK_MASK (15U << 0)
#define SPC5_ME_MC_SYSCLK(n) ((n) << 0)
#define SPC5_ME_MC_SYSCLK_IRC SPC5_ME_MC_SYSCLK(0)
#define SPC5_ME_MC_SYSCLK_DIVIRC SPC5_ME_MC_SYSCLK(1)
#define SPC5_ME_MC_SYSCLK_XOSC SPC5_ME_MC_SYSCLK(2)
#define SPC5_ME_MC_SYSCLK_DIVXOSC SPC5_ME_MC_SYSCLK(3)
#define SPC5_ME_MC_SYSCLK_FMPLL0 SPC5_ME_MC_SYSCLK(4)
#define SPC5_ME_MC_SYSCLK_DISABLED SPC5_ME_MC_SYSCLK(15)
#define SPC5_ME_MC_IRCON (1U << 4)
#define SPC5_ME_MC_XOSC0ON (1U << 5)
#define SPC5_ME_MC_PLL0ON (1U << 6)
#define SPC5_ME_MC_CFLAON_MASK (3U << 16)
#define SPC5_ME_MC_CFLAON(n) ((n) << 16)
#define SPC5_ME_MC_CFLAON_PD (1U << 16)
#define SPC5_ME_MC_CFLAON_LP (2U << 16)
#define SPC5_ME_MC_CFLAON_NORMAL (3U << 16)
#define SPC5_ME_MC_DFLAON_MASK (3U << 18)
#define SPC5_ME_MC_DFLAON(n) ((n) << 18)
#define SPC5_ME_MC_DFLAON_PD (1U << 18)
#define SPC5_ME_MC_DFLAON_LP (2U << 18)
#define SPC5_ME_MC_DFLAON_NORMAL (3U << 18)
#define SPC5_ME_MC_MVRON (1U << 20)
#define SPC5_ME_MC_PDO (1U << 23)
/** @} */
/**
* @name ME_MCTL register bits definitions
* @{
*/
#define SPC5_ME_MCTL_KEY 0x5AF0U
#define SPC5_ME_MCTL_KEY_INV 0xA50FU
#define SPC5_ME_MCTL_MODE_MASK (15U << 28)
#define SPC5_ME_MCTL_MODE(n) ((n) << 28)
/** @} */
/**
* @name ME_RUN_PCx registers bits definitions
* @{
*/
#define SPC5_ME_RUN_PC_TEST (1U << 1)
#define SPC5_ME_RUN_PC_SAFE (1U << 2)
#define SPC5_ME_RUN_PC_DRUN (1U << 3)
#define SPC5_ME_RUN_PC_RUN0 (1U << 4)
#define SPC5_ME_RUN_PC_RUN1 (1U << 5)
#define SPC5_ME_RUN_PC_RUN2 (1U << 6)
#define SPC5_ME_RUN_PC_RUN3 (1U << 7)
/** @} */
/**
* @name ME_LP_PCx registers bits definitions
* @{
*/
#define SPC5_ME_LP_PC_HALT0 (1U << 8)
#define SPC5_ME_LP_PC_STOP0 (1U << 10)
#define SPC5_ME_LP_PC_STANDBY0 (1U << 10)
/** @} */
/**
* @name ME_PCTL registers bits definitions
* @{
*/
#define SPC5_ME_PCTL_RUN_MASK (7U << 0)
#define SPC5_ME_PCTL_RUN(n) ((n) << 0)
#define SPC5_ME_PCTL_LP_MASK (7U << 3)
#define SPC5_ME_PCTL_LP(n) ((n) << 3)
#define SPC5_ME_PCTL_DBG (1U << 6)
/** @} */
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @brief Disables the clocks initialization in the HAL.
*/
#if !defined(SPC5_NO_INIT) || defined(__DOXYGEN__)
#define SPC5_NO_INIT FALSE
#endif
/**
* @brief Disables the overclock checks.
*/
#if !defined(SPC5_ALLOW_OVERCLOCK) || defined(__DOXYGEN__)
#define SPC5_ALLOW_OVERCLOCK FALSE
#endif
/**
* @brief Disables the watchdog on start.
*/
#if !defined(SPC5_DISABLE_WATCHDOG) || defined(__DOXYGEN__)
#define SPC5_DISABLE_WATCHDOG TRUE
#endif
/**
* @brief FMPLL0 IDF divider value.
* @note The default value is calculated for XOSC=8MHz and PHI=64MHz.
*/
#if !defined(SPC5_FMPLL0_IDF_VALUE) || defined(__DOXYGEN__)
#define SPC5_FMPLL0_IDF_VALUE 1
#endif
/**
* @brief FMPLL0 NDIV divider value.
* @note The default value is calculated for XOSC=8MHz and PHI=64MHz.
*/
#if !defined(SPC5_FMPLL0_NDIV_VALUE) || defined(__DOXYGEN__)
#define SPC5_FMPLL0_NDIV_VALUE 32
#endif
/**
* @brief FMPLL0 ODF divider value.
* @note The default value is calculated for XOSC=8MHz and PHI=64MHz.
*/
#if !defined(SPC5_FMPLL0_ODF) || defined(__DOXYGEN__)
#define SPC5_FMPLL0_ODF SPC5_FMPLL_ODF_DIV4
#endif
/**
* @brief XOSC divider value.
* @note The allowed range is 1...32.
*/
#if !defined(SPC5_XOSCDIV_VALUE) || defined(__DOXYGEN__)
#define SPC5_XOSCDIV_VALUE 1
#endif
/**
* @brief Fast IRC divider value.
* @note The allowed range is 1...32.
*/
#if !defined(SPC5_IRCDIV_VALUE) || defined(__DOXYGEN__)
#define SPC5_IRCDIV_VALUE 1
#endif
/**
* @brief Peripherals Set 1 clock divider value.
* @note Zero means disabled clock.
*/
#if !defined(SPC5_PERIPHERAL1_CLK_DIV_VALUE) || defined(__DOXYGEN__)
#define SPC5_PERIPHERAL1_CLK_DIV_VALUE 2
#endif
/**
* @brief Peripherals Set 2 clock divider value.
* @note Zero means disabled clock.
*/
#if !defined(SPC5_PERIPHERAL2_CLK_DIV_VALUE) || defined(__DOXYGEN__)
#define SPC5_PERIPHERAL2_CLK_DIV_VALUE 2
#endif
/**
* @brief Peripherals Set 3 clock divider value.
* @note Zero means disabled clock.
*/
#if !defined(SPC5_PERIPHERAL3_CLK_DIV_VALUE) || defined(__DOXYGEN__)
#define SPC5_PERIPHERAL3_CLK_DIV_VALUE 2
#endif
/**
* @brief Active run modes in ME_ME register.
* @note Modes RESET, SAFE, DRUN, and RUN0 modes are always enabled, there
* is no need to specify them.
*/
#if !defined(SPC5_ME_ME_BITS) || defined(__DOXYGEN__)
#define SPC5_ME_ME_BITS (SPC5_ME_ME_RUN1 | \
SPC5_ME_ME_RUN2 | \
SPC5_ME_ME_RUN3 | \
SPC5_ME_ME_HALT0 | \
SPC5_ME_ME_STOP0 | \
SPC5_ME_ME_STANDBY0)
#endif
/**
* @brief TEST mode settings.
*/
#if !defined(SPC5_ME_TEST_MC_BITS) || defined(__DOXYGEN__)
#define SPC5_ME_TEST_MC_BITS (SPC5_ME_MC_SYSCLK_IRC | \
SPC5_ME_MC_IRCON | \
SPC5_ME_MC_XOSC0ON | \
SPC5_ME_MC_PLL0ON | \
SPC5_ME_MC_CFLAON_NORMAL | \
SPC5_ME_MC_DFLAON_NORMAL | \
SPC5_ME_MC_MVRON)
#endif
/**
* @brief SAFE mode settings.
*/
#if !defined(SPC5_ME_SAFE_MC_BITS) || defined(__DOXYGEN__)
#define SPC5_ME_SAFE_MC_BITS (SPC5_ME_MC_PDO)
#endif
/**
* @brief DRUN mode settings.
*/
#if !defined(SPC5_ME_DRUN_MC_BITS) || defined(__DOXYGEN__)
#define SPC5_ME_DRUN_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
SPC5_ME_MC_IRCON | \
SPC5_ME_MC_XOSC0ON | \
SPC5_ME_MC_PLL0ON | \
SPC5_ME_MC_CFLAON_NORMAL | \
SPC5_ME_MC_DFLAON_NORMAL | \
SPC5_ME_MC_MVRON)
#endif
/**
* @brief RUN0 mode settings.
*/
#if !defined(SPC5_ME_RUN0_MC_BITS) || defined(__DOXYGEN__)
#define SPC5_ME_RUN0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
SPC5_ME_MC_IRCON | \
SPC5_ME_MC_XOSC0ON | \
SPC5_ME_MC_PLL0ON | \
SPC5_ME_MC_CFLAON_NORMAL | \
SPC5_ME_MC_DFLAON_NORMAL | \
SPC5_ME_MC_MVRON)
#endif
/**
* @brief RUN1 mode settings.
*/
#if !defined(SPC5_ME_RUN1_MC_BITS) || defined(__DOXYGEN__)
#define SPC5_ME_RUN1_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
SPC5_ME_MC_IRCON | \
SPC5_ME_MC_XOSC0ON | \
SPC5_ME_MC_PLL0ON | \
SPC5_ME_MC_CFLAON_NORMAL | \
SPC5_ME_MC_DFLAON_NORMAL | \
SPC5_ME_MC_MVRON)
#endif
/**
* @brief RUN2 mode settings.
*/
#if !defined(SPC5_ME_RUN2_MC_BITS) || defined(__DOXYGEN__)
#define SPC5_ME_RUN2_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
SPC5_ME_MC_IRCON | \
SPC5_ME_MC_XOSC0ON | \
SPC5_ME_MC_PLL0ON | \
SPC5_ME_MC_CFLAON_NORMAL | \
SPC5_ME_MC_DFLAON_NORMAL | \
SPC5_ME_MC_MVRON)
#endif
/**
* @brief RUN3 mode settings.
*/
#if !defined(SPC5_ME_RUN3_MC_BITS) || defined(__DOXYGEN__)
#define SPC5_ME_RUN3_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
SPC5_ME_MC_IRCON | \
SPC5_ME_MC_XOSC0ON | \
SPC5_ME_MC_PLL0ON | \
SPC5_ME_MC_CFLAON_NORMAL | \
SPC5_ME_MC_DFLAON_NORMAL | \
SPC5_ME_MC_MVRON)
#endif
/**
* @brief HALT0 mode settings.
*/
#if !defined(SPC5_ME_HALT0_MC_BITS) || defined(__DOXYGEN__)
#define SPC5_ME_HALT0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
SPC5_ME_MC_IRCON | \
SPC5_ME_MC_XOSC0ON | \
SPC5_ME_MC_PLL0ON | \
SPC5_ME_MC_CFLAON_NORMAL | \
SPC5_ME_MC_DFLAON_NORMAL | \
SPC5_ME_MC_MVRON)
#endif
/**
* @brief STOP0 mode settings.
*/
#if !defined(SPC5_ME_STOP0_MC_BITS) || defined(__DOXYGEN__)
#define SPC5_ME_STOP0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
SPC5_ME_MC_IRCON | \
SPC5_ME_MC_XOSC0ON | \
SPC5_ME_MC_PLL0ON | \
SPC5_ME_MC_CFLAON_NORMAL | \
SPC5_ME_MC_DFLAON_NORMAL | \
SPC5_ME_MC_MVRON)
#endif
/**
* @brief STANDBY0 mode settings.
*/
#if !defined(SPC5_ME_STANDBY0_MC_BITS) || defined(__DOXYGEN__)
#define SPC5_ME_STANDBY0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
SPC5_ME_MC_IRCON | \
SPC5_ME_MC_XOSC0ON | \
SPC5_ME_MC_PLL0ON | \
SPC5_ME_MC_CFLAON_NORMAL | \
SPC5_ME_MC_DFLAON_NORMAL | \
SPC5_ME_MC_MVRON)
#endif
/**
* @brief Peripheral mode 0 (run mode).
* @note Do not change this setting, it is expected to be the "never run"
* mode.
*/
#if !defined(SPC5_ME_RUN_PC0_BITS) || defined(__DOXYGEN__)
#define SPC5_ME_RUN_PC0_BITS 0
#endif
/**
* @brief Peripheral mode 1 (run mode).
* @note Do not change this setting, it is expected to be the "always run"
* mode.
*/
#if !defined(SPC5_ME_RUN_PC1_BITS) || defined(__DOXYGEN__)
#define SPC5_ME_RUN_PC1_BITS (SPC5_ME_RUN_PC_TEST | \
SPC5_ME_RUN_PC_SAFE | \
SPC5_ME_RUN_PC_DRUN | \
SPC5_ME_RUN_PC_RUN0 | \
SPC5_ME_RUN_PC_RUN1 | \
SPC5_ME_RUN_PC_RUN2 | \
SPC5_ME_RUN_PC_RUN3)
#endif
/**
* @brief Peripheral mode 2 (run mode).
* @note Do not change this setting, it is expected to be the "only during
* normal run" mode.
*/
#if !defined(SPC5_ME_RUN_PC2_BITS) || defined(__DOXYGEN__)
#define SPC5_ME_RUN_PC2_BITS (SPC5_ME_RUN_PC_DRUN | \
SPC5_ME_RUN_PC_RUN0 | \
SPC5_ME_RUN_PC_RUN1 | \
SPC5_ME_RUN_PC_RUN2 | \
SPC5_ME_RUN_PC_RUN3)
#endif
/**
* @brief Peripheral mode 3 (run mode).
* @note Not defined, available to application-specific modes.
*/
#if !defined(SPC5_ME_RUN_PC3_BITS) || defined(__DOXYGEN__)
#define SPC5_ME_RUN_PC3_BITS (SPC5_ME_RUN_PC_RUN0 | \
SPC5_ME_RUN_PC_RUN1 | \
SPC5_ME_RUN_PC_RUN2 | \
SPC5_ME_RUN_PC_RUN3)
#endif
/**
* @brief Peripheral mode 4 (run mode).
* @note Not defined, available to application-specific modes.
*/
#if !defined(SPC5_ME_RUN_PC4_BITS) || defined(__DOXYGEN__)
#define SPC5_ME_RUN_PC4_BITS (SPC5_ME_RUN_PC_RUN0 | \
SPC5_ME_RUN_PC_RUN1 | \
SPC5_ME_RUN_PC_RUN2 | \
SPC5_ME_RUN_PC_RUN3)
#endif
/**
* @brief Peripheral mode 5 (run mode).
* @note Not defined, available to application-specific modes.
*/
#if !defined(SPC5_ME_RUN_PC5_BITS) || defined(__DOXYGEN__)
#define SPC5_ME_RUN_PC5_BITS (SPC5_ME_RUN_PC_RUN0 | \
SPC5_ME_RUN_PC_RUN1 | \
SPC5_ME_RUN_PC_RUN2 | \
SPC5_ME_RUN_PC_RUN3)
#endif
/**
* @brief Peripheral mode 6 (run mode).
* @note Not defined, available to application-specific modes.
*/
#if !defined(SPC5_ME_RUN_PC6_BITS) || defined(__DOXYGEN__)
#define SPC5_ME_RUN_PC6_BITS (SPC5_ME_RUN_PC_RUN0 | \
SPC5_ME_RUN_PC_RUN1 | \
SPC5_ME_RUN_PC_RUN2 | \
SPC5_ME_RUN_PC_RUN3)
#endif
/**
* @brief Peripheral mode 7 (run mode).
* @note Not defined, available to application-specific modes.
*/
#if !defined(SPC5_ME_RUN_PC7_BITS) || defined(__DOXYGEN__)
#define SPC5_ME_RUN_PC7_BITS (SPC5_ME_RUN_PC_RUN0 | \
SPC5_ME_RUN_PC_RUN1 | \
SPC5_ME_RUN_PC_RUN2 | \
SPC5_ME_RUN_PC_RUN3)
#endif
/**
* @brief Peripheral mode 0 (low power mode).
* @note Do not change this setting, it is expected to be the "never run"
* mode.
*/
#if !defined(SPC5_ME_LP_PC0_BITS) || defined(__DOXYGEN__)
#define SPC5_ME_LP_PC0_BITS 0
#endif
/**
* @brief Peripheral mode 1 (low power mode).
* @note Do not change this setting, it is expected to be the "always run"
* mode.
*/
#if !defined(SPC5_ME_LP_PC1_BITS) || defined(__DOXYGEN__)
#define SPC5_ME_LP_PC1_BITS (SPC5_ME_LP_PC_HALT0 | \
SPC5_ME_LP_PC_STOP0 | \
SPC5_ME_LP_PC_STANDBY0)
#endif
/**
* @brief Peripheral mode 2 (low power mode).
* @note Do not change this setting, it is expected to be the "halt only"
* mode.
*/
#if !defined(SPC5_ME_LP_PC2_BITS) || defined(__DOXYGEN__)
#define SPC5_ME_LP_PC2_BITS (SPC5_ME_LP_PC_HALT0)
#endif
/**
* @brief Peripheral mode 3 (low power mode).
* @note Do not change this setting, it is expected to be the "stop only"
* mode.
*/
#if !defined(SPC5_ME_LP_PC3_BITS) || defined(__DOXYGEN__)
#define SPC5_ME_LP_PC3_BITS (SPC5_ME_LP_PC_STOP0)
#endif
/**
* @brief Peripheral mode 4 (low power mode).
* @note Not defined, available to application-specific modes.
*/
#if !defined(SPC5_ME_LP_PC4_BITS) || defined(__DOXYGEN__)
#define SPC5_ME_LP_PC4_BITS (SPC5_ME_LP_PC_HALT0 | \
SPC5_ME_LP_PC_STOP0)
#endif
/**
* @brief Peripheral mode 5 (low power mode).
* @note Not defined, available to application-specific modes.
*/
#if !defined(SPC5_ME_LP_PC5_BITS) || defined(__DOXYGEN__)
#define SPC5_ME_LP_PC5_BITS (SPC5_ME_LP_PC_HALT0 | \
SPC5_ME_LP_PC_STOP0)
#endif
/**
* @brief Peripheral mode 6 (low power mode).
* @note Not defined, available to application-specific modes.
*/
#if !defined(SPC5_ME_LP_PC6_BITS) || defined(__DOXYGEN__)
#define SPC5_ME_LP_PC6_BITS (SPC5_ME_LP_PC_HALT0 | \
SPC5_ME_LP_PC_STOP0)
#endif
/**
* @brief Peripheral mode 7 (low power mode).
* @note Not defined, available to application-specific modes.
*/
#if !defined(SPC5_ME_LP_PC7_BITS) || defined(__DOXYGEN__)
#define SPC5_ME_LP_PC7_BITS (SPC5_ME_LP_PC_HALT0 | \
SPC5_ME_LP_PC_STOP0)
#endif
/**
* @brief PIT channel 0 IRQ priority.
* @note This PIT channel is allocated permanently for system tick
* generation.
*/
#if !defined(SPC5_PIT0_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define SPC5_PIT0_IRQ_PRIORITY 4
#endif
/**
* @brief Clock initialization failure hook.
* @note The default is to stop the system and let the RTC restart it.
* @note The hook code must not return.
*/
#if !defined(SPC5_CLOCK_FAILURE_HOOK) || defined(__DOXYGEN__)
#define SPC5_CLOCK_FAILURE_HOOK() chSysHalt()
#endif
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/*
* Configuration-related checks.
*/
#if !defined(SPC560BCxx_MCUCONF)
#error "Using a wrong mcuconf.h file, SPC560BCxx_MCUCONF not defined"
#endif
/* Check on the XOSC frequency.*/
#if (SPC5_XOSC_CLK < SPC5_XOSC_CLK_MIN) || \
(SPC5_XOSC_CLK > SPC5_XOSC_CLK_MAX)
#error "invalid SPC5_XOSC_CLK value specified"
#endif
/* Check on the XOSC divider.*/
#if (SPC5_XOSCDIV_VALUE < 1) || (SPC5_XOSCDIV_VALUE > 32)
#error "invalid SPC5_XOSCDIV_VALUE value specified"
#endif
/* Check on the IRC divider.*/
#if (SPC5_IRCDIV_VALUE < 1) || (SPC5_IRCDIV_VALUE > 32)
#error "invalid SPC5_IRCDIV_VALUE value specified"
#endif
/* Check on SPC5_FMPLL0_IDF_VALUE.*/
#if (SPC5_FMPLL0_IDF_VALUE < 1) || (SPC5_FMPLL0_IDF_VALUE > 15)
#error "invalid SPC5_FMPLL0_IDF_VALUE value specified"
#endif
/* Check on SPC5_FMPLL0_NDIV_VALUE.*/
#if (SPC5_FMPLL0_NDIV_VALUE < 32) || (SPC5_FMPLL0_NDIV_VALUE > 96)
#error "invalid SPC5_FMPLL0_NDIV_VALUE value specified"
#endif
/* Check on SPC5_FMPLL0_ODF.*/
#if (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV2)
#define SPC5_FMPLL0_ODF_VALUE 2
#elif (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV4)
#define SPC5_FMPLL0_ODF_VALUE 4
#elif (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV8)
#define SPC5_FMPLL0_ODF_VALUE 8
#elif (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV16)
#define SPC5_FMPLL0_ODF_VALUE 16
#else
#error "invalid SPC5_FMPLL0_ODF value specified"
#endif
/**
* @brief SPC5_FMPLL0_VCO_CLK clock point.
*/
#define SPC5_FMPLL0_VCO_CLK \
((SPC5_XOSC_CLK / SPC5_FMPLL0_IDF_VALUE) * SPC5_FMPLL0_NDIV_VALUE)
/* Check on FMPLL0 VCO output.*/
#if (SPC5_FMPLL0_VCO_CLK < SPC5_FMPLLVCO_MIN) || \
(SPC5_FMPLL0_VCO_CLK > SPC5_FMPLLVCO_MAX)
#error "SPC5_FMPLL0_VCO_CLK outside acceptable range (SPC5_FMPLLVCO_MIN...SPC5_FMPLLVCO_MAX)"
#endif
/**
* @brief SPC5_FMPLL0_CLK clock point.
*/
#define SPC5_FMPLL0_CLK \
(SPC5_FMPLL0_VCO_CLK / SPC5_FMPLL0_ODF_VALUE)
/* Check on SPC5_FMPLL0_CLK.*/
#if (SPC5_FMPLL0_CLK > SPC5_FMPLL0_CLK_MAX) && !SPC5_ALLOW_OVERCLOCK
#error "SPC5_FMPLL0_CLK outside acceptable range (0...SPC5_FMPLL0_CLK_MAX)"
#endif
/* Check on the peripherals set 1 clock divider settings.*/
#if SPC5_PERIPHERAL1_CLK_DIV_VALUE == 0
#define SPC5_CGM_SC_DC0 0
#elif (SPC5_PERIPHERAL1_CLK_DIV_VALUE >= 1) && \
(SPC5_PERIPHERAL1_CLK_DIV_VALUE <= 16)
#define SPC5_CGM_SC_DC0 (0x80 | (SPC5_PERIPHERAL1_CLK_DIV_VALUE - 1))
#else
#error "invalid SPC5_PERIPHERAL1_CLK_DIV_VALUE value specified"
#endif
/* Check on the peripherals set 2 clock divider settings.*/
#if SPC5_PERIPHERAL2_CLK_DIV_VALUE == 0
#define SPC5_CGM_SC_DC1 0
#elif (SPC5_PERIPHERAL2_CLK_DIV_VALUE >= 1) && \
(SPC5_PERIPHERAL2_CLK_DIV_VALUE <= 16)
#define SPC5_CGM_SC_DC1 (0x80 | (SPC5_PERIPHERAL2_CLK_DIV_VALUE - 1))
#else
#error "invalid SPC5_PERIPHERAL2_CLK_DIV_VALUE value specified"
#endif
/* Check on the peripherals set 3 clock divider settings.*/
#if SPC5_PERIPHERAL3_CLK_DIV_VALUE == 0
#define SPC5_CGM_SC_DC2 0
#elif (SPC5_PERIPHERAL3_CLK_DIV_VALUE >= 1) && \
(SPC5_PERIPHERAL3_CLK_DIV_VALUE <= 16)
#define SPC5_CGM_SC_DC2 (0x80 | (SPC5_PERIPHERAL3_CLK_DIV_VALUE - 1))
#else
#error "invalid SPC5_PERIPHERAL3_CLK_DIV_VALUE value specified"
#endif
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
typedef enum {
SPC5_RUNMODE_TEST = 1,
SPC5_RUNMODE_SAFE = 2,
SPC5_RUNMODE_DRUN = 3,
SPC5_RUNMODE_RUN0 = 4,
SPC5_RUNMODE_RUN1 = 5,
SPC5_RUNMODE_RUN2 = 6,
SPC5_RUNMODE_RUN3 = 7,
SPC5_RUNMODE_HALT0 = 8,
SPC5_RUNMODE_STOP0 = 10
} spc5_runmode_t;
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#include "spc5_edma.h"
#ifdef __cplusplus
extern "C" {
#endif
void hal_lld_init(void);
void spc_clock_init(void);
bool_t halSPCSetRunMode(spc5_runmode_t mode);
void halSPCSetPeripheralClockMode(uint32_t n, uint32_t pctl);
#if !SPC5_NO_INIT
uint32_t halSPCGetSystemClock(void);
#endif
#ifdef __cplusplus
}
#endif
#endif /* _HAL_LLD_H_ */
/** @} */

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firmware/chibios/os/hal/platforms/SPC560BCxx/platform.mk Executable file
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# List of all the SPC560B/Cxx platform files.
PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/SPC560BCxx/hal_lld.c \
${CHIBIOS}/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.c \
${CHIBIOS}/os/hal/platforms/SPC5xx/SIUL_v1/pal_lld.c \
${CHIBIOS}/os/hal/platforms/SPC5xx/LINFlex_v1/serial_lld.c
# Required include directories
PLATFORMINC = ${CHIBIOS}/os/hal/platforms/SPC560BCxx \
${CHIBIOS}/os/hal/platforms/SPC5xx/EDMA_v1 \
${CHIBIOS}/os/hal/platforms/SPC5xx/SIUL_v1 \
${CHIBIOS}/os/hal/platforms/SPC5xx/LINFlex_v1

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firmware/chibios/os/hal/platforms/SPC560BCxx/spc560bc_registry.h Executable file
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/*
SPC5 HAL - Copyright (C) 2013 STMicroelectronics
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file SPC560BCxx/spc560bc_registry.h
* @brief SPC560B/Cxx capabilities registry.
*
* @addtogroup HAL
* @{
*/
#ifndef _SPC560BC_REGISTRY_H_
#define _SPC560BC_REGISTRY_H_
/*===========================================================================*/
/* Platform capabilities. */
/*===========================================================================*/
/**
* @name SPC560B/Cxx capabilities
* @{
*/
/* eDMA attributes.*/
#define SPC5_HAS_EDMA FALSE
/* LINFlex attributes.*/
#define SPC5_HAS_LINFLEX0 TRUE
#define SPC5_LINFLEX0_PCTL 48
#define SPC5_LINFLEX0_RXI_HANDLER vector79
#define SPC5_LINFLEX0_TXI_HANDLER vector80
#define SPC5_LINFLEX0_ERR_HANDLER vector81
#define SPC5_LINFLEX0_RXI_NUMBER 79
#define SPC5_LINFLEX0_TXI_NUMBER 80
#define SPC5_LINFLEX0_ERR_NUMBER 81
#define SPC5_LINFLEX0_CLK (halSPCGetSystemClock() / \
SPC5_PERIPHERAL1_CLK_DIV_VALUE)
#define SPC5_HAS_LINFLEX1 TRUE
#define SPC5_LINFLEX1_PCTL 49
#define SPC5_LINFLEX1_RXI_HANDLER vector99
#define SPC5_LINFLEX1_TXI_HANDLER vector100
#define SPC5_LINFLEX1_ERR_HANDLER vector101
#define SPC5_LINFLEX1_RXI_NUMBER 99
#define SPC5_LINFLEX1_TXI_NUMBER 100
#define SPC5_LINFLEX1_ERR_NUMBER 101
#define SPC5_LINFLEX1_CLK (halSPCGetSystemClock() / \
SPC5_PERIPHERAL1_CLK_DIV_VALUE)
#define SPC5_HAS_LINFLEX2 TRUE
#define SPC5_LINFLEX2_PCTL 50
#define SPC5_LINFLEX2_RXI_HANDLER vector119
#define SPC5_LINFLEX2_TXI_HANDLER vector120
#define SPC5_LINFLEX2_ERR_HANDLER vector121
#define SPC5_LINFLEX2_RXI_NUMBER 119
#define SPC5_LINFLEX2_TXI_NUMBER 120
#define SPC5_LINFLEX2_ERR_NUMBER 121
#define SPC5_LINFLEX2_CLK (halSPCGetSystemClock() / \
SPC5_PERIPHERAL1_CLK_DIV_VALUE)
#define SPC5_HAS_LINFLEX3 TRUE
#define SPC5_LINFLEX3_PCTL 51
#define SPC5_LINFLEX3_RXI_HANDLER vector122
#define SPC5_LINFLEX3_TXI_HANDLER vector123
#define SPC5_LINFLEX3_ERR_HANDLER vector124
#define SPC5_LINFLEX3_RXI_NUMBER 122
#define SPC5_LINFLEX3_TXI_NUMBER 123
#define SPC5_LINFLEX3_ERR_NUMBER 124
#define SPC5_LINFLEX3_CLK (halSPCGetSystemClock() / \
SPC5_PERIPHERAL1_CLK_DIV_VALUE)
/* SIUL attributes.*/
#define SPC5_HAS_SIUL TRUE
#define SPC5_SIUL_PCTL 68
#define SPC5_SIUL_NUM_PORTS 8
#define SPC5_SIUL_NUM_PCRS 123
#define SPC5_SIUL_NUM_PADSELS 32
#define SPC5_SIUL_SYSTEM_PINS 32,33,121,122
/** @} */
#endif /* _SPC560BC_REGISTRY_H_ */
/** @} */

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firmware/chibios/os/hal/platforms/SPC560BCxx/typedefs.h Executable file
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/*
SPC5 HAL - Copyright (C) 2013 STMicroelectronics
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file SPC560BCxx/typedefs.h
* @brief Dummy typedefs file.
*/
#ifndef _TYPEDEFS_H_
#define _TYPEDEFS_H_
#include "chtypes.h"
#endif /* _TYPEDEFS_H_ */

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firmware/chibios/os/hal/platforms/SPC560BCxx/xpc560bc.h Executable file
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