mirror of
https://github.com/portapack-mayhem/mayhem-firmware.git
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ChibiOS 2.6.8, until I can figure out where to get it from git.
This commit is contained in:
Jared Boone
281
firmware/chibios/os/hal/platforms/SPC560BCxx/hal_lld.c
Executable file
281
firmware/chibios/os/hal/platforms/SPC560BCxx/hal_lld.c
Executable file
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/*
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SPC5 HAL - Copyright (C) 2013 STMicroelectronics
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file SPC560BCxx/hal_lld.c
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* @brief SPC560B/Cxx HAL subsystem low level driver source.
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*
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* @addtogroup HAL
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* @{
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*/
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#include "ch.h"
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#include "hal.h"
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local variables and types. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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/**
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* @brief PIT channel 3 interrupt handler.
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*
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* @isr
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*/
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CH_IRQ_HANDLER(vector59) {
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CH_IRQ_PROLOGUE();
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chSysLockFromIsr();
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chSysTimerHandlerI();
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chSysUnlockFromIsr();
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/* Resets the PIT channel 3 IRQ flag.*/
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PIT.CH[0].TFLG.R = 1;
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CH_IRQ_EPILOGUE();
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}
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/**
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* @brief Low level HAL driver initialization.
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*
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* @notapi
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*/
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void hal_lld_init(void) {
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uint32_t reg;
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/* The system is switched to the RUN0 mode, the default for normal
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operations.*/
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if (halSPCSetRunMode(SPC5_RUNMODE_RUN0) == CH_FAILED) {
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SPC5_CLOCK_FAILURE_HOOK();
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}
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/* INTC initialization, software vector mode, 4 bytes vectors, starting
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at priority 0.*/
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INTC.MCR.R = 0;
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INTC.CPR.R = 0;
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INTC.IACKR.R = (uint32_t)_vectors;
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/* PIT channel 0 initialization for Kernel ticks, the PIT is configured
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to run in DRUN,RUN0...RUN3 and HALT0 modes, the clock is gated in other
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modes.*/
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INTC.PSR[59].R = SPC5_PIT0_IRQ_PRIORITY;
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halSPCSetPeripheralClockMode(92,
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SPC5_ME_PCTL_RUN(2) | SPC5_ME_PCTL_LP(2));
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reg = halSPCGetSystemClock() / CH_FREQUENCY - 1;
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PIT.PITMCR.R = 1; /* PIT clock enabled, stop while debugging. */
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PIT.CH[0].LDVAL.R = reg;
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PIT.CH[0].CVAL.R = reg;
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PIT.CH[0].TFLG.R = 1; /* Interrupt flag cleared. */
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PIT.CH[0].TCTRL.R = 3; /* Timer active, interrupt enabled. */
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}
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/**
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* @brief SPC560B/Cxx clocks and PLL initialization.
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* @note All the involved constants come from the file @p board.h and
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* @p hal_lld.h
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* @note This function must be invoked only after the system reset.
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*
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* @special
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*/
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void spc_clock_init(void) {
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/* Waiting for IRC stabilization before attempting anything else.*/
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while (!ME.GS.B.S_FIRC)
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;
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#if !SPC5_NO_INIT
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#if SPC5_DISABLE_WATCHDOG
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/* SWT disabled.*/
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SWT.SR.R = 0xC520;
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SWT.SR.R = 0xD928;
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SWT.CR.R = 0xFF00000A;
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#endif
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/* SSCM initialization. Setting up the most restrictive handling of
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invalid accesses to peripherals.*/
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SSCM.ERROR.R = 3; /* PAE and RAE bits. */
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/* RGM errors clearing.*/
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RGM.FES.R = 0xFFFF;
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RGM.DES.R = 0xFFFF;
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/* Oscillators dividers setup.*/
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CGM.FIRC_CTL.B.RCDIV = SPC5_IRCDIV_VALUE - 1;
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CGM.FXOSC_CTL.B.OSCDIV = SPC5_XOSCDIV_VALUE - 1;
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/* The system must be in DRUN mode on entry, if this is not the case then
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it is considered a serious anomaly.*/
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if (ME.GS.B.S_CURRENTMODE != SPC5_RUNMODE_DRUN) {
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SPC5_CLOCK_FAILURE_HOOK();
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}
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#if defined(SPC5_OSC_BYPASS)
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/* If the board is equipped with an oscillator instead of a xtal then the
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bypass must be activated.*/
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CGM.OSC_CTL.B.OSCBYP = TRUE;
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#endif /* SPC5_OSC_BYPASS */
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/* Setting the various dividers and source selectors.*/
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CGM.SC_DC[0].R = SPC5_CGM_SC_DC0;
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CGM.SC_DC[1].R = SPC5_CGM_SC_DC1;
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CGM.SC_DC[2].R = SPC5_CGM_SC_DC2;
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/* Initialization of the FMPLLs settings.*/
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CGM.FMPLL_CR.R = SPC5_FMPLL0_ODF |
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((SPC5_FMPLL0_IDF_VALUE - 1) << 26) |
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(SPC5_FMPLL0_NDIV_VALUE << 16);
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CGM.FMPLL_MR.R = 0; /* TODO: Add a setting. */
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/* Run modes initialization.*/
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ME.IS.R = 8; /* Resetting I_ICONF status.*/
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ME.MER.R = SPC5_ME_ME_BITS; /* Enabled run modes. */
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ME.TEST.R = SPC5_ME_TEST_MC_BITS; /* TEST run mode. */
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ME.SAFE.R = SPC5_ME_SAFE_MC_BITS; /* SAFE run mode. */
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ME.DRUN.R = SPC5_ME_DRUN_MC_BITS; /* DRUN run mode. */
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ME.RUN[0].R = SPC5_ME_RUN0_MC_BITS; /* RUN0 run mode. */
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ME.RUN[1].R = SPC5_ME_RUN1_MC_BITS; /* RUN1 run mode. */
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ME.RUN[2].R = SPC5_ME_RUN2_MC_BITS; /* RUN2 run mode. */
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ME.RUN[3].R = SPC5_ME_RUN3_MC_BITS; /* RUN0 run mode. */
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ME.HALT0.R = SPC5_ME_HALT0_MC_BITS; /* HALT0 run mode. */
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ME.STOP0.R = SPC5_ME_STOP0_MC_BITS; /* STOP0 run mode. */
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ME.STANDBY0.R = SPC5_ME_STANDBY0_MC_BITS; /* STANDBY0 run mode. */
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if (ME.IS.B.I_CONF) {
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/* Configuration rejected.*/
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SPC5_CLOCK_FAILURE_HOOK();
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}
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/* Peripherals run and low power modes initialization.*/
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ME.RUNPC[0].R = SPC5_ME_RUN_PC0_BITS;
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ME.RUNPC[1].R = SPC5_ME_RUN_PC1_BITS;
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ME.RUNPC[2].R = SPC5_ME_RUN_PC2_BITS;
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ME.RUNPC[3].R = SPC5_ME_RUN_PC3_BITS;
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ME.RUNPC[4].R = SPC5_ME_RUN_PC4_BITS;
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ME.RUNPC[5].R = SPC5_ME_RUN_PC5_BITS;
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ME.RUNPC[6].R = SPC5_ME_RUN_PC6_BITS;
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ME.RUNPC[7].R = SPC5_ME_RUN_PC7_BITS;
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ME.LPPC[0].R = SPC5_ME_LP_PC0_BITS;
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ME.LPPC[1].R = SPC5_ME_LP_PC1_BITS;
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ME.LPPC[2].R = SPC5_ME_LP_PC2_BITS;
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ME.LPPC[3].R = SPC5_ME_LP_PC3_BITS;
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ME.LPPC[4].R = SPC5_ME_LP_PC4_BITS;
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ME.LPPC[5].R = SPC5_ME_LP_PC5_BITS;
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ME.LPPC[6].R = SPC5_ME_LP_PC6_BITS;
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ME.LPPC[7].R = SPC5_ME_LP_PC7_BITS;
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/* CFLASH settings calculated for a maximum clock of 64MHz.*/
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CFLASH.PFCR0.B.BK0_APC = 2;
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CFLASH.PFCR0.B.BK0_RWSC = 2;
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CFLASH.PFCR1.B.BK1_APC = 2;
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CFLASH.PFCR1.B.BK1_RWSC = 2;
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/* Switches again to DRUN mode (current mode) in order to update the
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settings.*/
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if (halSPCSetRunMode(SPC5_RUNMODE_DRUN) == CH_FAILED) {
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SPC5_CLOCK_FAILURE_HOOK();
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}
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#endif /* !SPC5_NO_INIT */
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}
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/**
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* @brief Switches the system to the specified run mode.
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*
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* @param[in] mode one of the possible run modes
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*
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* @return The operation status.
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* @retval CH_SUCCESS if the switch operation has been completed.
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* @retval CH_FAILED if the switch operation failed.
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*/
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bool_t halSPCSetRunMode(spc5_runmode_t mode) {
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/* Clearing status register bits I_IMODE(4) and I_IMTC(1).*/
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ME.IS.R = 5;
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/* Starts a transition process.*/
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ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY;
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ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY_INV;
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/* Waits for the mode switch or an error condition.*/
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while (TRUE) {
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uint32_t r = ME.IS.R;
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if (r & 1)
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return CH_SUCCESS;
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if (r & 4)
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return CH_FAILED;
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}
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}
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/**
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* @brief Changes the clock mode of a peripheral.
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*
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* @param[in] n index of the @p PCTL register
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* @param[in] pctl new value for the @p PCTL register
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*
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* @notapi
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*/
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void halSPCSetPeripheralClockMode(uint32_t n, uint32_t pctl) {
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uint32_t mode;
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ME.PCTL[n].R = pctl;
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mode = ME.MCTL.B.TARGET_MODE;
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ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY;
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ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY_INV;
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}
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#if !SPC5_NO_INIT || defined(__DOXYGEN__)
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/**
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* @brief Returns the system clock under the current run mode.
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*
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* @return The system clock in Hertz.
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*/
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uint32_t halSPCGetSystemClock(void) {
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uint32_t sysclk;
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sysclk = ME.GS.B.S_SYSCLK;
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switch (sysclk) {
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case SPC5_ME_GS_SYSCLK_IRC:
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return SPC5_IRC_CLK;
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case SPC5_ME_GS_SYSCLK_DIVIRC:
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return SPC5_IRC_CLK / SPC5_IRCDIV_VALUE;
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case SPC5_ME_GS_SYSCLK_XOSC:
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return SPC5_XOSC_CLK / SPC5_XOSCDIV_VALUE;
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case SPC5_ME_GS_SYSCLK_DIVXOSC:
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return SPC5_XOSC_CLK;
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case SPC5_ME_GS_SYSCLK_FMPLL0:
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return SPC5_FMPLL0_CLK;
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default:
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return 0;
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}
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}
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#endif /* !SPC5_NO_INIT */
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/** @} */
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