mirror of
https://github.com/portapack-mayhem/mayhem-firmware.git
synced 2025-08-25 11:17:26 +00:00
ChibiOS 2.6.8, until I can figure out where to get it from git.
This commit is contained in:
Jared Boone
184
firmware/chibios/os/hal/platforms/STM32/GPIOv1/pal_lld.c
Executable file
184
firmware/chibios/os/hal/platforms/STM32/GPIOv1/pal_lld.c
Executable file
@@ -0,0 +1,184 @@
|
||||
/*
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||||
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
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|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
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||||
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/**
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* @file STM32/GPIOv1/pal_lld.c
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* @brief STM32F1xx GPIO low level driver code.
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*
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* @addtogroup PAL
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* @{
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*/
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#include "ch.h"
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#include "hal.h"
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#if HAL_USE_PAL || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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#if STM32_HAS_GPIOG
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#define APB2_EN_MASK (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | \
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RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | \
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RCC_APB2ENR_IOPEEN | RCC_APB2ENR_IOPFEN | \
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RCC_APB2ENR_IOPGEN | RCC_APB2ENR_AFIOEN)
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#elif STM32_HAS_GPIOE
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#define APB2_EN_MASK (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | \
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RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | \
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RCC_APB2ENR_IOPEEN | RCC_APB2ENR_AFIOEN)
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#else
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#define APB2_EN_MASK (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | \
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RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | \
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RCC_APB2ENR_AFIOEN)
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#endif
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local variables and types. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/**
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* @brief STM32 I/O ports configuration.
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* @details Ports A-D(E, F, G) clocks enabled, AFIO clock enabled.
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*
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* @param[in] config the STM32 ports configuration
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*
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* @notapi
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*/
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void _pal_lld_init(const PALConfig *config) {
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/*
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* Enables the GPIO related clocks.
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*/
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rccEnableAPB2(APB2_EN_MASK, FALSE);
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/*
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* Initial GPIO setup.
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*/
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GPIOA->ODR = config->PAData.odr;
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GPIOA->CRH = config->PAData.crh;
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GPIOA->CRL = config->PAData.crl;
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GPIOB->ODR = config->PBData.odr;
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GPIOB->CRH = config->PBData.crh;
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GPIOB->CRL = config->PBData.crl;
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GPIOC->ODR = config->PCData.odr;
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GPIOC->CRH = config->PCData.crh;
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GPIOC->CRL = config->PCData.crl;
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GPIOD->ODR = config->PDData.odr;
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GPIOD->CRH = config->PDData.crh;
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GPIOD->CRL = config->PDData.crl;
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#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
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GPIOE->ODR = config->PEData.odr;
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GPIOE->CRH = config->PEData.crh;
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GPIOE->CRL = config->PEData.crl;
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#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
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GPIOF->ODR = config->PFData.odr;
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GPIOF->CRH = config->PFData.crh;
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GPIOF->CRL = config->PFData.crl;
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#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
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GPIOG->ODR = config->PGData.odr;
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GPIOG->CRH = config->PGData.crh;
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GPIOG->CRL = config->PGData.crl;
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#endif
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#endif
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#endif
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}
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/**
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* @brief Pads mode setup.
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* @details This function programs a pads group belonging to the same port
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* with the specified mode.
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* @note @p PAL_MODE_UNCONNECTED is implemented as push pull output at 2MHz.
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* @note Writing on pads programmed as pull-up or pull-down has the side
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* effect to modify the resistor setting because the output latched
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* data is used for the resistor selection.
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*
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* @param[in] port the port identifier
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* @param[in] mask the group mask
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* @param[in] mode the mode
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*
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* @notapi
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*/
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void _pal_lld_setgroupmode(ioportid_t port,
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ioportmask_t mask,
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iomode_t mode) {
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static const uint8_t cfgtab[] = {
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4, /* PAL_MODE_RESET, implemented as input.*/
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2, /* PAL_MODE_UNCONNECTED, implemented as push pull output 2MHz.*/
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4, /* PAL_MODE_INPUT */
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8, /* PAL_MODE_INPUT_PULLUP */
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8, /* PAL_MODE_INPUT_PULLDOWN */
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0, /* PAL_MODE_INPUT_ANALOG */
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3, /* PAL_MODE_OUTPUT_PUSHPULL, 50MHz.*/
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7, /* PAL_MODE_OUTPUT_OPENDRAIN, 50MHz.*/
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8, /* Reserved.*/
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8, /* Reserved.*/
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8, /* Reserved.*/
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8, /* Reserved.*/
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8, /* Reserved.*/
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8, /* Reserved.*/
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8, /* Reserved.*/
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8, /* Reserved.*/
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0xB, /* PAL_MODE_STM32_ALTERNATE_PUSHPULL, 50MHz.*/
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0xF, /* PAL_MODE_STM32_ALTERNATE_OPENDRAIN, 50MHz.*/
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};
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uint32_t mh, ml, crh, crl, cfg;
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unsigned i;
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if (mode == PAL_MODE_INPUT_PULLUP)
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port->BSRR = mask;
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else if (mode == PAL_MODE_INPUT_PULLDOWN)
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port->BRR = mask;
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cfg = cfgtab[mode];
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mh = ml = crh = crl = 0;
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for (i = 0; i < 8; i++) {
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ml <<= 4;
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mh <<= 4;
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crl <<= 4;
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crh <<= 4;
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if ((mask & 0x0080) == 0)
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ml |= 0xf;
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else
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crl |= cfg;
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if ((mask & 0x8000) == 0)
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mh |= 0xf;
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else
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crh |= cfg;
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mask <<= 1;
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}
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port->CRH = (port->CRH & mh) | crh;
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port->CRL = (port->CRL & ml) | crl;
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}
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#endif /* HAL_USE_PAL */
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/** @} */
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334
firmware/chibios/os/hal/platforms/STM32/GPIOv1/pal_lld.h
Executable file
334
firmware/chibios/os/hal/platforms/STM32/GPIOv1/pal_lld.h
Executable file
@@ -0,0 +1,334 @@
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/*
|
||||
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
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* @file STM32/GPIOv1/pal_lld.h
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* @brief STM32F1xx GPIO low level driver header.
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*
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* @addtogroup PAL
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* @{
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*/
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#ifndef _PAL_LLD_H_
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#define _PAL_LLD_H_
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#if HAL_USE_PAL || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Unsupported modes and specific modes */
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/*===========================================================================*/
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/**
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* @name STM32-specific I/O mode flags
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* @{
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*/
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/**
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* @brief STM32 specific alternate push-pull output mode.
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*/
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#define PAL_MODE_STM32_ALTERNATE_PUSHPULL 16
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/**
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* @brief STM32 specific alternate open-drain output mode.
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*/
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#define PAL_MODE_STM32_ALTERNATE_OPENDRAIN 17
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/** @} */
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/*===========================================================================*/
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/* I/O Ports Types and constants. */
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/*===========================================================================*/
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/**
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* @brief GPIO port setup info.
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*/
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typedef struct {
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/** Initial value for ODR register.*/
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uint32_t odr;
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/** Initial value for CRL register.*/
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uint32_t crl;
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/** Initial value for CRH register.*/
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uint32_t crh;
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} stm32_gpio_setup_t;
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/**
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* @brief STM32 GPIO static initializer.
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* @details An instance of this structure must be passed to @p palInit() at
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* system startup time in order to initialize the digital I/O
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* subsystem. This represents only the initial setup, specific pads
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* or whole ports can be reprogrammed at later time.
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*/
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typedef struct {
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/** @brief Port A setup data.*/
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stm32_gpio_setup_t PAData;
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/** @brief Port B setup data.*/
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stm32_gpio_setup_t PBData;
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/** @brief Port C setup data.*/
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stm32_gpio_setup_t PCData;
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/** @brief Port D setup data.*/
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stm32_gpio_setup_t PDData;
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#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
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/** @brief Port E setup data.*/
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stm32_gpio_setup_t PEData;
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#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
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/** @brief Port F setup data.*/
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stm32_gpio_setup_t PFData;
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#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
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/** @brief Port G setup data.*/
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stm32_gpio_setup_t PGData;
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#endif
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||||
#endif
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#endif
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} PALConfig;
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/**
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* @brief Width, in bits, of an I/O port.
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*/
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#define PAL_IOPORTS_WIDTH 16
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/**
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* @brief Whole port mask.
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* @details This macro specifies all the valid bits into a port.
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*/
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#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFF)
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/**
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* @brief Digital I/O port sized unsigned type.
|
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*/
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typedef uint32_t ioportmask_t;
|
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/**
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* @brief Digital I/O modes.
|
||||
*/
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typedef uint32_t iomode_t;
|
||||
|
||||
/**
|
||||
* @brief Port Identifier.
|
||||
* @details This type can be a scalar or some kind of pointer, do not make
|
||||
* any assumption about it, use the provided macros when populating
|
||||
* variables of this type.
|
||||
*/
|
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typedef GPIO_TypeDef * ioportid_t;
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||||
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/*===========================================================================*/
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/* I/O Ports Identifiers. */
|
||||
/* The low level driver wraps the definitions already present in the STM32 */
|
||||
/* firmware library. */
|
||||
/*===========================================================================*/
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|
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/**
|
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* @brief GPIO port A identifier.
|
||||
*/
|
||||
#if STM32_HAS_GPIOA || defined(__DOXYGEN__)
|
||||
#define IOPORT1 GPIOA
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief GPIO port B identifier.
|
||||
*/
|
||||
#if STM32_HAS_GPIOB || defined(__DOXYGEN__)
|
||||
#define IOPORT2 GPIOB
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief GPIO port C identifier.
|
||||
*/
|
||||
#if STM32_HAS_GPIOC || defined(__DOXYGEN__)
|
||||
#define IOPORT3 GPIOC
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief GPIO port D identifier.
|
||||
*/
|
||||
#if STM32_HAS_GPIOD || defined(__DOXYGEN__)
|
||||
#define IOPORT4 GPIOD
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief GPIO port E identifier.
|
||||
*/
|
||||
#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
|
||||
#define IOPORT5 GPIOE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief GPIO port F identifier.
|
||||
*/
|
||||
#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
|
||||
#define IOPORT6 GPIOF
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief GPIO port G identifier.
|
||||
*/
|
||||
#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
|
||||
#define IOPORT7 GPIOG
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Implementation, some of the following macros could be implemented as */
|
||||
/* functions, if so please put them in pal_lld.c. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief GPIO ports subsystem initialization.
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
#define pal_lld_init(config) _pal_lld_init(config)
|
||||
|
||||
/**
|
||||
* @brief Reads an I/O port.
|
||||
* @details This function is implemented by reading the GPIO IDR register, the
|
||||
* implementation has no side effects.
|
||||
* @note This function is not meant to be invoked directly by the application
|
||||
* code.
|
||||
*
|
||||
* @param[in] port port identifier
|
||||
* @return The port bits.
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
#define pal_lld_readport(port) ((port)->IDR)
|
||||
|
||||
/**
|
||||
* @brief Reads the output latch.
|
||||
* @details This function is implemented by reading the GPIO ODR register, the
|
||||
* implementation has no side effects.
|
||||
* @note This function is not meant to be invoked directly by the application
|
||||
* code.
|
||||
*
|
||||
* @param[in] port port identifier
|
||||
* @return The latched logical states.
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
#define pal_lld_readlatch(port) ((port)->ODR)
|
||||
|
||||
/**
|
||||
* @brief Writes on a I/O port.
|
||||
* @details This function is implemented by writing the GPIO ODR register, the
|
||||
* implementation has no side effects.
|
||||
* @note Writing on pads programmed as pull-up or pull-down has the side
|
||||
* effect to modify the resistor setting because the output latched
|
||||
* data is used for the resistor selection.
|
||||
*
|
||||
* @param[in] port port identifier
|
||||
* @param[in] bits bits to be written on the specified port
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
#define pal_lld_writeport(port, bits) ((port)->ODR = (bits))
|
||||
|
||||
/**
|
||||
* @brief Sets a bits mask on a I/O port.
|
||||
* @details This function is implemented by writing the GPIO BSRR register, the
|
||||
* implementation has no side effects.
|
||||
* @note Writing on pads programmed as pull-up or pull-down has the side
|
||||
* effect to modify the resistor setting because the output latched
|
||||
* data is used for the resistor selection.
|
||||
*
|
||||
* @param[in] port port identifier
|
||||
* @param[in] bits bits to be ORed on the specified port
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
#define pal_lld_setport(port, bits) ((port)->BSRR = (bits))
|
||||
|
||||
/**
|
||||
* @brief Clears a bits mask on a I/O port.
|
||||
* @details This function is implemented by writing the GPIO BRR register, the
|
||||
* implementation has no side effects.
|
||||
* @note Writing on pads programmed as pull-up or pull-down has the side
|
||||
* effect to modify the resistor setting because the output latched
|
||||
* data is used for the resistor selection.
|
||||
*
|
||||
* @param[in] port port identifier
|
||||
* @param[in] bits bits to be cleared on the specified port
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
#define pal_lld_clearport(port, bits) ((port)->BRR = (bits))
|
||||
|
||||
/**
|
||||
* @brief Writes a group of bits.
|
||||
* @details This function is implemented by writing the GPIO BSRR register, the
|
||||
* implementation has no side effects.
|
||||
* @note Writing on pads programmed as pull-up or pull-down has the side
|
||||
* effect to modify the resistor setting because the output latched
|
||||
* data is used for the resistor selection.
|
||||
*
|
||||
* @param[in] port port identifier
|
||||
* @param[in] mask group mask
|
||||
* @param[in] offset the group bit offset within the port
|
||||
* @param[in] bits bits to be written. Values exceeding the group
|
||||
* width are masked.
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
#define pal_lld_writegroup(port, mask, offset, bits) \
|
||||
((port)->BSRR = ((~(bits) & (mask)) << (16 + (offset))) | \
|
||||
(((bits) & (mask)) << (offset)))
|
||||
|
||||
/**
|
||||
* @brief Pads group mode setup.
|
||||
* @details This function programs a pads group belonging to the same port
|
||||
* with the specified mode.
|
||||
* @note Writing on pads programmed as pull-up or pull-down has the side
|
||||
* effect to modify the resistor setting because the output latched
|
||||
* data is used for the resistor selection.
|
||||
*
|
||||
* @param[in] port port identifier
|
||||
* @param[in] mask group mask
|
||||
* @param[in] offset group bit offset within the port
|
||||
* @param[in] mode group mode
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
#define pal_lld_setgroupmode(port, mask, offset, mode) \
|
||||
_pal_lld_setgroupmode(port, mask << offset, mode)
|
||||
|
||||
/**
|
||||
* @brief Writes a logical state on an output pad.
|
||||
* @note Writing on pads programmed as pull-up or pull-down has the side
|
||||
* effect to modify the resistor setting because the output latched
|
||||
* data is used for the resistor selection.
|
||||
*
|
||||
* @param[in] port port identifier
|
||||
* @param[in] pad pad number within the port
|
||||
* @param[in] bit logical value, the value must be @p PAL_LOW or
|
||||
* @p PAL_HIGH
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
#define pal_lld_writepad(port, pad, bit) pal_lld_writegroup(port, 1, pad, bit)
|
||||
|
||||
extern const PALConfig pal_default_config;
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void _pal_lld_init(const PALConfig *config);
|
||||
void _pal_lld_setgroupmode(ioportid_t port,
|
||||
ioportmask_t mask,
|
||||
iomode_t mode);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* HAL_USE_PAL */
|
||||
|
||||
#endif /* _PAL_LLD_H_ */
|
||||
|
||||
/** @} */
|
||||
Reference in New Issue
Block a user