mirror of
https://github.com/portapack-mayhem/mayhem-firmware.git
synced 2025-08-25 05:27:45 +00:00
ChibiOS 2.6.8, until I can figure out where to get it from git.
This commit is contained in:
Jared Boone
298
firmware/chibios/os/hal/platforms/STM32F0xx/adc_lld.c
Executable file
298
firmware/chibios/os/hal/platforms/STM32F0xx/adc_lld.c
Executable file
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/*
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ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file STM32F0xx/adc_lld.c
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* @brief STM32F0xx ADC subsystem low level driver source.
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*
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* @addtogroup ADC
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* @{
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*/
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#include "ch.h"
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#include "hal.h"
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#if HAL_USE_ADC || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/** @brief ADC1 driver identifier.*/
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#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__)
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ADCDriver ADCD1;
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#endif
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/*===========================================================================*/
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/* Driver local variables and types. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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/**
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* @brief Stops an ongoing conversion, if any.
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*
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* @param[in] adc pointer to the ADC registers block
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*/
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static void adc_lld_stop_adc(ADC_TypeDef *adc) {
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if (adc->CR & ADC_CR_ADSTART) {
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adc->CR |= ADC_CR_ADSTP;
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while (adc->CR & ADC_CR_ADSTP)
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;
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}
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}
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/**
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* @brief ADC DMA ISR service routine.
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*
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* @param[in] adcp pointer to the @p ADCDriver object
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* @param[in] flags pre-shifted content of the ISR register
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*/
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static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) {
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/* DMA errors handling.*/
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if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
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/* DMA, this could help only if the DMA tries to access an unmapped
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address space or violates alignment rules.*/
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_adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE);
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}
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else {
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/* It is possible that the conversion group has already be reset by the
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ADC error handler, in this case this interrupt is spurious.*/
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if (adcp->grpp != NULL) {
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if ((flags & STM32_DMA_ISR_TCIF) != 0) {
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/* Transfer complete processing.*/
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_adc_isr_full_code(adcp);
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}
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else if ((flags & STM32_DMA_ISR_HTIF) != 0) {
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/* Half transfer processing.*/
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_adc_isr_half_code(adcp);
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}
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}
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}
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}
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__)
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/**
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* @brief ADC interrupt handler.
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*
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* @isr
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*/
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CH_IRQ_HANDLER(Vector70) {
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uint32_t isr;
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CH_IRQ_PROLOGUE();
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isr = ADC1->ISR;
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ADC1->ISR = isr;
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/* It could be a spurious interrupt caused by overflows after DMA disabling,
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just ignore it in this case.*/
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if (ADCD1.grpp != NULL) {
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/* Note, an overflow may occur after the conversion ended before the driver
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is able to stop the ADC, this is why the DMA channel is checked too.*/
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if ((isr & ADC_ISR_OVR) &&
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(dmaStreamGetTransactionSize(ADCD1.dmastp) > 0)) {
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/* ADC overflow condition, this could happen only if the DMA is unable
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to read data fast enough.*/
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_adc_isr_error_code(&ADCD1, ADC_ERR_OVERFLOW);
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}
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if (isr & ADC_ISR_AWD) {
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/* Analog watchdog error.*/
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_adc_isr_error_code(&ADCD1, ADC_ERR_AWD);
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}
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}
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CH_IRQ_EPILOGUE();
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}
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#endif
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/**
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* @brief Low level ADC driver initialization.
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*
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* @notapi
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*/
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void adc_lld_init(void) {
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#if STM32_ADC_USE_ADC1
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/* Driver initialization.*/
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adcObjectInit(&ADCD1);
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ADCD1.adc = ADC1;
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ADCD1.dmastp = STM32_DMA1_STREAM1;
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ADCD1.dmamode = STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) |
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STM32_DMA_CR_DIR_P2M |
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STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
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STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
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STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
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#endif
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/* The shared vector is initialized on driver initialization and never
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disabled.*/
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nvicEnableVector(12, CORTEX_PRIORITY_MASK(STM32_ADC_IRQ_PRIORITY));
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/* Calibration procedure.*/
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rccEnableADC1(FALSE);
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chDbgAssert(ADC1->CR == 0, "adc_lld_init(), #1", "invalid register state");
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ADC1->CR |= ADC_CR_ADCAL;
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while (ADC1->CR & ADC_CR_ADCAL)
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;
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rccDisableADC1(FALSE);
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}
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/**
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* @brief Configures and activates the ADC peripheral.
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*
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* @param[in] adcp pointer to the @p ADCDriver object
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*
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* @notapi
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*/
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void adc_lld_start(ADCDriver *adcp) {
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/* If in stopped state then enables the ADC and DMA clocks.*/
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if (adcp->state == ADC_STOP) {
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#if STM32_ADC_USE_ADC1
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if (&ADCD1 == adcp) {
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bool_t b;
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b = dmaStreamAllocate(adcp->dmastp,
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STM32_ADC_ADC1_DMA_IRQ_PRIORITY,
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(stm32_dmaisr_t)adc_lld_serve_rx_interrupt,
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(void *)adcp);
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chDbgAssert(!b, "adc_lld_start(), #1", "stream already allocated");
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dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR);
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rccEnableADC1(FALSE);
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#if STM32_ADCSW == STM32_ADCSW_HSI14
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/* Clock from HSI14, no need for jitter removal.*/
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ADC1->CFGR2 = 0;
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#else
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#if STM32_ADCPRE == STM32_ADCPRE_DIV2
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ADC1->CFGR2 = ADC_CFGR2_JITOFFDIV2;
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#else
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ADC1->CFGR2 = ADC_CFGR2_JITOFFDIV4;
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#endif
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#endif
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}
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#endif /* STM32_ADC_USE_ADC1 */
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/* ADC initial setup, starting the analog part here in order to reduce
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the latency when starting a conversion.*/
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adcp->adc->CR = ADC_CR_ADEN;
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while (!(adcp->adc->ISR & ADC_ISR_ADRDY))
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;
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}
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}
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/**
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* @brief Deactivates the ADC peripheral.
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*
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* @param[in] adcp pointer to the @p ADCDriver object
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*
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* @notapi
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*/
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void adc_lld_stop(ADCDriver *adcp) {
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/* If in ready state then disables the ADC clock and analog part.*/
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if (adcp->state == ADC_READY) {
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dmaStreamRelease(adcp->dmastp);
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/* Disabling ADC.*/
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if (adcp->adc->CR & ADC_CR_ADEN) {
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adc_lld_stop_adc(adcp->adc);
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adcp->adc->CR |= ADC_CR_ADDIS;
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while (adcp->adc->CR & ADC_CR_ADDIS)
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;
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}
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#if STM32_ADC_USE_ADC1
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if (&ADCD1 == adcp)
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rccDisableADC1(FALSE);
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#endif
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}
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}
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/**
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* @brief Starts an ADC conversion.
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*
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* @param[in] adcp pointer to the @p ADCDriver object
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*
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* @notapi
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*/
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void adc_lld_start_conversion(ADCDriver *adcp) {
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uint32_t mode, cfgr1;
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const ADCConversionGroup *grpp = adcp->grpp;
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/* DMA setup.*/
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mode = adcp->dmamode;
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cfgr1 = grpp->cfgr1 | ADC_CFGR1_DMAEN;
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if (grpp->circular) {
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mode |= STM32_DMA_CR_CIRC;
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cfgr1 |= ADC_CFGR1_DMACFG;
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if (adcp->depth > 1) {
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/* If circular buffer depth > 1, then the half transfer interrupt
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is enabled in order to allow streaming processing.*/
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mode |= STM32_DMA_CR_HTIE;
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}
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}
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dmaStreamSetMemory0(adcp->dmastp, adcp->samples);
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dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels *
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(uint32_t)adcp->depth);
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dmaStreamSetMode(adcp->dmastp, mode);
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dmaStreamEnable(adcp->dmastp);
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/* ADC setup, if it is defined a callback for the analog watch dog then it
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is enabled.*/
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adcp->adc->ISR = adcp->adc->ISR;
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adcp->adc->IER = ADC_IER_OVRIE | ADC_IER_AWDIE;
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adcp->adc->TR = grpp->tr;
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adcp->adc->SMPR = grpp->smpr;
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adcp->adc->CHSELR = grpp->chselr;
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/* ADC configuration and start.*/
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adcp->adc->CFGR1 = cfgr1;
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adcp->adc->CR |= ADC_CR_ADSTART;
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}
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/**
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* @brief Stops an ongoing conversion.
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*
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* @param[in] adcp pointer to the @p ADCDriver object
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*
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* @notapi
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*/
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void adc_lld_stop_conversion(ADCDriver *adcp) {
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dmaStreamDisable(adcp->dmastp);
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adc_lld_stop_adc(adcp->adc);
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}
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#endif /* HAL_USE_ADC */
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/** @} */
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