mirror of
https://github.com/portapack-mayhem/mayhem-firmware.git
synced 2025-08-25 08:38:18 +00:00
ChibiOS 2.6.8, until I can figure out where to get it from git.
This commit is contained in:
Jared Boone
528
firmware/chibios/os/hal/platforms/STM32F4xx/stm32_dma.c
Executable file
528
firmware/chibios/os/hal/platforms/STM32F4xx/stm32_dma.c
Executable file
@@ -0,0 +1,528 @@
|
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/*
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ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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||||
you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
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||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
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||||
limitations under the License.
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||||
*/
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/**
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* @file STM32F4xx/stm32_dma.c
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* @brief Enhanced DMA helper driver code.
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*
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* @addtogroup STM32F4xx_DMA
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* @details DMA sharing helper driver. In the STM32 the DMA streams are a
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* shared resource, this driver allows to allocate and free DMA
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* streams at runtime in order to allow all the other device
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* drivers to coordinate the access to the resource.
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* @note The DMA ISR handlers are all declared into this module because
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* sharing, the various device drivers can associate a callback to
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* ISRs when allocating streams.
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* @{
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*/
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#include "ch.h"
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#include "hal.h"
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/* The following macro is only defined if some driver requiring DMA services
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has been enabled.*/
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#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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/**
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* @brief Mask of the DMA1 streams in @p dma_streams_mask.
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*/
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#define STM32_DMA1_STREAMS_MASK 0x000000FF
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/**
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* @brief Mask of the DMA2 streams in @p dma_streams_mask.
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*/
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#define STM32_DMA2_STREAMS_MASK 0x0000FF00
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/**
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* @brief Post-reset value of the stream CR register.
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*/
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#define STM32_DMA_CR_RESET_VALUE 0x00000000
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/**
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* @brief Post-reset value of the stream FCR register.
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*/
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#define STM32_DMA_FCR_RESET_VALUE 0x00000021
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/**
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* @brief DMA streams descriptors.
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* @details This table keeps the association between an unique stream
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* identifier and the involved physical registers.
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* @note Don't use this array directly, use the appropriate wrapper macros
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* instead: @p STM32_DMA1_STREAM0, @p STM32_DMA1_STREAM1 etc.
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*/
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const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = {
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{DMA1_Stream0, &DMA1->LIFCR, 0, 0, DMA1_Stream0_IRQn},
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{DMA1_Stream1, &DMA1->LIFCR, 6, 1, DMA1_Stream1_IRQn},
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{DMA1_Stream2, &DMA1->LIFCR, 16, 2, DMA1_Stream2_IRQn},
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{DMA1_Stream3, &DMA1->LIFCR, 22, 3, DMA1_Stream3_IRQn},
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{DMA1_Stream4, &DMA1->HIFCR, 0, 4, DMA1_Stream4_IRQn},
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{DMA1_Stream5, &DMA1->HIFCR, 6, 5, DMA1_Stream5_IRQn},
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{DMA1_Stream6, &DMA1->HIFCR, 16, 6, DMA1_Stream6_IRQn},
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{DMA1_Stream7, &DMA1->HIFCR, 22, 7, DMA1_Stream7_IRQn},
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{DMA2_Stream0, &DMA2->LIFCR, 0, 8, DMA2_Stream0_IRQn},
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{DMA2_Stream1, &DMA2->LIFCR, 6, 9, DMA2_Stream1_IRQn},
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{DMA2_Stream2, &DMA2->LIFCR, 16, 10, DMA2_Stream2_IRQn},
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{DMA2_Stream3, &DMA2->LIFCR, 22, 11, DMA2_Stream3_IRQn},
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{DMA2_Stream4, &DMA2->HIFCR, 0, 12, DMA2_Stream4_IRQn},
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{DMA2_Stream5, &DMA2->HIFCR, 6, 13, DMA2_Stream5_IRQn},
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{DMA2_Stream6, &DMA2->HIFCR, 16, 14, DMA2_Stream6_IRQn},
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{DMA2_Stream7, &DMA2->HIFCR, 22, 15, DMA2_Stream7_IRQn},
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};
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/*===========================================================================*/
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/* Driver local variables and types. */
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/*===========================================================================*/
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/**
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* @brief DMA ISR redirector type.
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*/
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typedef struct {
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stm32_dmaisr_t dma_func; /**< @brief DMA callback function. */
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void *dma_param; /**< @brief DMA callback parameter. */
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} dma_isr_redir_t;
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/**
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* @brief Mask of the allocated streams.
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*/
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static uint32_t dma_streams_mask;
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/**
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* @brief DMA IRQ redirectors.
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*/
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static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS];
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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/**
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* @brief DMA1 stream 0 shared interrupt handler.
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*
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* @isr
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*/
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CH_IRQ_HANDLER(DMA1_Stream0_IRQHandler) {
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uint32_t flags;
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CH_IRQ_PROLOGUE();
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flags = (DMA1->LISR >> 0) & STM32_DMA_ISR_MASK;
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DMA1->LIFCR = flags << 0;
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if (dma_isr_redir[0].dma_func)
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dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags);
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CH_IRQ_EPILOGUE();
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}
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/**
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* @brief DMA1 stream 1 shared interrupt handler.
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*
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* @isr
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*/
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CH_IRQ_HANDLER(DMA1_Stream1_IRQHandler) {
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uint32_t flags;
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CH_IRQ_PROLOGUE();
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flags = (DMA1->LISR >> 6) & STM32_DMA_ISR_MASK;
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DMA1->LIFCR = flags << 6;
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if (dma_isr_redir[1].dma_func)
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dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags);
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CH_IRQ_EPILOGUE();
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}
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/**
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* @brief DMA1 stream 2 shared interrupt handler.
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*
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* @isr
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*/
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CH_IRQ_HANDLER(DMA1_Stream2_IRQHandler) {
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uint32_t flags;
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CH_IRQ_PROLOGUE();
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flags = (DMA1->LISR >> 16) & STM32_DMA_ISR_MASK;
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DMA1->LIFCR = flags << 16;
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if (dma_isr_redir[2].dma_func)
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dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags);
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CH_IRQ_EPILOGUE();
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}
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/**
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* @brief DMA1 stream 3 shared interrupt handler.
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*
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* @isr
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*/
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CH_IRQ_HANDLER(DMA1_Stream3_IRQHandler) {
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uint32_t flags;
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CH_IRQ_PROLOGUE();
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flags = (DMA1->LISR >> 22) & STM32_DMA_ISR_MASK;
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DMA1->LIFCR = flags << 22;
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if (dma_isr_redir[3].dma_func)
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dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags);
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CH_IRQ_EPILOGUE();
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}
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/**
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* @brief DMA1 stream 4 shared interrupt handler.
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*
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* @isr
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*/
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CH_IRQ_HANDLER(DMA1_Stream4_IRQHandler) {
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uint32_t flags;
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CH_IRQ_PROLOGUE();
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flags = (DMA1->HISR >> 0) & STM32_DMA_ISR_MASK;
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DMA1->HIFCR = flags << 0;
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if (dma_isr_redir[4].dma_func)
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dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags);
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CH_IRQ_EPILOGUE();
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}
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/**
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* @brief DMA1 stream 5 shared interrupt handler.
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*
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* @isr
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*/
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CH_IRQ_HANDLER(DMA1_Stream5_IRQHandler) {
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uint32_t flags;
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CH_IRQ_PROLOGUE();
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flags = (DMA1->HISR >> 6) & STM32_DMA_ISR_MASK;
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DMA1->HIFCR = flags << 6;
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if (dma_isr_redir[5].dma_func)
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dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags);
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CH_IRQ_EPILOGUE();
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}
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/**
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* @brief DMA1 stream 6 shared interrupt handler.
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*
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* @isr
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*/
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CH_IRQ_HANDLER(DMA1_Stream6_IRQHandler) {
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uint32_t flags;
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CH_IRQ_PROLOGUE();
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flags = (DMA1->HISR >> 16) & STM32_DMA_ISR_MASK;
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DMA1->HIFCR = flags << 16;
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if (dma_isr_redir[6].dma_func)
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dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags);
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CH_IRQ_EPILOGUE();
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}
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/**
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* @brief DMA1 stream 7 shared interrupt handler.
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*
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* @isr
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*/
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CH_IRQ_HANDLER(DMA1_Stream7_IRQHandler) {
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uint32_t flags;
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CH_IRQ_PROLOGUE();
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flags = (DMA1->HISR >> 22) & STM32_DMA_ISR_MASK;
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DMA1->HIFCR = flags << 22;
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if (dma_isr_redir[7].dma_func)
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dma_isr_redir[7].dma_func(dma_isr_redir[7].dma_param, flags);
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CH_IRQ_EPILOGUE();
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}
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/**
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* @brief DMA2 stream 0 shared interrupt handler.
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*
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* @isr
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*/
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CH_IRQ_HANDLER(DMA2_Stream0_IRQHandler) {
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uint32_t flags;
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CH_IRQ_PROLOGUE();
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flags = (DMA2->LISR >> 0) & STM32_DMA_ISR_MASK;
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DMA2->LIFCR = flags << 0;
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if (dma_isr_redir[8].dma_func)
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dma_isr_redir[8].dma_func(dma_isr_redir[8].dma_param, flags);
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CH_IRQ_EPILOGUE();
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}
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/**
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* @brief DMA2 stream 1 shared interrupt handler.
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*
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* @isr
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*/
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CH_IRQ_HANDLER(DMA2_Stream1_IRQHandler) {
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uint32_t flags;
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CH_IRQ_PROLOGUE();
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flags = (DMA2->LISR >> 6) & STM32_DMA_ISR_MASK;
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DMA2->LIFCR = flags << 6;
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if (dma_isr_redir[9].dma_func)
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dma_isr_redir[9].dma_func(dma_isr_redir[9].dma_param, flags);
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CH_IRQ_EPILOGUE();
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}
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/**
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* @brief DMA2 stream 2 shared interrupt handler.
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*
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* @isr
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*/
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CH_IRQ_HANDLER(DMA2_Stream2_IRQHandler) {
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uint32_t flags;
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CH_IRQ_PROLOGUE();
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flags = (DMA2->LISR >> 16) & STM32_DMA_ISR_MASK;
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DMA2->LIFCR = flags << 16;
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if (dma_isr_redir[10].dma_func)
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dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags);
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CH_IRQ_EPILOGUE();
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}
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/**
|
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* @brief DMA2 stream 3 shared interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(DMA2_Stream3_IRQHandler) {
|
||||
uint32_t flags;
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
flags = (DMA2->LISR >> 22) & STM32_DMA_ISR_MASK;
|
||||
DMA2->LIFCR = flags << 22;
|
||||
if (dma_isr_redir[11].dma_func)
|
||||
dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA2 stream 4 shared interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(DMA2_Stream4_IRQHandler) {
|
||||
uint32_t flags;
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
flags = (DMA2->HISR >> 0) & STM32_DMA_ISR_MASK;
|
||||
DMA2->HIFCR = flags << 0;
|
||||
if (dma_isr_redir[12].dma_func)
|
||||
dma_isr_redir[12].dma_func(dma_isr_redir[12].dma_param, flags);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA2 stream 5 shared interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(DMA2_Stream5_IRQHandler) {
|
||||
uint32_t flags;
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
flags = (DMA2->HISR >> 6) & STM32_DMA_ISR_MASK;
|
||||
DMA2->HIFCR = flags << 6;
|
||||
if (dma_isr_redir[13].dma_func)
|
||||
dma_isr_redir[13].dma_func(dma_isr_redir[13].dma_param, flags);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA2 stream 6 shared interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(DMA2_Stream6_IRQHandler) {
|
||||
uint32_t flags;
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
flags = (DMA2->HISR >> 16) & STM32_DMA_ISR_MASK;
|
||||
DMA2->HIFCR = flags << 16;
|
||||
if (dma_isr_redir[14].dma_func)
|
||||
dma_isr_redir[14].dma_func(dma_isr_redir[14].dma_param, flags);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA2 stream 7 shared interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(DMA2_Stream7_IRQHandler) {
|
||||
uint32_t flags;
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
flags = (DMA2->HISR >> 22) & STM32_DMA_ISR_MASK;
|
||||
DMA2->HIFCR = flags << 22;
|
||||
if (dma_isr_redir[15].dma_func)
|
||||
dma_isr_redir[15].dma_func(dma_isr_redir[15].dma_param, flags);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver exported functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief STM32 DMA helper initialization.
|
||||
*
|
||||
* @init
|
||||
*/
|
||||
void dmaInit(void) {
|
||||
int i;
|
||||
|
||||
dma_streams_mask = 0;
|
||||
for (i = 0; i < STM32_DMA_STREAMS; i++) {
|
||||
_stm32_dma_streams[i].stream->CR = 0;
|
||||
dma_isr_redir[i].dma_func = NULL;
|
||||
}
|
||||
DMA1->LIFCR = 0xFFFFFFFF;
|
||||
DMA1->HIFCR = 0xFFFFFFFF;
|
||||
DMA2->LIFCR = 0xFFFFFFFF;
|
||||
DMA2->HIFCR = 0xFFFFFFFF;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Allocates a DMA stream.
|
||||
* @details The stream is allocated and, if required, the DMA clock enabled.
|
||||
* The function also enables the IRQ vector associated to the stream
|
||||
* and initializes its priority.
|
||||
* @pre The stream must not be already in use or an error is returned.
|
||||
* @post The stream is allocated and the default ISR handler redirected
|
||||
* to the specified function.
|
||||
* @post The stream ISR vector is enabled and its priority configured.
|
||||
* @post The stream must be freed using @p dmaStreamRelease() before it can
|
||||
* be reused with another peripheral.
|
||||
* @post The stream is in its post-reset state.
|
||||
* @note This function can be invoked in both ISR or thread context.
|
||||
*
|
||||
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
|
||||
* @param[in] priority IRQ priority mask for the DMA stream
|
||||
* @param[in] func handling function pointer, can be @p NULL
|
||||
* @param[in] param a parameter to be passed to the handling function
|
||||
* @return The operation status.
|
||||
* @retval FALSE no error, stream taken.
|
||||
* @retval TRUE error, stream already taken.
|
||||
*
|
||||
* @special
|
||||
*/
|
||||
bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
|
||||
uint32_t priority,
|
||||
stm32_dmaisr_t func,
|
||||
void *param) {
|
||||
|
||||
chDbgCheck(dmastp != NULL, "dmaStreamAllocate");
|
||||
|
||||
/* Checks if the stream is already taken.*/
|
||||
if ((dma_streams_mask & (1 << dmastp->selfindex)) != 0)
|
||||
return TRUE;
|
||||
|
||||
/* Marks the stream as allocated.*/
|
||||
dma_isr_redir[dmastp->selfindex].dma_func = func;
|
||||
dma_isr_redir[dmastp->selfindex].dma_param = param;
|
||||
dma_streams_mask |= (1 << dmastp->selfindex);
|
||||
|
||||
/* Enabling DMA clocks required by the current streams set.*/
|
||||
if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) != 0)
|
||||
rccEnableDMA1(FALSE);
|
||||
if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) != 0)
|
||||
rccEnableDMA2(FALSE);
|
||||
|
||||
/* Putting the stream in a safe state.*/
|
||||
dmaStreamDisable(dmastp);
|
||||
dmastp->stream->CR = STM32_DMA_CR_RESET_VALUE;
|
||||
dmastp->stream->FCR = STM32_DMA_FCR_RESET_VALUE;
|
||||
|
||||
/* Enables the associated IRQ vector if a callback is defined.*/
|
||||
if (func != NULL)
|
||||
nvicEnableVector(dmastp->vector, CORTEX_PRIORITY_MASK(priority));
|
||||
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Releases a DMA stream.
|
||||
* @details The stream is freed and, if required, the DMA clock disabled.
|
||||
* Trying to release a unallocated stream is an illegal operation
|
||||
* and is trapped if assertions are enabled.
|
||||
* @pre The stream must have been allocated using @p dmaStreamAllocate().
|
||||
* @post The stream is again available.
|
||||
* @note This function can be invoked in both ISR or thread context.
|
||||
*
|
||||
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
|
||||
*
|
||||
* @special
|
||||
*/
|
||||
void dmaStreamRelease(const stm32_dma_stream_t *dmastp) {
|
||||
|
||||
chDbgCheck(dmastp != NULL, "dmaStreamRelease");
|
||||
|
||||
/* Check if the streams is not taken.*/
|
||||
chDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0,
|
||||
"dmaStreamRelease(), #1", "not allocated");
|
||||
|
||||
/* Disables the associated IRQ vector.*/
|
||||
nvicDisableVector(dmastp->vector);
|
||||
|
||||
/* Marks the stream as not allocated.*/
|
||||
dma_streams_mask &= ~(1 << dmastp->selfindex);
|
||||
|
||||
/* Shutting down clocks that are no more required, if any.*/
|
||||
if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0)
|
||||
rccDisableDMA1(FALSE);
|
||||
if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) == 0)
|
||||
rccDisableDMA2(FALSE);
|
||||
}
|
||||
|
||||
#endif /* STM32_DMA_REQUIRED */
|
||||
|
||||
/** @} */
|
||||
Reference in New Issue
Block a user