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ChibiOS 2.6.8, until I can figure out where to get it from git.

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Jared Boone
2015-07-08 08:40:23 -07:00
parent dc6fee8370
commit e1eea8e08a
1929 changed files with 575326 additions and 0 deletions
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69
firmware/chibios/os/ports/IAR/ARMCMx/LPC11xx/cmparams.h Executable file
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/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
/**
* @file IAR/ARMCMx/LPC11xx/cmparams.h
* @brief ARM Cortex-M0 parameters for the LPC11xx.
*
* @defgroup IAR_ARMCMx_LPC11xx LPC11xx Specific Parameters
* @ingroup IAR_ARMCMx_SPECIFIC
* @details This file contains the Cortex-M0 specific parameters for the
* LPC11xx platform.
* @{
*/
#ifndef _CMPARAMS_H_
#define _CMPARAMS_H_
/**
* @brief Cortex core model.
*/
#define CORTEX_MODEL CORTEX_M0
/**
* @brief Systick unit presence.
*/
#define CORTEX_HAS_ST TRUE
/**
* @brief Memory Protection unit presence.
*/
#define CORTEX_HAS_MPU FALSE
/**
* @brief Floating Point unit presence.
*/
#define CORTEX_HAS_FPU FALSE
/**
* @brief Number of bits in priority masks.
*/
#define CORTEX_PRIORITY_BITS 2
#endif /* _CMPARAMS_H_ */
/** @} */

194
firmware/chibios/os/ports/IAR/ARMCMx/LPC11xx/vectors.s Executable file
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/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
MODULE ?vectors
AAPCS INTERWORK, VFP_COMPATIBLE, RWPI_COMPATIBLE
PRESERVE8
SECTION IRQSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
PUBLIC __vector_table
DATA
__vector_table:
DCD SFE(IRQSTACK)
DCD __iar_program_start
DCD NMIVector
DCD HardFaultVector
DCD MemManageVector
DCD BusFaultVector
DCD UsageFaultVector
DCD Vector1C
DCD Vector20
DCD Vector24
DCD Vector28
DCD SVCallVector
DCD DebugMonitorVector
DCD Vector34
DCD PendSVVector
DCD SysTickVector
DCD Vector40
DCD Vector44
DCD Vector48
DCD Vector4C
DCD Vector50
DCD Vector54
DCD Vector58
DCD Vector5C
DCD Vector60
DCD Vector64
DCD Vector68
DCD Vector6C
DCD Vector70
DCD Vector74
DCD Vector78
DCD Vector7C
DCD Vector80
DCD Vector84
DCD Vector88
DCD Vector8C
DCD Vector90
DCD Vector94
DCD Vector98
DCD Vector9C
DCD VectorA0
DCD VectorA4
DCD VectorA8
DCD VectorAC
DCD VectorB0
DCD VectorB4
DCD VectorB8
DCD VectorBC
/*
* Default interrupt handlers.
*/
PUBWEAK NMIVector
PUBWEAK HardFaultVector
PUBWEAK MemManageVector
PUBWEAK BusFaultVector
PUBWEAK UsageFaultVector
PUBWEAK Vector1C
PUBWEAK Vector20
PUBWEAK Vector24
PUBWEAK Vector28
PUBWEAK SVCallVector
PUBWEAK DebugMonitorVector
PUBWEAK Vector34
PUBWEAK PendSVVector
PUBWEAK SysTickVector
PUBWEAK Vector40
PUBWEAK Vector44
PUBWEAK Vector48
PUBWEAK Vector4C
PUBWEAK Vector50
PUBWEAK Vector54
PUBWEAK Vector58
PUBWEAK Vector5C
PUBWEAK Vector60
PUBWEAK Vector64
PUBWEAK Vector68
PUBWEAK Vector6C
PUBWEAK Vector70
PUBWEAK Vector74
PUBWEAK Vector78
PUBWEAK Vector7C
PUBWEAK Vector80
PUBWEAK Vector84
PUBWEAK Vector88
PUBWEAK Vector8C
PUBWEAK Vector90
PUBWEAK Vector94
PUBWEAK Vector98
PUBWEAK Vector9C
PUBWEAK VectorA0
PUBWEAK VectorA4
PUBWEAK VectorA8
PUBWEAK VectorAC
PUBWEAK VectorB0
PUBWEAK VectorB4
PUBWEAK VectorB8
PUBWEAK VectorBC
PUBLIC _unhandled_exception
SECTION .text:CODE:REORDER(1)
THUMB
NMIVector
HardFaultVector
MemManageVector
BusFaultVector
UsageFaultVector
Vector1C
Vector20
Vector24
Vector28
SVCallVector
DebugMonitorVector
Vector34
PendSVVector
SysTickVector
Vector40
Vector44
Vector48
Vector4C
Vector50
Vector54
Vector58
Vector5C
Vector60
Vector64
Vector68
Vector6C
Vector70
Vector74
Vector78
Vector7C
Vector80
Vector84
Vector88
Vector8C
Vector90
Vector94
Vector98
Vector9C
VectorA0
VectorA4
VectorA8
VectorAC
VectorB0
VectorB4
VectorB8
VectorBC
_unhandled_exception
b _unhandled_exception
END

69
firmware/chibios/os/ports/IAR/ARMCMx/LPC13xx/cmparams.h Executable file
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/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
/**
* @file IAR/ARMCMx/LPC13xx/cmparams.h
* @brief ARM Cortex-M3 parameters for the LPC13xx.
*
* @defgroup IAR_ARMCMx_LPC13xx LPC13xx Specific Parameters
* @ingroup IAR_ARMCMx_SPECIFIC
* @details This file contains the Cortex-M3 specific parameters for the
* LPC13xx platform.
* @{
*/
#ifndef _CMPARAMS_H_
#define _CMPARAMS_H_
/**
* @brief Cortex core model.
*/
#define CORTEX_MODEL CORTEX_M3
/**
* @brief Systick unit presence.
*/
#define CORTEX_HAS_ST TRUE
/**
* @brief Memory Protection unit presence.
*/
#define CORTEX_HAS_MPU FALSE
/**
* @brief Floating Point unit presence.
*/
#define CORTEX_HAS_FPU FALSE
/**
* @brief Number of bits in priority masks.
*/
#define CORTEX_PRIORITY_BITS 3
#endif /* _CMPARAMS_H_ */
/** @} */

272
firmware/chibios/os/ports/IAR/ARMCMx/LPC13xx/vectors.s Executable file
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/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
MODULE ?vectors
AAPCS INTERWORK, VFP_COMPATIBLE, RWPI_COMPATIBLE
PRESERVE8
SECTION IRQSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
PUBLIC __vector_table
DATA
__vector_table:
DCD SFE(IRQSTACK)
DCD __iar_program_start
DCD NMIVector
DCD HardFaultVector
DCD MemManageVector
DCD BusFaultVector
DCD UsageFaultVector
DCD Vector1C
DCD Vector20
DCD Vector24
DCD Vector28
DCD SVCallVector
DCD DebugMonitorVector
DCD Vector34
DCD PendSVVector
DCD SysTickVector
DCD Vector40
DCD Vector44
DCD Vector48
DCD Vector4C
DCD Vector50
DCD Vector54
DCD Vector58
DCD Vector5C
DCD Vector60
DCD Vector64
DCD Vector68
DCD Vector6C
DCD Vector70
DCD Vector74
DCD Vector78
DCD Vector7C
DCD Vector80
DCD Vector84
DCD Vector88
DCD Vector8C
DCD Vector90
DCD Vector94
DCD Vector98
DCD Vector9C
DCD VectorA0
DCD VectorA4
DCD VectorA8
DCD VectorAC
DCD VectorB0
DCD VectorB4
DCD VectorB8
DCD VectorBC
DCD VectorC0
DCD VectorC4
DCD VectorC8
DCD VectorCC
DCD VectorD0
DCD VectorD4
DCD VectorD8
DCD VectorDC
DCD VectorE0
DCD VectorE4
DCD VectorE8
DCD VectorEC
DCD VectorF0
DCD VectorF4
DCD VectorF8
DCD VectorFC
DCD Vector100
DCD Vector104
DCD Vector108
DCD Vector10C
DCD Vector110
DCD Vector114
DCD Vector118
DCD Vector11C
DCD Vector120
DCD Vector124
/*
* Default interrupt handlers.
*/
PUBWEAK NMIVector
PUBWEAK HardFaultVector
PUBWEAK MemManageVector
PUBWEAK BusFaultVector
PUBWEAK UsageFaultVector
PUBWEAK Vector1C
PUBWEAK Vector20
PUBWEAK Vector24
PUBWEAK Vector28
PUBWEAK SVCallVector
PUBWEAK DebugMonitorVector
PUBWEAK Vector34
PUBWEAK PendSVVector
PUBWEAK SysTickVector
PUBWEAK Vector40
PUBWEAK Vector44
PUBWEAK Vector48
PUBWEAK Vector4C
PUBWEAK Vector50
PUBWEAK Vector54
PUBWEAK Vector58
PUBWEAK Vector5C
PUBWEAK Vector60
PUBWEAK Vector64
PUBWEAK Vector68
PUBWEAK Vector6C
PUBWEAK Vector70
PUBWEAK Vector74
PUBWEAK Vector78
PUBWEAK Vector7C
PUBWEAK Vector80
PUBWEAK Vector84
PUBWEAK Vector88
PUBWEAK Vector8C
PUBWEAK Vector90
PUBWEAK Vector94
PUBWEAK Vector98
PUBWEAK Vector9C
PUBWEAK VectorA0
PUBWEAK VectorA4
PUBWEAK VectorA8
PUBWEAK VectorAC
PUBWEAK VectorB0
PUBWEAK VectorB4
PUBWEAK VectorB8
PUBWEAK VectorBC
PUBWEAK VectorC0
PUBWEAK VectorC4
PUBWEAK VectorC8
PUBWEAK VectorCC
PUBWEAK VectorD0
PUBWEAK VectorD4
PUBWEAK VectorD8
PUBWEAK VectorDC
PUBWEAK VectorE0
PUBWEAK VectorE4
PUBWEAK VectorE8
PUBWEAK VectorEC
PUBWEAK VectorF0
PUBWEAK VectorF4
PUBWEAK VectorF8
PUBWEAK VectorFC
PUBWEAK Vector100
PUBWEAK Vector104
PUBWEAK Vector108
PUBWEAK Vector10C
PUBWEAK Vector110
PUBWEAK Vector114
PUBWEAK Vector118
PUBWEAK Vector11C
PUBWEAK Vector120
PUBWEAK Vector124
PUBLIC _unhandled_exception
SECTION .text:CODE:REORDER(1)
THUMB
NMIVector
HardFaultVector
MemManageVector
BusFaultVector
UsageFaultVector
Vector1C
Vector20
Vector24
Vector28
SVCallVector
DebugMonitorVector
Vector34
PendSVVector
SysTickVector
Vector40
Vector44
Vector48
Vector4C
Vector50
Vector54
Vector58
Vector5C
Vector60
Vector64
Vector68
Vector6C
Vector70
Vector74
Vector78
Vector7C
Vector80
Vector84
Vector88
Vector8C
Vector90
Vector94
Vector98
Vector9C
VectorA0
VectorA4
VectorA8
VectorAC
VectorB0
VectorB4
VectorB8
VectorBC
VectorC0
VectorC4
VectorC8
VectorCC
VectorD0
VectorD4
VectorD8
VectorDC
VectorE0
VectorE4
VectorE8
VectorEC
VectorF0
VectorF4
VectorF8
VectorFC
Vector100
Vector104
Vector108
Vector10C
Vector110
Vector114
Vector118
Vector11C
Vector120
Vector124
_unhandled_exception
b _unhandled_exception
END

69
firmware/chibios/os/ports/IAR/ARMCMx/STM32F1xx/cmparams.h Executable file
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/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
/**
* @file IAR/ARMCMx/STM32F1xx/cmparams.h
* @brief ARM Cortex-M3 parameters for the STM32F1xx.
*
* @defgroup IAR_ARMCMx_STM32F1xx STM32F1xx Specific Parameters
* @ingroup IAR_ARMCMx_SPECIFIC
* @details This file contains the Cortex-M3 specific parameters for the
* STM32F1xx platform.
* @{
*/
#ifndef _CMPARAMS_H_
#define _CMPARAMS_H_
/**
* @brief Cortex core model.
*/
#define CORTEX_MODEL CORTEX_M3
/**
* @brief Systick unit presence.
*/
#define CORTEX_HAS_ST TRUE
/**
* @brief Memory Protection unit presence.
*/
#define CORTEX_HAS_MPU FALSE
/**
* @brief Floating Point unit presence.
*/
#define CORTEX_HAS_FPU FALSE
/**
* @brief Number of bits in priority masks.
*/
#define CORTEX_PRIORITY_BITS 4
#endif /* _CMPARAMS_H_ */
/** @} */

317
firmware/chibios/os/ports/IAR/ARMCMx/STM32F1xx/vectors.s Executable file
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/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
#if !defined(STM32F10X_LD) && !defined(STM32F10X_LD_VL) && \
!defined(STM32F10X_MD) && !defined(STM32F10X_MD_VL) && \
!defined(STM32F10X_HD) && !defined(STM32F10X_XL) && \
!defined(STM32F10X_CL)
#define _FROM_ASM_
#include "board.h"
#endif
MODULE ?vectors
AAPCS INTERWORK, VFP_COMPATIBLE, RWPI_COMPATIBLE
PRESERVE8
SECTION IRQSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(3)
EXTERN __iar_program_start
PUBLIC __vector_table
DATA
__vector_table:
DCD SFE(IRQSTACK)
DCD __iar_program_start
DCD NMIVector
DCD HardFaultVector
DCD MemManageVector
DCD BusFaultVector
DCD UsageFaultVector
DCD Vector1C
DCD Vector20
DCD Vector24
DCD Vector28
DCD SVCallVector
DCD DebugMonitorVector
DCD Vector34
DCD PendSVVector
DCD SysTickVector
DCD Vector40
DCD Vector44
DCD Vector48
DCD Vector4C
DCD Vector50
DCD Vector54
DCD Vector58
DCD Vector5C
DCD Vector60
DCD Vector64
DCD Vector68
DCD Vector6C
DCD Vector70
DCD Vector74
DCD Vector78
DCD Vector7C
DCD Vector80
DCD Vector84
DCD Vector88
DCD Vector8C
DCD Vector90
DCD Vector94
DCD Vector98
DCD Vector9C
DCD VectorA0
DCD VectorA4
DCD VectorA8
DCD VectorAC
DCD VectorB0
DCD VectorB4
DCD VectorB8
DCD VectorBC
DCD VectorC0
DCD VectorC4
DCD VectorC8
DCD VectorCC
DCD VectorD0
DCD VectorD4
DCD VectorD8
DCD VectorDC
DCD VectorE0
DCD VectorE4
DCD VectorE8
#if defined(STM32F10X_MD_VL) || defined(STM32F10X_HD) || \
defined(STM32F10X_XL) || defined(STM32F10X_CL)
DCD VectorEC
DCD VectorF0
DCD VectorF4
#endif
#if defined(STM32F10X_HD) || defined(STM32F10X_XL) || defined(STM32F10X_CL)
DCD VectorF8
DCD VectorFC
DCD Vector100
DCD Vector104
DCD Vector108
DCD Vector10C
DCD Vector110
DCD Vector114
DCD Vector118
DCD Vector11C
DCD Vector120
DCD Vector124
DCD Vector128
DCD Vector12C
#endif
#if defined(STM32F10X_CL)
DCD Vector130
DCD Vector134
DCD Vector138
DCD Vector13C
DCD Vector140
DCD Vector144
DCD Vector148
DCD Vector14C
#endif
/*
* Default interrupt handlers.
*/
PUBWEAK NMIVector
PUBWEAK HardFaultVector
PUBWEAK MemManageVector
PUBWEAK BusFaultVector
PUBWEAK UsageFaultVector
PUBWEAK Vector1C
PUBWEAK Vector20
PUBWEAK Vector24
PUBWEAK Vector28
PUBWEAK SVCallVector
PUBWEAK DebugMonitorVector
PUBWEAK Vector34
PUBWEAK PendSVVector
PUBWEAK SysTickVector
PUBWEAK Vector40
PUBWEAK Vector44
PUBWEAK Vector48
PUBWEAK Vector4C
PUBWEAK Vector50
PUBWEAK Vector54
PUBWEAK Vector58
PUBWEAK Vector5C
PUBWEAK Vector60
PUBWEAK Vector64
PUBWEAK Vector68
PUBWEAK Vector6C
PUBWEAK Vector70
PUBWEAK Vector74
PUBWEAK Vector78
PUBWEAK Vector7C
PUBWEAK Vector80
PUBWEAK Vector84
PUBWEAK Vector88
PUBWEAK Vector8C
PUBWEAK Vector90
PUBWEAK Vector94
PUBWEAK Vector98
PUBWEAK Vector9C
PUBWEAK VectorA0
PUBWEAK VectorA4
PUBWEAK VectorA8
PUBWEAK VectorAC
PUBWEAK VectorB0
PUBWEAK VectorB4
PUBWEAK VectorB8
PUBWEAK VectorBC
PUBWEAK VectorC0
PUBWEAK VectorC4
PUBWEAK VectorC8
PUBWEAK VectorCC
PUBWEAK VectorD0
PUBWEAK VectorD4
PUBWEAK VectorD8
PUBWEAK VectorDC
PUBWEAK VectorE0
PUBWEAK VectorE4
PUBWEAK VectorE8
PUBWEAK VectorEC
PUBWEAK VectorF0
PUBWEAK VectorF4
PUBWEAK VectorF8
PUBWEAK VectorFC
PUBWEAK Vector100
PUBWEAK Vector104
PUBWEAK Vector108
PUBWEAK Vector10C
PUBWEAK Vector110
PUBWEAK Vector114
PUBWEAK Vector118
PUBWEAK Vector11C
PUBWEAK Vector120
PUBWEAK Vector124
PUBWEAK Vector128
PUBWEAK Vector12C
PUBWEAK Vector130
PUBWEAK Vector134
PUBWEAK Vector138
PUBWEAK Vector13C
PUBWEAK Vector140
PUBWEAK Vector144
PUBWEAK Vector148
PUBWEAK Vector14C
PUBLIC _unhandled_exception
SECTION .text:CODE:REORDER(1)
THUMB
NMIVector
HardFaultVector
MemManageVector
BusFaultVector
UsageFaultVector
Vector1C
Vector20
Vector24
Vector28
SVCallVector
DebugMonitorVector
Vector34
PendSVVector
SysTickVector
Vector40
Vector44
Vector48
Vector4C
Vector50
Vector54
Vector58
Vector5C
Vector60
Vector64
Vector68
Vector6C
Vector70
Vector74
Vector78
Vector7C
Vector80
Vector84
Vector88
Vector8C
Vector90
Vector94
Vector98
Vector9C
VectorA0
VectorA4
VectorA8
VectorAC
VectorB0
VectorB4
VectorB8
VectorBC
VectorC0
VectorC4
VectorC8
VectorCC
VectorD0
VectorD4
VectorD8
VectorDC
VectorE0
VectorE4
VectorE8
VectorEC
VectorF0
VectorF4
VectorF8
VectorFC
Vector100
Vector104
Vector108
Vector10C
Vector110
Vector114
Vector118
Vector11C
Vector120
Vector124
Vector128
Vector12C
Vector130
Vector134
Vector138
Vector13C
Vector140
Vector144
Vector148
Vector14C
_unhandled_exception
b _unhandled_exception
END

69
firmware/chibios/os/ports/IAR/ARMCMx/STM32F4xx/cmparams.h Executable file
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@@ -0,0 +1,69 @@
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
/**
* @file IAR/ARMCMx/STM32F4xx/cmparams.h
* @brief ARM Cortex-M3 parameters for the STM32F4xx.
*
* @defgroup IAR_ARMCMx_STM32F4xx STM32F4xx Specific Parameters
* @ingroup IAR_ARMCMx_SPECIFIC
* @details This file contains the Cortex-M4 specific parameters for the
* STM32F4xx platform.
* @{
*/
#ifndef _CMPARAMS_H_
#define _CMPARAMS_H_
/**
* @brief Cortex core model.
*/
#define CORTEX_MODEL CORTEX_M4
/**
* @brief Systick unit presence.
*/
#define CORTEX_HAS_ST TRUE
/**
* @brief Memory Protection unit presence.
*/
#define CORTEX_HAS_MPU TRUE
/**
* @brief Floating Point unit presence.
*/
#define CORTEX_HAS_FPU TRUE
/**
* @brief Number of bits in priority masks.
*/
#define CORTEX_PRIORITY_BITS 4
#endif /* _CMPARAMS_H_ */
/** @} */

344
firmware/chibios/os/ports/IAR/ARMCMx/STM32F4xx/vectors.s Executable file
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/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
MODULE ?vectors
AAPCS INTERWORK, VFP_COMPATIBLE, RWPI_COMPATIBLE
PRESERVE8
SECTION IRQSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(3)
EXTERN __iar_program_start
PUBLIC __vector_table
DATA
__vector_table:
DCD SFE(IRQSTACK)
DCD __iar_program_start
DCD NMIVector
DCD HardFaultVector
DCD MemManageVector
DCD BusFaultVector
DCD UsageFaultVector
DCD Vector1C
DCD Vector20
DCD Vector24
DCD Vector28
DCD SVCallVector
DCD DebugMonitorVector
DCD Vector34
DCD PendSVVector
DCD SysTickVector
DCD Vector40
DCD Vector44
DCD Vector48
DCD Vector4C
DCD Vector50
DCD Vector54
DCD Vector58
DCD Vector5C
DCD Vector60
DCD Vector64
DCD Vector68
DCD Vector6C
DCD Vector70
DCD Vector74
DCD Vector78
DCD Vector7C
DCD Vector80
DCD Vector84
DCD Vector88
DCD Vector8C
DCD Vector90
DCD Vector94
DCD Vector98
DCD Vector9C
DCD VectorA0
DCD VectorA4
DCD VectorA8
DCD VectorAC
DCD VectorB0
DCD VectorB4
DCD VectorB8
DCD VectorBC
DCD VectorC0
DCD VectorC4
DCD VectorC8
DCD VectorCC
DCD VectorD0
DCD VectorD4
DCD VectorD8
DCD VectorDC
DCD VectorE0
DCD VectorE4
DCD VectorE8
DCD VectorEC
DCD VectorF0
DCD VectorF4
DCD VectorF8
DCD VectorFC
DCD Vector100
DCD Vector104
DCD Vector108
DCD Vector10C
DCD Vector110
DCD Vector114
DCD Vector118
DCD Vector11C
DCD Vector120
DCD Vector124
DCD Vector128
DCD Vector12C
DCD Vector130
DCD Vector134
DCD Vector138
DCD Vector13C
DCD Vector140
DCD Vector144
DCD Vector148
DCD Vector14C
DCD Vector150
DCD Vector154
DCD Vector158
DCD Vector15C
DCD Vector160
DCD Vector164
DCD Vector168
DCD Vector16C
DCD Vector170
DCD Vector174
DCD Vector178
DCD Vector17C
DCD Vector180
DCD Vector184
/*
* Default interrupt handlers.
*/
PUBWEAK NMIVector
PUBWEAK HardFaultVector
PUBWEAK MemManageVector
PUBWEAK BusFaultVector
PUBWEAK UsageFaultVector
PUBWEAK Vector1C
PUBWEAK Vector20
PUBWEAK Vector24
PUBWEAK Vector28
PUBWEAK SVCallVector
PUBWEAK DebugMonitorVector
PUBWEAK Vector34
PUBWEAK PendSVVector
PUBWEAK SysTickVector
PUBWEAK Vector40
PUBWEAK Vector44
PUBWEAK Vector48
PUBWEAK Vector4C
PUBWEAK Vector50
PUBWEAK Vector54
PUBWEAK Vector58
PUBWEAK Vector5C
PUBWEAK Vector60
PUBWEAK Vector64
PUBWEAK Vector68
PUBWEAK Vector6C
PUBWEAK Vector70
PUBWEAK Vector74
PUBWEAK Vector78
PUBWEAK Vector7C
PUBWEAK Vector80
PUBWEAK Vector84
PUBWEAK Vector88
PUBWEAK Vector8C
PUBWEAK Vector90
PUBWEAK Vector94
PUBWEAK Vector98
PUBWEAK Vector9C
PUBWEAK VectorA0
PUBWEAK VectorA4
PUBWEAK VectorA8
PUBWEAK VectorAC
PUBWEAK VectorB0
PUBWEAK VectorB4
PUBWEAK VectorB8
PUBWEAK VectorBC
PUBWEAK VectorC0
PUBWEAK VectorC4
PUBWEAK VectorC8
PUBWEAK VectorCC
PUBWEAK VectorD0
PUBWEAK VectorD4
PUBWEAK VectorD8
PUBWEAK VectorDC
PUBWEAK VectorE0
PUBWEAK VectorE4
PUBWEAK VectorE8
PUBWEAK VectorEC
PUBWEAK VectorF0
PUBWEAK VectorF4
PUBWEAK VectorF8
PUBWEAK VectorFC
PUBWEAK Vector100
PUBWEAK Vector104
PUBWEAK Vector108
PUBWEAK Vector10C
PUBWEAK Vector110
PUBWEAK Vector114
PUBWEAK Vector118
PUBWEAK Vector11C
PUBWEAK Vector120
PUBWEAK Vector124
PUBWEAK Vector128
PUBWEAK Vector12C
PUBWEAK Vector130
PUBWEAK Vector134
PUBWEAK Vector138
PUBWEAK Vector13C
PUBWEAK Vector140
PUBWEAK Vector144
PUBWEAK Vector148
PUBWEAK Vector14C
PUBWEAK Vector150
PUBWEAK Vector154
PUBWEAK Vector158
PUBWEAK Vector15C
PUBWEAK Vector160
PUBWEAK Vector164
PUBWEAK Vector168
PUBWEAK Vector16C
PUBWEAK Vector170
PUBWEAK Vector174
PUBWEAK Vector178
PUBWEAK Vector17C
PUBWEAK Vector180
PUBWEAK Vector184
PUBLIC _unhandled_exception
SECTION .text:CODE:REORDER(1)
THUMB
NMIVector
HardFaultVector
MemManageVector
BusFaultVector
UsageFaultVector
Vector1C
Vector20
Vector24
Vector28
SVCallVector
DebugMonitorVector
Vector34
PendSVVector
SysTickVector
Vector40
Vector44
Vector48
Vector4C
Vector50
Vector54
Vector58
Vector5C
Vector60
Vector64
Vector68
Vector6C
Vector70
Vector74
Vector78
Vector7C
Vector80
Vector84
Vector88
Vector8C
Vector90
Vector94
Vector98
Vector9C
VectorA0
VectorA4
VectorA8
VectorAC
VectorB0
VectorB4
VectorB8
VectorBC
VectorC0
VectorC4
VectorC8
VectorCC
VectorD0
VectorD4
VectorD8
VectorDC
VectorE0
VectorE4
VectorE8
VectorEC
VectorF0
VectorF4
VectorF8
VectorFC
Vector100
Vector104
Vector108
Vector10C
Vector110
Vector114
Vector118
Vector11C
Vector120
Vector124
Vector128
Vector12C
Vector130
Vector134
Vector138
Vector13C
Vector140
Vector144
Vector148
Vector14C
Vector150
Vector154
Vector158
Vector15C
Vector160
Vector164
Vector168
Vector16C
Vector170
Vector174
Vector178
Vector17C
Vector180
Vector184
_unhandled_exception
b _unhandled_exception
END

69
firmware/chibios/os/ports/IAR/ARMCMx/STM32L1xx/cmparams.h Executable file
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/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
/**
* @file IAR/ARMCMx/STM32L1xx/cmparams.h
* @brief ARM Cortex-M3 parameters for the STM32L1xx.
*
* @defgroup IAR_ARMCMx_STM32L1xx STM32L1xx Specific Parameters
* @ingroup IAR_ARMCMx_SPECIFIC
* @details This file contains the Cortex-M3 specific parameters for the
* STM32L1xx platform.
* @{
*/
#ifndef _CMPARAMS_H_
#define _CMPARAMS_H_
/**
* @brief Cortex core model.
*/
#define CORTEX_MODEL CORTEX_M3
/**
* @brief Systick unit presence.
*/
#define CORTEX_HAS_ST TRUE
/**
* @brief Memory Protection unit presence.
*/
#define CORTEX_HAS_MPU TRUE
/**
* @brief Floating Point unit presence.
*/
#define CORTEX_HAS_FPU FALSE
/**
* @brief Number of bits in priority masks.
*/
#define CORTEX_PRIORITY_BITS 4
#endif /* _CMPARAMS_H_ */
/** @} */

238
firmware/chibios/os/ports/IAR/ARMCMx/STM32L1xx/vectors.s Executable file
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/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
#if !defined(STM32L1XX_MD)
#define _FROM_ASM_
#include "board.h"
#endif
MODULE ?vectors
AAPCS INTERWORK, VFP_COMPATIBLE, RWPI_COMPATIBLE
PRESERVE8
SECTION IRQSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(3)
EXTERN __iar_program_start
PUBLIC __vector_table
DATA
__vector_table:
DCD SFE(IRQSTACK)
DCD __iar_program_start
DCD NMIVector
DCD HardFaultVector
DCD MemManageVector
DCD BusFaultVector
DCD UsageFaultVector
DCD Vector1C
DCD Vector20
DCD Vector24
DCD Vector28
DCD SVCallVector
DCD DebugMonitorVector
DCD Vector34
DCD PendSVVector
DCD SysTickVector
DCD Vector40
DCD Vector44
DCD Vector48
DCD Vector4C
DCD Vector50
DCD Vector54
DCD Vector58
DCD Vector5C
DCD Vector60
DCD Vector64
DCD Vector68
DCD Vector6C
DCD Vector70
DCD Vector74
DCD Vector78
DCD Vector7C
DCD Vector80
DCD Vector84
DCD Vector88
DCD Vector8C
DCD Vector90
DCD Vector94
DCD Vector98
DCD Vector9C
DCD VectorA0
DCD VectorA4
DCD VectorA8
DCD VectorAC
DCD VectorB0
DCD VectorB4
DCD VectorB8
DCD VectorBC
DCD VectorC0
DCD VectorC4
DCD VectorC8
DCD VectorCC
DCD VectorD0
DCD VectorD4
DCD VectorD8
DCD VectorDC
DCD VectorE0
DCD VectorE4
DCD VectorE8
DCD VectorEC
DCD VectorF0
/*
* Default interrupt handlers.
*/
PUBWEAK NMIVector
PUBWEAK HardFaultVector
PUBWEAK MemManageVector
PUBWEAK BusFaultVector
PUBWEAK UsageFaultVector
PUBWEAK Vector1C
PUBWEAK Vector20
PUBWEAK Vector24
PUBWEAK Vector28
PUBWEAK SVCallVector
PUBWEAK DebugMonitorVector
PUBWEAK Vector34
PUBWEAK PendSVVector
PUBWEAK SysTickVector
PUBWEAK Vector40
PUBWEAK Vector44
PUBWEAK Vector48
PUBWEAK Vector4C
PUBWEAK Vector50
PUBWEAK Vector54
PUBWEAK Vector58
PUBWEAK Vector5C
PUBWEAK Vector60
PUBWEAK Vector64
PUBWEAK Vector68
PUBWEAK Vector6C
PUBWEAK Vector70
PUBWEAK Vector74
PUBWEAK Vector78
PUBWEAK Vector7C
PUBWEAK Vector80
PUBWEAK Vector84
PUBWEAK Vector88
PUBWEAK Vector8C
PUBWEAK Vector90
PUBWEAK Vector94
PUBWEAK Vector98
PUBWEAK Vector9C
PUBWEAK VectorA0
PUBWEAK VectorA4
PUBWEAK VectorA8
PUBWEAK VectorAC
PUBWEAK VectorB0
PUBWEAK VectorB4
PUBWEAK VectorB8
PUBWEAK VectorBC
PUBWEAK VectorC0
PUBWEAK VectorC4
PUBWEAK VectorC8
PUBWEAK VectorCC
PUBWEAK VectorD0
PUBWEAK VectorD4
PUBWEAK VectorD8
PUBWEAK VectorDC
PUBWEAK VectorE0
PUBWEAK VectorE4
PUBWEAK VectorE8
PUBWEAK VectorEC
PUBWEAK VectorF0
PUBLIC _unhandled_exception
SECTION .text:CODE:REORDER(1)
THUMB
NMIVector
HardFaultVector
MemManageVector
BusFaultVector
UsageFaultVector
Vector1C
Vector20
Vector24
Vector28
SVCallVector
DebugMonitorVector
Vector34
PendSVVector
SysTickVector
Vector40
Vector44
Vector48
Vector4C
Vector50
Vector54
Vector58
Vector5C
Vector60
Vector64
Vector68
Vector6C
Vector70
Vector74
Vector78
Vector7C
Vector80
Vector84
Vector88
Vector8C
Vector90
Vector94
Vector98
Vector9C
VectorA0
VectorA4
VectorA8
VectorAC
VectorB0
VectorB4
VectorB8
VectorBC
VectorC0
VectorC4
VectorC8
VectorCC
VectorD0
VectorD4
VectorD8
VectorDC
VectorE0
VectorE4
VectorE8
VectorEC
VectorF0
_unhandled_exception
b _unhandled_exception
END

53
firmware/chibios/os/ports/IAR/ARMCMx/chcore.c Executable file
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@@ -0,0 +1,53 @@
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
/**
* @file IAR/ARMCMx/chcore.c
* @brief ARM Cortex-Mx port code.
*
* @addtogroup IAR_ARMCMx_CORE
* @{
*/
#include "ch.h"
/**
* @brief Halts the system.
* @note The function is declared as a weak symbol, it is possible
* to redefine it in your application code.
*/
#if !defined(__DOXYGEN__)
__weak
#endif
void port_halt(void) {
port_disable();
while (TRUE) {
}
}
/** @} */

196
firmware/chibios/os/ports/IAR/ARMCMx/chcore.h Executable file
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/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
/**
* @file IAR/ARMCMx/chcore.h
* @brief ARM Cortex-Mx port macros and structures.
*
* @addtogroup IAR_ARMCMx_CORE
* @{
*/
#ifndef _CHCORE_H_
#define _CHCORE_H_
/*===========================================================================*/
/* Port constants (common). */
/*===========================================================================*/
/* Added to make the header stand-alone when included from asm.*/
#ifndef FALSE
#define FALSE 0
#endif
#ifndef TRUE
#define TRUE (!FALSE)
#endif
#define CORTEX_M0 0 /**< @brief Cortex-M0 variant. */
#define CORTEX_M1 1 /**< @brief Cortex-M1 variant. */
#define CORTEX_M3 3 /**< @brief Cortex-M3 variant. */
#define CORTEX_M4 4 /**< @brief Cortex-M4 variant. */
/* Inclusion of the Cortex-Mx implementation specific parameters.*/
#include "cmparams.h"
/* Cortex model check, only M0 and M3 supported right now.*/
#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M3) || \
(CORTEX_MODEL == CORTEX_M4)
#elif (CORTEX_MODEL == CORTEX_M1)
#error "untested Cortex-M model"
#else
#error "unknown or unsupported Cortex-M model"
#endif
/**
* @brief Total priority levels.
*/
#define CORTEX_PRIORITY_LEVELS (1 << CORTEX_PRIORITY_BITS)
/**
* @brief Minimum priority level.
* @details This minimum priority level is calculated from the number of
* priority bits supported by the specific Cortex-Mx implementation.
*/
#define CORTEX_MINIMUM_PRIORITY (CORTEX_PRIORITY_LEVELS - 1)
/**
* @brief Maximum priority level.
* @details The maximum allowed priority level is always zero.
*/
#define CORTEX_MAXIMUM_PRIORITY 0
/*===========================================================================*/
/* Port macros (common). */
/*===========================================================================*/
/**
* @brief Priority level verification macro.
*/
#define CORTEX_IS_VALID_PRIORITY(n) \
(((n) >= 0) && ((n) < CORTEX_PRIORITY_LEVELS))
/**
* @brief Priority level verification macro.
*/
#define CORTEX_IS_VALID_KERNEL_PRIORITY(n) \
(((n) >= CORTEX_MAX_KERNEL_PRIORITY) && ((n) < CORTEX_PRIORITY_LEVELS))
/**
* @brief Priority level to priority mask conversion macro.
*/
#define CORTEX_PRIORITY_MASK(n) \
((n) << (8 - CORTEX_PRIORITY_BITS))
/*===========================================================================*/
/* Port configurable parameters (common). */
/*===========================================================================*/
/*===========================================================================*/
/* Port derived parameters (common). */
/*===========================================================================*/
/*===========================================================================*/
/* Port exported info (common). */
/*===========================================================================*/
/**
* @brief Macro defining a generic ARM architecture.
*/
#define CH_ARCHITECTURE_ARM
/**
* @brief Name of the compiler supported by this port.
*/
#define CH_COMPILER_NAME "IAR"
/*===========================================================================*/
/* Port implementation part (common). */
/*===========================================================================*/
/* Includes the sub-architecture-specific part.*/
#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M1)
#include "chcore_v6m.h"
#elif (CORTEX_MODEL == CORTEX_M3) || (CORTEX_MODEL == CORTEX_M4)
#include "chcore_v7m.h"
#endif
#if !defined(_FROM_ASM_)
#include <intrinsics.h>
#include "nvic.h"
/* The following declarations are there just for Doxygen documentation, the
real declarations are inside the sub-headers.*/
#if defined(__DOXYGEN__)
/**
* @brief Stack and memory alignment enforcement.
* @note In this architecture the stack alignment is enforced to 64 bits,
* 32 bits alignment is supported by hardware but deprecated by ARM,
* the implementation choice is to not offer the option.
*/
typedef uint64_t stkalign_t;
/**
* @brief Interrupt saved context.
* @details This structure represents the stack frame saved during a
* preemption-capable interrupt handler.
* @note It is implemented to match the Cortex-Mx exception context.
*/
struct extctx {};
/**
* @brief System saved context.
* @details This structure represents the inner stack frame during a context
* switching.
*/
struct intctx {};
#endif /* defined(__DOXYGEN__) */
/**
* @brief Excludes the default @p chSchIsPreemptionRequired()implementation.
*/
#define PORT_OPTIMIZED_ISPREEMPTIONREQUIRED
#if (CH_TIME_QUANTUM > 0) || defined(__DOXYGEN__)
/**
* @brief Inline-able version of this kernel function.
*/
#define chSchIsPreemptionRequired() \
(currp->p_preempt ? firstprio(&rlist.r_queue) > currp->p_prio : \
firstprio(&rlist.r_queue) >= currp->p_prio)
#else /* CH_TIME_QUANTUM == 0 */
#define chSchIsPreemptionRequired() \
(firstprio(&rlist.r_queue) > currp->p_prio)
#endif /* CH_TIME_QUANTUM == 0 */
#endif /* _FROM_ASM_ */
#endif /* _CHCORE_H_ */
/** @} */

132
firmware/chibios/os/ports/IAR/ARMCMx/chcore_v6m.c Executable file
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/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
/**
* @file IAR/ARMCMx/chcore_v6m.c
* @brief ARMv6-M architecture port code.
*
* @addtogroup IAR_ARMCMx_V6M_CORE
* @{
*/
#include "ch.h"
/*===========================================================================*/
/* Port interrupt handlers. */
/*===========================================================================*/
/**
* @brief System Timer vector.
* @details This interrupt is used as system tick.
* @note The timer must be initialized in the startup code.
*/
CH_IRQ_HANDLER(SysTickVector) {
CH_IRQ_PROLOGUE();
chSysLockFromIsr();
chSysTimerHandlerI();
chSysUnlockFromIsr();
CH_IRQ_EPILOGUE();
}
#if !CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__)
/**
* @brief NMI vector.
* @details The NMI vector is used for exception mode re-entering after a
* context switch.
*/
void NMIVector(void) {
register struct extctx *ctxp;
/* Discarding the current exception context and positioning the stack to
point to the real one.*/
ctxp = (struct extctx *)__get_PSP();
ctxp++;
__set_PSP((unsigned long)ctxp);
port_unlock_from_isr();
}
#endif /* !CORTEX_ALTERNATE_SWITCH */
#if CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__)
/**
* @brief PendSV vector.
* @details The PendSV vector is used for exception mode re-entering after a
* context switch.
*/
void PendSVVector(void) {
register struct extctx *ctxp;
/* Discarding the current exception context and positioning the stack to
point to the real one.*/
ctxp = (struct extctx *)__get_PSP();
ctxp++;
__set_PSP((unsigned long)ctxp);
}
#endif /* CORTEX_ALTERNATE_SWITCH */
/*===========================================================================*/
/* Port exported functions. */
/*===========================================================================*/
/**
* @brief IRQ epilogue code.
*
* @param[in] lr value of the @p LR register on ISR entry
*/
void _port_irq_epilogue(regarm_t lr) {
if (lr != (regarm_t)0xFFFFFFF1) {
register struct extctx *ctxp;
port_lock_from_isr();
/* Adding an artificial exception return context, there is no need to
populate it fully.*/
ctxp = (struct extctx *)__get_PSP();
ctxp--;
__set_PSP((unsigned long)ctxp);
ctxp->xpsr = (regarm_t)0x01000000;
/* The exit sequence is different depending on if a preemption is
required or not.*/
if (chSchIsPreemptionRequired()) {
/* Preemption is required we need to enforce a context switch.*/
ctxp->pc = (regarm_t)_port_switch_from_isr;
}
else {
/* Preemption not required, we just need to exit the exception
atomically.*/
ctxp->pc = (regarm_t)_port_exit_from_isr;
}
/* Note, returning without unlocking is intentional, this is done in
order to keep the rest of the context switch atomic.*/
}
}
/** @} */

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/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
/**
* @file IAR/ARMCMx/chcore_v6m.h
* @brief ARMv6-M architecture port macros and structures.
*
* @addtogroup IAR_ARMCMx_V6M_CORE
* @{
*/
#ifndef _CHCORE_V6M_H_
#define _CHCORE_V6M_H_
/*===========================================================================*/
/* Port constants. */
/*===========================================================================*/
/**
* @brief PendSV priority level.
* @note This priority is enforced to be equal to @p 0,
* this handler always has the highest priority that cannot preempt
* the kernel.
*/
#define CORTEX_PRIORITY_PENDSV 0
/*===========================================================================*/
/* Port macros. */
/*===========================================================================*/
/*===========================================================================*/
/* Port configurable parameters. */
/*===========================================================================*/
/**
* @brief Stack size for the system idle thread.
* @details This size depends on the idle thread implementation, usually
* the idle thread should take no more space than those reserved
* by @p PORT_INT_REQUIRED_STACK.
* @note In this port it is set to 16 because the idle thread does have
* a stack frame when compiling without optimizations. You may
* reduce this value to zero when compiling with optimizations.
*/
#if !defined(PORT_IDLE_THREAD_STACK_SIZE)
#define PORT_IDLE_THREAD_STACK_SIZE 16
#endif
/**
* @brief Per-thread stack overhead for interrupts servicing.
* @details This constant is used in the calculation of the correct working
* area size.
* @note In this port this value is conservatively set to 32 because the
* function @p chSchDoReschedule() can have a stack frame, especially
* with compiler optimizations disabled. The value can be reduced
* when compiler optimizations are enabled.
*/
#if !defined(PORT_INT_REQUIRED_STACK)
#define PORT_INT_REQUIRED_STACK 32
#endif
/**
* @brief Enables the use of the WFI instruction in the idle thread loop.
*/
#if !defined(CORTEX_ENABLE_WFI_IDLE)
#define CORTEX_ENABLE_WFI_IDLE FALSE
#endif
/**
* @brief SYSTICK handler priority.
* @note The default SYSTICK handler priority is calculated as the priority
* level in the middle of the numeric priorities range.
*/
#if !defined(CORTEX_PRIORITY_SYSTICK)
#define CORTEX_PRIORITY_SYSTICK (CORTEX_PRIORITY_LEVELS >> 1)
#elif !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SYSTICK)
/* If it is externally redefined then better perform a validity check on it.*/
#error "invalid priority level specified for CORTEX_PRIORITY_SYSTICK"
#endif
/**
* @brief Alternate preemption method.
* @details Activating this option will make the Kernel use the PendSV
* handler for preemption instead of the NMI handler.
*/
#ifndef CORTEX_ALTERNATE_SWITCH
#define CORTEX_ALTERNATE_SWITCH FALSE
#endif
/*===========================================================================*/
/* Port derived parameters. */
/*===========================================================================*/
/**
* @brief Maximum usable priority for normal ISRs.
*/
#if CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__)
#define CORTEX_MAX_KERNEL_PRIORITY 1
#else
#define CORTEX_MAX_KERNEL_PRIORITY 0
#endif
/*===========================================================================*/
/* Port exported info. */
/*===========================================================================*/
/**
* @brief Macro defining the specific ARM architecture.
*/
#define CH_ARCHITECTURE_ARM_v6M
/**
* @brief Name of the implemented architecture.
*/
#define CH_ARCHITECTURE_NAME "ARMv6-M"
/**
* @brief Name of the architecture variant.
*/
#if (CORTEX_MODEL == CORTEX_M0) || defined(__DOXYGEN__)
#define CH_CORE_VARIANT_NAME "Cortex-M0"
#elif (CORTEX_MODEL == CORTEX_M1)
#define CH_CORE_VARIANT_NAME "Cortex-M1"
#endif
/**
* @brief Port-specific information string.
*/
#if !CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__)
#define CH_PORT_INFO "Preemption through NMI"
#else
#define CH_PORT_INFO "Preemption through PendSV"
#endif
/*===========================================================================*/
/* Port implementation part. */
/*===========================================================================*/
#if !defined(_FROM_ASM_)
/**
* @brief Generic ARM register.
*/
typedef void *regarm_t;
/**
* @brief Stack and memory alignment enforcement.
* @note In this architecture the stack alignment is enforced to 64 bits,
* 32 bits alignment is supported by hardware but deprecated by ARM,
* the implementation choice is to not offer the option.
*/
typedef uint64_t stkalign_t;
/* The documentation of the following declarations is in chconf.h in order
to not have duplicated structure names into the documentation.*/
#if !defined(__DOXYGEN__)
struct extctx {
regarm_t r0;
regarm_t r1;
regarm_t r2;
regarm_t r3;
regarm_t r12;
regarm_t lr_thd;
regarm_t pc;
regarm_t xpsr;
};
struct intctx {
regarm_t r8;
regarm_t r9;
regarm_t r10;
regarm_t r11;
regarm_t r4;
regarm_t r5;
regarm_t r6;
regarm_t r7;
regarm_t lr;
};
#endif /* !defined(__DOXYGEN__) */
/**
* @brief Platform dependent part of the @p Thread structure.
* @details In this port the structure just holds a pointer to the @p intctx
* structure representing the stack pointer at context switch time.
*/
struct context {
struct intctx *r13;
};
/**
* @brief Platform dependent part of the @p chThdCreateI() API.
* @details This code usually setup the context switching frame represented
* by an @p intctx structure.
*/
#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \
tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace + \
wsize - \
sizeof(struct intctx)); \
tp->p_ctx.r13->r4 = (regarm_t)pf; \
tp->p_ctx.r13->r5 = (regarm_t)arg; \
tp->p_ctx.r13->lr = (regarm_t)_port_thread_start; \
}
/**
* @brief Enforces a correct alignment for a stack area size value.
*/
#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1)
/**
* @brief Computes the thread working area global size.
*/
#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \
sizeof(struct intctx) + \
sizeof(struct extctx) + \
(n) + (PORT_INT_REQUIRED_STACK))
/**
* @brief Static working area allocation.
* @details This macro is used to allocate a static thread working area
* aligned as both position and size.
*/
#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)]
/**
* @brief IRQ prologue code.
* @details This macro must be inserted at the start of all IRQ handlers
* enabled to invoke system APIs.
*/
#define PORT_IRQ_PROLOGUE() regarm_t _saved_lr = (regarm_t)__get_LR()
/**
* @brief IRQ epilogue code.
* @details This macro must be inserted at the end of all IRQ handlers
* enabled to invoke system APIs.
*/
#define PORT_IRQ_EPILOGUE() _port_irq_epilogue(_saved_lr)
/**
* @brief IRQ handler function declaration.
* @note @p id can be a function name or a vector number depending on the
* port implementation.
*/
#define PORT_IRQ_HANDLER(id) void id(void)
/**
* @brief Fast IRQ handler function declaration.
* @note @p id can be a function name or a vector number depending on the
* port implementation.
*/
#define PORT_FAST_IRQ_HANDLER(id) void id(void)
/**
* @brief Port-related initialization code.
*/
#define port_init() { \
SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0); \
nvicSetSystemHandlerPriority(HANDLER_PENDSV, \
CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_PENDSV)); \
nvicSetSystemHandlerPriority(HANDLER_SYSTICK, \
CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK)); \
}
/**
* @brief Kernel-lock action.
* @details Usually this function just disables interrupts but may perform
* more actions.
*/
#define port_lock() __disable_interrupt()
/**
* @brief Kernel-unlock action.
* @details Usually this function just enables interrupts but may perform
* more actions.
*/
#define port_unlock() __enable_interrupt()
/**
* @brief Kernel-lock action from an interrupt handler.
* @details This function is invoked before invoking I-class APIs from
* interrupt handlers. The implementation is architecture dependent,
* in its simplest form it is void.
* @note Same as @p port_lock() in this port.
*/
#define port_lock_from_isr() port_lock()
/**
* @brief Kernel-unlock action from an interrupt handler.
* @details This function is invoked after invoking I-class APIs from interrupt
* handlers. The implementation is architecture dependent, in its
* simplest form it is void.
* @note Same as @p port_lock() in this port.
*/
#define port_unlock_from_isr() port_unlock()
/**
* @brief Disables all the interrupt sources.
*/
#define port_disable() __disable_interrupt()
/**
* @brief Disables the interrupt sources below kernel-level priority.
*/
#define port_suspend() __disable_interrupt()
/**
* @brief Enables all the interrupt sources.
*/
#define port_enable() __enable_interrupt()
/**
* @brief Enters an architecture-dependent IRQ-waiting mode.
* @details The function is meant to return when an interrupt becomes pending.
* The simplest implementation is an empty function or macro but this
* would not take advantage of architecture-specific power saving
* modes.
* @note Implemented as an inlined @p WFI instruction.
*/
#if CORTEX_ENABLE_WFI_IDLE || defined(__DOXYGEN__)
#define port_wait_for_interrupt() asm ("wfi")
#else
#define port_wait_for_interrupt()
#endif
/**
* @brief Performs a context switch between two threads.
* @details This is the most critical code in any port, this function
* is responsible for the context switch between 2 threads.
* @note The implementation of this code affects <b>directly</b> the context
* switch performance so optimize here as much as you can.
*
* @param[in] ntp the thread to be switched in
* @param[in] otp the thread to be switched out
*/
#if !CH_DBG_ENABLE_STACK_CHECK || defined(__DOXYGEN__)
#define port_switch(ntp, otp) _port_switch(ntp, otp)
#else
#define port_switch(ntp, otp) { \
if ((stkalign_t *)(__get_SP() - sizeof(struct intctx)) < otp->p_stklimit) \
chDbgPanic("stack overflow"); \
_port_switch(ntp, otp); \
}
#endif
#ifdef __cplusplus
extern "C" {
#endif
void port_halt(void);
void _port_irq_epilogue(regarm_t lr);
void _port_switch_from_isr(void);
void _port_exit_from_isr(void);
void _port_switch(Thread *ntp, Thread *otp);
void _port_thread_start(void);
#ifdef __cplusplus
}
#endif
#endif /* _FROM_ASM_ */
#endif /* _CHCORE_V6M_H_ */
/** @} */

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/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
/**
* @file IAR/ARMCMx/chcore_v7m.c
* @brief ARMv7-M architecture port code.
*
* @addtogroup IAR_ARMCMx_V7M_CORE
* @{
*/
#include "ch.h"
/*===========================================================================*/
/* Port interrupt handlers. */
/*===========================================================================*/
/**
* @brief System Timer vector.
* @details This interrupt is used as system tick.
* @note The timer must be initialized in the startup code.
*/
CH_IRQ_HANDLER(SysTickVector) {
CH_IRQ_PROLOGUE();
chSysLockFromIsr();
chSysTimerHandlerI();
chSysUnlockFromIsr();
CH_IRQ_EPILOGUE();
}
#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
/**
* @brief SVC vector.
* @details The SVC vector is used for exception mode re-entering after a
* context switch.
* @note The PendSV vector is only used in advanced kernel mode.
*/
void SVCallVector(void) {
struct extctx *ctxp;
#if CORTEX_USE_FPU
/* Enforcing unstacking of the FP part of the context.*/
SCB_FPCCR &= ~FPCCR_LSPACT;
#endif
/* Current PSP value.*/
ctxp = (struct extctx *)__get_PSP();
/* Discarding the current exception context and positioning the stack to
point to the real one.*/
ctxp++;
/* Restoring real position of the original stack frame.*/
__set_PSP((unsigned long)ctxp);
port_unlock_from_isr();
}
#endif /* !CORTEX_SIMPLIFIED_PRIORITY */
#if CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
/**
* @brief PendSV vector.
* @details The PendSV vector is used for exception mode re-entering after a
* context switch.
* @note The PendSV vector is only used in compact kernel mode.
*/
void PendSVVector(void) {
struct extctx *ctxp;
#if CORTEX_USE_FPU
/* Enforcing unstacking of the FP part of the context.*/
SCB_FPCCR &= ~FPCCR_LSPACT;
#endif
/* Current PSP value.*/
ctxp = (struct extctx *)__get_PSP();
/* Discarding the current exception context and positioning the stack to
point to the real one.*/
ctxp++;
/* Restoring real position of the original stack frame.*/
__set_PSP((unsigned long)ctxp);
}
#endif /* CORTEX_SIMPLIFIED_PRIORITY */
/*===========================================================================*/
/* Port exported functions. */
/*===========================================================================*/
/**
* @brief Port-related initialization code.
*/
void _port_init(void) {
/* Initialization of the vector table and priority related settings.*/
SCB_VTOR = CORTEX_VTOR_INIT;
SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(CORTEX_PRIGROUP_INIT);
#if CORTEX_USE_FPU
{
/* Initializing the FPU context save in lazy mode.*/
SCB_FPCCR = FPCCR_ASPEN | FPCCR_LSPEN;
/* CP10 and CP11 set to full access.*/
SCB_CPACR |= 0x00F00000;
/* Enables FPU context save/restore on exception entry/exit (FPCA bit).*/
__set_CONTROL(__get_CONTROL() | 4);
/* FPSCR and FPDSCR initially zero.*/
__set_FPSCR(0);
SCB_FPDSCR = 0;
}
#endif
/* Initialization of the system vectors used by the port.*/
nvicSetSystemHandlerPriority(HANDLER_SVCALL,
CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SVCALL));
nvicSetSystemHandlerPriority(HANDLER_PENDSV,
CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_PENDSV));
nvicSetSystemHandlerPriority(HANDLER_SYSTICK,
CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK));
}
/**
* @brief Exception exit redirection to _port_switch_from_isr().
*/
void _port_irq_epilogue(void) {
port_lock_from_isr();
if ((SCB_ICSR & ICSR_RETTOBASE) != 0) {
struct extctx *ctxp;
#if CORTEX_USE_FPU
/* Enforcing a lazy FPU state save. Note, it goes in the original
context because the FPCAR register has not been modified.*/
(void)__get_FPSCR();
#endif
/* Current PSP value.*/
ctxp = (struct extctx *)__get_PSP();
/* Adding an artificial exception return context, there is no need to
populate it fully.*/
ctxp--;
ctxp->xpsr = (regarm_t)0x01000000;
#if CORTEX_USE_FPU
ctxp->fpscr = (regarm_t)SCB_FPDSCR;
#endif
__set_PSP((unsigned long)ctxp);
/* The exit sequence is different depending on if a preemption is
required or not.*/
if (chSchIsPreemptionRequired()) {
/* Preemption is required we need to enforce a context switch.*/
ctxp->pc = (regarm_t)_port_switch_from_isr;
}
else {
/* Preemption not required, we just need to exit the exception
atomically.*/
ctxp->pc = (regarm_t)_port_exit_from_isr;
}
/* Note, returning without unlocking is intentional, this is done in
order to keep the rest of the context switch atomic.*/
return;
}
port_unlock_from_isr();
}
/** @} */

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/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
/**
* @file IAR/ARMCMx/chcore_v7m.h
* @brief ARMv7-M architecture port macros and structures.
*
* @addtogroup IAR_ARMCMx_V7M_CORE
* @{
*/
#ifndef _CHCORE_V7M_H_
#define _CHCORE_V7M_H_
/*===========================================================================*/
/* Port constants. */
/*===========================================================================*/
/**
* @brief Disabled value for BASEPRI register.
*/
#define CORTEX_BASEPRI_DISABLED 0
/*===========================================================================*/
/* Port macros. */
/*===========================================================================*/
/*===========================================================================*/
/* Port configurable parameters. */
/*===========================================================================*/
/**
* @brief Stack size for the system idle thread.
* @details This size depends on the idle thread implementation, usually
* the idle thread should take no more space than those reserved
* by @p PORT_INT_REQUIRED_STACK.
* @note In this port it is set to 16 because the idle thread does have
* a stack frame when compiling without optimizations. You may
* reduce this value to zero when compiling with optimizations.
*/
#if !defined(PORT_IDLE_THREAD_STACK_SIZE)
#define PORT_IDLE_THREAD_STACK_SIZE 16
#endif
/**
* @brief Per-thread stack overhead for interrupts servicing.
* @details This constant is used in the calculation of the correct working
* area size.
* @note In this port this value is conservatively set to 32 because the
* function @p chSchDoReschedule() can have a stack frame, especially
* with compiler optimizations disabled. The value can be reduced
* when compiler optimizations are enabled.
*/
#if !defined(PORT_INT_REQUIRED_STACK)
#define PORT_INT_REQUIRED_STACK 32
#endif
/**
* @brief Enables the use of the WFI instruction in the idle thread loop.
*/
#if !defined(CORTEX_ENABLE_WFI_IDLE)
#define CORTEX_ENABLE_WFI_IDLE FALSE
#endif
/**
* @brief SYSTICK handler priority.
* @note The default SYSTICK handler priority is calculated as the priority
* level in the middle of the numeric priorities range.
*/
#if !defined(CORTEX_PRIORITY_SYSTICK)
#define CORTEX_PRIORITY_SYSTICK (CORTEX_PRIORITY_LEVELS >> 1)
#elif !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SYSTICK)
/* If it is externally redefined then better perform a validity check on it.*/
#error "invalid priority level specified for CORTEX_PRIORITY_SYSTICK"
#endif
/**
* @brief FPU support in context switch.
* @details Activating this option activates the FPU support in the kernel.
*/
#if !defined(CORTEX_USE_FPU)
#define CORTEX_USE_FPU CORTEX_HAS_FPU
#elif CORTEX_USE_FPU && !CORTEX_HAS_FPU
/* This setting requires an FPU presence check in case it is externally
redefined.*/
#error "the selected core does not have an FPU"
#endif
/**
* @brief Simplified priority handling flag.
* @details Activating this option makes the Kernel work in compact mode.
*/
#if !defined(CORTEX_SIMPLIFIED_PRIORITY)
#define CORTEX_SIMPLIFIED_PRIORITY FALSE
#endif
/**
* @brief SVCALL handler priority.
* @note The default SVCALL handler priority is defaulted to
* @p CORTEX_MAXIMUM_PRIORITY+1, this reserves the
* @p CORTEX_MAXIMUM_PRIORITY priority level as fast interrupts
* priority level.
*/
#if !defined(CORTEX_PRIORITY_SVCALL)
#define CORTEX_PRIORITY_SVCALL (CORTEX_MAXIMUM_PRIORITY + 1)
#elif !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SVCALL)
/* If it is externally redefined then better perform a validity check on it.*/
#error "invalid priority level specified for CORTEX_PRIORITY_SVCALL"
#endif
/**
* @brief NVIC VTOR initialization expression.
*/
#if !defined(CORTEX_VTOR_INIT) || defined(__DOXYGEN__)
#define CORTEX_VTOR_INIT 0x00000000
#endif
/**
* @brief NVIC PRIGROUP initialization expression.
* @details The default assigns all available priority bits as preemption
* priority with no sub-priority.
*/
#if !defined(CORTEX_PRIGROUP_INIT) || defined(__DOXYGEN__)
#define CORTEX_PRIGROUP_INIT (7 - CORTEX_PRIORITY_BITS)
#endif
/*===========================================================================*/
/* Port derived parameters. */
/*===========================================================================*/
#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
/**
* @brief Maximum usable priority for normal ISRs.
*/
#define CORTEX_MAX_KERNEL_PRIORITY (CORTEX_PRIORITY_SVCALL + 1)
/**
* @brief BASEPRI level within kernel lock.
* @note In compact kernel mode this constant value is enforced to zero.
*/
#define CORTEX_BASEPRI_KERNEL \
CORTEX_PRIORITY_MASK(CORTEX_MAX_KERNEL_PRIORITY)
#else
#define CORTEX_MAX_KERNEL_PRIORITY 1
#define CORTEX_BASEPRI_KERNEL 0
#endif
/**
* @brief PendSV priority level.
* @note This priority is enforced to be equal to
* @p CORTEX_MAX_KERNEL_PRIORITY, this handler always have the
* highest priority that cannot preempt the kernel.
*/
#define CORTEX_PRIORITY_PENDSV CORTEX_MAX_KERNEL_PRIORITY
/*===========================================================================*/
/* Port exported info. */
/*===========================================================================*/
#if (CORTEX_MODEL == CORTEX_M3) || defined(__DOXYGEN__)
/**
* @brief Macro defining the specific ARM architecture.
*/
#define CH_ARCHITECTURE_ARM_v7M
/**
* @brief Name of the implemented architecture.
*/
#define CH_ARCHITECTURE_NAME "ARMv7-M"
/**
* @brief Name of the architecture variant.
*/
#define CH_CORE_VARIANT_NAME "Cortex-M3"
#elif (CORTEX_MODEL == CORTEX_M4)
#define CH_ARCHITECTURE_ARM_v7ME
#define CH_ARCHITECTURE_NAME "ARMv7-ME"
#if CORTEX_USE_FPU
#define CH_CORE_VARIANT_NAME "Cortex-M4F"
#else
#define CH_CORE_VARIANT_NAME "Cortex-M4"
#endif
#endif
/**
* @brief Port-specific information string.
*/
#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
#define CH_PORT_INFO "Advanced kernel mode"
#else
#define CH_PORT_INFO "Compact kernel mode"
#endif
/*===========================================================================*/
/* Port implementation part. */
/*===========================================================================*/
#if !defined(_FROM_ASM_)
/**
* @brief Generic ARM register.
*/
typedef void *regarm_t;
/**
* @brief Stack and memory alignment enforcement.
* @note In this architecture the stack alignment is enforced to 64 bits,
* 32 bits alignment is supported by hardware but deprecated by ARM,
* the implementation choice is to not offer the option.
*/
typedef uint64_t stkalign_t;
/* The documentation of the following declarations is in chconf.h in order
to not have duplicated structure names into the documentation.*/
#if !defined(__DOXYGEN__)
struct extctx {
regarm_t r0;
regarm_t r1;
regarm_t r2;
regarm_t r3;
regarm_t r12;
regarm_t lr_thd;
regarm_t pc;
regarm_t xpsr;
#if CORTEX_USE_FPU
regarm_t s0;
regarm_t s1;
regarm_t s2;
regarm_t s3;
regarm_t s4;
regarm_t s5;
regarm_t s6;
regarm_t s7;
regarm_t s8;
regarm_t s9;
regarm_t s10;
regarm_t s11;
regarm_t s12;
regarm_t s13;
regarm_t s14;
regarm_t s15;
regarm_t fpscr;
regarm_t reserved;
#endif /* CORTEX_USE_FPU */
};
struct intctx {
#if CORTEX_USE_FPU
regarm_t s16;
regarm_t s17;
regarm_t s18;
regarm_t s19;
regarm_t s20;
regarm_t s21;
regarm_t s22;
regarm_t s23;
regarm_t s24;
regarm_t s25;
regarm_t s26;
regarm_t s27;
regarm_t s28;
regarm_t s29;
regarm_t s30;
regarm_t s31;
#endif /* CORTEX_USE_FPU */
regarm_t r4;
regarm_t r5;
regarm_t r6;
regarm_t r7;
regarm_t r8;
regarm_t r9;
regarm_t r10;
regarm_t r11;
regarm_t lr;
};
#endif /* !defined(__DOXYGEN__) */
/**
* @brief Platform dependent part of the @p Thread structure.
* @details In this port the structure just holds a pointer to the @p intctx
* structure representing the stack pointer at context switch time.
*/
struct context {
struct intctx *r13;
};
/**
* @brief Platform dependent part of the @p chThdCreateI() API.
* @details This code usually setup the context switching frame represented
* by an @p intctx structure.
*/
#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \
tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace + \
wsize - \
sizeof(struct intctx)); \
tp->p_ctx.r13->r4 = (regarm_t)pf; \
tp->p_ctx.r13->r5 = (regarm_t)arg; \
tp->p_ctx.r13->lr = (regarm_t)_port_thread_start; \
}
/**
* @brief Enforces a correct alignment for a stack area size value.
*/
#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1)
/**
* @brief Computes the thread working area global size.
*/
#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \
sizeof(struct intctx) + \
sizeof(struct extctx) + \
(n) + (PORT_INT_REQUIRED_STACK))
/**
* @brief Static working area allocation.
* @details This macro is used to allocate a static thread working area
* aligned as both position and size.
*/
#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)]
/**
* @brief IRQ prologue code.
* @details This macro must be inserted at the start of all IRQ handlers
* enabled to invoke system APIs.
*/
#define PORT_IRQ_PROLOGUE()
/**
* @brief IRQ epilogue code.
* @details This macro must be inserted at the end of all IRQ handlers
* enabled to invoke system APIs.
*/
#define PORT_IRQ_EPILOGUE() _port_irq_epilogue()
/**
* @brief IRQ handler function declaration.
* @note @p id can be a function name or a vector number depending on the
* port implementation.
*/
#define PORT_IRQ_HANDLER(id) void id(void)
/**
* @brief Fast IRQ handler function declaration.
* @note @p id can be a function name or a vector number depending on the
* port implementation.
*/
#define PORT_FAST_IRQ_HANDLER(id) void id(void)
/**
* @brief Port-related initialization code.
*/
#define port_init() _port_init()
/**
* @brief Kernel-lock action.
* @details Usually this function just disables interrupts but may perform
* more actions.
* @note In this port this it raises the base priority to kernel level.
*/
#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
#define port_lock() __set_BASEPRI(CORTEX_BASEPRI_KERNEL)
#else /* CORTEX_SIMPLIFIED_PRIORITY */
#define port_lock() __disable_interrupt()
#endif /* CORTEX_SIMPLIFIED_PRIORITY */
/**
* @brief Kernel-unlock action.
* @details Usually this function just enables interrupts but may perform
* more actions.
* @note In this port this it lowers the base priority to user level.
*/
#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
#define port_unlock() __set_BASEPRI(CORTEX_BASEPRI_DISABLED)
#else /* CORTEX_SIMPLIFIED_PRIORITY */
#define port_unlock() __enable_interrupt()
#endif /* CORTEX_SIMPLIFIED_PRIORITY */
/**
* @brief Kernel-lock action from an interrupt handler.
* @details This function is invoked before invoking I-class APIs from
* interrupt handlers. The implementation is architecture dependent,
* in its simplest form it is void.
* @note Same as @p port_lock() in this port.
*/
#define port_lock_from_isr() port_lock()
/**
* @brief Kernel-unlock action from an interrupt handler.
* @details This function is invoked after invoking I-class APIs from interrupt
* handlers. The implementation is architecture dependent, in its
* simplest form it is void.
* @note Same as @p port_unlock() in this port.
*/
#define port_unlock_from_isr() port_unlock()
/**
* @brief Disables all the interrupt sources.
* @note Of course non-maskable interrupt sources are not included.
* @note In this port it disables all the interrupt sources by raising
* the priority mask to level 0.
*/
#define port_disable() __disable_interrupt()
/**
* @brief Disables the interrupt sources below kernel-level priority.
* @note Interrupt sources above kernel level remains enabled.
* @note In this port it raises/lowers the base priority to kernel level.
*/
#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
#define port_suspend() { \
__set_BASEPRI(CORTEX_BASEPRI_KERNEL); \
__enable_interrupt(); \
}
#else /* CORTEX_SIMPLIFIED_PRIORITY */
#define port_suspend() __disable_interrupt()
#endif /* CORTEX_SIMPLIFIED_PRIORITY */
/**
* @brief Enables all the interrupt sources.
* @note In this port it lowers the base priority to user level.
*/
#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)
#define port_enable() { \
__set_BASEPRI(CORTEX_BASEPRI_DISABLED); \
__enable_interrupt(); \
}
#else /* CORTEX_SIMPLIFIED_PRIORITY */
#define port_enable() __enable_interrupt()
#endif /* CORTEX_SIMPLIFIED_PRIORITY */
/**
* @brief Enters an architecture-dependent IRQ-waiting mode.
* @details The function is meant to return when an interrupt becomes pending.
* The simplest implementation is an empty function or macro but this
* would not take advantage of architecture-specific power saving
* modes.
* @note Implemented as an inlined @p WFI instruction.
*/
#if CORTEX_ENABLE_WFI_IDLE || defined(__DOXYGEN__)
#define port_wait_for_interrupt() asm ("wfi")
#else
#define port_wait_for_interrupt()
#endif
/**
* @brief Performs a context switch between two threads.
* @details This is the most critical code in any port, this function
* is responsible for the context switch between 2 threads.
* @note The implementation of this code affects <b>directly</b> the context
* switch performance so optimize here as much as you can.
*
* @param[in] ntp the thread to be switched in
* @param[in] otp the thread to be switched out
*/
#if !CH_DBG_ENABLE_STACK_CHECK || defined(__DOXYGEN__)
#define port_switch(ntp, otp) _port_switch(ntp, otp)
#else
#define port_switch(ntp, otp) { \
if ((stkalign_t *)(__get_SP() - sizeof(struct intctx)) < otp->p_stklimit) \
chDbgPanic("stack overflow"); \
_port_switch(ntp, otp); \
}
#endif
#ifdef __cplusplus
extern "C" {
#endif
void port_halt(void);
void _port_init(void);
void _port_irq_epilogue(void);
void _port_switch_from_isr(void);
void _port_exit_from_isr(void);
void _port_switch(Thread *ntp, Thread *otp);
void _port_thread_start(void);
#ifdef __cplusplus
}
#endif
#endif /* _FROM_ASM_ */
#endif /* _CHCORE_V7M_H_ */
/** @} */

118
firmware/chibios/os/ports/IAR/ARMCMx/chcoreasm_v6m.s Executable file
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/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
MODULE ?chcoreasm_v6m
AAPCS INTERWORK, VFP_COMPATIBLE
PRESERVE8
/*
* Imports the Cortex-Mx configuration headers.
*/
#define _FROM_ASM_
#include "chconf.h"
#include "chcore.h"
CONTEXT_OFFSET SET 12
SCB_ICSR SET 0xE000ED04
SECTION .text:CODE:NOROOT(2)
EXTERN chThdExit
EXTERN chSchDoReschedule
#if CH_DBG_SYSTEM_STATE_CHECK
EXTERN dbg_check_unlock
EXTERN dbg_check_lock
#endif
THUMB
/*
* Performs a context switch between two threads.
*/
PUBLIC _port_switch
_port_switch:
push {r4, r5, r6, r7, lr}
mov r4, r8
mov r5, r9
mov r6, r10
mov r7, r11
push {r4, r5, r6, r7}
mov r3, sp
str r3, [r1, #CONTEXT_OFFSET]
ldr r3, [r0, #CONTEXT_OFFSET]
mov sp, r3
pop {r4, r5, r6, r7}
mov r8, r4
mov r9, r5
mov r10, r6
mov r11, r7
pop {r4, r5, r6, r7, pc}
/*
* Start a thread by invoking its work function.
* If the work function returns @p chThdExit() is automatically invoked.
*/
PUBLIC _port_thread_start
_port_thread_start:
#if CH_DBG_SYSTEM_STATE_CHECK
bl dbg_check_unlock
#endif
cpsie i
mov r0, r5
blx r4
bl chThdExit
/*
* Post-IRQ switch code.
* Exception handlers return here for context switching.
*/
PUBLIC _port_switch_from_isr
PUBLIC _port_exit_from_isr
_port_switch_from_isr:
#if CH_DBG_SYSTEM_STATE_CHECK
bl dbg_check_lock
#endif
bl chSchDoReschedule
#if CH_DBG_SYSTEM_STATE_CHECK
bl dbg_check_unlock
#endif
_port_exit_from_isr:
ldr r2, =SCB_ICSR
movs r3, #128
#if CORTEX_ALTERNATE_SWITCH
lsls r3, r3, #21
str r3, [r2, #0]
cpsie i
#else
lsls r3, r3, #24
str r3, [r2, #0]
#endif
waithere:
b waithere
END

116
firmware/chibios/os/ports/IAR/ARMCMx/chcoreasm_v7m.s Executable file
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/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
MODULE ?chcoreasm_v7m
AAPCS INTERWORK, VFP_COMPATIBLE
PRESERVE8
/*
* Imports the Cortex-Mx configuration headers.
*/
#define _FROM_ASM_
#include "chconf.h"
#include "chcore.h"
CONTEXT_OFFSET SET 12
SCB_ICSR SET 0xE000ED04
ICSR_PENDSVSET SET 0x10000000
SECTION .text:CODE:NOROOT(2)
EXTERN chThdExit
EXTERN chSchDoReschedule
#if CH_DBG_SYSTEM_STATE_CHECK
EXTERN dbg_check_unlock
EXTERN dbg_check_lock
#endif
THUMB
/*
* Performs a context switch between two threads.
*/
PUBLIC _port_switch
_port_switch:
push {r4, r5, r6, r7, r8, r9, r10, r11, lr}
#if CORTEX_USE_FPU
vpush {s16-s31}
#endif
str sp, [r1, #CONTEXT_OFFSET]
ldr sp, [r0, #CONTEXT_OFFSET]
#if CORTEX_USE_FPU
vpop {s16-s31}
#endif
pop {r4, r5, r6, r7, r8, r9, r10, r11, pc}
/*
* Start a thread by invoking its work function.
* If the work function returns @p chThdExit() is automatically invoked.
*/
PUBLIC _port_thread_start
_port_thread_start:
#if CH_DBG_SYSTEM_STATE_CHECK
bl dbg_check_unlock
#endif
#if CORTEX_SIMPLIFIED_PRIORITY
cpsie i
#else
movs r3, #CORTEX_BASEPRI_DISABLED
msr BASEPRI, r3
#endif
mov r0, r5
blx r4
bl chThdExit
/*
* Post-IRQ switch code.
* Exception handlers return here for context switching.
*/
PUBLIC _port_switch_from_isr
PUBLIC _port_exit_from_isr
_port_switch_from_isr:
#if CH_DBG_SYSTEM_STATE_CHECK
bl dbg_check_lock
#endif
bl chSchDoReschedule
#if CH_DBG_SYSTEM_STATE_CHECK
bl dbg_check_unlock
#endif
_port_exit_from_isr:
#if CORTEX_SIMPLIFIED_PRIORITY
mov r3, #LWRD SCB_ICSR
movt r3, #HWRD SCB_ICSR
mov r2, #ICSR_PENDSVSET
str r2, [r3]
cpsie i
.L3: b .L3
#else
svc #0
#endif
END

91
firmware/chibios/os/ports/IAR/ARMCMx/chtypes.h Executable file
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/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
/**
* @file IAR/ARMCMx/chtypes.h
* @brief ARM Cortex-Mx port system types.
*
* @addtogroup IAR_ARMCMx_CORE
* @{
*/
#ifndef _CHTYPES_H_
#define _CHTYPES_H_
#include <stddef.h>
#include <stdint.h>
#include <stdbool.h>
typedef bool bool_t; /**< Fast boolean type. */
typedef uint8_t tmode_t; /**< Thread flags. */
typedef uint8_t tstate_t; /**< Thread state. */
typedef uint8_t trefs_t; /**< Thread references counter. */
typedef uint8_t tslices_t; /**< Thread time slices counter. */
typedef uint32_t tprio_t; /**< Thread priority. */
typedef int32_t msg_t; /**< Inter-thread message. */
typedef int32_t eventid_t; /**< Event Id. */
typedef uint32_t eventmask_t; /**< Event mask. */
typedef uint32_t flagsmask_t; /**< Event flags. */
typedef uint32_t systime_t; /**< System time. */
typedef int32_t cnt_t; /**< Resources counter. */
/**
* @brief Inline function modifier.
*/
#define INLINE inline
/**
* @brief ROM constant modifier.
* @note It is set to use the "const" keyword in this port.
*/
#define ROMCONST const
/**
* @brief Packed structure modifier (within).
* @note Empty in this port.
*/
#define PACK_STRUCT_STRUCT
/**
* @brief Packed structure modifier (before).
*/
#define PACK_STRUCT_BEGIN __packed
/**
* @brief Packed structure modifier (after).
* @note Empty in this port.
*/
#define PACK_STRUCT_END
/**
* @brief Packed variable specifier.
*/
#define PACKED_VAR __packed
#endif /* _CHTYPES_H_ */
/** @} */

75
firmware/chibios/os/ports/IAR/ARMCMx/cstartup.s Executable file
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/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
MODULE ?cstartup
CONTROL_MODE_PRIVILEGED SET 0
CONTROL_MODE_UNPRIVILEGED SET 1
CONTROL_USE_MSP SET 0
CONTROL_USE_PSP SET 2
AAPCS INTERWORK, VFP_COMPATIBLE, ROPI
PRESERVE8
SECTION .intvec:CODE:NOROOT(3)
SECTION CSTACK:DATA:NOROOT(3)
PUBLIC __main_thread_stack_base__
__main_thread_stack_base__:
PUBLIC __heap_end__
__heap_end__:
SECTION SYSHEAP:DATA:NOROOT(3)
PUBLIC __heap_base__
__heap_base__:
PUBLIC __iar_program_start
EXTERN __vector_table
EXTWEAK __iar_init_core
EXTWEAK __iar_init_vfp
EXTERN __cmain
SECTION .text:CODE:REORDER(2)
REQUIRE __vector_table
THUMB
__iar_program_start:
cpsid i
ldr r0, =SFE(CSTACK)
msr PSP, r0
movs r0, #CONTROL_MODE_PRIVILEGED | CONTROL_USE_PSP
msr CONTROL, r0
isb
bl __early_init
bl __iar_init_core
bl __iar_init_vfp
b __cmain
PUBWEAK __early_init
__early_init:
bx lr
END

235
firmware/chibios/os/ports/IAR/ARMCMx/port.dox Executable file
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/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
/**
* @defgroup IAR_ARMCMx ARM Cortex-Mx
* @details ARM Cortex-Mx port for the IAR compiler.
* @section IAR_ARMCMx_INTRO Introduction
* This port supports all the cores implementing the ARMv6-M and ARMv7-M
* architectures.
*
* @section IAR_ARMCMx_MODES Kernel Modes
* The Cortex-Mx port supports two distinct kernel modes:
* - <b>Advanced Kernel</b> mode. In this mode the kernel only masks
* interrupt sources with priorities below or equal to the
* @p CORTEX_BASEPRI_KERNEL level. Higher priorities are not affected by
* the kernel critical sections and can be used for fast interrupts.
* This mode is not available in the ARMv6-M architecture which does not
* support priority masking.
* - <b>Compact Kernel</b> mode. In this mode the kernel handles IRQ priorities
* in a simplified way, all interrupt sources are disabled when the kernel
* enters into a critical zone and re-enabled on exit. This is simple and
* adequate for most applications, this mode results in a more compact and
* faster kernel.
* .
* The selection of the mode is performed using the port configuration option
* @p CORTEX_SIMPLIFIED_PRIORITY. Apart from the different handling of
* interrupts there are no other differences between the two modes. The
* kernel API is exactly the same.
*
* @section IAR_ARMCMx_STATES_A System logical states in Compact Kernel mode
* The ChibiOS/RT logical @ref system_states are mapped as follow in Compact
* Kernel mode:
* - <b>Init</b>. This state is represented by the startup code and the
* initialization code before @p chSysInit() is executed. It has not a
* special hardware state associated.
* - <b>Normal</b>. This is the state the system has after executing
* @p chSysInit(). In this state interrupts are enabled. The processor
* is running in thread-privileged mode.
* - <b>Suspended</b>. In this state the interrupt sources are globally
* disabled. The processor is running in thread-privileged mode. In this
* mode this state is not different from the <b>Disabled</b> state.
* - <b>Disabled</b>. In this state the interrupt sources are globally
* disabled. The processor is running in thread-privileged mode. In this
* mode this state is not different from the <b>Suspended</b> state.
* - <b>Sleep</b>. This state is entered with the execution of the specific
* instruction @p <b>wfi</b>.
* - <b>S-Locked</b>. In this state the interrupt sources are globally
* disabled. The processor is running in thread-privileged mode.
* - <b>I-Locked</b>. In this state the interrupt sources are globally
* disabled. The processor is running in exception-privileged mode.
* - <b>Serving Regular Interrupt</b>. In this state the interrupt sources are
* not globally masked but only interrupts with higher priority can preempt
* the current handler. The processor is running in exception-privileged
* mode.
* - <b>Serving Fast Interrupt</b>. Not implemented in compact kernel mode.
* - <b>Serving Non-Maskable Interrupt</b>. The Cortex-Mx has a specific
* asynchronous NMI vector and several synchronous fault vectors that can
* be considered belonging to this category.
* - <b>Halted</b>. Implemented as an infinite loop after globally masking all
* the maskable interrupt sources. The ARM state is whatever the processor
* was running when @p chSysHalt() was invoked.
*
* @section IAR_ARMCMx_STATES_B System logical states in Advanced Kernel mode
* The ChibiOS/RT logical @ref system_states are mapped as follow in the
* Advanced Kernel mode:
* - <b>Init</b>. This state is represented by the startup code and the
* initialization code before @p chSysInit() is executed. It has not a
* special hardware state associated.
* - <b>Normal</b>. This is the state the system has after executing
* @p chSysInit(). In this state the ARM Cortex-Mx has the BASEPRI register
* set at @p CORTEX_BASEPRI_USER level, interrupts are not masked. The
* processor is running in thread-privileged mode.
* - <b>Suspended</b>. In this state the interrupt sources are not globally
* masked but the BASEPRI register is set to @p CORTEX_BASEPRI_KERNEL thus
* masking any interrupt source with lower or equal priority. The processor
* is running in thread-privileged mode.
* - <b>Disabled</b>. Interrupt sources are globally masked. The processor
* is running in thread-privileged mode.
* - <b>Sleep</b>. This state is entered with the execution of the specific
* instruction @p <b>wfi</b>.
* - <b>S-Locked</b>. In this state the interrupt sources are not globally
* masked but the BASEPRI register is set to @p CORTEX_BASEPRI_KERNEL thus
* masking any interrupt source with lower or equal priority. The processor
* is running in thread-privileged mode.
* - <b>I-Locked</b>. In this state the interrupt sources are not globally
* masked but the BASEPRI register is set to @p CORTEX_BASEPRI_KERNEL thus
* masking any interrupt source with lower or equal priority. The processor
* is running in exception-privileged mode.
* - <b>Serving Regular Interrupt</b>. In this state the interrupt sources are
* not globally masked but only interrupts with higher priority can preempt
* the current handler. The processor is running in exception-privileged
* mode.
* - <b>Serving Fast Interrupt</b>. Fast interrupts are defined as interrupt
* sources having higher priority level than the kernel
* (@p CORTEX_BASEPRI_KERNEL). In this state is not possible to switch to
* the I-Locked state because fast interrupts can preempt the kernel
* critical zone.<br>
* This state is not implemented in the ARMv6-M implementation because
* priority masking is not present in this architecture.
* - <b>Serving Non-Maskable Interrupt</b>. The Cortex-Mx has a specific
* asynchronous NMI vector and several synchronous fault vectors that can
* be considered belonging to this category.
* - <b>Halted</b>. Implemented as an infinite loop after globally masking all
* the maskable interrupt sources. The ARM state is whatever the processor
* was running when @p chSysHalt() was invoked.
* .
* @section IAR_ARMCMx_NOTES ARM Cortex-Mx/IAR port notes
* The ARM Cortex-Mx port is organized as follow:
* - The @p main() function is invoked in thread-privileged mode.
* - Each thread has a private process stack, the system has a single main
* stack where all the interrupts and exceptions are processed.
* - The threads are started in thread-privileged mode.
* - Interrupt nesting and the other advanced core/NVIC features are supported.
* - The Cortex-Mx port is perfectly generic, support for more devices can be
* easily added by adding a subdirectory under <tt>./os/ports/IAR/ARMCMx</tt>
* and giving it the name of the new device, then copy the files from another
* device into the new directory and customize them for the new device.
* .
* @ingroup iar
*/
/**
* @defgroup IAR_ARMCMx_CONF Configuration Options
* @details ARM Cortex-Mx Configuration Options. The ARMCMx port allows some
* architecture-specific configurations settings that can be overridden
* by redefining them in @p chconf.h. Usually there is no need to change
* the default values.
* - @p INT_REQUIRED_STACK, this value represent the amount of stack space used
* by an interrupt handler between the @p extctx and @p intctx
* structures.
* - @p IDLE_THREAD_STACK_SIZE, stack area size to be assigned to the IDLE
* thread. Usually there is no need to change this value unless inserting
* code in the IDLE thread using the @p IDLE_LOOP_HOOK hook macro.
* - @p CORTEX_PRIORITY_SYSTICK, priority of the SYSTICK handler.
* - @p CORTEX_PRIORITY_PENDSV, priority of the PENDSV handler.
* - @p CORTEX_ENABLE_WFI_IDLE, if set to @p TRUE enables the use of the
* @p <b>wfi</b> instruction from within the idle loop. This option is
* defaulted to FALSE because it can create problems with some debuggers.
* Setting this option to TRUE reduces the system power requirements.
* .
* @section IAR_ARMCMx_CONF_1 ARMv6-M specific options
* The following options are specific for the ARMv6-M architecture:
* - @p CORTEX_ALTERNATE_SWITCH, when activated makes the OS use the PendSV
* exception instead of NMI as preemption handler.
* .
* @section IAR_ARMCMx_CONF_2 ARMv7-M specific options
* The following options are specific for the ARMv6-M architecture:
* - @p CORTEX_PRIORITY_SVCALL, priority of the SVCALL handler.
* - @p CORTEX_SIMPLIFIED_PRIORITY, when enabled activates the Compact kernel
* mode.
* .
* @ingroup IAR_ARMCMx
*/
/**
* @defgroup IAR_ARMCMx_CORE Core Port Implementation
* @details ARM Cortex-Mx specific port code, structures and macros.
*
* @ingroup IAR_ARMCMx
*/
/**
* @defgroup IAR_ARMCMx_V6M_CORE ARMv6-M Specific Implementation
* @details ARMv6-M specific port code, structures and macros.
*
* @ingroup IAR_ARMCMx_CORE
*/
/**
* @defgroup IAR_ARMCMx_V7M_CORE ARMv7-M Specific Implementation
* @details ARMv7-M specific port code, structures and macros.
*
* @ingroup IAR_ARMCMx_CORE
*/
/**
* @defgroup IAR_ARMCMx_STARTUP Startup Support
* @details ChibiOS/RT provides its own generic startup file for the ARM
* Cortex-Mx port.
* Of course it is not mandatory to use it but care should be taken about the
* startup phase details.
*
* @section IAR_ARMCMx_STARTUP_1 Startup Process
* The startup process, as implemented, is the following:
* -# Interrupts are masked globally.
* -# The two stacks are initialized by assigning them the sizes defined in the
* linker script (usually named @p ch.icf).
* -# The CPU state is switched to Privileged and the PSP stack is used.
* -# An early initialization routine @p __early_init() is invoked, if the
* symbol is not defined then an empty default routine is executed
* (weak symbol).
* -# Control is passed to the C runtime entry point @p __cmain that performs
* the required initializations before invoking the @p main() function.
* .
* @ingroup IAR_ARMCMx
*/
/**
* @defgroup IAR_ARMCMx_NVIC NVIC Support
* @details ARM Cortex-Mx NVIC support.
*
* @ingroup IAR_ARMCMx
*/
/**
* @defgroup IAR_ARMCMx_SPECIFIC Specific Implementations
* @details Platform-specific port code.
*
* @ingroup IAR_ARMCMx
*/