Jared Boone
29243a5fd1
Schematic and netlist from schematic modifications.
2015-08-27 16:54:38 -07:00
Jared Boone
70d7ecc51b
Clean up PCB net labels to match code, CPLD.
2015-08-27 16:54:38 -07:00
Jared Boone
75d9aa9c73
Remove extra CPLD code internal signals.
2015-08-27 16:54:38 -07:00
Jared Boone
19764ce693
Swap function of P2_8, P2_4 in schematic, firmware, CPLD.
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gpio_unused: P2_4 -> P2_8
gpio_lcd_rd: P2_8 -> P2_4
P2_8 is a very long line, shared with DFU button.
Revise schematic to match CPLD signal names.
2015-08-27 16:54:38 -07:00
Jared Boone
b6e25692dc
Label 1V8 regulator bypass/adjust capacitor as DNI.
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Was already DNI in assembly BOM. TCR2EF shows that pin as NC.
2015-08-27 16:54:38 -07:00
Jared Boone
1ca4f45d9e
Change VBAT capacitor to DNI.
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HackRF One has 100nF capacitor on VBAT. Having 10uF capacitor on PortaPack VBAT may slowly drain the coin cell when in storage, and add a bit of leakage current when installed.
2015-08-27 16:54:38 -07:00
Jared Boone
8dfd68a6b3
Removed electret microphone.
2015-08-27 16:54:37 -07:00
Jared Boone
cd4840f1f9
Remove line in/out circuitry.
2015-08-27 16:54:37 -07:00
Jared Boone
84ffaaef33
Back-annotate CVPCB data into schematic.
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Remove CVPCB .cmp file, since it's a deprecated by the KiCad project.
2015-08-27 16:54:37 -07:00
Jared Boone
bf4521bf35
Update schematic issue/copyright date.
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KiCad also made some automatic tweaks for latest build (bzr 6109).
2015-08-27 16:54:37 -07:00
Jared Boone
fcec6d6100
OpenSCAD version of case.
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Minor changes were made between this version and the final version. This earlier version is available via Shapeways, at https://www.shapeways.com/product/EGG3EWPAY/portapack-h1-case-round-20150410-0945
Addresses issue #30 .
2015-08-01 22:27:08 -07:00
Jared Boone
565ea41e92
Hardware gitignore
2015-07-16 10:01:19 -07:00
Jared Boone
604389f8cd
Initial release of schematic, PCB, CPLD code.
2015-07-16 09:54:15 -07:00
