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1,324 Commits 2 Branches 488 Tags 423 MiB
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11 Commits

Author SHA1 Message Date
Jared Boone
b3c21c3762 CPLD: Ask Quartus to use maximum number of processors. 2017-06-13 21:21:25 -07:00
Jared Boone
9a0fa128c0 CPLD: Clean up *.qws files. 2017-06-13 21:20:19 -07:00
Jared Boone
76c2cc77af CPLD: Move around some .gitignores. 2017-06-01 15:20:16 -07:00
Jared Boone
797e63a590 CPLD: Use correct bitstream for updating hardware. 
Determine hardware version and use one of two CPLD bitstream files.
 2017-05-31 22:28:07 -07:00
Jared Boone
73d62367d1 CPLD: Makefiles for both hardware variants. 2017-05-31 21:05:47 -07:00
Jared Boone
7c715ed913 CPLD: HDL for 20170522 hardware variant. 2017-05-31 15:21:25 -07:00
Jared Boone
0fd52a7483 CPLD: Move HDL project to hardware revision-specific directory. 2017-05-31 11:50:59 -07:00
Jared Boone
2add96d42d CPLD: Add .svf output file so CMake can generate data for firmware. 2016-07-10 15:01:04 -07:00
Jared Boone
75d9aa9c73 Remove extra CPLD code internal signals. 2015-08-27 16:54:38 -07:00
Jared Boone
19764ce693 Swap function of P2_8, P2_4 in schematic, firmware, CPLD. 
gpio_unused: P2_4 -> P2_8
gpio_lcd_rd: P2_8 -> P2_4
P2_8 is a very long line, shared with DFU button.
Revise schematic to match CPLD signal names.
 2015-08-27 16:54:38 -07:00
Jared Boone
604389f8cd Initial release of schematic, PCB, CPLD code. 2015-07-16 09:54:15 -07:00