mirror of
https://github.com/portapack-mayhem/mayhem-firmware.git
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452 lines
14 KiB
C
Executable File
452 lines
14 KiB
C
Executable File
/*
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ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file AT91SAM7/gpt_lld.c
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* @brief AT91SAM7 GPT subsystem low level driver source.
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*
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* @addtogroup GPT
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* @{
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*/
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#include "ch.h"
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#include "hal.h"
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#if HAL_USE_GPT || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/**
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* @brief GPTD1 driver identifier.
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* @note The driver GPTD1 allocates the complex timer TC0 when enabled.
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*/
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#if AT91_GPT_USE_TC0 || defined(__DOXYGEN__)
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GPTDriver GPTD1;
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#endif
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/**
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* @brief GPTD2 driver identifier.
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* @note The driver GPTD2 allocates the timer TC1 when enabled.
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*/
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#if AT91_GPT_USE_TC1 || defined(__DOXYGEN__)
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GPTDriver GPTD2;
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#endif
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/**
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* @brief GPTD3 driver identifier.
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* @note The driver GPTD3 allocates the timer TC2 when enabled.
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*/
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#if AT91_GPT_USE_TC2 || defined(__DOXYGEN__)
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GPTDriver GPTD3;
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#endif
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/*===========================================================================*/
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/* Driver local variables and types. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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/**
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* @brief Shared IRQ handler.
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*
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* @param[in] gptp pointer to a @p GPTDriver object
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*/
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static void gpt_lld_serve_interrupt(GPTDriver *gptp) {
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// Read the status to clear the interrupts
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{ uint32_t isr = gptp->tc->TC_SR; (void) isr; }
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// Do the callback
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gptp->config->callback(gptp);
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}
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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#if AT91_GPT_USE_TC0
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/**
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* @brief TC1 interrupt handler.
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*
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* @isr
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*/
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CH_IRQ_HANDLER(TC0_IRQHandler) {
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CH_IRQ_PROLOGUE();
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gpt_lld_serve_interrupt(&GPTD1);
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AT91C_BASE_AIC->AIC_EOICR = 0;
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CH_IRQ_EPILOGUE();
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}
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#endif /* AT91_GPT_USE_TC0 */
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#if AT91_GPT_USE_TC1
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/**
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* @brief TC1 interrupt handler.
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*
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* @isr
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*/
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CH_IRQ_HANDLER(TC1_IRQHandler) {
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CH_IRQ_PROLOGUE();
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gpt_lld_serve_interrupt(&GPTD2);
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AT91C_BASE_AIC->AIC_EOICR = 0;
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CH_IRQ_EPILOGUE();
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}
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#endif /* AT91_GPT_USE_TC1 */
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#if AT91_GPT_USE_TC2
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/**
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* @brief TC1 interrupt handler.
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*
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* @isr
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*/
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CH_IRQ_HANDLER(TC2_IRQHandler) {
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CH_IRQ_PROLOGUE();
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gpt_lld_serve_interrupt(&GPTD2);
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AT91C_BASE_AIC->AIC_EOICR = 0;
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CH_IRQ_EPILOGUE();
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}
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}
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#endif /* AT91_GPT_USE_TC2 */
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/**
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* @brief Low level GPT driver initialization.
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*
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* @notapi
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*/
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void gpt_lld_init(void) {
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#if AT91_GPT_USE_TC0
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AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC0); // Turn on the power
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GPTD1.tc = AT91C_BASE_TC0;
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gptObjectInit(&GPTD1);
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gpt_lld_stop(&GPTD1); // Make sure it is disabled
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AIC_ConfigureIT(AT91C_ID_TC0, AT91C_AIC_SRCTYPE_HIGH_LEVEL | AT91_GPT_TC0_IRQ_PRIORITY, TC0_IRQHandler);
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AIC_EnableIT(AT91C_ID_TC0);
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#endif
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#if AT91_GPT_USE_TC1
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AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1); // Turn on the power
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GPTD2.tc = AT91C_BASE_TC1;
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gptObjectInit(&GPTD2);
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gpt_lld_stop(&GPTD2); // Make sure it is disabled
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AIC_ConfigureIT(AT91C_ID_TC1, AT91C_AIC_SRCTYPE_HIGH_LEVEL | AT91_GPT_TC1_IRQ_PRIORITY, TC1_IRQHandler);
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AIC_EnableIT(AT91C_ID_TC1);
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#endif
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#if AT91_GPT_USE_TC2
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AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC2); // Turn on the power
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GPTD3.tc = AT91C_BASE_TC2;
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gptObjectInit(&GPTD3);
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gpt_lld_stop(&GPTD3); // Make sure it is disabled
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AIC_ConfigureIT(AT91C_ID_TC2, AT91C_AIC_SRCTYPE_HIGH_LEVEL | AT91_GPT_TC2_IRQ_PRIORITY, TC2_IRQHandler);
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AIC_EnableIT(AT91C_ID_TC2);
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#endif
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}
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/**
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* @brief Configures and activates the GPT peripheral.
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*
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* @param[in] gptp pointer to the @p GPTDriver object
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*
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* @notapi
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*/
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void gpt_lld_start(GPTDriver *gptp) {
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uint32_t cmr, bmr;
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bmr = *AT91C_TCB_BMR;
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cmr = (AT91C_TC_ASWTRG_CLEAR | AT91C_TC_ACPC_CLEAR | AT91C_TC_ACPA_SET |
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AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO);
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// Calculate clock
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switch(gptp->config->clocksource) {
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case GPT_CLOCK_MCLK:
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switch(gptp->config->frequency) {
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case MCK/2: cmr |= AT91C_TC_CLKS_TIMER_DIV1_CLOCK; break;
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case MCK/8: cmr |= AT91C_TC_CLKS_TIMER_DIV2_CLOCK; break;
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case MCK/32: cmr |= AT91C_TC_CLKS_TIMER_DIV3_CLOCK; break;
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case MCK/128: cmr |= AT91C_TC_CLKS_TIMER_DIV4_CLOCK; break;
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case MCK/1024: cmr |= AT91C_TC_CLKS_TIMER_DIV5_CLOCK; break;
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default:
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chDbgAssert(TRUE, "gpt_lld_start(), #1", "invalid frequency");
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cmr |= AT91C_TC_CLKS_TIMER_DIV5_CLOCK;
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break;
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}
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break;
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case GPT_CLOCK_FREQUENCY:
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/* The mode and period will be calculated when the timer is started */
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cmr |= AT91C_TC_CLKS_TIMER_DIV5_CLOCK;
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break;
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case GPT_CLOCK_RE_TCLK0:
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case GPT_CLOCK_FE_TCLK0:
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if ((gptp->config->clocksource & 1)) cmr |= AT91C_TC_CLKI;
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cmr |= AT91C_TC_CLKS_XC0;
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#if AT91_GPT_USE_TC0
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if (gptp == &GPTD1) bmr = (bmr & ~AT91C_TCB_TC0XC0S) | AT91C_TCB_TC0XC0S_TCLK0;
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#endif
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break;
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case GPT_CLOCK_RE_TCLK1:
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case GPT_CLOCK_FE_TCLK1:
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if ((gptp->config->clocksource & 1)) cmr |= AT91C_TC_CLKI;
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cmr |= AT91C_TC_CLKS_XC1;
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#if AT91_GPT_USE_TC1
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if (gptp == &GPTD2) bmr = (bmr & ~AT91C_TCB_TC1XC1S) | AT91C_TCB_TC1XC1S_TCLK1;
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#endif
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break;
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case GPT_CLOCK_RE_TCLK2:
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case GPT_CLOCK_FE_TCLK2:
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if ((gptp->config->clocksource & 1)) cmr |= AT91C_TC_CLKI;
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cmr |= AT91C_TC_CLKS_XC2;
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#if AT91_GPT_USE_TC2
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if (gptp == &GPTD3) bmr = (bmr & ~AT91C_TCB_TC2XC2S) | AT91C_TCB_TC2XC2S_TCLK2;
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#endif
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break;
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case GPT_CLOCK_RE_TC0:
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case GPT_CLOCK_FE_TC0:
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if ((gptp->config->clocksource & 1)) cmr |= AT91C_TC_CLKI;
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#if AT91_GPT_USE_TC0
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if (gptp == &GPTD1) {
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chDbgAssert(TRUE, "gpt_lld_start(), #2", "invalid clock");
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cmr |= AT91C_TC_CLKS_XC0;
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bmr = (bmr & ~AT91C_TCB_TC0XC0S) | AT91C_TCB_TC0XC0S_NONE;
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break;
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}
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#endif
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#if AT91_GPT_USE_TC1
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if (gptp == &GPTD2) {
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cmr |= AT91C_TC_CLKS_XC1;
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bmr = (bmr & ~AT91C_TCB_TC1XC1S) | AT91C_TCB_TC1XC1S_TIOA0;
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break;
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}
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#endif
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#if AT91_GPT_USE_TC2
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if (gptp == &GPTD3) {
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cmr |= AT91C_TC_CLKS_XC2;
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bmr = (bmr & ~AT91C_TCB_TC2XC2S) | AT91C_TCB_TC2XC2S_TIOA0;
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break;
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}
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#endif
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chDbgAssert(TRUE, "gpt_lld_start(), #3", "invalid GPT device");
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cmr |= AT91C_TC_CLKS_TIMER_DIV5_CLOCK;
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break;
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case GPT_CLOCK_RE_TC1:
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case GPT_CLOCK_FE_TC1:
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if ((gptp->config->clocksource & 1)) cmr |= AT91C_TC_CLKI;
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#if AT91_GPT_USE_TC0
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if (gptp == &GPTD1) {
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cmr |= AT91C_TC_CLKS_XC0;
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bmr = (bmr & ~AT91C_TCB_TC0XC0S) | AT91C_TCB_TC0XC0S_TIOA1;
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break;
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}
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#endif
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#if AT91_GPT_USE_TC1
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if (gptp == &GPTD2) {
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chDbgAssert(TRUE, "gpt_lld_start(), #4", "invalid clock");
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cmr |= AT91C_TC_CLKS_XC1;
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bmr = (bmr & ~AT91C_TCB_TC1XC1S) | AT91C_TCB_TC1XC1S_NONE;
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break;
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}
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#endif
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#if AT91_GPT_USE_TC2
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if (gptp == &GPTD3) {
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cmr |= AT91C_TC_CLKS_XC2;
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bmr = (bmr & ~AT91C_TCB_TC2XC2S) | AT91C_TCB_TC2XC2S_TIOA1;
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break;
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}
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#endif
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chDbgAssert(TRUE, "gpt_lld_start(), #5", "invalid GPT device");
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cmr |= AT91C_TC_CLKS_TIMER_DIV5_CLOCK;
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break;
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case GPT_CLOCK_RE_TC2:
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case GPT_CLOCK_FE_TC2:
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if ((gptp->config->clocksource & 1)) cmr |= AT91C_TC_CLKI;
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#if AT91_GPT_USE_TC0
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if (gptp == &GPTD1) {
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cmr |= AT91C_TC_CLKS_XC0;
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bmr = (bmr & ~AT91C_TCB_TC0XC0S) | AT91C_TCB_TC0XC0S_TIOA2;
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break;
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}
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#endif
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#if AT91_GPT_USE_TC1
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if (gptp == &GPTD2) {
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cmr |= AT91C_TC_CLKS_XC1;
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bmr = (bmr & ~AT91C_TCB_TC1XC1S) | AT91C_TCB_TC1XC1S_TIOA2;
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break;
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}
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#endif
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#if AT91_GPT_USE_TC2
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if (gptp == &GPTD3) {
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chDbgAssert(TRUE, "gpt_lld_start(), #6", "invalid clock");
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cmr |= AT91C_TC_CLKS_XC2;
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bmr = (bmr & ~AT91C_TCB_TC2XC2S) | AT91C_TCB_TC2XC2S_NONE;
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break;
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}
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#endif
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chDbgAssert(TRUE, "gpt_lld_start(), #7", "invalid GPT device");
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cmr |= AT91C_TC_CLKS_TIMER_DIV5_CLOCK;
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break;
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default:
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chDbgAssert(TRUE, "gpt_lld_start(), #8", "invalid clock");
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cmr |= AT91C_TC_CLKS_TIMER_DIV5_CLOCK;
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break;
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}
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// Calculate clock gating
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chDbgAssert(gptp->config->clockgate == GPT_GATE_NONE || gptp->config->clockgate == GPT_GATE_TCLK0
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|| gptp->config->clockgate == GPT_GATE_TCLK1 || gptp->config->clockgate == GPT_GATE_TCLK2
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, "gpt_lld_start(), #9", "invalid clockgate");
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cmr |= ((uint32_t)(gptp->config->clockgate & 0x03)) << 4; // special magic numbers here
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// Calculate triggers
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chDbgAssert(gptp->config->trigger == GPT_TRIGGER_NONE
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|| gptp->config->trigger == GPT_TRIGGER_RE_TIOB || gptp->config->trigger == GPT_TRIGGER_FE_TIOB || gptp->config->trigger == GPT_TRIGGER_BE_TIOB
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|| gptp->config->trigger == GPT_TRIGGER_RE_TCLK0 || gptp->config->trigger == GPT_TRIGGER_FE_TCLK0 || gptp->config->trigger == GPT_TRIGGER_BE_TCLK0
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|| gptp->config->trigger == GPT_TRIGGER_RE_TCLK1 || gptp->config->trigger == GPT_TRIGGER_FE_TCLK1 || gptp->config->trigger == GPT_TRIGGER_BE_TCLK1
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|| gptp->config->trigger == GPT_TRIGGER_RE_TCLK2 || gptp->config->trigger == GPT_TRIGGER_FE_TCLK2 || gptp->config->trigger == GPT_TRIGGER_BE_TCLK2
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, "gpt_lld_start(), #10", "invalid trigger");
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cmr |= ((uint32_t)(gptp->config->trigger & 0x03)) << 10; // special magic numbers here
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cmr |= ((uint32_t)(gptp->config->trigger & 0x30)) << (8-4); // special magic numbers here
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/* Set everything up but disabled */
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gptp->tc->TC_CCR = AT91C_TC_CLKDIS;
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gptp->tc->TC_IDR = 0xFFFFFFFF;
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gptp->tc->TC_CMR = cmr;
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gptp->tc->TC_RC = 65535;
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gptp->tc->TC_RA = 32768;
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*AT91C_TCB_BMR = bmr;
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cmr = gptp->tc->TC_SR; // Clear any pending interrupts
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}
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/**
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* @brief Deactivates the GPT peripheral.
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*
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* @param[in] gptp pointer to the @p GPTDriver object
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*
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* @notapi
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*/
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void gpt_lld_stop(GPTDriver *gptp) {
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gptp->tc->TC_CCR = AT91C_TC_CLKDIS;
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gptp->tc->TC_IDR = 0xFFFFFFFF;
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{ uint32_t isr = gptp->tc->TC_SR; (void)isr; }
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}
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/**
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* @brief Starts the timer in continuous mode.
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*
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* @param[in] gptp pointer to the @p GPTDriver object
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* @param[in] interval period in ticks
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*
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* @notapi
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*/
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void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) {
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gpt_lld_change_interval(gptp, interval);
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if (gptp->state == GPT_ONESHOT)
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gptp->tc->TC_CMR |= AT91C_TC_CPCDIS;
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else
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gptp->tc->TC_CMR &= ~AT91C_TC_CPCDIS;
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gptp->tc->TC_CCR = AT91C_TC_CLKEN|AT91C_TC_SWTRG;
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if (gptp->config->callback)
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gptp->tc->TC_IER = AT91C_TC_CPCS|AT91C_TC_COVFS;
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}
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/**
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* @brief Stops the timer.
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*
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* @param[in] gptp pointer to the @p GPTDriver object
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*
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* @notapi
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*/
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void gpt_lld_stop_timer(GPTDriver *gptp) {
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gptp->tc->TC_CCR = AT91C_TC_CLKDIS;
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gptp->tc->TC_IDR = 0xFFFFFFFF;
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{ uint32_t isr = gptp->tc->TC_SR; (void)isr; }
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}
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/**
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* @brief Changes the interval of GPT peripheral.
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* @details This function changes the interval of a running GPT unit.
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* @pre The GPT unit must have been activated using @p gptStart().
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* @pre The GPT unit must have been running in continuous mode using
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* @p gptStartContinuous().
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* @post The GPT unit interval is changed to the new value.
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* @note The function has effect at the next cycle start.
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*
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* @param[in] gptp pointer to a @p GPTDriver object
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* @param[in] interval new cycle time in timer ticks
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* @notapi
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*/
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void gpt_lld_change_interval(GPTDriver *gptp, gptcnt_t interval) {
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if (gptp->config->clocksource == GPT_CLOCK_FREQUENCY) {
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uint32_t rc, cmr;
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// Reset the timer to the (possibly) new frequency value
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rc = (MCK/2)/gptp->config->frequency;
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if (rc < (0x10000<<0)) {
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cmr = AT91C_TC_CLKS_TIMER_DIV1_CLOCK;
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} else if (rc < (0x10000<<2)) {
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rc >>= 2;
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cmr = AT91C_TC_CLKS_TIMER_DIV2_CLOCK;
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} else if (rc < (0x10000<<4)) {
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rc >>= 4;
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cmr = AT91C_TC_CLKS_TIMER_DIV3_CLOCK;
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} else if (rc < (0x10000<<6)) {
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rc >>= 6;
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cmr = AT91C_TC_CLKS_TIMER_DIV4_CLOCK;
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} else {
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rc >>= 9;
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cmr = AT91C_TC_CLKS_TIMER_DIV5_CLOCK;
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|
}
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|
gptp->tc->TC_CMR = (gptp->tc->TC_CMR & ~AT91C_TC_CLKS) | cmr;
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|
gptp->tc->TC_RC = rc;
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|
gptp->tc->TC_RA = rc/2;
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|
} else {
|
|
gptp->tc->TC_RC = interval;
|
|
gptp->tc->TC_RA = interval/2;
|
|
}
|
|
}
|
|
|
|
/**
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|
* @brief Starts the timer in one shot mode and waits for completion.
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|
* @details This function specifically polls the timer waiting for completion
|
|
* in order to not have extra delays caused by interrupt servicing,
|
|
* this function is only recommended for short delays.
|
|
*
|
|
* @param[in] gptp pointer to the @p GPTDriver object
|
|
* @param[in] interval time interval in ticks
|
|
*
|
|
* @notapi
|
|
*/
|
|
void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) {
|
|
|
|
gpt_lld_change_interval(gptp, interval);
|
|
gptp->tc->TC_CMR |= AT91C_TC_CPCDIS;
|
|
gptp->tc->TC_CCR = AT91C_TC_CLKEN|AT91C_TC_SWTRG;
|
|
while (!(gptp->tc->TC_SR & (AT91C_TC_CPCS|AT91C_TC_COVFS)));
|
|
}
|
|
|
|
#endif /* HAL_USE_GPT */
|
|
|
|
/** @} */
|