mirror of
https://github.com/portapack-mayhem/mayhem-firmware.git
synced 2024-12-13 11:44:31 +00:00
412 lines
9.4 KiB
C++
412 lines
9.4 KiB
C++
/*
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* Copyright (C) 2014 Jared Boone, ShareBrained Technology, Inc.
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*
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* This file is part of PortaPack.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 51 Franklin Street,
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* Boston, MA 02110-1301, USA.
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*/
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#ifndef __SI5351_H__
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#define __SI5351_H__
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#include <cstdint>
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#include <array>
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#include <algorithm>
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#include "ch.h"
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#include "hal.h"
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#include "i2c_pp.hpp"
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namespace si5351 {
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namespace Register {
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enum {
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DeviceStatus = 0,
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InterruptStatusSticky = 1,
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InterruptStatusMask = 2,
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OutputEnableControl = 3,
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OEBPinEnableControlMask = 9,
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PLLInputSource = 15,
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CLKControl_Base = 16,
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CLKControl0 = 16,
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CLKControl1 = 17,
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CLKControl2 = 18,
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CLKControl3 = 19,
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CLKControl4 = 20,
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CLKControl5 = 21,
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CLKControl6 = 22,
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CLKControl7 = 23,
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CLK3_0DisableState = 24,
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CLK7_4DisableState = 25,
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MultisynthNAParameters_Base = 26,
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MultisynthNBParameters_Base = 34,
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Multisynth0Parameters_Base = 42,
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Multisynth1Parameters_Base = 50,
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Multisynth2Parameters_Base = 58,
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Multisynth3Parameters_Base = 66,
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Multisynth4Parameters_Base = 74,
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Multisynth5Parameters_Base = 82,
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Multisynth6Parameters = 90,
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Multisynth7Parameters = 91,
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Clock6And7OutputDivider = 92,
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SpreadSpectrumParameters_Base = 149,
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VCXOParameters_Base = 162,
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CLKInitialPhaseOffset_Base = 165,
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PLLReset = 177,
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CrystalInternalLoadCapacitance = 183,
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FanoutEnable = 187,
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};
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}
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namespace DeviceStatus {
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using Type = uint8_t;
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enum {
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REVID_Mask = (0b11 << 0),
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LOS_Mask = (1 << 4),
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LOS_ValidClockAtCLKIN = (0 << 4),
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LOS_LossOfSignalAtCLKIN = (1 << 4),
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LOL_A_Mask = (1 << 5),
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LOL_A_PLLALocked = (0 << 5),
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LOL_A_PLLAUnlocked = (1 << 5),
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LOL_B_Mask = (1 << 6),
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LOL_B_PLLBLocked = (0 << 6),
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LOL_B_PLLBUnlocked = (1 << 6),
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SYS_INIT_Mask = (1 << 7),
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SYS_INIT_Complete = (0 << 7),
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SYS_INIT_Initializing = (1 << 7),
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};
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}
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namespace ClockControl {
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using Type = uint8_t;
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enum {
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CLK_IDRV_Mask = (0b11 << 0),
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CLK_IDRV_2mA = (0b00 << 0),
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CLK_IDRV_4mA = (0b01 << 0),
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CLK_IDRV_6mA = (0b10 << 0),
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CLK_IDRV_8mA = (0b11 << 0),
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CLK_SRC_Mask = (0b11 << 2),
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CLK_SRC_XTAL = (0b00 << 2),
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CLK_SRC_CLKIN = (0b01 << 2),
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CLK_SRC_MS_Group = (0b10 << 2),
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CLK_SRC_MS_Self = (0b11 << 2),
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CLK_INV_Mask = (1 << 4),
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CLK_INV_Normal = (0 << 4),
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CLK_INV_Invert = (1 << 4),
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MS_SRC_Mask = (1 << 5),
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MS_SRC_PLLA = (0 << 5),
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MS_SRC_PLLB = (1 << 5),
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MS_INT_Mask = (1 << 6),
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MS_INT_Fractional = (0 << 6),
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MS_INT_Integer = (1 << 6),
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CLK_PDN_Mask = (1 << 7),
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CLK_PDN_Power_On = (0 << 7),
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CLK_PDN_Power_Off = (1 << 7),
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};
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}
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using ClockControls = std::array<ClockControl::Type, 8>;
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namespace CrystalInternalLoadCapacitance {
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using Type = uint8_t;
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enum {
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XTAL_CL_Mask = (0b11 << 6),
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XTAL_CL_6pF = (0b01 << 6),
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XTAL_CL_8pF = (0b10 << 6),
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XTAL_CL_10pF = (0b11 << 6),
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};
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}
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namespace PLLInputSource {
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using Type = uint8_t;
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enum {
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PLLA_Source_Mask = (1 << 2),
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PLLA_Source_XTAL = (0 << 2),
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PLLA_Source_CLKIN = (1 << 2),
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PLLB_Source_Mask = (1 << 3),
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PLLB_Source_XTAL = (0 << 3),
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PLLB_Source_CLKIN = (1 << 3),
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CLKIN_Div_Mask = (0b11 << 6),
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CLKIN_Div1 = (0b00 << 6),
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CLKIN_Div2 = (0b01 << 6),
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CLKIN_Div4 = (0b10 << 6),
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CLKIN_Div8 = (0b11 << 6),
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};
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}
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struct Inputs {
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const uint32_t f_xtal;
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const uint32_t f_clkin;
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const uint32_t clkin_div;
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constexpr uint32_t f_clkin_out() {
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return f_clkin / clkin_div;
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}
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};
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using PLLReg = std::array<uint8_t, 9>;
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struct PLL {
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const uint32_t f_in;
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const uint32_t a;
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const uint32_t b;
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const uint32_t c;
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constexpr uint32_t f_vco() {
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return f_in * (a + (float)b / (float)c);
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}
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constexpr uint32_t p1() {
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return 128 * a + (uint32_t)(128 * (float)b / (float)c) - 512;
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}
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constexpr uint32_t p2() {
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return 128 * b - c * (uint32_t)(128 * (float)b / (float)c);
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}
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constexpr uint32_t p3() {
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return c;
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}
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constexpr PLLReg reg(const uint8_t pll_n) {
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return {
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uint8_t(26 + (pll_n * 8)),
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uint8_t((p3() >> 8) & 0xff),
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uint8_t((p3() >> 0) & 0xff),
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uint8_t((p1() >> 16) & 0x03),
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uint8_t((p1() >> 8) & 0xff),
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uint8_t((p1() >> 0) & 0xff),
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uint8_t(
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(((p3() >> 16) & 0x0f) << 4)
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| ((p2() >> 16) & 0x0f)
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),
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uint8_t((p2() >> 8) & 0xff),
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uint8_t((p2() >> 0) & 0xff),
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};
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}
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};
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using MultisynthFractionalReg = std::array<uint8_t, 9>;
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struct MultisynthFractional {
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const uint32_t f_src;
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const uint32_t a;
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const uint32_t b;
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const uint32_t c;
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const uint32_t r_div;
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constexpr uint32_t p1() {
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return 128 * a + (uint32_t)(128 * (float)b / (float)c) - 512;
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}
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constexpr uint32_t p2() {
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return 128 * b - c * (uint32_t)(128 * (float)b / (float)c);
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}
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constexpr uint32_t p3() {
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return c;
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}
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constexpr uint32_t f_out() {
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return f_src / (a + (float)b / (float)c) / (1 << r_div);
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}
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constexpr MultisynthFractionalReg reg(const uint8_t multisynth_n) {
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return {
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uint8_t(42 + (multisynth_n * 8)),
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uint8_t((p3() >> 8) & 0xFF),
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uint8_t((p3() >> 0) & 0xFF),
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uint8_t((r_div << 4) | (0 << 2) | ((p1() >> 16) & 0x3)),
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uint8_t((p1() >> 8) & 0xFF),
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uint8_t((p1() >> 0) & 0xFF),
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uint8_t((((p3() >> 16) & 0xF) << 4) | (((p2() >> 16) & 0xF) << 0)),
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uint8_t((p2() >> 8) & 0xFF),
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uint8_t((p2() >> 0) & 0xFF)
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};
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}
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};
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struct MultisynthInteger {
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const uint32_t f_src;
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const uint32_t a;
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const uint32_t r_div;
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constexpr uint8_t p1() {
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return a;
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}
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constexpr uint32_t f_out() {
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return f_src / a / (1 << r_div);
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}
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};
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using Multisynth6And7Reg = std::array<uint8_t, 4>;
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constexpr Multisynth6And7Reg ms6_7_reg(
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const MultisynthInteger& ms6,
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const MultisynthInteger& ms7
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) {
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return {
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Register::Multisynth6Parameters,
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uint8_t(ms6.p1() & 0xff),
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uint8_t(ms7.p1() & 0xff),
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uint8_t(((ms7.r_div & 7) << 4) | ((ms6.r_div & 7) << 0)),
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};
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}
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class Si5351 {
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public:
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using regvalue_t = uint8_t;
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constexpr Si5351(I2C& bus, I2C::address_t address) :
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_clock_control({
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ClockControl::CLK_PDN_Power_Off, ClockControl::CLK_PDN_Power_Off,
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ClockControl::CLK_PDN_Power_Off, ClockControl::CLK_PDN_Power_Off,
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ClockControl::CLK_PDN_Power_Off, ClockControl::CLK_PDN_Power_Off,
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ClockControl::CLK_PDN_Power_Off, ClockControl::CLK_PDN_Power_Off
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}),
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_bus(bus),
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_address(address),
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_output_enable(0x00)
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{
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}
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void reset();
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uint8_t device_status() {
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return read_register(Register::DeviceStatus);
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}
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void wait_for_device_ready() {
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while(device_status() & 0x80);
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}
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void enable_fanout() {
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write_register(Register::FanoutEnable, 0b11010000);
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}
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void reset_plls() {
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write_register(Register::PLLReset, 0xa0);
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}
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regvalue_t read_register(const uint8_t reg);
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template<size_t N>
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void write(const std::array<uint8_t, N>& values) {
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_bus.transmit(_address, values.data(), values.size());
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}
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void write_register(const uint8_t reg, const regvalue_t value) {
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write(std::array<uint8_t, 2>{
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reg, value
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});
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}
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void write(const size_t ms_number, const MultisynthFractional& config) {
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write(config.reg(ms_number));
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}
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void set_ms_frequency(
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const size_t ms_number,
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const uint32_t frequency,
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const uint32_t vco_frequency,
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const size_t r_div
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);
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void set_crystal_internal_load_capacitance(const CrystalInternalLoadCapacitance::Type xtal_cl) {
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write_register(Register::CrystalInternalLoadCapacitance, xtal_cl);
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}
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void set_pll_input_sources(const PLLInputSource::Type value) {
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write_register(Register::PLLInputSource, value);
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}
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void enable_output_mask(const uint8_t mask) {
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_output_enable |= mask;
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update_output_enable_control();
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}
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void enable_output(const size_t n) {
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enable_output_mask(1 << n);
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}
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void disable_output_mask(const uint8_t mask) {
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_output_enable &= ~mask;
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update_output_enable_control();
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}
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void disable_output(const size_t n) {
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disable_output_mask(1 << n);
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}
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void set_clock_control(const ClockControls& clock_control) {
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_clock_control = clock_control;
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update_all_clock_control();
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}
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void enable_clock(const size_t n) {
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_clock_control[n] &= ~ClockControl::CLK_PDN_Mask;
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write_register(Register::CLKControl_Base + n, _clock_control[n]);
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}
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void disable_clock(const size_t n) {
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_clock_control[n] |= ClockControl::CLK_PDN_Mask;
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write_register(Register::CLKControl_Base + n, _clock_control[n]);
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}
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template<size_t N>
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void write_registers(const uint8_t reg, const std::array<uint8_t, N>& values) {
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std::array<uint8_t, N + 1> data;
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data[0] = reg;
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std::copy(values.cbegin(), values.cend(), data.begin() + 1);
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write(data);
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}
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private:
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std::array<uint8_t, 8> _clock_control;
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I2C& _bus;
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const I2C::address_t _address;
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uint8_t _output_enable;
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void update_output_enable_control() {
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write_register(Register::OutputEnableControl, ~_output_enable);
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}
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void update_all_clock_control() {
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write_registers(Register::CLKControl_Base, _clock_control);
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}
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};
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}
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#endif/*__SI5351_H__*/
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