mirror of
https://github.com/portapack-mayhem/mayhem-firmware.git
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293 lines
9.9 KiB
Plaintext
Executable File
293 lines
9.9 KiB
Plaintext
Executable File
/*
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ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @defgroup STM32F0xx_DRIVERS STM32F0xx Drivers
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* @details This section describes all the supported drivers on the STM32F0xx
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* platform and the implementation details of the single drivers.
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*
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* @ingroup platforms
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*/
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/**
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* @defgroup STM32F0xx_HAL STM32F0xx Initialization Support
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* @details The STM32F0xx HAL support is responsible for system initialization.
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*
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* @section stm32f0xx_hal_1 Supported HW resources
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* - PLL1.
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* - RCC.
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* - Flash.
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* .
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* @section stm32f0xx_hal_2 STM32F0xx HAL driver implementation features
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* - PLL startup and stabilization.
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* - Clock tree initialization.
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* - Clock source selection.
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* - Flash wait states initialization based on the selected clock options.
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* - SYSTICK initialization based on current clock and kernel required rate.
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* - DMA support initialization.
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* .
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* @ingroup STM32F0xx_DRIVERS
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*/
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/**
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* @defgroup STM32F0xx_ADC STM32F0xx ADC Support
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* @details The STM32F0xx ADC driver supports the ADC peripherals using DMA
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* channels for maximum performance.
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*
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* @section stm32f0xx_adc_1 Supported HW resources
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* - ADC1.
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* - DMA1.
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* .
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* @section stm32f0xx_adc_2 STM32F0xx ADC driver implementation features
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* - Clock stop for reduced power usage when the driver is in stop state.
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* - Streaming conversion using DMA for maximum performance.
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* - Programmable ADC interrupt priority level.
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* - Programmable DMA bus priority for each DMA channel.
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* - Programmable DMA interrupt priority for each DMA channel.
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* - DMA errors detection.
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* .
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* @ingroup STM32F0xx_DRIVERS
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*/
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/**
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* @defgroup STM32F0xx_EXT STM32F0xx EXT Support
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* @details The STM32F0xx EXT driver uses the EXTI peripheral.
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*
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* @section stm32f0xx_ext_1 Supported HW resources
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* - EXTI.
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* .
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* @section stm32f0xx_ext_2 STM32F0xx EXT driver implementation features
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* - Each EXTI channel can be independently enabled and programmed.
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* - Programmable EXTI interrupts priority level.
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* - Capability to work as event sources (WFE) rather than interrupt sources.
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* .
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* @ingroup STM32F0xx_DRIVERS
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*/
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/**
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* @defgroup STM32F0xx_GPT STM32F0xx GPT Support
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* @details The STM32F0xx GPT driver uses the TIMx peripherals.
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*
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* @section stm32f0xx_gpt_1 Supported HW resources
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* - TIM1.
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* - TIM2.
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* - TIM3.
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* .
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* @section stm32f0xx_gpt_2 STM32F0xx GPT driver implementation features
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* - Each timer can be independently enabled and programmed. Unused
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* peripherals are left in low power mode.
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* - Programmable TIMx interrupts priority level.
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* .
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* @ingroup STM32F0xx_DRIVERS
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*/
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/**
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* @defgroup STM32F0xx_ICU STM32F0xx ICU Support
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* @details The STM32F0xx ICU driver uses the TIMx peripherals.
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*
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* @section stm32f0xx_icu_1 Supported HW resources
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* - TIM1.
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* - TIM2.
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* - TIM3.
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* .
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* @section stm32f0xx_icu_2 STM32F0xx ICU driver implementation features
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* - Each timer can be independently enabled and programmed. Unused
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* peripherals are left in low power mode.
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* - Programmable TIMx interrupts priority level.
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* .
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* @ingroup STM32F0xx_DRIVERS
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*/
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/**
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* @defgroup STM32F0xx_PAL STM32F0xx PAL Support
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* @details The STM32F0xx PAL driver uses the GPIO peripherals.
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*
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* @section stm32f0xx_pal_1 Supported HW resources
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* - GPIOA.
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* - GPIOB.
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* - GPIOC.
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* - GPIOD.
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* - GPIOF.
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* .
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* @section stm32f0xx_pal_2 STM32F0xx PAL driver implementation features
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* The PAL driver implementation fully supports the following hardware
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* capabilities:
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* - 16 bits wide ports.
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* - Atomic set/reset functions.
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* - Atomic set+reset function (atomic bus operations).
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* - Output latched regardless of the pad setting.
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* - Direct read of input pads regardless of the pad setting.
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* .
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* @section stm32f0xx_pal_3 Supported PAL setup modes
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* The STM32F0xx PAL driver supports the following I/O modes:
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* - @p PAL_MODE_RESET.
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* - @p PAL_MODE_UNCONNECTED.
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* - @p PAL_MODE_INPUT.
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* - @p PAL_MODE_INPUT_PULLUP.
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* - @p PAL_MODE_INPUT_PULLDOWN.
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* - @p PAL_MODE_INPUT_ANALOG.
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* - @p PAL_MODE_OUTPUT_PUSHPULL.
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* - @p PAL_MODE_OUTPUT_OPENDRAIN.
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* - @p PAL_MODE_ALTERNATE (non standard).
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* .
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* Any attempt to setup an invalid mode is ignored.
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*
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* @section stm32f0xx_pal_4 Suboptimal behavior
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* The STM32F0xx GPIO is less than optimal in several areas, the limitations
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* should be taken in account while using the PAL driver:
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* - Pad/port toggling operations are not atomic.
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* - Pad/group mode setup is not atomic.
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* .
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* @ingroup STM32F0xx_DRIVERS
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*/
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/**
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* @defgroup STM32F0xx_PWM STM32F0xx PWM Support
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* @details The STM32F0xx PWM driver uses the TIMx peripherals.
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*
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* @section stm32f0xx_pwm_1 Supported HW resources
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* - TIM1.
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* - TIM2.
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* - TIM3.
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* .
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* @section stm32f0xx_pwm_2 STM32F0xx PWM driver implementation features
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* - Each timer can be independently enabled and programmed. Unused
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* peripherals are left in low power mode.
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* - Four independent PWM channels per timer.
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* - Programmable TIMx interrupts priority level.
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* .
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* @ingroup STM32F0xx_DRIVERS
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*/
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/**
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* @defgroup STM32F0xx_SERIAL STM32F0xx Serial Support
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* @details The STM32F0xx Serial driver uses the USART/UART peripherals in a
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* buffered, interrupt driven, implementation.
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*
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* @section stm32f0xx_serial_1 Supported HW resources
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* The serial driver can support any of the following hardware resources:
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* - USART1.
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* - USART2.
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* .
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* @section stm32f0xx_serial_2 STM32F0xx Serial driver implementation features
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* - Clock stop for reduced power usage when the driver is in stop state.
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* - Each UART/USART can be independently enabled and programmed. Unused
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* peripherals are left in low power mode.
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* - Fully interrupt driven.
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* - Programmable priority levels for each UART/USART.
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* .
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* @ingroup STM32F0xx_DRIVERS
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*/
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/**
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* @defgroup STM32F0xx_SPI STM32F0xx SPI Support
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* @details The SPI driver supports the STM32F0xx SPI peripherals using DMA
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* channels for maximum performance.
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*
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* @section stm32f0xx_spi_1 Supported HW resources
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* - SPI1.
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* - SPI2.
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* - DMA1.
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* .
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* @section stm32f0xx_spi_2 STM32F0xx SPI driver implementation features
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* - Clock stop for reduced power usage when the driver is in stop state.
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* - Each SPI can be independently enabled and programmed. Unused
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* peripherals are left in low power mode.
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* - Programmable interrupt priority levels for each SPI.
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* - DMA is used for receiving and transmitting.
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* - Programmable DMA bus priority for each DMA channel.
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* - Programmable DMA interrupt priority for each DMA channel.
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* - Programmable DMA error hook.
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* .
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* @ingroup STM32F0xx_DRIVERS
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*/
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/**
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* @defgroup STM32F0xx_UART STM32F0xx UART Support
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* @details The UART driver supports the STM32F0xx USART peripherals using DMA
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* channels for maximum performance.
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*
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* @section stm32f0xx_uart_1 Supported HW resources
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* The UART driver can support any of the following hardware resources:
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* - USART1.
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* - USART2.
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* - DMA1.
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* .
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* @section stm32f0xx_uart_2 STM32F0xx UART driver implementation features
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* - Clock stop for reduced power usage when the driver is in stop state.
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* - Each UART/USART can be independently enabled and programmed. Unused
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* peripherals are left in low power mode.
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* - Programmable interrupt priority levels for each UART/USART.
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* - DMA is used for receiving and transmitting.
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* - Programmable DMA bus priority for each DMA channel.
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* - Programmable DMA interrupt priority for each DMA channel.
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* - Programmable DMA error hook.
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* .
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* @ingroup STM32F0xx_DRIVERS
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*/
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/**
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* @defgroup STM32F0xx_PLATFORM_DRIVERS STM32F0xx Platform Drivers
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* @details Platform support drivers. Platform drivers do not implement HAL
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* standard driver templates, their role is to support platform
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* specific functionalities.
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*
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* @ingroup STM32F0xx_DRIVERS
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*/
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/**
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* @defgroup STM32F0xx_DMA STM32F0xx DMA Support
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* @details This DMA helper driver is used by the other drivers in order to
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* access the shared DMA resources in a consistent way.
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*
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* @section stm32f0xx_dma_1 Supported HW resources
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* The DMA driver can support any of the following hardware resources:
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* - DMA1.
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* - DMA2 (where present).
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* .
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* @section stm32f0xx_dma_2 STM32F0xx DMA driver implementation features
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* - Exports helper functions/macros to the other drivers that share the
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* DMA resource.
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* - Automatic DMA clock stop when not in use by any driver.
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* - DMA streams and interrupt vectors sharing among multiple drivers.
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* .
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* @ingroup STM32F0xx_PLATFORM_DRIVERS
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*/
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/**
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* @defgroup STM32F0xx_ISR STM32F0xx ISR Support
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* @details This ISR helper driver is used by the other drivers in order to
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* map ISR names to physical vector names.
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*
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* @ingroup STM32F0xx_PLATFORM_DRIVERS
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*/
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/**
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* @defgroup STM32F0xx_RCC STM32F0xx RCC Support
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* @details This RCC helper driver is used by the other drivers in order to
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* access the shared RCC resources in a consistent way.
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*
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* @section stm32f0xx_rcc_1 Supported HW resources
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* - RCC.
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* .
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* @section stm32f0xx_rcc_2 STM32F0xx RCC driver implementation features
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* - Peripherals reset.
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* - Peripherals clock enable.
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* - Peripherals clock disable.
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* .
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* @ingroup STM32F0xx_PLATFORM_DRIVERS
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*/
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