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259 lines
13 KiB
Plaintext
Executable File
259 lines
13 KiB
Plaintext
Executable File
/*
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
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2011,2012,2013 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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---
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A special exception to the GPL can be applied should you wish to distribute
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a combined work that includes ChibiOS/RT, without being obliged to provide
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the source code for any proprietary components. See the file exception.txt
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for full details of how and when the exception can be applied.
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*/
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/**
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* @defgroup ARMCMx ARM Cortex-Mx
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* @details ARM Cortex-Mx port for the GCC compiler.
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*
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* @section ARMCMx_INTRO Introduction
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* This port supports all the cores implementing the ARMv6-M and ARMv7-M
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* architectures.
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*
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* @section ARMCMx_MODES Kernel Modes
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* The Cortex-Mx port supports two distinct kernel modes:
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* - <b>Advanced Kernel</b> mode. In this mode the kernel only masks
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* interrupt sources with priorities below or equal to the
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* @p CORTEX_BASEPRI_KERNEL level. Higher priorities are not affected by
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* the kernel critical sections and can be used for fast interrupts.
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* This mode is not available in the ARMv6-M architecture which does not
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* support priority masking.
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* - <b>Compact Kernel</b> mode. In this mode the kernel handles IRQ priorities
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* in a simplified way, all interrupt sources are disabled when the kernel
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* enters into a critical zone and re-enabled on exit. This is simple and
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* adequate for most applications, this mode results in a more compact and
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* faster kernel.
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* .
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* The selection of the mode is performed using the port configuration option
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* @p CORTEX_SIMPLIFIED_PRIORITY. Apart from the different handling of
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* interrupts there are no other differences between the two modes. The
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* kernel API is exactly the same.
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*
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* @section ARMCMx_STATES_A System logical states in Compact Kernel mode
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* The ChibiOS/RT logical @ref system_states are mapped as follow in Compact
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* Kernel mode:
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* - <b>Init</b>. This state is represented by the startup code and the
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* initialization code before @p chSysInit() is executed. It has not a
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* special hardware state associated.
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* - <b>Normal</b>. This is the state the system has after executing
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* @p chSysInit(). In this state interrupts are enabled. The processor
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* is running in thread-privileged mode.
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* - <b>Suspended</b>. In this state the interrupt sources are globally
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* disabled. The processor is running in thread-privileged mode. In this
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* mode this state is not different from the <b>Disabled</b> state.
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* - <b>Disabled</b>. In this state the interrupt sources are globally
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* disabled. The processor is running in thread-privileged mode. In this
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* mode this state is not different from the <b>Suspended</b> state.
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* - <b>Sleep</b>. This state is entered with the execution of the specific
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* instruction @p <b>wfi</b>.
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* - <b>S-Locked</b>. In this state the interrupt sources are globally
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* disabled. The processor is running in thread-privileged mode.
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* - <b>I-Locked</b>. In this state the interrupt sources are globally
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* disabled. The processor is running in exception-privileged mode.
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* - <b>Serving Regular Interrupt</b>. In this state the interrupt sources are
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* not globally masked but only interrupts with higher priority can preempt
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* the current handler. The processor is running in exception-privileged
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* mode.
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* - <b>Serving Fast Interrupt</b>. Not implemented in compact kernel mode.
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* - <b>Serving Non-Maskable Interrupt</b>. The Cortex-Mx has a specific
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* asynchronous NMI vector and several synchronous fault vectors that can
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* be considered belonging to this category.
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* - <b>Halted</b>. Implemented as an infinite loop after globally masking all
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* the maskable interrupt sources. The ARM state is whatever the processor
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* was running when @p chSysHalt() was invoked.
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*
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* @section ARMCMx_STATES_B System logical states in Advanced Kernel mode
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* The ChibiOS/RT logical @ref system_states are mapped as follow in the
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* Advanced Kernel mode:
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* - <b>Init</b>. This state is represented by the startup code and the
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* initialization code before @p chSysInit() is executed. It has not a
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* special hardware state associated.
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* - <b>Normal</b>. This is the state the system has after executing
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* @p chSysInit(). In this state the ARM Cortex-Mx has the BASEPRI register
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* set at @p CORTEX_BASEPRI_USER level, interrupts are not masked. The
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* processor is running in thread-privileged mode.
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* - <b>Suspended</b>. In this state the interrupt sources are not globally
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* masked but the BASEPRI register is set to @p CORTEX_BASEPRI_KERNEL thus
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* masking any interrupt source with lower or equal priority. The processor
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* is running in thread-privileged mode.
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* - <b>Disabled</b>. Interrupt sources are globally masked. The processor
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* is running in thread-privileged mode.
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* - <b>Sleep</b>. This state is entered with the execution of the specific
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* instruction @p <b>wfi</b>.
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* - <b>S-Locked</b>. In this state the interrupt sources are not globally
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* masked but the BASEPRI register is set to @p CORTEX_BASEPRI_KERNEL thus
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* masking any interrupt source with lower or equal priority. The processor
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* is running in thread-privileged mode.
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* - <b>I-Locked</b>. In this state the interrupt sources are not globally
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* masked but the BASEPRI register is set to @p CORTEX_BASEPRI_KERNEL thus
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* masking any interrupt source with lower or equal priority. The processor
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* is running in exception-privileged mode.
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* - <b>Serving Regular Interrupt</b>. In this state the interrupt sources are
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* not globally masked but only interrupts with higher priority can preempt
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* the current handler. The processor is running in exception-privileged
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* mode.
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* - <b>Serving Fast Interrupt</b>. Fast interrupts are defined as interrupt
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* sources having higher priority level than the kernel
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* (@p CORTEX_BASEPRI_KERNEL). In this state is not possible to switch to
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* the I-Locked state because fast interrupts can preempt the kernel
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* critical zone.<br>
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* This state is not implemented in the ARMv6-M implementation because
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* priority masking is not present in this architecture.
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* - <b>Serving Non-Maskable Interrupt</b>. The Cortex-Mx has a specific
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* asynchronous NMI vector and several synchronous fault vectors that can
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* be considered belonging to this category.
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* - <b>Halted</b>. Implemented as an infinite loop after globally masking all
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* the maskable interrupt sources. The ARM state is whatever the processor
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* was running when @p chSysHalt() was invoked.
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* .
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* @section ARMCMx_NOTES ARM Cortex-Mx/GCC port notes
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* The ARM Cortex-Mx port is organized as follow:
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* - The @p main() function is invoked in thread-privileged mode.
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* - Each thread has a private process stack, the system has a single main
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* stack where all the interrupts and exceptions are processed.
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* - The threads are started in thread-privileged mode.
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* - Interrupt nesting and the other advanced core/NVIC features are supported.
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* - The Cortex-Mx port is perfectly generic, support for more devices can be
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* easily added by adding a subdirectory under <tt>./os/ports/GCC/ARMCMx</tt>
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* and giving it the name of the new device, then copy the files from another
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* device into the new directory and customize them for the new device.
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* .
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* @ingroup gcc
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*/
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/**
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* @defgroup ARMCMx_CONF Configuration Options
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* @details ARM Cortex-Mx Configuration Options. The ARMCMx port allows some
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* architecture-specific configurations settings that can be overridden
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* by redefining them in @p chconf.h. Usually there is no need to change
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* the default values.
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* - @p INT_REQUIRED_STACK, this value represent the amount of stack space used
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* by an interrupt handler between the @p extctx and @p intctx
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* structures.
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* - @p IDLE_THREAD_STACK_SIZE, stack area size to be assigned to the IDLE
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* thread. Usually there is no need to change this value unless inserting
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* code in the IDLE thread using the @p IDLE_LOOP_HOOK hook macro.
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* - @p CORTEX_PRIORITY_SYSTICK, priority of the SYSTICK handler.
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* - @p CORTEX_PRIORITY_PENDSV, priority of the PENDSV handler.
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* - @p CORTEX_ENABLE_WFI_IDLE, if set to @p TRUE enables the use of the
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* @p <b>wfi</b> instruction from within the idle loop. This option is
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* defaulted to FALSE because it can create problems with some debuggers.
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* Setting this option to TRUE reduces the system power requirements.
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* .
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* @section ARMCMx_CONF_1 ARMv6-M specific options
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* The following options are specific for the ARMv6-M architecture:
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* - @p CORTEX_ALTERNATE_SWITCH, when activated makes the OS use the PendSV
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* exception instead of NMI as preemption handler.
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* .
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* @section ARMCMx_CONF_2 ARMv7-M specific options
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* The following options are specific for the ARMv6-M architecture:
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* - @p CORTEX_PRIORITY_SVCALL, priority of the SVCALL handler.
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* - @p CORTEX_SIMPLIFIED_PRIORITY, when enabled activates the Compact kernel
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* mode.
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* .
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* @ingroup ARMCMx
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*/
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/**
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* @defgroup ARMCMx_CORE Core Port Implementation
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* @details ARM Cortex-Mx specific port code, structures and macros.
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*
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* @ingroup ARMCMx
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*/
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/**
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* @defgroup ARMCMx_V6M_CORE ARMv6-M Specific Implementation
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* @details ARMv6-M specific port code, structures and macros.
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*
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* @ingroup ARMCMx_CORE
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*/
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/**
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* @defgroup ARMCMx_V7M_CORE ARMv7-M Specific Implementation
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* @details ARMv7-M specific port code, structures and macros.
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*
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* @ingroup ARMCMx_CORE
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*/
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/**
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* @defgroup ARMCMx_STARTUP Startup Support
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* @details ChibiOS/RT provides its own generic startup file for the ARM
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* Cortex-Mx port.
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* Of course it is not mandatory to use it but care should be taken about the
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* startup phase details.
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*
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* @section ARMCMx_STARTUP_1 Startup Process
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* The startup process, as implemented, is the following:
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* -# Interrupts are masked globally.
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* -# The two stacks are initialized by assigning them the sizes defined in
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* the linker script (also known as scatter file).
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* -# The CPU state is switched to Privileged and the PSP stack is used.
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* -# An early initialization routine @p __early_init() is invoked, if the
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* symbol is not defined then an empty default routine is executed
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* (weak symbol).
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* -# DATA and BSS segments are initialized.
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* -# Constructors are invoked.
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* -# The @p main() function is invoked with no parameters.
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* -# Destructors are invoked.
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* -# A branch is performed to the weak symbol @p _default_exit(). The
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* default code is an endless empty loop.
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* .
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* @section ARMCMx_STARTUP_2 Expected linker symbols
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* The startup code starts at the symbol @p ResetHandler and expects the
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* following symbols to be defined in the linker script:
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* - @p __ram_end__, end of RAM.
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* - @p __main_stack_base__, main stack lower boundary.
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* - @p __main_stack_end__, main stack initial position.
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* - @p __process_stack_base__, process stack lower boundary.
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* - @p __process_stack_end__, process stack initial position.
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* - @p _textdata, address of the data segment source read only data.
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* - @p _data, start of the data segment.
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* - @p _edata, end of the data segment end location.
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* - @p _bss_start, start of the BSS.
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* - @p _bss_end, end of the BSS segment.
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* - @p __init_array_start, start of the constructors array.
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* - @p __init_array_end, end of the constructors array.
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* - @p __fini_array_start, start of the destructors array.
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* - @p __fini_array_end, end of the destructors array.
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* .
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* Additionally the kernel expects the following symbols:
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* - @p __main_thread_stack_base__, this symbol is required when the
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* stack checking is enabled (<tt>CH_DBG_ENABLE_STACK_CHECK==TRUE</tt>),
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* it is an alias of @p __process_stack_base__ in this port.
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* - @p __heap_base__ and @p __heap_end__, those symbols are required
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* if the memory core manager is enabled (<tt>CH_USE_MEMCORE==TRUE</tt>)
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* with a default core size set to zero (<tt>CH_MEMCORE_SIZE==0</tt>).
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* .
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* @ingroup ARMCMx
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*/
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/**
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* @defgroup ARMCMx_SPECIFIC Specific Implementations
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* @details Platform-specific port code.
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*
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* @ingroup ARMCMx
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*/
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