mirror of
https://github.com/portapack-mayhem/mayhem-firmware.git
synced 2024-12-16 13:08:13 +00:00
230 lines
6.1 KiB
C++
230 lines
6.1 KiB
C++
/*
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* Copyright (C) 2014 Jared Boone, ShareBrained Technology, Inc.
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*
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* This file is part of PortaPack.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 51 Franklin Street,
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* Boston, MA 02110-1301, USA.
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*/
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#include "cpld_max5.hpp"
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#include "jtag.hpp"
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#include <cstdint>
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#include <array>
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namespace cpld {
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namespace max5 {
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/* Enter ISP:
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* Ensures that the I/O pins transition smoothly from user mode to ISP
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* mode.
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*/
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void CPLD::enter_isp() {
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/* Enter ISP */
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shift_ir(0x2cc); //(199);
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jtag.runtest_tck(18003); // 1ms
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}
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void CPLD::exit_isp() {
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/* Exit ISP? Reset? */
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shift_ir(0x201); //166);
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jtag.runtest_tck(18003); // 1ms
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shift_ir(0x3FF);
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jtag.runtest_tck(18000); // 1ms
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}
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/* Sector erase:
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* Involves shifting in the instruction to erase the device and applying
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* an erase pulse or pulses. The erase pulse is automatically generated
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* internally by waiting in the run, test, or idle state for the
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* specified erase pulse time of 500 ms for the CFM block and 500 ms for
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* each sector of the user flash memory (UFM) block.
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*/
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void CPLD::bulk_erase() {
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erase_sector(0x0011);
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erase_sector(0x0001);
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erase_sector(0x0000);
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}
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bool CPLD::program(
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const std::array<uint16_t, 3328>& block_0,
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const std::array<uint16_t, 512>& block_1
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) {
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bulk_erase();
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/* Program:
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* involves shifting in the address, data, and program instruction and
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* generating the program pulse to program the flash cells. The program
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* pulse is automatically generated internally by waiting in the run/test/
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* idle state for the specified program pulse time of 75 μs. This process
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* is repeated for each address in the CFM and UFM blocks.
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*/
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program_block(0x0000, block_0);
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program_block(0x0001, block_1);
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const auto verify_ok = verify(block_0, block_1);
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if( verify_ok ) {
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/* Do "something". Not sure what, but it happens after verify. */
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/* Starts with a sequence the same as Program: Block 0. */
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/* Perhaps it is a write to tell the CPLD that the bitstream
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* verified OK, and it's OK to load and execute? And despite only
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* one bit changing, a write must be a multiple of a particular
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* length (64 bits)? */
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sector_select(0x0000);
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shift_ir(0x2F4); // Program
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jtag.runtest_tck(93); // 5 us
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/* TODO: Use data from cpld_block_0, with appropriate bit(s) changed */
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/* Perhaps this is the "ISP_DONE" bit? */
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jtag.shift_dr(16, block_0[0] & 0xfbff);
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jtag.runtest_tck(1800); // 100us
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jtag.shift_dr(16, block_0[1]);
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jtag.runtest_tck(1800); // 100us
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jtag.shift_dr(16, block_0[2]);
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jtag.runtest_tck(1800); // 100us
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jtag.shift_dr(16, block_0[3]);
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jtag.runtest_tck(1800); // 100us
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}
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return verify_ok;
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}
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bool CPLD::verify(
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const std::array<uint16_t, 3328>& block_0,
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const std::array<uint16_t, 512>& block_1
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) {
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/* Verify */
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const auto block_0_success = verify_block(0x0000, block_0);
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const auto block_1_success = verify_block(0x0001, block_1);
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return block_0_success && block_1_success;
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}
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void CPLD::sector_select(const uint16_t id) {
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shift_ir(0x203); // Sector select
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jtag.runtest_tck(93); // 5us
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jtag.shift_dr(13, id); // Sector ID
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}
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bool CPLD::idcode_ok() {
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shift_ir(Instruction::IDCODE);
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const auto idcode = jtag.shift_dr(32, 0);
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return (idcode == IDCODE);
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}
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std::array<uint16_t, 5> CPLD::read_silicon_id() {
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sector_select(0x0089);
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shift_ir(0x205);
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jtag.runtest_tck(93); // 5us
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std::array<uint16_t, 5> silicon_id;
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silicon_id[0] = jtag.shift_dr(16, 0xffff);
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silicon_id[1] = jtag.shift_dr(16, 0xffff);
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silicon_id[2] = jtag.shift_dr(16, 0xffff);
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silicon_id[3] = jtag.shift_dr(16, 0xffff);
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silicon_id[4] = jtag.shift_dr(16, 0xffff);
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return silicon_id;
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}
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/* Check ID:
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* The silicon ID is checked before any Program or Verify process. The
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* time required to read this silicon ID is relatively small compared to
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* the overall programming time.
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*/
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bool CPLD::silicon_id_ok() {
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const auto silicon_id = read_silicon_id();
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return (
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(silicon_id[0] == 0x8232) &&
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(silicon_id[1] == 0x2aa2) &&
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(silicon_id[2] == 0x4a82) &&
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(silicon_id[3] == 0x8c0c) &&
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(silicon_id[4] == 0x0000)
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);
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}
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void CPLD::erase_sector(const uint16_t id) {
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sector_select(id);
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shift_ir(0x2F2); // Erase pulse
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jtag.runtest_tck(9000003); // 500ms
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}
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void CPLD::program_block(
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const uint16_t id,
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const uint16_t* const data,
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const size_t count
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) {
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sector_select(id);
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shift_ir(0x2F4); // Program
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jtag.runtest_tck(93); // 5us
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for(size_t i=0; i<count; i++) {
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jtag.shift_dr(16, data[i]);
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jtag.runtest_tck(1800);
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}
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}
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bool CPLD::verify_block(
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const uint16_t id,
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const uint16_t* const data,
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const size_t count
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) {
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sector_select(id);
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shift_ir(0x205); // Read
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jtag.runtest_tck(93); // 5us
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bool success = true;
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for(size_t i=0; i<count; i++) {
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const auto from_device = jtag.shift_dr(16, 0xffff);
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if( (id == 0) && (i == 0) ) {
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// Account for bit that indicates bitstream is valid.
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if( (from_device & 0xfbff) != (data[i] & 0xfbff) ) {
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success = false;
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}
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} else {
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if( from_device != data[i] ) {
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success = false;
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}
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}
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}
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return success;
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}
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bool CPLD::is_blank_block(const uint16_t id, const size_t count) {
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sector_select(id);
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shift_ir(0x205); // Read
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jtag.runtest_tck(93); // 5us
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bool success = true;
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for(size_t i=0; i<count; i++) {
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const auto from_device = jtag.shift_dr(16, 0xffff);
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if( from_device != 0xffff ) {
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success = false;
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}
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}
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return success;
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}
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bool CPLD::is_blank() {
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const auto block_0_blank = is_blank_block(0x0000, 3328);
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const auto block_1_blank = is_blank_block(0x0001, 512);
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return block_0_blank && block_1_blank;
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}
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} /* namespace max5 */
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} /* namespace cpld */
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