mirror of
https://github.com/portapack-mayhem/mayhem-firmware.git
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219 lines
7.0 KiB
C
Executable File
219 lines
7.0 KiB
C
Executable File
/*
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ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file LPC11Uxx/hal_lld.h
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* @brief HAL subsystem low level driver header template.
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*
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* @addtogroup HAL
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* @{
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*/
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#ifndef _HAL_LLD_H_
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#define _HAL_LLD_H_
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#include "LPC11Uxx.h"
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#include "nvic.h"
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/**
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* @brief Defines the support for realtime counters in the HAL.
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*/
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#define HAL_IMPLEMENTS_COUNTERS FALSE
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/**
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* @brief Platform name.
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*/
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#define PLATFORM_NAME "LPC11Uxx"
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#define IRCOSCCLK 12000000 /**< High speed internal clock. */
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#define WDGOSCCLK 1600000 /**< Watchdog internal clock. */
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#define SYSPLLCLKSEL_IRCOSC 0 /**< Internal RC oscillator
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clock source. */
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#define SYSPLLCLKSEL_SYSOSC 1 /**< System oscillator clock
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source. */
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#define SYSMAINCLKSEL_IRCOSC 0 /**< Clock source is IRC. */
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#define SYSMAINCLKSEL_PLLIN 1 /**< Clock source is PLLIN. */
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#define SYSMAINCLKSEL_WDGOSC 2 /**< Clock source is WDGOSC. */
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#define SYSMAINCLKSEL_PLLOUT 3 /**< Clock source is PLLOUT. */
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/**
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* @brief System PLL clock source.
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*/
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#if !defined(LPC_PLLCLK_SOURCE) || defined(__DOXYGEN__)
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#define LPC_PLLCLK_SOURCE SYSPLLCLKSEL_SYSOSC
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#endif
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/**
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* @brief System PLL multiplier.
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* @note The value must be in the 1..32 range and the final frequency
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* must not exceed the CCO ratings.
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*/
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#if !defined(LPC_SYSPLL_MUL) || defined(__DOXYGEN__)
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#define LPC_SYSPLL_MUL 4
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#endif
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/**
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* @brief System PLL divider.
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* @note The value must be chosen between (2, 4, 8, 16).
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*/
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#if !defined(LPC_SYSPLL_DIV) || defined(__DOXYGEN__)
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#define LPC_SYSPLL_DIV 4
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#endif
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/**
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* @brief System main clock source.
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*/
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#if !defined(LPC_MAINCLK_SOURCE) || defined(__DOXYGEN__)
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#define LPC_MAINCLK_SOURCE SYSMAINCLKSEL_PLLOUT
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#endif
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/**
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* @brief AHB clock divider.
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* @note The value must be chosen between (1...255).
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*/
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#if !defined(LPC_SYSCLK_DIV) || defined(__DOXYGEN__)
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#define LPC_SYSABHCLK_DIV 1
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#endif
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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/**
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* @brief Calculated SYSOSCCTRL setting.
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*/
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#if (SYSOSCCLK < 20000000) || defined(__DOXYGEN__)
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#define LPC_SYSOSCCTRL 0
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#else
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#define LPC_SYSOSCCTRL 1
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#endif
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/**
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* @brief PLL input clock frequency.
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*/
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#if (LPC_PLLCLK_SOURCE == SYSPLLCLKSEL_SYSOSC) || defined(__DOXYGEN__)
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#define LPC_SYSPLLCLKIN SYSOSCCLK
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#elif LPC_PLLCLK_SOURCE == SYSPLLCLKSEL_IRCOSC
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#define LPC_SYSPLLCLKIN IRCOSCCLK
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#else
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#error "invalid LPC_PLLCLK_SOURCE clock source specified"
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#endif
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/**
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* @brief MSEL mask in SYSPLLCTRL register.
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*/
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#if (LPC_SYSPLL_MUL >= 1) && (LPC_SYSPLL_MUL <= 32) || defined(__DOXYGEN__)
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#define LPC_SYSPLLCTRL_MSEL (LPC_SYSPLL_MUL - 1)
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#else
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#error "LPC_SYSPLL_MUL out of range (1...32)"
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#endif
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/**
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* @brief PSEL mask in SYSPLLCTRL register.
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*/
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#if (LPC_SYSPLL_DIV == 2) || defined(__DOXYGEN__)
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#define LPC_SYSPLLCTRL_PSEL (0 << 5)
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#elif LPC_SYSPLL_DIV == 4
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#define LPC_SYSPLLCTRL_PSEL (1 << 5)
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#elif LPC_SYSPLL_DIV == 8
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#define LPC_SYSPLLCTRL_PSEL (2 << 5)
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#elif LPC_SYSPLL_DIV == 16
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#define LPC_SYSPLLCTRL_PSEL (3 << 5)
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#else
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#error "invalid LPC_SYSPLL_DIV value (2,4,8,16)"
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#endif
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/**
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* @brief CCP frequency.
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*/
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#define LPC_SYSPLLCCO (LPC_SYSPLLCLKIN * LPC_SYSPLL_MUL * \
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LPC_SYSPLL_DIV)
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#if (LPC_SYSPLLCCO < 156000000) || (LPC_SYSPLLCCO > 320000000)
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#error "CCO frequency out of the acceptable range (156...320)"
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#endif
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/**
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* @brief PLL output clock frequency.
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*/
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#define LPC_SYSPLLCLKOUT (LPC_SYSPLLCCO / LPC_SYSPLL_DIV)
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#if (LPC_MAINCLK_SOURCE == SYSMAINCLKSEL_IRCOSC) || defined(__DOXYGEN__)
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#define LPC_MAINCLK IRCOSCCLK
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#elif LPC_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLIN
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#define LPC_MAINCLK LPC_SYSPLLCLKIN
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#elif LPC_MAINCLK_SOURCE == SYSMAINCLKSEL_WDGOSC
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#define LPC_MAINCLK WDGOSCCLK
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#elif LPC_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT
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#define LPC_MAINCLK LPC_SYSPLLCLKOUT
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#else
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#error "invalid LPC_MAINCLK_SOURCE clock source specified"
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#endif
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/**
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* @brief AHB clock.
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*/
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#define LPC_SYSCLK (LPC_MAINCLK / LPC_SYSABHCLK_DIV)
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#if LPC_SYSCLK > 50000000
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#error "AHB clock frequency out of the acceptable range (50MHz max)"
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#endif
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/**
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* @brief Flash wait states.
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*/
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#if (LPC_SYSCLK <= 20000000) || defined(__DOXYGEN__)
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#define LPC_FLASHCFG_FLASHTIM 0
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#elif LPC_SYSCLK <= 40000000
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#define LPC_FLASHCFG_FLASHTIM 1
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#else
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#define LPC_FLASHCFG_FLASHTIM 2
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#endif
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver macros. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* External declarations. */
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/*===========================================================================*/
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#ifdef __cplusplus
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extern "C" {
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#endif
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void hal_lld_init(void);
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void lpc_clock_init(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _HAL_LLD_H_ */
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/** @} */
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