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https://github.com/portapack-mayhem/mayhem-firmware.git
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836 lines
19 KiB
C
Executable File
836 lines
19 KiB
C
Executable File
/*
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ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file STM32F30x/stm32_rcc.h
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* @brief RCC helper driver header.
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* @note This file requires definitions from the ST header file
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* @p stm32f30x.h.
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*
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* @addtogroup STM32F30x_RCC
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* @{
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*/
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#ifndef _STM32_RCC_
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#define _STM32_RCC_
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver macros. */
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/*===========================================================================*/
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/**
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* @name Generic RCC operations
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* @{
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*/
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/**
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* @brief Enables the clock of one or more peripheral on the APB1 bus.
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*
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* @param[in] mask APB1 peripherals mask
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableAPB1(mask, lp) { \
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RCC->APB1ENR |= (mask); \
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}
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/**
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* @brief Disables the clock of one or more peripheral on the APB1 bus.
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*
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* @param[in] mask APB1 peripherals mask
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccDisableAPB1(mask, lp) { \
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RCC->APB1ENR &= ~(mask); \
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}
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/**
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* @brief Resets one or more peripheral on the APB1 bus.
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*
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* @param[in] mask APB1 peripherals mask
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*
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* @api
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*/
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#define rccResetAPB1(mask) { \
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RCC->APB1RSTR |= (mask); \
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RCC->APB1RSTR = 0; \
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}
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/**
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* @brief Enables the clock of one or more peripheral on the APB2 bus.
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*
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* @param[in] mask APB2 peripherals mask
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableAPB2(mask, lp) { \
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RCC->APB2ENR |= (mask); \
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}
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/**
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* @brief Disables the clock of one or more peripheral on the APB2 bus.
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*
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* @param[in] mask APB2 peripherals mask
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccDisableAPB2(mask, lp) { \
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RCC->APB2ENR &= ~(mask); \
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}
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/**
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* @brief Resets one or more peripheral on the APB2 bus.
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*
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* @param[in] mask APB2 peripherals mask
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*
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* @api
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*/
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#define rccResetAPB2(mask) { \
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RCC->APB2RSTR |= (mask); \
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RCC->APB2RSTR = 0; \
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}
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/**
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* @brief Enables the clock of one or more peripheral on the AHB bus.
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*
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* @param[in] mask AHB peripherals mask
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableAHB(mask, lp) { \
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RCC->AHBENR |= (mask); \
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}
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/**
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* @brief Disables the clock of one or more peripheral on the AHB bus.
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*
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* @param[in] mask AHB peripherals mask
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccDisableAHB(mask, lp) { \
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RCC->AHBENR &= ~(mask); \
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}
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/**
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* @brief Resets one or more peripheral on the AHB bus.
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*
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* @param[in] mask AHB peripherals mask
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*
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* @api
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*/
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#define rccResetAHB(mask) { \
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RCC->AHBRSTR |= (mask); \
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RCC->AHBRSTR = 0; \
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}
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/** @} */
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/**
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* @name ADC peripherals specific RCC operations
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* @{
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*/
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/**
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* @brief Enables the ADC1/ADC2 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableADC12(lp) rccEnableAHB(RCC_AHBENR_ADC12EN, lp)
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/**
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* @brief Disables the ADC1/ADC2 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccDisableADC12(lp) rccDisableAHB(RCC_AHBENR_ADC12EN, lp)
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/**
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* @brief Resets the ADC1/ADC2 peripheral.
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*
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* @api
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*/
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#define rccResetADC12() rccResetAHB(RCC_AHBRSTR_ADC12RST)
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/**
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* @brief Enables the ADC3/ADC4 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableADC34(lp) rccEnableAHB(RCC_AHBENR_ADC34EN, lp)
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/**
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* @brief Disables the ADC3/ADC4 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccDisableADC34(lp) rccDisableAHB(RCC_AHBENR_ADC34EN, lp)
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/**
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* @brief Resets the ADC3/ADC4 peripheral.
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*
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* @api
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*/
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#define rccResetADC34() rccResetAHB(RCC_AHBRSTR_ADC34RST)
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/** @} */
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/**
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* @name CAN peripherals specific RCC operations
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* @{
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*/
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/**
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* @brief Enables the CAN1 peripheral clock.
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* @note The @p lp parameter is ignored in this family.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableCAN1(lp) rccEnableAPB1(RCC_APB1ENR_CAN1EN, lp)
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/**
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* @brief Disables the CAN1 peripheral clock.
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* @note The @p lp parameter is ignored in this family.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccDisableCAN1(lp) rccDisableAPB1(RCC_APB1ENR_CAN1EN, lp)
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/**
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* @brief Resets the CAN1 peripheral.
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*
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* @api
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*/
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#define rccResetCAN1() rccResetAPB1(RCC_APB1RSTR_CAN1RST)
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/** @} */
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/**
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* @name DMA peripheral specific RCC operations
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* @{
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*/
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/**
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* @brief Enables the DMA1 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableDMA1(lp) rccEnableAHB(RCC_AHBENR_DMA1EN, lp)
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/**
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* @brief Disables the DMA1 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccDisableDMA1(lp) rccDisableAHB(RCC_AHBENR_DMA1EN, lp)
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/**
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* @brief Resets the DMA1 peripheral.
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*
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* @api
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*/
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#define rccResetDMA1() rccResetAHB(RCC_AHBRSTR_DMA1RST)
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/**
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* @brief Enables the DMA2 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableDMA2(lp) rccEnableAHB(RCC_AHBENR_DMA2EN, lp)
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/**
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* @brief Disables the DMA2 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccDisableDMA2(lp) rccDisableAHB(RCC_AHBENR_DMA2EN, lp)
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/**
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* @brief Resets the DMA2 peripheral.
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*
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* @api
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*/
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#define rccResetDMA2() rccResetAHB(RCC_AHBRSTR_DMA2RST)
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/** @} */
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/**
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* @name PWR interface specific RCC operations
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* @{
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*/
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/**
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* @brief Enables the PWR interface clock.
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* @note The @p lp parameter is ignored in this family.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnablePWRInterface(lp) rccEnableAPB1(RCC_APB1ENR_PWREN, lp)
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/**
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* @brief Disables PWR interface clock.
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* @note The @p lp parameter is ignored in this family.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccDisablePWRInterface(lp) rccDisableAPB1(RCC_APB1ENR_PWREN, lp)
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/**
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* @brief Resets the PWR interface.
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*
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* @api
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*/
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#define rccResetPWRInterface() rccResetAPB1(RCC_APB1RSTR_PWRRST)
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/** @} */
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/**
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* @name I2C peripherals specific RCC operations
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* @{
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*/
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/**
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* @brief Enables the I2C1 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableI2C1(lp) rccEnableAPB1(RCC_APB1ENR_I2C1EN, lp)
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/**
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* @brief Disables the I2C1 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccDisableI2C1(lp) rccDisableAPB1(RCC_APB1ENR_I2C1EN, lp)
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/**
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* @brief Resets the I2C1 peripheral.
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*
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* @api
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*/
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#define rccResetI2C1() rccResetAPB1(RCC_APB1RSTR_I2C1RST)
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/**
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* @brief Enables the I2C2 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableI2C2(lp) rccEnableAPB1(RCC_APB1ENR_I2C2EN, lp)
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/**
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* @brief Disables the I2C2 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccDisableI2C2(lp) rccDisableAPB1(RCC_APB1ENR_I2C2EN, lp)
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/**
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* @brief Resets the I2C2 peripheral.
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*
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* @api
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*/
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#define rccResetI2C2() rccResetAPB1(RCC_APB1RSTR_I2C2RST)
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/** @} */
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/**
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* @name SPI peripherals specific RCC operations
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* @{
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*/
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/**
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* @brief Enables the SPI1 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableSPI1(lp) rccEnableAPB2(RCC_APB2ENR_SPI1EN, lp)
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/**
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* @brief Disables the SPI1 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccDisableSPI1(lp) rccDisableAPB2(RCC_APB2ENR_SPI1EN, lp)
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/**
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* @brief Resets the SPI1 peripheral.
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*
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* @api
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*/
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#define rccResetSPI1() rccResetAPB2(RCC_APB2RSTR_SPI1RST)
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/**
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* @brief Enables the SPI2 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableSPI2(lp) rccEnableAPB1(RCC_APB1ENR_SPI2EN, lp)
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/**
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* @brief Disables the SPI2 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccDisableSPI2(lp) rccDisableAPB1(RCC_APB1ENR_SPI2EN, lp)
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/**
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* @brief Resets the SPI2 peripheral.
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*
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* @api
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*/
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#define rccResetSPI2() rccResetAPB1(RCC_APB1RSTR_SPI2RST)
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/**
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* @brief Enables the SPI3 peripheral clock.
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* @note The @p lp parameter is ignored in this family.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableSPI3(lp) rccEnableAPB1(RCC_APB1ENR_SPI3EN, lp)
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/**
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* @brief Disables the SPI3 peripheral clock.
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* @note The @p lp parameter is ignored in this family.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccDisableSPI3(lp) rccDisableAPB1(RCC_APB1ENR_SPI3EN, lp)
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/**
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* @brief Resets the SPI3 peripheral.
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*
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* @api
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*/
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#define rccResetSPI3() rccResetAPB1(RCC_APB1RSTR_SPI3RST)
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/** @} */
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/**
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* @name TIM peripherals specific RCC operations
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* @{
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*/
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/**
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* @brief Enables the TIM1 peripheral clock.
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* @note The @p lp parameter is ignored in this family.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableTIM1(lp) rccEnableAPB2(RCC_APB2ENR_TIM1EN, lp)
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/**
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* @brief Disables the TIM1 peripheral clock.
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* @note The @p lp parameter is ignored in this family.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccDisableTIM1(lp) rccDisableAPB2(RCC_APB2ENR_TIM1EN, lp)
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/**
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* @brief Resets the TIM1 peripheral.
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*
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* @api
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*/
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#define rccResetTIM1() rccResetAPB2(RCC_APB2RSTR_TIM1RST)
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/**
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* @brief Enables the TIM2 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableTIM2(lp) rccEnableAPB1(RCC_APB1ENR_TIM2EN, lp)
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/**
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* @brief Disables the TIM2 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccDisableTIM2(lp) rccDisableAPB1(RCC_APB1ENR_TIM2EN, lp)
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/**
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* @brief Resets the TIM2 peripheral.
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*
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* @api
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*/
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#define rccResetTIM2() rccResetAPB1(RCC_APB1RSTR_TIM2RST)
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/**
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* @brief Enables the TIM3 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableTIM3(lp) rccEnableAPB1(RCC_APB1ENR_TIM3EN, lp)
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/**
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* @brief Disables the TIM3 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccDisableTIM3(lp) rccDisableAPB1(RCC_APB1ENR_TIM3EN, lp)
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/**
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* @brief Resets the TIM3 peripheral.
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*
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* @api
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*/
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#define rccResetTIM3() rccResetAPB1(RCC_APB1RSTR_TIM3RST)
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/**
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* @brief Enables the TIM4 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableTIM4(lp) rccEnableAPB1(RCC_APB1ENR_TIM4EN, lp)
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/**
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* @brief Disables the TIM4 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccDisableTIM4(lp) rccDisableAPB1(RCC_APB1ENR_TIM4EN, lp)
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/**
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* @brief Resets the TIM4 peripheral.
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*
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* @api
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*/
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#define rccResetTIM4() rccResetAPB1(RCC_APB1RSTR_TIM4RST)
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/**
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* @brief Enables the TIM6 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableTIM6(lp) rccEnableAPB1(RCC_APB1ENR_TIM6EN, lp)
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/**
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* @brief Disables the TIM6 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccDisableTIM6(lp) rccDisableAPB1(RCC_APB1ENR_TIM6EN, lp)
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/**
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* @brief Resets the TIM6 peripheral.
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*
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* @api
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*/
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#define rccResetTIM6() rccResetAPB1(RCC_APB1RSTR_TIM6RST)
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/**
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* @brief Enables the TIM7 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableTIM7(lp) rccEnableAPB1(RCC_APB1ENR_TIM7EN, lp)
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/**
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* @brief Disables the TIM7 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccDisableTIM7(lp) rccDisableAPB1(RCC_APB1ENR_TIM7EN, lp)
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/**
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* @brief Resets the TIM7 peripheral.
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*
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* @api
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*/
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#define rccResetTIM7() rccResetAPB1(RCC_APB1RSTR_TIM7RST)
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/**
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* @brief Enables the TIM8 peripheral clock.
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* @note The @p lp parameter is ignored in this family.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableTIM8(lp) rccEnableAPB2(RCC_APB2ENR_TIM8EN, lp)
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/**
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* @brief Disables the TIM8 peripheral clock.
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* @note The @p lp parameter is ignored in this family.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccDisableTIM8(lp) rccDisableAPB2(RCC_APB2ENR_TIM8EN, lp)
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/**
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* @brief Resets the TIM8 peripheral.
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*
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* @api
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*/
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#define rccResetTIM8() rccResetAPB2(RCC_APB2RSTR_TIM8RST)
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/** @} */
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/**
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* @name USART/UART peripherals specific RCC operations
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* @{
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*/
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/**
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* @brief Enables the USART1 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableUSART1(lp) rccEnableAPB2(RCC_APB2ENR_USART1EN, lp)
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/**
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* @brief Disables the USART1 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccDisableUSART1(lp) rccDisableAPB2(RCC_APB2ENR_USART1EN, lp)
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/**
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* @brief Resets the USART1 peripheral.
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*
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* @api
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*/
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#define rccResetUSART1() rccResetAPB2(RCC_APB2RSTR_USART1RST)
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/**
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* @brief Enables the USART2 peripheral clock.
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*
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|
* @param[in] lp low power enable flag
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*
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|
* @api
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*/
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#define rccEnableUSART2(lp) rccEnableAPB1(RCC_APB1ENR_USART2EN, lp)
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/**
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|
* @brief Disables the USART2 peripheral clock.
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*
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|
* @param[in] lp low power enable flag
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*
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|
* @api
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|
*/
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#define rccDisableUSART2(lp) rccDisableAPB1(RCC_APB1ENR_USART2EN, lp)
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/**
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* @brief Resets the USART2 peripheral.
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*
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|
* @api
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|
*/
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#define rccResetUSART2() rccResetAPB1(RCC_APB1RSTR_USART2RST)
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/**
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|
* @brief Enables the USART3 peripheral clock.
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|
*
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|
* @param[in] lp low power enable flag
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|
*
|
|
* @api
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|
*/
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|
#define rccEnableUSART3(lp) rccEnableAPB1(RCC_APB1ENR_USART3EN, lp)
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/**
|
|
* @brief Disables the USART3 peripheral clock.
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|
*
|
|
* @param[in] lp low power enable flag
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|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableUSART3(lp) rccDisableAPB1(RCC_APB1ENR_USART3EN, lp)
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|
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/**
|
|
* @brief Resets the USART3 peripheral.
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|
*
|
|
* @api
|
|
*/
|
|
#define rccResetUSART3() rccResetAPB1(RCC_APB1RSTR_USART3RST)
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|
|
/**
|
|
* @brief Enables the UART4 peripheral clock.
|
|
* @note The @p lp parameter is ignored in this family.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableUART4(lp) rccEnableAPB1(RCC_APB1ENR_UART4EN, lp)
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|
|
|
/**
|
|
* @brief Disables the UART4 peripheral clock.
|
|
* @note The @p lp parameter is ignored in this family.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableUART4(lp) rccDisableAPB1(RCC_APB1ENR_UART4EN, lp)
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|
|
|
/**
|
|
* @brief Resets the UART4 peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetUART4() rccResetAPB1(RCC_APB1RSTR_UART4RST)
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|
|
|
/**
|
|
* @brief Enables the UART5 peripheral clock.
|
|
* @note The @p lp parameter is ignored in this family.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableUART5(lp) rccEnableAPB1(RCC_APB1ENR_UART5EN, lp)
|
|
|
|
/**
|
|
* @brief Disables the UART5 peripheral clock.
|
|
* @note The @p lp parameter is ignored in this family.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableUART5(lp) rccDisableAPB1(RCC_APB1ENR_UART5EN, lp)
|
|
|
|
/**
|
|
* @brief Resets the UART5 peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetUART5() rccResetAPB1(RCC_APB1RSTR_UART5RST)
|
|
/** @} */
|
|
|
|
/**
|
|
* @name USB peripheral specific RCC operations
|
|
* @{
|
|
*/
|
|
/**
|
|
* @brief Enables the USB peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccEnableUSB(lp) rccEnableAPB1(RCC_APB1ENR_USBEN, lp)
|
|
|
|
/**
|
|
* @brief Disables the USB peripheral clock.
|
|
*
|
|
* @param[in] lp low power enable flag
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccDisableUSB(lp) rccDisableAPB1(RCC_APB1ENR_USBEN, lp)
|
|
|
|
/**
|
|
* @brief Resets the USB peripheral.
|
|
*
|
|
* @api
|
|
*/
|
|
#define rccResetUSB() rccResetAPB1(RCC_APB1RSTR_USBRST)
|
|
/** @} */
|
|
|
|
/*===========================================================================*/
|
|
/* External declarations. */
|
|
/*===========================================================================*/
|
|
|
|
#ifdef __cplusplus
|
|
extern "C" {
|
|
#endif
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* _STM32_RCC_ */
|
|
|
|
/** @} */
|