mirror of
https://github.com/portapack-mayhem/mayhem-firmware.git
synced 2024-12-14 04:04:34 +00:00
d4c43044e0
Bootstrap is now 64k @ 0x00000. HackRF image is 64k @ 0x10000. Baseband image is 128k @ 0x20000. Application image is remainder of SPI flash, @ 0x40000.
114 lines
3.5 KiB
C
114 lines
3.5 KiB
C
/*
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* Copyright (C) 2015 Jared Boone, ShareBrained Technology, Inc.
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*
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* This file is part of PortaPack.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 51 Franklin Street,
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* Boston, MA 02110-1301, USA.
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*/
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#include <lpc43xx_m4.h>
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#include <nvic.h>
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/* Bootstrap runs from SPIFI on the M4, immediately after the LPC43xx built-in
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* boot ROM runs.
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*/
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/* After boot ROM executes:
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* PLL1 is at 288MHz (IRC * 24)
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* IDIVB_CTRL = PLL1 / 9 = 32MHz
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* IDIVC_CTRL = PLL1 / 3 = 96MHz
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* BASE_SPIFI_CLK.CLK_SEL = IDIVB
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*/
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/* SPIFI config must run from RAM because SPIFI memory mode may/must be
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* re-initialized during the transition
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*/
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/* An ARM veneer will be created to make the long jump between code in the
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* SPIFI address range and the RAM address range.
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*/
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__attribute__ ((section("fast")))
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void configure_spifi(void) {
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/* Configure pins first, to enable SCK input buffer for feedback */
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/* Configure SPIFI pins for maximum I/O rate */
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const uint32_t scu_spifi_io =
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(3 << 0) /* Function 3 */
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| (0 << 3) /* Disable pull-down */
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| (1 << 4) /* Disable pull-up */
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| (1 << 5) /* Fast slew rate */
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| (1 << 6) /* Enable input buffer */
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| (1 << 7) /* Disable input glitch filter */
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;
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LPC_SCU->SFSP3_3 = scu_spifi_io;
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LPC_SCU->SFSP3_4 = scu_spifi_io;
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LPC_SCU->SFSP3_5 = scu_spifi_io;
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LPC_SCU->SFSP3_6 = scu_spifi_io;
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LPC_SCU->SFSP3_7 = scu_spifi_io;
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LPC_SCU->SFSP3_8 = scu_spifi_io;
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/* Tweak SPIFI mode */
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LPC_SPIFI->CTRL =
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(0xffff << 0) /* Timeout */
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| (0x1 << 16) /* CS high time in "clocks - 1" */
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| (0 << 21) /* 0: Attempt speculative prefetch on data accesses */
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| (0 << 22) /* 0: No interrupt on command ended */
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| (0 << 23) /* 0: SCK driven low after rising edge at which last bit of command is captured. Stays low while CS# is high. */
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| (0 << 27) /* 0: Cache prefetching enabled */
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| (0 << 28) /* 0: Quad protocol, IO3:0 */
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| (1 << 29) /* 1: Read data sampled on falling edge of clock */
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| (1 << 30) /* 1: Read data is sampled using feedback clock from SCK pin */
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| (0 << 31) /* 0: DMA request disabled */
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;
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/* Throttle up the SPIFI interface to 96MHz (PLL1 / 3) */
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LPC_CGU->IDIVB_CTRL =
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(0 << 0) /* PD */
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| (1 << 2) /* IDIV (/2) */
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| (1 << 11) /* AUTOBLOCK */
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| (9 << 24) /* PLL1 */
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;
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}
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int main(void) {
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#if 0
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/* Configure LEDs and make sure they're off to start */
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LPC_SCU->SFSP4_1 = (1 << 4) | 0; /* GPIO2[1] */
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LPC_SCU->SFSP4_2 = (1 << 4) | 0; /* GPIO2[2] */
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LPC_SCU->SFSP6_12 = (1 << 4) | 0; /* GPIO2[8] */
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LPC_GPIO->CLR[2] = (1 << 8) | (1 << 2) | (1 << 1);
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LPC_GPIO->DIR[2] = (1 << 8) | (1 << 2) | (1 << 1);
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/* Indicate M4 is working */
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LPC_GPIO->SET[2] = (1 << 1);
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#endif
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configure_spifi();
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/* NOTE: MEMMAP registers are ORed with the shadow address to create the
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* actual address.
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*/
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LPC_CREG->M0APPMEMMAP = LPC_SPIFI_DATA_CACHED_BASE + 0x40000;
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/* Change M0APP_RST to 0 */
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LPC_RGU->RESET_CTRL[1] = 0;
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while(1) {
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__WFE();
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}
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}
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void SystemInit(void) {
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}
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