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https://github.com/portapack-mayhem/mayhem-firmware.git
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279 lines
11 KiB
C
Executable File
279 lines
11 KiB
C
Executable File
/*
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SPC5 HAL - Copyright (C) 2013 STMicroelectronics
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file SPC564Axx/hal_lld.h
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* @brief SPC564Axx HAL subsystem low level driver header.
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* @pre This module requires the following macros to be defined in the
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* @p board.h file:
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* - SPC5_XOSC_CLK.
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* .
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*
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* @addtogroup HAL
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* @{
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*/
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#ifndef _HAL_LLD_H_
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#define _HAL_LLD_H_
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#include "xpc564a.h"
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#include "spc564a_registry.h"
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/**
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* @brief Defines the support for realtime counters in the HAL.
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*/
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#define HAL_IMPLEMENTS_COUNTERS FALSE
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/**
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* @brief Platform name.
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*/
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#define PLATFORM_NAME "SPC564Axx Powertrain"
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/**
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* @name ESYNCR2 register definitions
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* @{
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*/
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#define SPC5_RFD_DIV2 0 /**< Divide VCO frequency by 2. */
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#define SPC5_RFD_DIV4 1 /**< Divide VCO frequency by 4. */
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#define SPC5_RFD_DIV8 2 /**< Divide VCO frequency by 8. */
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#define SPC5_RFD_DIV16 3 /**< Divide VCO frequency by 16.*/
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/** @} */
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/**
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* @name BIUCR register definitions
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* @{
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*/
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#define BIUCR_BANK1_TOO 0x01000000 /**< Use settings for bank1 too.*/
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#define BIUCR_MASTER7_PREFETCH 0x00800000 /**< Enable master 7 prefetch. */
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#define BIUCR_MASTER6_PREFETCH 0x00400000 /**< Enable master 6 prefetch. */
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#define BIUCR_MASTER5_PREFETCH 0x00200000 /**< Enable master 5 prefetch. */
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#define BIUCR_MASTER4_PREFETCH 0x00100000 /**< Enable master 4 prefetch. */
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#define BIUCR_MASTER3_PREFETCH 0x00080000 /**< Enable master 3 prefetch. */
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#define BIUCR_MASTER2_PREFETCH 0x00040000 /**< Enable master 2 prefetch. */
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#define BIUCR_MASTER1_PREFETCH 0x00020000 /**< Enable master 1 prefetch. */
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#define BIUCR_MASTER0_PREFETCH 0x00010000 /**< Enable master 0 prefetch. */
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#define BIUCR_APC_MASK 0x0000E000 /**< APC field mask. */
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#define BIUCR_APC_0 (0 << 13) /**< No additional hold cycles. */
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#define BIUCR_APC_1 (1 << 13) /**< 1 additional hold cycle. */
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#define BIUCR_APC_2 (2 << 13) /**< 2 additional hold cycles. */
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#define BIUCR_APC_3 (3 << 13) /**< 3 additional hold cycles. */
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#define BIUCR_APC_4 (4 << 13) /**< 4 additional hold cycles. */
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#define BIUCR_APC_5 (5 << 13) /**< 5 additional hold cycles. */
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#define BIUCR_APC_6 (6 << 13) /**< 6 additional hold cycles. */
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#define BIUCR_WWSC_MASK 0x00001800 /**< WWSC field mask. */
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#define BIUCR_WWSC_0 (0 << 11) /**< No write wait states. */
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#define BIUCR_WWSC_1 (1 << 11) /**< 1 write wait state. */
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#define BIUCR_WWSC_2 (2 << 11) /**< 2 write wait states. */
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#define BIUCR_WWSC_3 (3 << 11) /**< 3 write wait states. */
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#define BIUCR_RWSC_MASK 0x00001800 /**< RWSC field mask. */
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#define BIUCR_RWSC_0 (0 << 8) /**< No read wait states. */
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#define BIUCR_RWSC_1 (1 << 8) /**< 1 read wait state. */
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#define BIUCR_RWSC_2 (2 << 8) /**< 2 read wait states. */
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#define BIUCR_RWSC_3 (3 << 8) /**< 3 read wait states. */
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#define BIUCR_RWSC_4 (4 << 8) /**< 4 read wait states. */
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#define BIUCR_RWSC_5 (5 << 8) /**< 5 read wait states. */
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#define BIUCR_RWSC_6 (6 << 8) /**< 6 read wait states. */
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#define BIUCR_RWSC_7 (7 << 8) /**< 7 read wait states. */
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#define BIUCR_DPFEN 0x00000040 /**< Data prefetch enable. */
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#define BIUCR_IPFEN 0x00000010 /**< Instr. prefetch enable. */
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#define BIUCR_PFLIM_MASK 0x00000060 /**< PFLIM field mask. */
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#define BIUCR_PFLIM_NO (0 << 1) /**< No prefetching. */
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#define BIUCR_PFLIM_ON_MISS (1 << 1) /**< Prefetch on miss. */
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#define BIUCR_PFLIM_ON_HITMISS (2 << 1) /**< Prefetch on hit and miss. */
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#define BIUCR_BFEN 0x00000001 /**< Flash buffering enable. */
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/** @} */
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/**
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* @brief Disables the clocks initialization in the HAL.
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*/
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#if !defined(SPC5_NO_INIT) || defined(__DOXYGEN__)
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#define SPC5_NO_INIT FALSE
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#endif
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/**
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* @brief Clock bypass.
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* @note If set to @p TRUE then the PLL is not started and initialized, the
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* external clock is used as-is and the other clock-related settings
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* are ignored.
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*/
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#if !defined(SPC5_CLK_BYPASS) || defined(__DOXYGEN__)
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#define SPC5_CLK_BYPASS FALSE
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#endif
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/**
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* @brief Disables the overclock checks.
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*/
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#if !defined(SPC5_ALLOW_OVERCLOCK) || defined(__DOXYGEN__)
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#define SPC5_ALLOW_OVERCLOCK FALSE
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#endif
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/**
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* @brief External clock pre-divider.
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* @note Must be in range 1...15.
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*/
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#if !defined(SPC5_CLK_PREDIV_VALUE) || defined(__DOXYGEN__)
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#define SPC5_CLK_PREDIV_VALUE 2
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#endif
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/**
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* @brief Multiplication factor divider.
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* @note Must be in range 32...96.
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*/
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#if !defined(SPC5_CLK_MFD_VALUE) || defined(__DOXYGEN__)
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#define SPC5_CLK_MFD_VALUE 75
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#endif
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/**
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* @brief Reduced frequency divider.
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*/
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#if !defined(SPC5_CLK_RFD) || defined(__DOXYGEN__)
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#define SPC5_CLK_RFD RFD_DIV2
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#endif
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/**
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* @brief Flash buffer and prefetching settings.
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* @note Please refer to the SPC564Axx reference manual about the meaning
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* of the following bits, if in doubt DO NOT MODIFY IT.
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* @note Do not specify the APC, WWSC, RWSC bits in this value because
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* those are calculated from the system clock and ORed with this
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* value.
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*/
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#if !defined(SPC5_FLASH_BIUCR) || defined(__DOXYGEN__)
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#define SPC5_FLASH_BIUCR (BIUCR_BANK1_TOO | \
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BIUCR_MASTER4_PREFETCH | \
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BIUCR_MASTER0_PREFETCH | \
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BIUCR_DPFEN | \
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BIUCR_IPFEN | \
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BIUCR_PFLIM_ON_MISS | \
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BIUCR_BFEN)
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#endif
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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/*
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* Configuration-related checks.
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*/
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#if !defined(SPC564Axx_MCUCONF)
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#error "Using a wrong mcuconf.h file, SPC564Axx_MCUCONF not defined"
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#endif
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#if (SPC5_CLK_PREDIV_VALUE < 1) || (SPC5_CLK_PREDIV_VALUE > 15)
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#error "invalid SPC5_CLK_PREDIV_VALUE value specified"
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#endif
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#if (SPC5_CLK_MFD_VALUE < 32) || (SPC5_CLK_MFD_VALUE > 96)
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#error "invalid SPC5_CLK_MFD_VALUE value specified"
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#endif
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#if (SPC5_CLK_RFD != SPC5_RFD_DIV2) && (SPC5_CLK_RFD != SPC5_RFD_DIV4) && \
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(SPC5_CLK_RFD != SPC5_RFD_DIV8) && (SPC5_CLK_RFD != SPC5_RFD_DIV16)
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#error "invalid SPC5_CLK_RFD value specified"
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#endif
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/**
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* @brief PLL input divider.
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*/
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#define SPC5_CLK_PREDIV (SPC5_CLK_PREDIV_VALUE - 1)
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/**
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* @brief PLL multiplier.
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*/
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#define SPC5_CLK_MFD (SPC5_CLK_MFD_VALUE)
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/**
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* @brief PLL output clock.
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*/
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#define SPC5_PLLCLK ((SPC5_XOSC_CLK / SPC5_CLK_PREDIV_VALUE) * \
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SPC5_CLK_MFD_VALUE)
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#if (SPC5_PLLCLK < 256000000) || (SPC5_PLLCLK > 512000000)
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#error "VCO frequency out of the acceptable range (256...512)"
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#endif
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/**
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* @brief PLL output clock.
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*/
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#if !SPC5_CLK_BYPASS || defined(__DOXYGEN__)
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#define SPC5_SYSCLK (SPC5_PLLCLK / (1 << (SPC5_CLK_RFD + 1)))
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#else
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#define SPC5_SYSCLK SPC5_XOSC_CLK
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#endif
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#if (SPC5_SYSCLK > 150000000) && !SPC5_ALLOW_OVERCLOCK
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#error "System clock above maximum rated frequency (150MHz)"
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#endif
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/**
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* @brief Flash wait states are a function of the system clock.
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*/
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#if (SPC5_SYSCLK <= 20000000) || defined(__DOXYGEN__)
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#define SPC5_FLASH_WS (BIUCR_APC_0 | BIUCR_RWSC_0 | BIUCR_WWSC_3)
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#elif SPC5_SYSCLK <= 61000000
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#define SPC5_FLASH_WS (BIUCR_APC_1 | BIUCR_RWSC_1 | BIUCR_WWSC_3)
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#elif SPC5_SYSCLK <= 90000000
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#define SPC5_FLASH_WS (BIUCR_APC_2 | BIUCR_RWSC_2 | BIUCR_WWSC_3)
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#elif SPC5_SYSCLK <= 123000000
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#define SPC5_FLASH_WS (BIUCR_APC_3 | BIUCR_RWSC_3 | BIUCR_WWSC_3)
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#else
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#define SPC5_FLASH_WS (BIUCR_APC_4 | BIUCR_RWSC_4 | BIUCR_WWSC_3)
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#endif
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/**
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* @brief RAM wait states are a function of the system clock.
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*/
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#if (SPC5_SYSCLK <= 98000000) || defined(__DOXYGEN__)
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#define SPC5_RAM_WS 0
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#else
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#define SPC5_RAM_WS 0x40000000
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#endif
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver macros. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* External declarations. */
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/*===========================================================================*/
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#include "spc5_edma.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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void hal_lld_init(void);
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void spc_clock_init(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _HAL_LLD_H_ */
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/** @} */
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