mirror of
https://github.com/portapack-mayhem/mayhem-firmware.git
synced 2024-12-15 12:38:11 +00:00
223 lines
7.6 KiB
C
Executable File
223 lines
7.6 KiB
C
Executable File
/*
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ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file STM32F30x/hal_lld.c
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* @brief STM32F30x HAL subsystem low level driver source.
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*
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* @addtogroup HAL
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* @{
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*/
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#include "ch.h"
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#include "hal.h"
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local variables and types. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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/**
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* @brief Initializes the backup domain.
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* @note WARNING! Changing clock source impossible without resetting
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* of the whole BKP domain.
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*/
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static void hal_lld_backup_domain_init(void) {
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/* Backup domain access enabled and left open.*/
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PWR->CR |= PWR_CR_DBP;
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/* Reset BKP domain if different clock source selected.*/
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if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL){
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/* Backup domain reset.*/
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RCC->BDCR = RCC_BDCR_BDRST;
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RCC->BDCR = 0;
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}
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/* If enabled then the LSE is started.*/
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#if STM32_LSE_ENABLED
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#if defined(STM32_LSE_BYPASS)
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/* LSE Bypass.*/
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RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
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#else
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/* No LSE Bypass.*/
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RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON;
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#endif
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while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
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; /* Waits until LSE is stable. */
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#endif
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#if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK
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/* If the backup domain hasn't been initialized yet then proceed with
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initialization.*/
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if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
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/* Selects clock source.*/
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RCC->BDCR |= STM32_RTCSEL;
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/* RTC clock enabled.*/
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RCC->BDCR |= RCC_BDCR_RTCEN;
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}
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#endif /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */
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}
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/**
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* @brief Low level HAL driver initialization.
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*
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* @notapi
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*/
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void hal_lld_init(void) {
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/* Reset of all peripherals.*/
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rccResetAHB(0xFFFFFFFF);
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rccResetAPB1(0xFFFFFFFF);
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rccResetAPB2(0xFFFFFFFF);
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/* SysTick initialization using the system clock.*/
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SysTick->LOAD = STM32_HCLK / CH_FREQUENCY - 1;
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SysTick->VAL = 0;
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SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
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SysTick_CTRL_ENABLE_Msk |
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SysTick_CTRL_TICKINT_Msk;
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/* DWT cycle counter enable.*/
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SCS_DEMCR |= SCS_DEMCR_TRCENA;
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DWT_CTRL |= DWT_CTRL_CYCCNTENA;
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/* PWR clock enabled.*/
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rccEnablePWRInterface(FALSE);
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/* Initializes the backup domain.*/
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hal_lld_backup_domain_init();
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#if defined(STM32_DMA_REQUIRED)
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dmaInit();
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#endif
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/* Programmable voltage detector enable.*/
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#if STM32_PVD_ENABLE
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PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK);
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#endif /* STM32_PVD_ENABLE */
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/* SYSCFG clock enabled here because it is a multi-functional unit shared
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among multiple drivers.*/
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rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE);
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/* USB IRQ relocated to not conflict with CAN.*/
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SYSCFG->CFGR1 |= SYSCFG_CFGR1_USB_IT_RMP;
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}
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/**
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* @brief STM32 clocks and PLL initialization.
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* @note All the involved constants come from the file @p board.h.
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* @note This function should be invoked just after the system reset.
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*
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* @special
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*/
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void stm32_clock_init(void) {
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#if !STM32_NO_INIT
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/* HSI setup, it enforces the reset situation in order to handle possible
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problems with JTAG probes and re-initializations.*/
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RCC->CR |= RCC_CR_HSION; /* Make sure HSI is ON. */
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while (!(RCC->CR & RCC_CR_HSIRDY))
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; /* Wait until HSI is stable. */
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/* HSI is selected as new source without touching the other fields in
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CFGR. Clearing the register has to be postponed after HSI is the
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new source.*/
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RCC->CFGR &= ~RCC_CFGR_SW; /* Reset SW */
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RCC->CFGR |= RCC_CFGR_SWS_HSI; /* Select HSI as internal*/
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while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
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; /* Wait until HSI is selected. */
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/* Registers finally cleared to reset values.*/
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RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value. */
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RCC->CFGR = 0; /* CFGR reset value. */
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#if STM32_HSE_ENABLED
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/* HSE activation.*/
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#if defined(STM32_HSE_BYPASS)
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/* HSE Bypass.*/
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RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP;
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#else
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/* No HSE Bypass.*/
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RCC->CR |= RCC_CR_HSEON;
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#endif
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while (!(RCC->CR & RCC_CR_HSERDY))
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; /* Waits until HSE is stable. */
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#endif
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#if STM32_LSI_ENABLED
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/* LSI activation.*/
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RCC->CSR |= RCC_CSR_LSION;
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while ((RCC->CSR & RCC_CSR_LSIRDY) == 0)
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; /* Waits until LSI is stable. */
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#endif
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/* Clock settings.*/
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RCC->CFGR = STM32_MCOSEL | STM32_USBPRE | STM32_PLLMUL |
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STM32_PLLSRC | STM32_PPRE1 | STM32_PPRE2 |
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STM32_HPRE;
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RCC->CFGR2 = STM32_ADC34PRES | STM32_ADC12PRES | STM32_PREDIV;
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RCC->CFGR3 = STM32_UART5SW | STM32_UART4SW | STM32_USART3SW |
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STM32_USART2SW | STM32_I2C2SW | STM32_I2C1SW |
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STM32_USART1SW;
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#if STM32_ACTIVATE_PLL
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/* PLL activation.*/
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RCC->CR |= RCC_CR_PLLON;
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while (!(RCC->CR & RCC_CR_PLLRDY))
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; /* Waits until PLL is stable. */
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#endif
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/* Flash setup and final clock selection. */
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FLASH->ACR = STM32_FLASHBITS;
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/* Switching to the configured clock source if it is different from HSI.*/
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#if (STM32_SW != STM32_SW_HSI)
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/* Switches clock source.*/
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RCC->CFGR |= STM32_SW;
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while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
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; /* Waits selection complete. */
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#endif
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/* After PLL activation because the special requirements for TIM1 and
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TIM8 bits.*/
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RCC->CFGR3 |= STM32_TIM8SW | STM32_TIM1SW;
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#endif /* !STM32_NO_INIT */
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}
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/** @} */
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