mirror of
https://github.com/portapack-mayhem/mayhem-firmware.git
synced 2024-12-15 12:38:11 +00:00
920b98f7c9
* Power: Turn off additional peripheral clock branches. * Update schematic with new symbol table and KiCad standard symbols. Fix up wires. * Schematic: Update power net labels. * Schematic: Update footprint names to match library changes. * Schematic: Update header vendor and part numbers. * Schematic: Specify (arbitrary) value for PDN# net. * Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space. * Schematic: Add reference oscillator -- options for clipped sine or HCMOS output. * Schematic: Update copyright year. * Schematic: Remove CLKOUT to CPLD. It was a half-baked idea. * Schematic: Add (experimental) GPS circuit. Add note about charging circuit. Update date and revision to match PCB. * PCB: Update from schematic change: now revision 20180819. Diff was extensive due to net renumbering... * PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual. PCB: Address DRC clearance violation between via and oscillator pad. * PCB: Update copyright on drawing. * Update schematic and PCB date and revision. * gitignore: Sublime Text editor project/workspace files * Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze... * Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field. * LPC43xx: Add CGU IDIVx struct/union type. * Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use. * HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02) * MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class. * MAX V CPLD: Add BYPASS, SAMPLE support. Rename enter_isp -> enable, exit_isp -> disable. Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing. * MAX V CPLD: Reverse verify data checking logic to make it a little faster. * CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream. * Si5351: Refactor code, make one of the registers more type-safe. Clock Manager: Track selected reference clock source for later use in user interface. * Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal. It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise... * PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external. * CPLD: Add pins and logic for new PortaPack hardware feature(s). * CPLD: Bitstream to support new hardware features. * Clock Generator: Add a couple more setter methods for ClockControl registers. * Clock Manager: Use shared MCU CLKIN clock control configuration constant. * Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty. * Clock Manager: Remove redundant clock generator output enable. * Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM. * Bootstrap: Get CPU operating at max frequency as soon as possible. Update SPIFI speed comment. Make some more LPC43xx types into unions with uint32_t. * Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it. * Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream. * Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated. * Bootstrap: Consolidate clock configuration, update SPIFI rate comment. * Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward. Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out... * ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution. * PortaPack IO: Expose method to set reference oscillator enable pin. * Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader. * Pin configuration: Disable input buffers on pins that are never read. * Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution." This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03. * Remove unused board files. * Add LPC43xx functions. * chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits. * LPC43xx: Add MCPWM peripheral struct. * clock generator: Use recommended PLL reset register value. Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000. * GPIO: Tweak masking of SCU function. I don't remember why I thought this was necessary... * HAL: Explicitly turn on timer peripheral clocks used as systicks, during init. * SCU: Add struct to hold pin configuration. * PAL: Add functions to address The Glitch. https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/ * PAL/board: New IO initialization code Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch. * Merge M0 and M4 to eliminate need for bootstrap firmware During _early_init, detect if we're running on the M4 or M0. If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep. If M0: do all the other things. * Pins: Miscellaneous SCU configuration tweaks. * Little code clarity improvement. * bootstrap: Remove, not necessary. * Clock Manager: Large re-working to support external references. * Fix merge conflicts
383 lines
8.6 KiB
C++
383 lines
8.6 KiB
C++
/*
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* Copyright (C) 2014 Jared Boone, ShareBrained Technology, Inc.
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*
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* This file is part of PortaPack.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 51 Franklin Street,
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* Boston, MA 02110-1301, USA.
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*/
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#ifndef __PORTAPACK_IO_H__
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#define __PORTAPACK_IO_H__
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#include <cstdint>
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#include <cstddef>
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#include <array>
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#include "gpio.hpp"
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#include "ui.hpp"
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namespace portapack {
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class IO {
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public:
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enum class TouchPinsConfig : uint8_t {
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XN_BIT = (1 << 0),
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XP_BIT = (1 << 1),
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YN_BIT = (1 << 2),
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YP_BIT = (1 << 3),
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XN_OE = (1 << 4),
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XP_OE = (1 << 5),
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YN_OE = (1 << 6),
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YP_OE = (1 << 7),
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XN_IN = XN_BIT,
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XN_OUT_1 = XN_OE | XN_BIT,
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XN_OUT_0 = XN_OE,
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XP_IN = XP_BIT,
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XP_OUT_1 = XP_OE | XP_BIT,
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XP_OUT_0 = XP_OE,
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YN_IN = YN_BIT,
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YN_OUT_1 = YN_OE | YN_BIT,
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YN_OUT_0 = YN_OE,
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YP_IN = YP_BIT,
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YP_OUT_1 = YP_OE | YP_BIT,
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YP_OUT_0 = YP_OE,
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/* Allow pins to be pulled up by CPLD pull-ups. */
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Float = XP_IN | XN_IN | YP_IN | YN_IN,
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/* Drive one plane to 0V, other plane is pulled up. Watch for when pulled-up
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* plane falls to ~0V.
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*/
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WaitTouch = XP_OUT_0 | XN_OUT_0 | YP_IN | YN_IN,
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/* Create a voltage divider between X plane, touch resistance, Y plane. */
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SensePressure = XP_IN | XN_OUT_0 | YP_OUT_1 | YN_IN,
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/* Create a voltage divider across X plane, read voltage from Y plane. */
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SenseX = XP_OUT_1 | XN_OUT_0 | YP_IN | YN_IN,
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/* Create a voltage divider across Y plane, read voltage from X plane. */
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SenseY = XP_IN | XN_IN | YP_OUT_1 | YN_OUT_0,
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};
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constexpr IO(
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GPIO gpio_dir,
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GPIO gpio_lcd_rdx,
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GPIO gpio_lcd_wrx,
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GPIO gpio_io_stbx,
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GPIO gpio_addr,
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GPIO gpio_rot_a,
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GPIO gpio_rot_b
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) : gpio_dir { gpio_dir },
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gpio_lcd_rdx { gpio_lcd_rdx },
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gpio_lcd_wrx { gpio_lcd_wrx },
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gpio_io_stbx { gpio_io_stbx },
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gpio_addr { gpio_addr },
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gpio_rot_a { gpio_rot_a },
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gpio_rot_b { gpio_rot_b }
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{
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};
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void init();
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void lcd_backlight(const bool value);
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void lcd_reset_state(const bool active);
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void audio_reset_state(const bool active);
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void reference_oscillator(const bool enable);
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void lcd_data_write_command_and_data(
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const uint_fast8_t command,
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const uint8_t* data,
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const size_t data_count
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) {
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lcd_command(command);
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for(size_t i=0; i<data_count; i++) {
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lcd_write_data(data[i]);
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}
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}
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void lcd_data_write_command_and_data(
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const uint_fast8_t command,
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const std::initializer_list<uint8_t>& data
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) {
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lcd_command(command);
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for(const auto d : data) {
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lcd_write_data(d);
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}
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}
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void lcd_data_read_command_and_data(
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const uint_fast8_t command,
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uint16_t* const data,
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const size_t data_count
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) {
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lcd_command(command);
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for(size_t i=0; i<data_count; i++) {
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data[i] = lcd_read_data();
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}
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}
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void lcd_write_word(const uint32_t w) {
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lcd_write_data(w);
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}
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void lcd_write_words(const uint16_t* const w, size_t n) {
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for(size_t i=0; i<n; i++) {
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lcd_write_data(w[i]);
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}
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}
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void lcd_write_pixel(const ui::Color pixel) {
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lcd_write_data(pixel.v);
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}
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uint32_t lcd_read_word() {
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return lcd_read_data();
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}
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void lcd_write_pixels(const ui::Color pixel, size_t n) {
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while(n--) {
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lcd_write_data(pixel.v);
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}
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}
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void lcd_write_pixels_unrolled8(const ui::Color pixel, size_t n) {
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auto v = pixel.v;
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n >>= 3;
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while(n--) {
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lcd_write_data(v);
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lcd_write_data(v);
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lcd_write_data(v);
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lcd_write_data(v);
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lcd_write_data(v);
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lcd_write_data(v);
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lcd_write_data(v);
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lcd_write_data(v);
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}
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}
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void lcd_write_pixels(const ui::Color* const pixels, size_t n) {
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for(size_t i=0; i<n; i++) {
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lcd_write_pixel(pixels[i]);
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}
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}
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void lcd_read_bytes(uint8_t* byte, size_t byte_count) {
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size_t word_count = byte_count / 2;
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while(word_count) {
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const auto word = lcd_read_data();
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*(byte++) = word >> 8;
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*(byte++) = word >> 0;
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word_count--;
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}
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if( byte_count & 1 ) {
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const auto word = lcd_read_data();
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*(byte++) = word >> 8;
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}
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}
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uint32_t io_read() {
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io_stb_assert();
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dir_read();
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addr_0();
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__asm__("nop");
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__asm__("nop");
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__asm__("nop");
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const auto switches_raw = data_read();
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io_stb_deassert();
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return switches_raw;
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}
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uint32_t io_update(const TouchPinsConfig write_value);
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uint32_t lcd_te() {
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return gpio_rot_a.read();
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}
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private:
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const GPIO gpio_dir;
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const GPIO gpio_lcd_rdx;
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const GPIO gpio_lcd_wrx;
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const GPIO gpio_io_stbx;
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const GPIO gpio_addr;
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const GPIO gpio_rot_a;
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const GPIO gpio_rot_b;
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static constexpr ioportid_t gpio_data_port_id = 3;
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static constexpr size_t gpio_data_shift = 8;
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static constexpr ioportmask_t gpio_data_mask = 0xffU << gpio_data_shift;
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uint8_t io_reg { 0x03 };
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void lcd_rd_assert() {
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gpio_lcd_rdx.clear();
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}
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void lcd_rd_deassert() {
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gpio_lcd_rdx.set();
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}
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void lcd_wr_assert() {
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gpio_lcd_wrx.clear();
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}
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void lcd_wr_deassert() {
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gpio_lcd_wrx.set();
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}
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void io_stb_assert() {
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gpio_io_stbx.clear();
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}
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void io_stb_deassert() {
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gpio_io_stbx.set();
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}
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void addr(const bool value) {
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gpio_addr.write(value);
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}
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void addr_1() {
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gpio_addr.set();
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}
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void addr_0() {
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gpio_addr.clear();
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}
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void data_mask_set() {
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LPC_GPIO->MASK[gpio_data_port_id] = ~gpio_data_mask;
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}
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void dir_write() {
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gpio_dir.clear();
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LPC_GPIO->DIR[gpio_data_port_id] |= gpio_data_mask;
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/* TODO: Manipulating DIR[3] makes me queasy. The RFFC5072 DATA pin
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* is also on port 3, and switches direction periodically...
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* Time to resort to bit-banding to enforce atomicity? But then, how
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* to change direction on eight bits efficiently? Or do I care, since
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* the PortaPack data bus shouldn't change direction too frequently?
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*/
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}
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void dir_read() {
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LPC_GPIO->DIR[gpio_data_port_id] &= ~gpio_data_mask;
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gpio_dir.set();
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}
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void data_write_low(const uint32_t value) {
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LPC_GPIO->MPIN[gpio_data_port_id] = (value << gpio_data_shift);
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}
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void data_write_high(const uint32_t value) {
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LPC_GPIO->MPIN[gpio_data_port_id] = value;
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}
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uint32_t data_read() {
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return (LPC_GPIO->MPIN[gpio_data_port_id] >> gpio_data_shift) & 0xffU;
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}
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void lcd_command(const uint32_t value) {
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data_write_high(0); /* Drive high byte (with zero -- don't care) */
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dir_write(); /* Turn around data bus, MCU->CPLD */
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addr(0); /* Indicate command */
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__asm__("nop");
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__asm__("nop");
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__asm__("nop");
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lcd_wr_assert(); /* Latch high byte */
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data_write_low(value); /* Drive low byte (pass-through) */
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__asm__("nop");
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__asm__("nop");
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__asm__("nop");
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lcd_wr_deassert(); /* Complete write operation */
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addr(1); /* Set up for data phase (most likely after a command) */
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}
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void lcd_write_data(const uint32_t value) __attribute__((always_inline)) {
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// NOTE: Assumes and DIR=0 and ADDR=1 from command phase.
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data_write_high(value); /* Drive high byte */
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__asm__("nop");
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lcd_wr_assert(); /* Latch high byte */
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data_write_low(value); /* Drive low byte (pass-through) */
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__asm__("nop");
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__asm__("nop");
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__asm__("nop");
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lcd_wr_deassert(); /* Complete write operation */
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}
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uint32_t lcd_read_data() {
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// NOTE: Assumes ADDR=1 from command phase.
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dir_read();
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/* Start read operation */
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lcd_rd_assert();
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/* Wait for passthrough data(15:8) to settle -- ~16ns (3 cycles) typical */
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/* Wait for read control L duration (355ns) */
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halPolledDelay(71); // 355ns
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const auto value_high = data_read();
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/* Latch data[7:0] */
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lcd_rd_deassert();
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/* Wait for latched data[7:0] to settle -- ~26ns (5 cycles) typical */
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/* Wait for read control H duration (90ns) */
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halPolledDelay(18); // 90ns
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const auto value_low = data_read();
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return (value_high << 8) | value_low;
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}
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void io_write(const bool address, const uint_fast16_t value) {
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data_write_low(value);
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dir_write();
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addr(address);
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__asm__("nop");
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__asm__("nop");
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__asm__("nop");
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io_stb_assert();
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__asm__("nop");
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__asm__("nop");
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__asm__("nop");
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io_stb_deassert();
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}
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/*
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void lcd_data_write_command_and_data(
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const uint_fast16_t command,
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const uint8_t* const data,
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const size_t count
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) {
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lcd_data_write_command(command);
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for(size_t i=0; i<count; i++) {
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lcd_data_write_data(data[i]);
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}
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}
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*/
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};
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extern IO io;
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} /* namespace portapack */
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#endif/*__PORTAPACK_IO_H__*/
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