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Updated Settings (markdown)

Brumi-2021 2023-12-26 10:22:46 +01:00
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Settings.md

@ -5,18 +5,18 @@ This allow the setting of the tone Key mixer setting as a percent of the audio l
In the radio section there are two options, In the radio section there are two options,
1. Enable/disable the Clock Output. 1. Enable/disable the Clock Output.
Note 1 : In r9 Hackrf platform , due to our complex fw Architecture and usage of Si5351A , we have fixed the synthetized CLK out freq to 10Mhz. > Note 1 : In r9 Hackrf platform , due to our complex fw Architecture and usage of Si5351A , we have fixed the synthetized CLK out freq to 10Mhz.
Note 2 : In all previous r1 to r8 Hackrf platforms , as we are using Si5351C, we do not have that limitation , and user can change the CLKOUT frequency between 4 kHz to 60000 kHz; press OK when the frequency is highlighted to select which digit position to modify and then use the encoder to scroll through the digit values. (it works with both clock references, the internal Hackrf (25Mhz) and the external -when available- from Portapack (TCXO 10Mhz ). > Note 2 : In all previous r1 to r8 Hackrf platforms , as we are using Si5351C, we do not have that limitation , and user can change the CLKOUT frequency between 4 kHz to 60000 kHz; press OK when the frequency is highlighted to select which digit position to modify and then use the encoder to scroll through the digit values. (it works with both clock references, the internal Hackrf (25Mhz) and the external -when available- from Portapack (TCXO 10Mhz ).
![image](https://github.com/eried/portapack-mayhem/assets/86470699/5c44e075-cf84-4f8f-8ca6-a7979c1bf4aa) > ![image](https://github.com/eried/portapack-mayhem/assets/86470699/5c44e075-cf84-4f8f-8ca6-a7979c1bf4aa)
Warning note : be awared that some of current market Portapack boards use to have an integrated TCXO 10Mhz clock generator, and when is mounted, it is connected in parallel to the Hackrf CLK in port connector. So in that case , that signal is present always in the SMA CLK in connector , and you should better to not connect any other external signal generator there (unless you remove the Portapack from Hackrf) , because otherwise, you may damage that Portapack TCXO clock IC. > Warning note : be awared that some of current market Portapack boards use to have an integrated TCXO 10Mhz clock generator, and when is mounted, it is connected in parallel to the Hackrf CLK in port connector. So in that case , that signal is present always in the SMA CLK in connector , and you should better to not connect any other external signal generator there (unless you remove the Portapack from Hackrf) , because otherwise, you may damage that Portapack TCXO clock IC.
Here below , you can see two different examples of the embedded TCXO 10Mhz ref. clock, > Here below , you can see two different examples of the embedded TCXO 10Mhz ref. clock,
in a PP H1 brd (left side ) , PP H2 brd (right side) boards : > in a PP H1 brd (left side ) , PP H2 brd (right side) boards :
![image](https://github.com/eried/portapack-mayhem/assets/86470699/ad83b637-4532-4ea8-994b-4372a38f9d15) > ![image](https://github.com/eried/portapack-mayhem/assets/86470699/ad83b637-4532-4ea8-994b-4372a38f9d15)
2. Enable/disable the Antenna Bias voltage. If enabled, ensure that all devices attached to the antenna connector can accept a DC bias voltage. 2. Enable/disable the Antenna Bias voltage. If enabled, ensure that all devices attached to the antenna connector can accept a DC bias voltage.