From 5009e9c9851250019803ec8e3ef3f1dc8cd00e82 Mon Sep 17 00:00:00 2001
From: Brumi-2021 <86470699+Brumi-2021@users.noreply.github.com>
Date: Tue, 26 Dec 2023 11:23:07 +0100
Subject: [PATCH] Updated Settings (markdown)

---
 Settings.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Settings.md b/Settings.md
index ff3fbfa..0125f34 100644
--- a/Settings.md
+++ b/Settings.md
@@ -18,7 +18,7 @@ In the radio section there are three options,
 > ![image](https://github.com/eried/portapack-mayhem/assets/86470699/820c12d9-c724-48ed-ba1d-f3c31e096a07)
 
 
-> Warning note : be awared that some of current market Portapack boards may have an integrated low ppm TCXO 10Mhz clock generator mounted, and when it is built in,  it is connected in parallel to the Hackrf CLK_in port connector. So in that case , that signal is present always in the SMA  CLK in connector , and you should better to not connect any other external signal generator there (unless you remove the Portapack from Hackrf) , because otherwise, you may damage that Portapack TCXO clock IC. 
+> Warning note : be awared that some of current market Portapack boards may have an integrated low ppm TCXO 10Mhz clock generator mounted, and when it is built in,  it is connected in parallel to the Hackrf CLK_in port connector. So in that special case ,  that internal clock signal is present always in the SMA  CLK in connector (it is a strange case, CLK_in is behaving as real embedded ref. output of internal TCXO 10Mhz clock) , and you should better to not connect any other external signal generator there (unless you remove the Portapack from Hackrf) , because otherwise, you may damage that Portapack TCXO clock IC. 
 
 > Here below , you can see two different examples of the embedded TCXO 10Mhz ref. clock,	
 >  in a PP  H1 brd (left side ) , PP  H2 brd (right side) boards :