From edbfa878b6050dd69db9d33ee5d109133425e0d0 Mon Sep 17 00:00:00 2001
From: Brumi-2021 <86470699+Brumi-2021@users.noreply.github.com>
Date: Tue, 26 Dec 2023 09:46:18 +0100
Subject: [PATCH] Updated Settings (markdown)

---
 Settings.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Settings.md b/Settings.md
index d87929d..3bc6d60 100644
--- a/Settings.md
+++ b/Settings.md
@@ -11,7 +11,7 @@ Note 2 : In all previous r1 to r8 Hackrf platforms , as we are using Si5351C, we
 
 ![image](https://github.com/eried/portapack-mayhem/assets/86470699/5c44e075-cf84-4f8f-8ca6-a7979c1bf4aa)
 
-Warning note : be awared that some of current market Portapack boards use to have an integrated TCXO 10Mhz clock generator, and when is mounted,  it is connected in parallel to the Hackrf CLK in port connector. So in that case , that signal is present always in the SMA  CLK in connector , and you should better to not connect any other external signal generator there (unless you remove the Portapack from Hackrf) , because you may damage that Portapack TCXO clock IC).
+Warning note : be awared that some of current market Portapack boards use to have an integrated TCXO 10Mhz clock generator, and when is mounted,  it is connected in parallel to the Hackrf CLK in port connector. So in that case , that signal is present always in the SMA  CLK in connector , and you should better to not connect any other external signal generator there (unless you remove the Portapack from Hackrf) , because otherwise, you may damage that Portapack TCXO clock IC. 
 
 2. Enable/disable the Antenna Bias voltage.  If enabled, ensure that all devices attached to the antenna connector can accept a DC bias voltage.