mirror of
https://github.com/oxen-io/session-android.git
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461 lines
7.5 KiB
Perl
461 lines
7.5 KiB
Perl
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#!/usr/bin/env perl
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#
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# ====================================================================
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# Written by Andy Polyakov <appro@openssl.org> for the OpenSSL
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# project. The module is, however, dual licensed under OpenSSL and
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# CRYPTOGAMS licenses depending on where you obtain it. For further
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# details see http://www.openssl.org/~appro/cryptogams/.
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# ====================================================================
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#
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# March 2010
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#
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# The module implements "4-bit" GCM GHASH function and underlying
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# single multiplication operation in GF(2^128). "4-bit" means that it
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# uses 256 bytes per-key table [+128 bytes shared table]. Even though
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# loops are aggressively modulo-scheduled in respect to references to
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# Htbl and Z.hi updates for 8 cycles per byte, measured performance is
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# ~12 cycles per processed byte on 21264 CPU. It seems to be a dynamic
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# scheduling "glitch," because uprofile(1) indicates uniform sample
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# distribution, as if all instruction bundles execute in 1.5 cycles.
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# Meaning that it could have been even faster, yet 12 cycles is ~60%
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# better than gcc-generated code and ~80% than code generated by vendor
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# compiler.
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$cnt="v0"; # $0
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$t0="t0";
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$t1="t1";
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$t2="t2";
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$Thi0="t3"; # $4
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$Tlo0="t4";
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$Thi1="t5";
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$Tlo1="t6";
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$rem="t7"; # $8
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#################
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$Xi="a0"; # $16, input argument block
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$Htbl="a1";
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$inp="a2";
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$len="a3";
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$nlo="a4"; # $20
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$nhi="a5";
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$Zhi="t8";
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$Zlo="t9";
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$Xhi="t10"; # $24
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$Xlo="t11";
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$remp="t12";
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$rem_4bit="AT"; # $28
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{ my $N;
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sub loop() {
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$N++;
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$code.=<<___;
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.align 4
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extbl $Xlo,7,$nlo
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and $nlo,0xf0,$nhi
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sll $nlo,4,$nlo
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and $nlo,0xf0,$nlo
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addq $nlo,$Htbl,$nlo
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ldq $Zlo,8($nlo)
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addq $nhi,$Htbl,$nhi
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ldq $Zhi,0($nlo)
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and $Zlo,0x0f,$remp
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sll $Zhi,60,$t0
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lda $cnt,6(zero)
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extbl $Xlo,6,$nlo
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ldq $Tlo1,8($nhi)
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s8addq $remp,$rem_4bit,$remp
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ldq $Thi1,0($nhi)
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srl $Zlo,4,$Zlo
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ldq $rem,0($remp)
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srl $Zhi,4,$Zhi
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xor $t0,$Zlo,$Zlo
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and $nlo,0xf0,$nhi
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xor $Tlo1,$Zlo,$Zlo
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sll $nlo,4,$nlo
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xor $Thi1,$Zhi,$Zhi
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and $nlo,0xf0,$nlo
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addq $nlo,$Htbl,$nlo
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ldq $Tlo0,8($nlo)
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addq $nhi,$Htbl,$nhi
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ldq $Thi0,0($nlo)
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.Looplo$N:
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and $Zlo,0x0f,$remp
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sll $Zhi,60,$t0
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subq $cnt,1,$cnt
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srl $Zlo,4,$Zlo
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ldq $Tlo1,8($nhi)
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xor $rem,$Zhi,$Zhi
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ldq $Thi1,0($nhi)
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s8addq $remp,$rem_4bit,$remp
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ldq $rem,0($remp)
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srl $Zhi,4,$Zhi
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xor $t0,$Zlo,$Zlo
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extbl $Xlo,$cnt,$nlo
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and $nlo,0xf0,$nhi
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xor $Thi0,$Zhi,$Zhi
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xor $Tlo0,$Zlo,$Zlo
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sll $nlo,4,$nlo
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and $Zlo,0x0f,$remp
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sll $Zhi,60,$t0
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and $nlo,0xf0,$nlo
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srl $Zlo,4,$Zlo
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s8addq $remp,$rem_4bit,$remp
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xor $rem,$Zhi,$Zhi
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addq $nlo,$Htbl,$nlo
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addq $nhi,$Htbl,$nhi
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ldq $rem,0($remp)
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srl $Zhi,4,$Zhi
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ldq $Tlo0,8($nlo)
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xor $t0,$Zlo,$Zlo
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xor $Tlo1,$Zlo,$Zlo
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xor $Thi1,$Zhi,$Zhi
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ldq $Thi0,0($nlo)
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bne $cnt,.Looplo$N
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and $Zlo,0x0f,$remp
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sll $Zhi,60,$t0
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lda $cnt,7(zero)
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srl $Zlo,4,$Zlo
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ldq $Tlo1,8($nhi)
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xor $rem,$Zhi,$Zhi
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ldq $Thi1,0($nhi)
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s8addq $remp,$rem_4bit,$remp
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ldq $rem,0($remp)
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srl $Zhi,4,$Zhi
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xor $t0,$Zlo,$Zlo
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extbl $Xhi,$cnt,$nlo
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and $nlo,0xf0,$nhi
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xor $Thi0,$Zhi,$Zhi
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xor $Tlo0,$Zlo,$Zlo
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sll $nlo,4,$nlo
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and $Zlo,0x0f,$remp
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sll $Zhi,60,$t0
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and $nlo,0xf0,$nlo
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srl $Zlo,4,$Zlo
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s8addq $remp,$rem_4bit,$remp
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xor $rem,$Zhi,$Zhi
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addq $nlo,$Htbl,$nlo
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addq $nhi,$Htbl,$nhi
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ldq $rem,0($remp)
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srl $Zhi,4,$Zhi
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ldq $Tlo0,8($nlo)
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xor $t0,$Zlo,$Zlo
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xor $Tlo1,$Zlo,$Zlo
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xor $Thi1,$Zhi,$Zhi
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ldq $Thi0,0($nlo)
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unop
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.Loophi$N:
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and $Zlo,0x0f,$remp
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sll $Zhi,60,$t0
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subq $cnt,1,$cnt
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srl $Zlo,4,$Zlo
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ldq $Tlo1,8($nhi)
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xor $rem,$Zhi,$Zhi
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ldq $Thi1,0($nhi)
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s8addq $remp,$rem_4bit,$remp
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ldq $rem,0($remp)
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srl $Zhi,4,$Zhi
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xor $t0,$Zlo,$Zlo
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extbl $Xhi,$cnt,$nlo
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and $nlo,0xf0,$nhi
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xor $Thi0,$Zhi,$Zhi
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xor $Tlo0,$Zlo,$Zlo
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sll $nlo,4,$nlo
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and $Zlo,0x0f,$remp
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sll $Zhi,60,$t0
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and $nlo,0xf0,$nlo
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srl $Zlo,4,$Zlo
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s8addq $remp,$rem_4bit,$remp
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xor $rem,$Zhi,$Zhi
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addq $nlo,$Htbl,$nlo
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addq $nhi,$Htbl,$nhi
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ldq $rem,0($remp)
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srl $Zhi,4,$Zhi
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ldq $Tlo0,8($nlo)
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xor $t0,$Zlo,$Zlo
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xor $Tlo1,$Zlo,$Zlo
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xor $Thi1,$Zhi,$Zhi
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ldq $Thi0,0($nlo)
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bne $cnt,.Loophi$N
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and $Zlo,0x0f,$remp
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sll $Zhi,60,$t0
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srl $Zlo,4,$Zlo
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ldq $Tlo1,8($nhi)
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xor $rem,$Zhi,$Zhi
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ldq $Thi1,0($nhi)
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s8addq $remp,$rem_4bit,$remp
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ldq $rem,0($remp)
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srl $Zhi,4,$Zhi
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xor $t0,$Zlo,$Zlo
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xor $Tlo0,$Zlo,$Zlo
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xor $Thi0,$Zhi,$Zhi
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and $Zlo,0x0f,$remp
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sll $Zhi,60,$t0
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srl $Zlo,4,$Zlo
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s8addq $remp,$rem_4bit,$remp
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xor $rem,$Zhi,$Zhi
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ldq $rem,0($remp)
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srl $Zhi,4,$Zhi
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xor $Tlo1,$Zlo,$Zlo
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xor $Thi1,$Zhi,$Zhi
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xor $t0,$Zlo,$Zlo
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xor $rem,$Zhi,$Zhi
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___
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}}
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$code=<<___;
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#ifdef __linux__
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#include <asm/regdef.h>
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#else
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#include <asm.h>
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#include <regdef.h>
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#endif
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.text
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.set noat
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.set noreorder
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.globl gcm_gmult_4bit
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.align 4
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.ent gcm_gmult_4bit
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gcm_gmult_4bit:
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.frame sp,0,ra
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.prologue 0
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ldq $Xlo,8($Xi)
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ldq $Xhi,0($Xi)
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bsr $t0,picmeup
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nop
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___
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&loop();
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$code.=<<___;
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srl $Zlo,24,$t0 # byte swap
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srl $Zlo,8,$t1
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sll $Zlo,8,$t2
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sll $Zlo,24,$Zlo
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zapnot $t0,0x11,$t0
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zapnot $t1,0x22,$t1
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zapnot $Zlo,0x88,$Zlo
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or $t0,$t1,$t0
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zapnot $t2,0x44,$t2
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or $Zlo,$t0,$Zlo
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srl $Zhi,24,$t0
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srl $Zhi,8,$t1
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or $Zlo,$t2,$Zlo
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sll $Zhi,8,$t2
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sll $Zhi,24,$Zhi
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srl $Zlo,32,$Xlo
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sll $Zlo,32,$Zlo
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zapnot $t0,0x11,$t0
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zapnot $t1,0x22,$t1
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or $Zlo,$Xlo,$Xlo
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zapnot $Zhi,0x88,$Zhi
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or $t0,$t1,$t0
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zapnot $t2,0x44,$t2
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or $Zhi,$t0,$Zhi
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or $Zhi,$t2,$Zhi
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srl $Zhi,32,$Xhi
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sll $Zhi,32,$Zhi
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or $Zhi,$Xhi,$Xhi
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stq $Xlo,8($Xi)
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stq $Xhi,0($Xi)
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ret (ra)
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.end gcm_gmult_4bit
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___
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$inhi="s0";
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$inlo="s1";
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$code.=<<___;
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.globl gcm_ghash_4bit
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.align 4
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.ent gcm_ghash_4bit
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gcm_ghash_4bit:
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lda sp,-32(sp)
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stq ra,0(sp)
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stq s0,8(sp)
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stq s1,16(sp)
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.mask 0x04000600,-32
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.frame sp,32,ra
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.prologue 0
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ldq_u $inhi,0($inp)
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ldq_u $Thi0,7($inp)
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ldq_u $inlo,8($inp)
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ldq_u $Tlo0,15($inp)
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ldq $Xhi,0($Xi)
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ldq $Xlo,8($Xi)
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bsr $t0,picmeup
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nop
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.Louter:
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extql $inhi,$inp,$inhi
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extqh $Thi0,$inp,$Thi0
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or $inhi,$Thi0,$inhi
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lda $inp,16($inp)
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extql $inlo,$inp,$inlo
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extqh $Tlo0,$inp,$Tlo0
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or $inlo,$Tlo0,$inlo
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subq $len,16,$len
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xor $Xlo,$inlo,$Xlo
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xor $Xhi,$inhi,$Xhi
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___
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&loop();
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$code.=<<___;
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srl $Zlo,24,$t0 # byte swap
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srl $Zlo,8,$t1
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sll $Zlo,8,$t2
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sll $Zlo,24,$Zlo
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zapnot $t0,0x11,$t0
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zapnot $t1,0x22,$t1
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zapnot $Zlo,0x88,$Zlo
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or $t0,$t1,$t0
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zapnot $t2,0x44,$t2
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or $Zlo,$t0,$Zlo
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srl $Zhi,24,$t0
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srl $Zhi,8,$t1
|
||
|
|
|
||
|
|
or $Zlo,$t2,$Zlo
|
||
|
|
sll $Zhi,8,$t2
|
||
|
|
sll $Zhi,24,$Zhi
|
||
|
|
|
||
|
|
srl $Zlo,32,$Xlo
|
||
|
|
sll $Zlo,32,$Zlo
|
||
|
|
beq $len,.Ldone
|
||
|
|
|
||
|
|
zapnot $t0,0x11,$t0
|
||
|
|
zapnot $t1,0x22,$t1
|
||
|
|
or $Zlo,$Xlo,$Xlo
|
||
|
|
ldq_u $inhi,0($inp)
|
||
|
|
|
||
|
|
zapnot $Zhi,0x88,$Zhi
|
||
|
|
or $t0,$t1,$t0
|
||
|
|
zapnot $t2,0x44,$t2
|
||
|
|
ldq_u $Thi0,7($inp)
|
||
|
|
|
||
|
|
or $Zhi,$t0,$Zhi
|
||
|
|
or $Zhi,$t2,$Zhi
|
||
|
|
ldq_u $inlo,8($inp)
|
||
|
|
ldq_u $Tlo0,15($inp)
|
||
|
|
|
||
|
|
srl $Zhi,32,$Xhi
|
||
|
|
sll $Zhi,32,$Zhi
|
||
|
|
|
||
|
|
or $Zhi,$Xhi,$Xhi
|
||
|
|
br zero,.Louter
|
||
|
|
|
||
|
|
.Ldone:
|
||
|
|
zapnot $t0,0x11,$t0
|
||
|
|
zapnot $t1,0x22,$t1
|
||
|
|
or $Zlo,$Xlo,$Xlo
|
||
|
|
|
||
|
|
zapnot $Zhi,0x88,$Zhi
|
||
|
|
or $t0,$t1,$t0
|
||
|
|
zapnot $t2,0x44,$t2
|
||
|
|
|
||
|
|
or $Zhi,$t0,$Zhi
|
||
|
|
or $Zhi,$t2,$Zhi
|
||
|
|
|
||
|
|
srl $Zhi,32,$Xhi
|
||
|
|
sll $Zhi,32,$Zhi
|
||
|
|
|
||
|
|
or $Zhi,$Xhi,$Xhi
|
||
|
|
|
||
|
|
stq $Xlo,8($Xi)
|
||
|
|
stq $Xhi,0($Xi)
|
||
|
|
|
||
|
|
.set noreorder
|
||
|
|
/*ldq ra,0(sp)*/
|
||
|
|
ldq s0,8(sp)
|
||
|
|
ldq s1,16(sp)
|
||
|
|
lda sp,32(sp)
|
||
|
|
ret (ra)
|
||
|
|
.end gcm_ghash_4bit
|
||
|
|
|
||
|
|
.align 4
|
||
|
|
.ent picmeup
|
||
|
|
picmeup:
|
||
|
|
.frame sp,0,$t0
|
||
|
|
.prologue 0
|
||
|
|
br $rem_4bit,.Lpic
|
||
|
|
.Lpic: lda $rem_4bit,12($rem_4bit)
|
||
|
|
ret ($t0)
|
||
|
|
.end picmeup
|
||
|
|
nop
|
||
|
|
rem_4bit:
|
||
|
|
.long 0,0x0000<<16, 0,0x1C20<<16, 0,0x3840<<16, 0,0x2460<<16
|
||
|
|
.long 0,0x7080<<16, 0,0x6CA0<<16, 0,0x48C0<<16, 0,0x54E0<<16
|
||
|
|
.long 0,0xE100<<16, 0,0xFD20<<16, 0,0xD940<<16, 0,0xC560<<16
|
||
|
|
.long 0,0x9180<<16, 0,0x8DA0<<16, 0,0xA9C0<<16, 0,0xB5E0<<16
|
||
|
|
.ascii "GHASH for Alpha, CRYPTOGAMS by <appro\@openssl.org>"
|
||
|
|
.align 4
|
||
|
|
|
||
|
|
___
|
||
|
|
$output=shift and open STDOUT,">$output";
|
||
|
|
print $code;
|
||
|
|
close STDOUT;
|
||
|
|
|