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202 lines
4.3 KiB
ArmAsm
202 lines
4.3 KiB
ArmAsm
#include "arm_arch.h"
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.text
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.code 32
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#if __ARM_ARCH__>=7
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.fpu neon
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#endif
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.type mul_1x1_ialu,%function
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.align 5
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mul_1x1_ialu:
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mov r4,#0
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bic r5,r1,#3<<30 @ a1=a&0x3fffffff
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str r4,[sp,#0] @ tab[0]=0
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add r6,r5,r5 @ a2=a1<<1
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str r5,[sp,#4] @ tab[1]=a1
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eor r7,r5,r6 @ a1^a2
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str r6,[sp,#8] @ tab[2]=a2
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mov r8,r5,lsl#2 @ a4=a1<<2
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str r7,[sp,#12] @ tab[3]=a1^a2
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eor r9,r5,r8 @ a1^a4
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str r8,[sp,#16] @ tab[4]=a4
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eor r4,r6,r8 @ a2^a4
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str r9,[sp,#20] @ tab[5]=a1^a4
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eor r7,r7,r8 @ a1^a2^a4
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str r4,[sp,#24] @ tab[6]=a2^a4
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and r8,r12,r0,lsl#2
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str r7,[sp,#28] @ tab[7]=a1^a2^a4
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and r9,r12,r0,lsr#1
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ldr r5,[sp,r8] @ tab[b & 0x7]
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and r8,r12,r0,lsr#4
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ldr r7,[sp,r9] @ tab[b >> 3 & 0x7]
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and r9,r12,r0,lsr#7
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ldr r6,[sp,r8] @ tab[b >> 6 & 0x7]
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eor r5,r5,r7,lsl#3 @ stall
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mov r4,r7,lsr#29
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ldr r7,[sp,r9] @ tab[b >> 9 & 0x7]
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and r8,r12,r0,lsr#10
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eor r5,r5,r6,lsl#6
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eor r4,r4,r6,lsr#26
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ldr r6,[sp,r8] @ tab[b >> 12 & 0x7]
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and r9,r12,r0,lsr#13
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eor r5,r5,r7,lsl#9
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eor r4,r4,r7,lsr#23
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ldr r7,[sp,r9] @ tab[b >> 15 & 0x7]
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and r8,r12,r0,lsr#16
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eor r5,r5,r6,lsl#12
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eor r4,r4,r6,lsr#20
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ldr r6,[sp,r8] @ tab[b >> 18 & 0x7]
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and r9,r12,r0,lsr#19
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eor r5,r5,r7,lsl#15
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eor r4,r4,r7,lsr#17
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ldr r7,[sp,r9] @ tab[b >> 21 & 0x7]
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and r8,r12,r0,lsr#22
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eor r5,r5,r6,lsl#18
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eor r4,r4,r6,lsr#14
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ldr r6,[sp,r8] @ tab[b >> 24 & 0x7]
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and r9,r12,r0,lsr#25
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eor r5,r5,r7,lsl#21
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eor r4,r4,r7,lsr#11
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ldr r7,[sp,r9] @ tab[b >> 27 & 0x7]
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tst r1,#1<<30
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and r8,r12,r0,lsr#28
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eor r5,r5,r6,lsl#24
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eor r4,r4,r6,lsr#8
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ldr r6,[sp,r8] @ tab[b >> 30 ]
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eorne r5,r5,r0,lsl#30
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eorne r4,r4,r0,lsr#2
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tst r1,#1<<31
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eor r5,r5,r7,lsl#27
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eor r4,r4,r7,lsr#5
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eorne r5,r5,r0,lsl#31
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eorne r4,r4,r0,lsr#1
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eor r5,r5,r6,lsl#30
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eor r4,r4,r6,lsr#2
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mov pc,lr
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.size mul_1x1_ialu,.-mul_1x1_ialu
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.global bn_GF2m_mul_2x2
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.type bn_GF2m_mul_2x2,%function
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.align 5
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bn_GF2m_mul_2x2:
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#if __ARM_ARCH__>=7
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ldr r12,.LOPENSSL_armcap
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.Lpic: ldr r12,[pc,r12]
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tst r12,#1
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beq .Lialu
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ldr r12, [sp] @ 5th argument
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vmov.32 d26, r2, r1
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vmov.32 d27, r12, r3
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vmov.i64 d28, #0x0000ffffffffffff
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vmov.i64 d29, #0x00000000ffffffff
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vmov.i64 d30, #0x000000000000ffff
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vext.8 d2, d26, d26, #1 @ A1
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vmull.p8 q1, d2, d27 @ F = A1*B
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vext.8 d0, d27, d27, #1 @ B1
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vmull.p8 q0, d26, d0 @ E = A*B1
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vext.8 d4, d26, d26, #2 @ A2
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vmull.p8 q2, d4, d27 @ H = A2*B
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vext.8 d16, d27, d27, #2 @ B2
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vmull.p8 q8, d26, d16 @ G = A*B2
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vext.8 d6, d26, d26, #3 @ A3
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veor q1, q1, q0 @ L = E + F
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vmull.p8 q3, d6, d27 @ J = A3*B
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vext.8 d0, d27, d27, #3 @ B3
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veor q2, q2, q8 @ M = G + H
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vmull.p8 q0, d26, d0 @ I = A*B3
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veor d2, d2, d3 @ t0 = (L) (P0 + P1) << 8
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vand d3, d3, d28
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vext.8 d16, d27, d27, #4 @ B4
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veor d4, d4, d5 @ t1 = (M) (P2 + P3) << 16
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vand d5, d5, d29
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vmull.p8 q8, d26, d16 @ K = A*B4
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veor q3, q3, q0 @ N = I + J
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veor d2, d2, d3
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veor d4, d4, d5
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veor d6, d6, d7 @ t2 = (N) (P4 + P5) << 24
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vand d7, d7, d30
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vext.8 q1, q1, q1, #15
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veor d16, d16, d17 @ t3 = (K) (P6 + P7) << 32
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vmov.i64 d17, #0
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vext.8 q2, q2, q2, #14
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veor d6, d6, d7
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vmull.p8 q0, d26, d27 @ D = A*B
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vext.8 q8, q8, q8, #12
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vext.8 q3, q3, q3, #13
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veor q1, q1, q2
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veor q3, q3, q8
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veor q0, q0, q1
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veor q0, q0, q3
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vst1.32 {q0}, [r0]
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bx lr @ bx lr
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.align 4
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.Lialu:
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#endif
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stmdb sp!,{r4-r10,lr}
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mov r10,r0 @ reassign 1st argument
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mov r0,r3 @ r0=b1
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ldr r3,[sp,#32] @ load b0
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mov r12,#7<<2
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sub sp,sp,#32 @ allocate tab[8]
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bl mul_1x1_ialu @ a1·b1
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str r5,[r10,#8]
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str r4,[r10,#12]
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eor r0,r0,r3 @ flip b0 and b1
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eor r1,r1,r2 @ flip a0 and a1
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eor r3,r3,r0
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eor r2,r2,r1
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eor r0,r0,r3
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eor r1,r1,r2
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bl mul_1x1_ialu @ a0·b0
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str r5,[r10]
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str r4,[r10,#4]
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eor r1,r1,r2
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eor r0,r0,r3
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bl mul_1x1_ialu @ (a1+a0)·(b1+b0)
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ldmia r10,{r6-r9}
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eor r5,r5,r4
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eor r4,r4,r7
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eor r5,r5,r6
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eor r4,r4,r8
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eor r5,r5,r9
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eor r4,r4,r9
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str r4,[r10,#8]
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eor r5,r5,r4
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add sp,sp,#32 @ destroy tab[8]
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str r5,[r10,#4]
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#if __ARM_ARCH__>=5
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ldmia sp!,{r4-r10,pc}
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#else
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ldmia sp!,{r4-r10,lr}
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tst lr,#1
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moveq pc,lr @ be binary compatible with V4, yet
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.word 0xe12fff1e @ interoperable with Thumb ISA:-)
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#endif
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.size bn_GF2m_mul_2x2,.-bn_GF2m_mul_2x2
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#if __ARM_ARCH__>=7
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.align 5
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.LOPENSSL_armcap:
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.word OPENSSL_armcap_P-(.Lpic+8)
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#endif
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.asciz "GF(2^m) Multiplication for ARMv4/NEON, CRYPTOGAMS by <appro@openssl.org>"
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.align 5
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.comm OPENSSL_armcap_P,4,4
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