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241 lines
6.0 KiB
Perl
241 lines
6.0 KiB
Perl
#!/usr/bin/env perl
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#
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# ====================================================================
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# Written by Andy Polyakov <appro@openssl.org> for the OpenSSL
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# project. The module is, however, dual licensed under OpenSSL and
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# CRYPTOGAMS licenses depending on where you obtain it. For further
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# details see http://www.openssl.org/~appro/cryptogams/.
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# ====================================================================
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#
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# GHASH for ARMv8 Crypto Extension, 64-bit polynomial multiplication.
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#
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# June 2014
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#
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# Initial version was developed in tight cooperation with Ard
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# Biesheuvel <ard.biesheuvel@linaro.org> from bits-n-pieces from
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# other assembly modules. Just like aesv8-armx.pl this module
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# supports both AArch32 and AArch64 execution modes.
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#
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# Current performance in cycles per processed byte:
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#
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# PMULL[2] 32-bit NEON(*)
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# Apple A7 1.76 5.62
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# Cortex-A5x n/a n/a
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#
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# (*) presented for reference/comparison purposes;
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$flavour = shift;
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open STDOUT,">".shift;
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$Xi="x0"; # argument block
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$Htbl="x1";
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$inp="x2";
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$len="x3";
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$inc="x12";
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{
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my ($Xl,$Xm,$Xh,$IN)=map("q$_",(0..3));
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my ($t0,$t1,$t2,$t3,$H,$Hhl)=map("q$_",(8..14));
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$code=<<___;
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#include "arm_arch.h"
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.text
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___
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$code.=".arch armv8-a+crypto\n" if ($flavour =~ /64/);
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$code.=".fpu neon\n.code 32\n" if ($flavour !~ /64/);
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$code.=<<___;
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.global gcm_init_v8
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.type gcm_init_v8,%function
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.align 4
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gcm_init_v8:
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vld1.64 {$t1},[x1] @ load H
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vmov.i8 $t0,#0xe1
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vext.8 $IN,$t1,$t1,#8
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vshl.i64 $t0,$t0,#57
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vshr.u64 $t2,$t0,#63
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vext.8 $t0,$t2,$t0,#8 @ t0=0xc2....01
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vdup.32 $t1,${t1}[1]
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vshr.u64 $t3,$IN,#63
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vshr.s32 $t1,$t1,#31 @ broadcast carry bit
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vand $t3,$t3,$t0
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vshl.i64 $IN,$IN,#1
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vext.8 $t3,$t3,$t3,#8
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vand $t0,$t0,$t1
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vorr $IN,$IN,$t3 @ H<<<=1
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veor $IN,$IN,$t0 @ twisted H
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vst1.64 {$IN},[x0]
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ret
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.size gcm_init_v8,.-gcm_init_v8
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.global gcm_gmult_v8
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.type gcm_gmult_v8,%function
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.align 4
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gcm_gmult_v8:
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vld1.64 {$t1},[$Xi] @ load Xi
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vmov.i8 $t3,#0xe1
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vld1.64 {$H},[$Htbl] @ load twisted H
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vshl.u64 $t3,$t3,#57
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#ifndef __ARMEB__
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vrev64.8 $t1,$t1
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#endif
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vext.8 $Hhl,$H,$H,#8
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mov $len,#0
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vext.8 $IN,$t1,$t1,#8
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mov $inc,#0
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veor $Hhl,$Hhl,$H @ Karatsuba pre-processing
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mov $inp,$Xi
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b .Lgmult_v8
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.size gcm_gmult_v8,.-gcm_gmult_v8
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.global gcm_ghash_v8
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.type gcm_ghash_v8,%function
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.align 4
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gcm_ghash_v8:
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vld1.64 {$Xl},[$Xi] @ load [rotated] Xi
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subs $len,$len,#16
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vmov.i8 $t3,#0xe1
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mov $inc,#16
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vld1.64 {$H},[$Htbl] @ load twisted H
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cclr $inc,eq
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vext.8 $Xl,$Xl,$Xl,#8
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vshl.u64 $t3,$t3,#57
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vld1.64 {$t1},[$inp],$inc @ load [rotated] inp
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vext.8 $Hhl,$H,$H,#8
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#ifndef __ARMEB__
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vrev64.8 $Xl,$Xl
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vrev64.8 $t1,$t1
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#endif
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veor $Hhl,$Hhl,$H @ Karatsuba pre-processing
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vext.8 $IN,$t1,$t1,#8
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b .Loop_v8
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.align 4
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.Loop_v8:
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vext.8 $t2,$Xl,$Xl,#8
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veor $IN,$IN,$Xl @ inp^=Xi
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veor $t1,$t1,$t2 @ $t1 is rotated inp^Xi
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.Lgmult_v8:
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vpmull.p64 $Xl,$H,$IN @ H.lo·Xi.lo
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veor $t1,$t1,$IN @ Karatsuba pre-processing
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vpmull2.p64 $Xh,$H,$IN @ H.hi·Xi.hi
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subs $len,$len,#16
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vpmull.p64 $Xm,$Hhl,$t1 @ (H.lo+H.hi)·(Xi.lo+Xi.hi)
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cclr $inc,eq
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vext.8 $t1,$Xl,$Xh,#8 @ Karatsuba post-processing
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veor $t2,$Xl,$Xh
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veor $Xm,$Xm,$t1
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vld1.64 {$t1},[$inp],$inc @ load [rotated] inp
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veor $Xm,$Xm,$t2
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vpmull.p64 $t2,$Xl,$t3 @ 1st phase
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vmov $Xh#lo,$Xm#hi @ Xh|Xm - 256-bit result
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vmov $Xm#hi,$Xl#lo @ Xm is rotated Xl
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#ifndef __ARMEB__
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vrev64.8 $t1,$t1
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#endif
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veor $Xl,$Xm,$t2
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vext.8 $IN,$t1,$t1,#8
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vext.8 $t2,$Xl,$Xl,#8 @ 2nd phase
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vpmull.p64 $Xl,$Xl,$t3
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veor $t2,$t2,$Xh
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veor $Xl,$Xl,$t2
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b.hs .Loop_v8
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#ifndef __ARMEB__
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vrev64.8 $Xl,$Xl
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#endif
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vext.8 $Xl,$Xl,$Xl,#8
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vst1.64 {$Xl},[$Xi] @ write out Xi
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ret
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.size gcm_ghash_v8,.-gcm_ghash_v8
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___
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}
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$code.=<<___;
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.asciz "GHASH for ARMv8, CRYPTOGAMS by <appro\@openssl.org>"
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.align 2
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___
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if ($flavour =~ /64/) { ######## 64-bit code
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sub unvmov {
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my $arg=shift;
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$arg =~ m/q([0-9]+)#(lo|hi),\s*q([0-9]+)#(lo|hi)/o &&
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sprintf "ins v%d.d[%d],v%d.d[%d]",$1,($2 eq "lo")?0:1,$3,($4 eq "lo")?0:1;
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}
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foreach(split("\n",$code)) {
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s/cclr\s+([wx])([^,]+),\s*([a-z]+)/csel $1$2,$1zr,$1$2,$3/o or
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s/vmov\.i8/movi/o or # fix up legacy mnemonics
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s/vmov\s+(.*)/unvmov($1)/geo or
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s/vext\.8/ext/o or
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s/vshr\.s/sshr\.s/o or
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s/vshr/ushr/o or
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s/^(\s+)v/$1/o or # strip off v prefix
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s/\bbx\s+lr\b/ret/o;
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s/\bq([0-9]+)\b/"v".($1<8?$1:$1+8).".16b"/geo; # old->new registers
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s/@\s/\/\//o; # old->new style commentary
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# fix up remainig legacy suffixes
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s/\.[ui]?8(\s)/$1/o;
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s/\.[uis]?32//o and s/\.16b/\.4s/go;
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m/\.p64/o and s/\.16b/\.1q/o; # 1st pmull argument
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m/l\.p64/o and s/\.16b/\.1d/go; # 2nd and 3rd pmull arguments
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s/\.[uisp]?64//o and s/\.16b/\.2d/go;
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s/\.[42]([sd])\[([0-3])\]/\.$1\[$2\]/o;
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print $_,"\n";
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}
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} else { ######## 32-bit code
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sub unvdup32 {
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my $arg=shift;
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$arg =~ m/q([0-9]+),\s*q([0-9]+)\[([0-3])\]/o &&
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sprintf "vdup.32 q%d,d%d[%d]",$1,2*$2+($3>>1),$3&1;
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}
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sub unvpmullp64 {
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my ($mnemonic,$arg)=@_;
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if ($arg =~ m/q([0-9]+),\s*q([0-9]+),\s*q([0-9]+)/o) {
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my $word = 0xf2a00e00|(($1&7)<<13)|(($1&8)<<19)
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|(($2&7)<<17)|(($2&8)<<4)
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|(($3&7)<<1) |(($3&8)<<2);
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$word |= 0x00010001 if ($mnemonic =~ "2");
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# since ARMv7 instructions are always encoded little-endian.
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# correct solution is to use .inst directive, but older
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# assemblers don't implement it:-(
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sprintf ".byte\t0x%02x,0x%02x,0x%02x,0x%02x\t@ %s %s",
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$word&0xff,($word>>8)&0xff,
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($word>>16)&0xff,($word>>24)&0xff,
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$mnemonic,$arg;
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}
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}
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foreach(split("\n",$code)) {
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s/\b[wx]([0-9]+)\b/r$1/go; # new->old registers
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s/\bv([0-9])\.[12468]+[bsd]\b/q$1/go; # new->old registers
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s/\/\/\s?/@ /o; # new->old style commentary
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# fix up remainig new-style suffixes
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s/\],#[0-9]+/]!/o;
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s/cclr\s+([^,]+),\s*([a-z]+)/mov$2 $1,#0/o or
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s/vdup\.32\s+(.*)/unvdup32($1)/geo or
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s/v?(pmull2?)\.p64\s+(.*)/unvpmullp64($1,$2)/geo or
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s/\bq([0-9]+)#(lo|hi)/sprintf "d%d",2*$1+($2 eq "hi")/geo or
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s/^(\s+)b\./$1b/o or
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s/^(\s+)ret/$1bx\tlr/o;
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print $_,"\n";
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}
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}
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close STDOUT; # enforce flush
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