mirror of
https://github.com/oxen-io/session-android.git
synced 2024-12-21 07:27:30 +00:00
403 lines
7.8 KiB
ArmAsm
403 lines
7.8 KiB
ArmAsm
#if defined(__SUNPRO_C) && defined(__sparcv9)
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# define ABI64 /* They've said -xarch=v9 at command line */
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#elif defined(__GNUC__) && defined(__arch64__)
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# define ABI64 /* They've said -m64 at command line */
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#endif
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#ifdef ABI64
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.register %g2,#scratch
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.register %g3,#scratch
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# define FRAME -192
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# define BIAS 2047
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#else
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# define FRAME -96
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# define BIAS 0
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#endif
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.text
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.align 32
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.global OPENSSL_wipe_cpu
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.type OPENSSL_wipe_cpu,#function
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! Keep in mind that this does not excuse us from wiping the stack!
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! This routine wipes registers, but not the backing store [which
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! resides on the stack, toward lower addresses]. To facilitate for
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! stack wiping I return pointer to the top of stack of the *caller*.
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OPENSSL_wipe_cpu:
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save %sp,FRAME,%sp
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nop
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#ifdef __sun
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#include <sys/trap.h>
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ta ST_CLEAN_WINDOWS
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#else
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call .walk.reg.wins
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#endif
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nop
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call .PIC.zero.up
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mov .zero-(.-4),%o0
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ld [%o0],%f0
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ld [%o0],%f1
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subcc %g0,1,%o0
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! Following is V9 "rd %ccr,%o0" instruction. However! V8
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! specification says that it ("rd %asr2,%o0" in V8 terms) does
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! not cause illegal_instruction trap. It therefore can be used
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! to determine if the CPU the code is executing on is V8- or
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! V9-compliant, as V9 returns a distinct value of 0x99,
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! "negative" and "borrow" bits set in both %icc and %xcc.
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.word 0x91408000 !rd %ccr,%o0
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cmp %o0,0x99
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bne .v8
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nop
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! Even though we do not use %fp register bank,
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! we wipe it as memcpy might have used it...
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.word 0xbfa00040 !fmovd %f0,%f62
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.word 0xbba00040 !...
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.word 0xb7a00040
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.word 0xb3a00040
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.word 0xafa00040
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.word 0xaba00040
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.word 0xa7a00040
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.word 0xa3a00040
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.word 0x9fa00040
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.word 0x9ba00040
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.word 0x97a00040
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.word 0x93a00040
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.word 0x8fa00040
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.word 0x8ba00040
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.word 0x87a00040
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.word 0x83a00040 !fmovd %f0,%f32
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.v8: fmovs %f1,%f31
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clr %o0
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fmovs %f0,%f30
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clr %o1
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fmovs %f1,%f29
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clr %o2
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fmovs %f0,%f28
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clr %o3
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fmovs %f1,%f27
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clr %o4
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fmovs %f0,%f26
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clr %o5
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fmovs %f1,%f25
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clr %o7
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fmovs %f0,%f24
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clr %l0
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fmovs %f1,%f23
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clr %l1
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fmovs %f0,%f22
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clr %l2
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fmovs %f1,%f21
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clr %l3
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fmovs %f0,%f20
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clr %l4
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fmovs %f1,%f19
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clr %l5
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fmovs %f0,%f18
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clr %l6
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fmovs %f1,%f17
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clr %l7
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fmovs %f0,%f16
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clr %i0
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fmovs %f1,%f15
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clr %i1
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fmovs %f0,%f14
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clr %i2
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fmovs %f1,%f13
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clr %i3
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fmovs %f0,%f12
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clr %i4
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fmovs %f1,%f11
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clr %i5
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fmovs %f0,%f10
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clr %g1
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fmovs %f1,%f9
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clr %g2
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fmovs %f0,%f8
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clr %g3
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fmovs %f1,%f7
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clr %g4
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fmovs %f0,%f6
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clr %g5
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fmovs %f1,%f5
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fmovs %f0,%f4
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fmovs %f1,%f3
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fmovs %f0,%f2
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add %fp,BIAS,%i0 ! return pointer to caller´s top of stack
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ret
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restore
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.zero: .long 0x0,0x0
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.PIC.zero.up:
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retl
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add %o0,%o7,%o0
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#ifdef DEBUG
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.global walk_reg_wins
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.type walk_reg_wins,#function
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walk_reg_wins:
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#endif
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.walk.reg.wins:
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save %sp,FRAME,%sp
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cmp %i7,%o7
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be 2f
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clr %o0
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cmp %o7,0 ! compiler never cleans %o7...
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be 1f ! could have been a leaf function...
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clr %o1
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call .walk.reg.wins
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nop
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1: clr %o2
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clr %o3
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clr %o4
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clr %o5
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clr %o7
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clr %l0
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clr %l1
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clr %l2
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clr %l3
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clr %l4
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clr %l5
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clr %l6
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clr %l7
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add %o0,1,%i0 ! used for debugging
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2: ret
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restore
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.size OPENSSL_wipe_cpu,.-OPENSSL_wipe_cpu
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.global OPENSSL_atomic_add
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.type OPENSSL_atomic_add,#function
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.align 32
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OPENSSL_atomic_add:
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#ifndef ABI64
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subcc %g0,1,%o2
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.word 0x95408000 !rd %ccr,%o2, see comment above
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cmp %o2,0x99
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be .v9
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nop
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save %sp,FRAME,%sp
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ba .enter
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nop
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#ifdef __sun
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! Note that you do not have to link with libthread to call thr_yield,
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! as libc provides a stub, which is overloaded the moment you link
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! with *either* libpthread or libthread...
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#define YIELD_CPU thr_yield
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#else
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! applies at least to Linux and FreeBSD... Feedback expected...
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#define YIELD_CPU sched_yield
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#endif
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.spin: call YIELD_CPU
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nop
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.enter: ld [%i0],%i2
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cmp %i2,-4096
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be .spin
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mov -1,%i2
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swap [%i0],%i2
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cmp %i2,-1
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be .spin
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add %i2,%i1,%i2
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stbar
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st %i2,[%i0]
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sra %i2,%g0,%i0
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ret
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restore
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.v9:
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#endif
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ld [%o0],%o2
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1: add %o1,%o2,%o3
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.word 0xd7e2100a !cas [%o0],%o2,%o3, compare [%o0] with %o2 and swap %o3
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cmp %o2,%o3
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bne 1b
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mov %o3,%o2 ! cas is always fetching to dest. register
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add %o1,%o2,%o0 ! OpenSSL expects the new value
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retl
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sra %o0,%g0,%o0 ! we return signed int, remember?
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.size OPENSSL_atomic_add,.-OPENSSL_atomic_add
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.global _sparcv9_rdtick
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.align 32
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_sparcv9_rdtick:
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subcc %g0,1,%o0
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.word 0x91408000 !rd %ccr,%o0
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cmp %o0,0x99
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bne .notick
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xor %o0,%o0,%o0
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.word 0x91410000 !rd %tick,%o0
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retl
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.word 0x93323020 !srlx %o0,32,%o1
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.notick:
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retl
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xor %o1,%o1,%o1
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.type _sparcv9_rdtick,#function
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.size _sparcv9_rdtick,.-_sparcv9_rdtick
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.global _sparcv9_vis1_probe
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.align 8
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_sparcv9_vis1_probe:
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add %sp,BIAS+2,%o1
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.word 0xc19a5a40 !ldda [%o1]ASI_FP16_P,%f0
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retl
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.word 0x81b00d80 !fxor %f0,%f0,%f0
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.type _sparcv9_vis1_probe,#function
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.size _sparcv9_vis1_probe,.-_sparcv9_vis1_probe
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! Probe and instrument VIS1 instruction. Output is number of cycles it
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! takes to execute rdtick and pair of VIS1 instructions. US-Tx VIS unit
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! is slow (documented to be 6 cycles on T2) and the core is in-order
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! single-issue, it should be possible to distinguish Tx reliably...
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! Observed return values are:
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!
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! UltraSPARC IIe 7
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! UltraSPARC III 7
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! UltraSPARC T1 24
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!
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! Numbers for T2 and SPARC64 V-VII are more than welcomed.
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!
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! It would be possible to detect specifically US-T1 by instrumenting
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! fmul8ulx16, which is emulated on T1 and as such accounts for quite
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! a lot of %tick-s, couple of thousand on Linux...
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.global _sparcv9_vis1_instrument
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.align 8
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_sparcv9_vis1_instrument:
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.word 0x91410000 !rd %tick,%o0
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.word 0x81b00d80 !fxor %f0,%f0,%f0
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.word 0x85b08d82 !fxor %f2,%f2,%f2
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.word 0x93410000 !rd %tick,%o1
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.word 0x81b00d80 !fxor %f0,%f0,%f0
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.word 0x85b08d82 !fxor %f2,%f2,%f2
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.word 0x95410000 !rd %tick,%o2
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.word 0x81b00d80 !fxor %f0,%f0,%f0
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.word 0x85b08d82 !fxor %f2,%f2,%f2
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.word 0x97410000 !rd %tick,%o3
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.word 0x81b00d80 !fxor %f0,%f0,%f0
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.word 0x85b08d82 !fxor %f2,%f2,%f2
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.word 0x99410000 !rd %tick,%o4
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! calculate intervals
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sub %o1,%o0,%o0
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sub %o2,%o1,%o1
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sub %o3,%o2,%o2
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sub %o4,%o3,%o3
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! find minumum value
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cmp %o0,%o1
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.word 0x38680002 !bgu,a %xcc,.+8
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mov %o1,%o0
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cmp %o0,%o2
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.word 0x38680002 !bgu,a %xcc,.+8
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mov %o2,%o0
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cmp %o0,%o3
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.word 0x38680002 !bgu,a %xcc,.+8
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mov %o3,%o0
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retl
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nop
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.type _sparcv9_vis1_instrument,#function
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.size _sparcv9_vis1_instrument,.-_sparcv9_vis1_instrument
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.global _sparcv9_vis2_probe
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.align 8
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_sparcv9_vis2_probe:
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retl
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.word 0x81b00980 !bshuffle %f0,%f0,%f0
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.type _sparcv9_vis2_probe,#function
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.size _sparcv9_vis2_probe,.-_sparcv9_vis2_probe
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.global _sparcv9_fmadd_probe
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.align 8
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_sparcv9_fmadd_probe:
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.word 0x81b00d80 !fxor %f0,%f0,%f0
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.word 0x85b08d82 !fxor %f2,%f2,%f2
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retl
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.word 0x81b80440 !fmaddd %f0,%f0,%f2,%f0
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.type _sparcv9_fmadd_probe,#function
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.size _sparcv9_fmadd_probe,.-_sparcv9_fmadd_probe
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.global OPENSSL_cleanse
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.align 32
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OPENSSL_cleanse:
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cmp %o1,14
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nop
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#ifdef ABI64
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bgu %xcc,.Lot
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#else
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bgu .Lot
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#endif
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cmp %o1,0
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bne .Little
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nop
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retl
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nop
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.Little:
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stb %g0,[%o0]
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subcc %o1,1,%o1
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bnz .Little
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add %o0,1,%o0
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retl
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nop
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.align 32
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.Lot:
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#ifndef ABI64
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subcc %g0,1,%g1
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! see above for explanation
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.word 0x83408000 !rd %ccr,%g1
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cmp %g1,0x99
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bne .v8lot
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nop
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#endif
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.v9lot: andcc %o0,7,%g0
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bz .v9aligned
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nop
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stb %g0,[%o0]
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sub %o1,1,%o1
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ba .v9lot
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add %o0,1,%o0
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.align 16,0x01000000
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.v9aligned:
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.word 0xc0720000 !stx %g0,[%o0]
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sub %o1,8,%o1
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andcc %o1,-8,%g0
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#ifdef ABI64
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.word 0x126ffffd !bnz %xcc,.v9aligned
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#else
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.word 0x124ffffd !bnz %icc,.v9aligned
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#endif
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add %o0,8,%o0
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cmp %o1,0
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bne .Little
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nop
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retl
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nop
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#ifndef ABI64
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.v8lot: andcc %o0,3,%g0
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bz .v8aligned
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nop
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stb %g0,[%o0]
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sub %o1,1,%o1
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ba .v8lot
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add %o0,1,%o0
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nop
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.v8aligned:
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st %g0,[%o0]
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sub %o1,4,%o1
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andcc %o1,-4,%g0
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bnz .v8aligned
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add %o0,4,%o0
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cmp %o1,0
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bne .Little
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nop
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retl
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nop
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#endif
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.type OPENSSL_cleanse,#function
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.size OPENSSL_cleanse,.-OPENSSL_cleanse
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.section ".init",#alloc,#execinstr
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call OPENSSL_cpuid_setup
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nop
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